sim/testsuite/sim/frv/fr500/dcul.cgs

   1 # FRV testcase for dcul GRi
   2 # mach: frv fr500
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global dcul
   9 dcul:
  10         or_spr_immed    0xc8000000,hsr0 ; caches enabled -- copy-back mode
  11
  12         ; preload and lock all the lines in set 0 of the data cache
  13         set_gr_immed    0x70000,gr10
  14         lock_data_cache gr10
  15         set_mem_immed   0x11111111,gr10
  16         test_mem_immed  0x11111111,gr10
  17
  18         inc_gr_immed    0x1000,gr10
  19         set_gr_immed    1,gr11
  20         lock_data_cache gr10
  21         set_mem_immed   0x22222222,gr10
  22         test_mem_immed  0x22222222,gr10
  23
  24         inc_gr_immed    0x1000,gr10
  25         set_gr_immed    63,gr11
  26         lock_data_cache gr10
  27         set_mem_immed   0x33333333,gr10
  28         test_mem_immed  0x33333333,gr10
  29
  30         inc_gr_immed    0x1000,gr10
  31         set_gr_immed    64,gr11
  32         lock_data_cache gr10
  33         set_mem_immed   0x44444444,gr10
  34         test_mem_immed  0x44444444,gr10
  35
  36         ; Now write to another address which should be in the same set
  37         ; the write should go through to memory, since all the lines in the
  38         ; set are locked
  39         inc_gr_immed    0x1000,gr10
  40         set_mem_immed   0xdeadbeef,gr10
  41         test_mem_immed  0xdeadbeef,gr10
  42
  43         ; Invalidate the data cache. Only the last value stored should have made
  44         ; it through to memory
  45         set_gr_immed    0x70000,gr10
  46         invalidate_data_cache   gr10
  47         test_mem_immed  0,gr10
  48
  49         inc_gr_immed    0x1000,gr10
  50         invalidate_data_cache   gr10
  51         test_mem_immed  0,gr10
  52
  53         inc_gr_immed    0x1000,gr10
  54         invalidate_data_cache   gr10
  55         test_mem_immed  0,gr10
  56
  57         inc_gr_immed    0x1000,gr10
  58         invalidate_data_cache   gr10
  59         test_mem_immed  0,gr10
  60
  61         inc_gr_immed    0x1000,gr10
  62         invalidate_data_cache   gr10
  63         test_mem_immed  0xdeadbeef,gr10
  64
  65         ; Now preload load and lock all the lines in set 0 of the data cache
  66         ; again
  67         set_gr_immed    0x70000,gr10
  68         lock_data_cache gr10
  69         set_mem_immed   0x11111111,gr10
  70         test_mem_immed  0x11111111,gr10
  71
  72         inc_gr_immed    0x1000,gr10
  73         set_gr_immed    1,gr11
  74         lock_data_cache gr10
  75         set_mem_immed   0x22222222,gr10
  76         test_mem_immed  0x22222222,gr10
  77
  78         inc_gr_immed    0x1000,gr10
  79         set_gr_immed    63,gr11
  80         lock_data_cache gr10
  81         set_mem_immed   0x33333333,gr10
  82         test_mem_immed  0x33333333,gr10
  83
  84         inc_gr_immed    0x1000,gr10
  85         set_gr_immed    64,gr11
  86         lock_data_cache gr10
  87         set_mem_immed   0x44444444,gr10
  88         test_mem_immed  0x44444444,gr10
  89
  90         ; unlock one line
  91         set_gr_immed    0x72000,gr10
  92         dcul            gr10
  93
  94         ; Now write to another address which should be in the same set.
  95         set_gr_immed    0x75000,gr10
  96         set_mem_immed   0xbeefdead,gr10
  97
  98         ; All of the stored values should be retrievable
  99
 100         set_gr_immed    0x70000,gr10
 101         test_mem_immed  0x11111111,gr10
 102
 103         inc_gr_immed    0x1000,gr10
 104         test_mem_immed  0x22222222,gr10
 105
 106         inc_gr_immed    0x1000,gr10
 107         test_mem_immed  0x33333333,gr10
 108
 109         inc_gr_immed    0x1000,gr10
 110         test_mem_immed  0x44444444,gr10
 111
 112         inc_gr_immed    0x1000,gr10
 113         test_mem_immed  0xdeadbeef,gr10
 114
 115         inc_gr_immed    0x1000,gr10
 116         test_mem_immed  0xbeefdead,gr10
 117
 118         pass