+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and
+ TRUE with true throughout.
+
2021-03-29 Alan Modra <amodra@gmail.com>
* frv.opc (frv_is_branch_major, frv_is_float_major),
const CGEN_INSN * insn[FRV_VLIW_SIZE];
} FRV_VLIW;
-bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_branch_insn (const CGEN_INSN *);
-bfd_boolean frv_is_float_insn (const CGEN_INSN *);
-bfd_boolean frv_is_media_insn (const CGEN_INSN *);
-void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
-bfd_boolean spr_valid (long);
+bool frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_branch_insn (const CGEN_INSN *);
+bool frv_is_float_insn (const CGEN_INSN *);
+bool frv_is_media_insn (const CGEN_INSN *);
+void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
+bool spr_valid (long);
/* -- */
\f
/* -- opc.c */
/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
development tree. */
-bfd_boolean
+bool
frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
- return TRUE;
+ return true;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
- return TRUE;
+ return true;
break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */
-bfd_boolean
+bool
frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
- return FALSE;
+ return false;
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
/* Returns TRUE if {MAJOR,MACH} supports media insns. */
-bfd_boolean
+bool
frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
- return TRUE;
+ return true;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
- return TRUE;
+ return true;
break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_branch_insn (const CGEN_INSN *insn)
{
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_float_insn (const CGEN_INSN *insn)
{
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_media_insn (const CGEN_INSN *insn)
{
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* This table represents the allowable packing for vliw insns for the fr400.
/* Return TRUE if unit1 is a match for unit2.
Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
*_allowed_vliw tables above. */
-static bfd_boolean
+static bool
match_unit (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
{
unit1 = vliw->unit_mapping[unit1];
if (unit1 == unit2)
- return TRUE;
+ return true;
if (unit1 < unit2)
- return FALSE;
+ return false;
switch (unit1)
{
/* The 01 versions of these units are within 2 enums of the 0 or 1
versions. */
if (unit1 - unit2 <= 2)
- return TRUE;
+ return true;
break;
case UNIT_IALL:
case UNIT_FMALL:
/* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
versions. */
if (unit1 - unit2 <= 5)
- return TRUE;
+ return true;
break;
default:
break;
}
- return FALSE;
+ return false;
}
/* Return TRUE if the vliws match, FALSE otherwise. */
-static bfd_boolean
+static bool
match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
{
int i;
for (i = 0; i < vliw_size; ++i)
if ((*vliw1)[i] != (*vliw2)[i])
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Find the next vliw vliw in the table that can accomodate the new insn.
/* Look for the given major insn type in the given vliw.
Returns TRUE if found, FALSE otherwise. */
-static bfd_boolean
+static bool
find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Check for constraints between the insns in the vliw due to major insn
types. */
-static bfd_boolean
+static bool
fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
/* In the cpu file, all media insns are represented as being allowed in
default:
break;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
CGEN_ATTR_VALUE_ENUM_TYPE other_major;
/* (M4, M5) and (M4, M6) are allowed. */
if (other_major == FR450_MAJOR_M_4)
if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
- return TRUE;
+ return true;
/* Otherwise, instructions in even-numbered media categories cannot be
executed in parallel with other media instructions. */
|| other_major == FR450_MAJOR_M_6);
default:
- return TRUE;
+ return true;
}
}
-static bfd_boolean
+static bool
find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
- return TRUE;
+ return true;
- return FALSE; /* Not found. */
+ return false; /* Not found. */
}
-static bfd_boolean
+static bool
find_major_in_slot (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
CGEN_ATTR_VALUE_ENUM_TYPE slot)
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_find_media_in_vliw (FRV_VLIW *vliw)
{
int i;
|| CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
continue;
- return TRUE; /* Found one. */
+ return true; /* Found one. */
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_find_float_in_vliw (FRV_VLIW *vliw)
{
int i;
if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
continue;
- return TRUE; /* Found one. */
+ return true; /* Found one. */
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
const CGEN_INSN *insn)
default:
break;
}
- return TRUE; /* All OK. */
+ return true; /* All OK. */
}
-static bfd_boolean
+static bool
fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
/* TODO: A table might be faster for some of the more complex instances
case FR500_MAJOR_F_4:
case FR500_MAJOR_F_8:
case FR500_MAJOR_M_8:
- return TRUE; /* OK */
+ return true; /* OK */
case FR500_MAJOR_I_2:
/* Cannot coexist with I-3 insn. */
return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
abort ();
break;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
const CGEN_INSN *insn)
return 1;
}
-bfd_boolean
+bool
spr_valid (long regno)
{
- if (regno < 0) return FALSE;
- if (regno <= 4095) return TRUE;
- return FALSE;
+ if (regno < 0) return false;
+ if (regno <= 4095) return true;
+ return false;
}
/* -- */
\f
+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * sysdep.h (POISON_BFD_BOOLEAN): Define.
+ * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
+ * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
+ * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
+ * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
+ * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
+ * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
+ * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
+ * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
+ * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
+ * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
+ * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
+ * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
+ * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
+ and TRUE with true throughout.
+
2021-03-31 Alan Modra <amodra@gmail.com>
* aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
return aarch64_opcode_table + value;
}
-bfd_boolean
+bool
aarch64_insert_operand (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
/* Operand inserters. */
/* Insert nothing. */
-bfd_boolean
+bool
aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
aarch64_insn *code ATTRIBUTE_UNUSED,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- return TRUE;
+ return true;
}
/* Insert register number. */
-bfd_boolean
+bool
aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, info->reg.regno, 0);
- return TRUE;
+ return true;
}
/* Insert register number, index and/or other data for SIMD register element
operand, e.g. the last source operand in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
-bfd_boolean
+bool
aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
assert (0);
}
}
- return TRUE;
+ return true;
}
/* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
-bfd_boolean
+bool
aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
insert_field (self->fields[0], code, info->reglist.first_regno, 0);
/* len */
insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
- return TRUE;
+ return true;
}
/* Insert Rt and opcode fields for a register list operand, e.g. Vt
in AdvSIMD load/store instructions. */
-bfd_boolean
+bool
aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
}
insert_field (FLD_opcode, code, value, 0);
- return TRUE;
+ return true;
}
/* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
single structure to all lanes instructions. */
-bfd_boolean
+bool
aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
value = (aarch64_insn) 1;
insert_field (FLD_S, code, value, 0);
- return TRUE;
+ return true;
}
/* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
operand e.g. Vt in AdvSIMD load/store single element instructions. */
-bfd_boolean
+bool
aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
insert_field_2 (&field, code, opcodeh2, 0);
- return TRUE;
+ return true;
}
/* Insert fields immh:immb and/or Q for e.g. the shift immediate in
SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
or SSHR <V><d>, <V><n>, #<shift>. */
-bfd_boolean
+bool
aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
imm = info->imm.value + (8 << (unsigned)val);
insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
- return TRUE;
+ return true;
}
/* Insert fields for e.g. the immediate operands in
BFM <Wd>, <Wn>, #<immr>, #<imms>. */
-bfd_boolean
+bool
aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
if (operand_need_shift_by_four (self))
imm >>= 4;
insert_all_fields (self, code, imm);
- return TRUE;
+ return true;
}
/* Insert immediate and its shift amount for e.g. the last operand in
MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
-bfd_boolean
+bool
aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
aarch64_operand_error *errors)
aarch64_ins_imm (self, info, code, inst, errors);
/* hw */
insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
- return TRUE;
+ return true;
}
/* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
-bfd_boolean
+bool
aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
if (kind == AARCH64_MOD_NONE)
- return TRUE;
+ return true;
/* shift amount partially in cmode */
assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
/* For 8-bit move immediate, the optional LSL #0 does not require
encoding. */
if (esize == 1)
- return TRUE;
+ return true;
amount >>= 3;
if (esize == 4)
gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */
}
insert_field_2 (&field, code, amount, 0);
- return TRUE;
+ return true;
}
/* Insert fields for an 8-bit floating-point immediate. */
-bfd_boolean
+bool
aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
insert_all_fields (self, code, info->imm.value);
- return TRUE;
+ return true;
}
/* Insert 1-bit rotation immediate (#90 or #270). */
-bfd_boolean
+bool
aarch64_ins_imm_rotate1 (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
uint64_t rot = (info->imm.value - 90) / 180;
assert (rot < 2U);
insert_field (self->fields[0], code, rot, inst->opcode->mask);
- return TRUE;
+ return true;
}
/* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */
-bfd_boolean
+bool
aarch64_ins_imm_rotate2 (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
uint64_t rot = info->imm.value / 90;
assert (rot < 4U);
insert_field (self->fields[0], code, rot, inst->opcode->mask);
- return TRUE;
+ return true;
}
/* Insert #<fbits> for the immediate operand in fp fix-point instructions,
e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
-bfd_boolean
+bool
aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, 64 - info->imm.value, 0);
- return TRUE;
+ return true;
}
/* Insert arithmetic immediate for e.g. the last operand in
SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
-bfd_boolean
+bool
aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
insert_field (self->fields[0], code, value, 0);
/* imm12 (unsigned) */
insert_field (self->fields[1], code, info->imm.value, 0);
- return TRUE;
+ return true;
}
/* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether
the operand should be inverted before encoding. */
-static bfd_boolean
+static bool
aarch64_ins_limm_1 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
- const aarch64_inst *inst, bfd_boolean invert_p,
+ const aarch64_inst *inst, bool invert_p,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- bfd_boolean res;
+ bool res;
aarch64_insn value;
uint64_t imm = info->imm.value;
int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
/* Insert logical/bitmask immediate for e.g. the last operand in
ORR <Wd|WSP>, <Wn>, #<imm>. */
-bfd_boolean
+bool
aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
}
/* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */
-bfd_boolean
+bool
aarch64_ins_inv_limm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors);
+ return aarch64_ins_limm_1 (self, info, code, inst, true, errors);
}
/* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
-bfd_boolean
+bool
aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst,
aarch64_operand_error *errors)
insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
}
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
-bfd_boolean
+bool
aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* Rn */
insert_field (FLD_Rn, code, info->addr.base_regno, 0);
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-bfd_boolean
+bool
aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
S = info->shifter.operator_present && info->shifter.amount_present;
insert_field (FLD_S, code, S, 0);
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
-bfd_boolean
+bool
aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
assert (info->addr.preind == 1 && info->addr.postind == 0);
insert_field (self->fields[2], code, 1, 0);
}
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
-bfd_boolean
+bool
aarch64_ins_addr_simm (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[1], code, 1, 0);
}
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
-bfd_boolean
+bool
aarch64_ins_addr_simm10 (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
assert (info->addr.preind == 1 && info->addr.postind == 0);
insert_field (self->fields[3], code, 1, 0);
}
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
-bfd_boolean
+bool
aarch64_ins_addr_uimm12 (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[0], code, info->addr.base_regno, 0);
/* uimm12 */
insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
- return TRUE;
+ return true;
}
/* Encode the address operand for e.g.
LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
-bfd_boolean
+bool
aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
else
insert_field (FLD_Rm, code, 0x1f, 0);
- return TRUE;
+ return true;
}
/* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
-bfd_boolean
+bool
aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* cond */
insert_field (FLD_cond, code, info->cond->value, 0);
- return TRUE;
+ return true;
}
/* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
-bfd_boolean
+bool
aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
detail->error = _("specified register cannot be read from");
detail->index = info->idx;
- detail->non_fatal = TRUE;
+ detail->non_fatal = true;
}
else if (opcode_flags == F_SYS_WRITE
&& sysreg_flags
detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
detail->error = _("specified register cannot be written to");
detail->index = info->idx;
- detail->non_fatal = TRUE;
+ detail->non_fatal = true;
}
}
/* op0:op1:CRn:CRm:op2 */
insert_fields (code, info->sysreg.value, inst->opcode->mask, 5,
FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
- return TRUE;
+ return true;
}
/* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
-bfd_boolean
+bool
aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* op1:op2 */
insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
FLD_op2, FLD_op1);
- return TRUE;
+ return true;
}
/* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
-bfd_boolean
+bool
aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* op1:CRn:CRm:op2 */
insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
- return TRUE;
+ return true;
}
/* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
-bfd_boolean
+bool
aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* CRm */
insert_field (FLD_CRm, code, info->barrier->value, 0);
- return TRUE;
+ return true;
}
/* Encode the memory barrier option operand for DSB <option>nXS|#<imm>. */
-bfd_boolean
+bool
aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
encoded in CRm<3:2>. */
aarch64_insn value = (info->barrier->value >> 2) - 4;
insert_field (FLD_CRm_dsb_nxs, code, value, 0);
- return TRUE;
+ return true;
}
/* Encode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
-bfd_boolean
+bool
aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* prfop in Rt */
insert_field (FLD_Rt, code, info->prfop->value, 0);
- return TRUE;
+ return true;
}
/* Encode the hint number for instructions that alias HINT but take an
operand. */
-bfd_boolean
+bool
aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* CRm:op2. */
insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
- return TRUE;
+ return true;
}
/* Encode the extended register operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-bfd_boolean
+bool
aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* imm3 */
insert_field (FLD_imm3, code, info->shifter.amount, 0);
- return TRUE;
+ return true;
}
/* Encode the shifted register operand for e.g.
SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
-bfd_boolean
+bool
aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* imm6 */
insert_field (FLD_imm6, code, info->shifter.amount, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
where <simm4> is a 4-bit signed value and where <factor> is 1 plus
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm4> is encoded in the SVE_imm4 field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
int factor = 1 + get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
where <simm6> is a 6-bit signed value and where <factor> is 1 plus
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm6> is encoded in the SVE_imm6 field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
int factor = 1 + get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
and imm3 fields, with imm3 being the less-significant part. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_fields (code, info->addr.offset.imm / factor, 0,
2, FLD_imm3, FLD_SVE_imm6);
- return TRUE;
+ return true;
}
/* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
is a 4-bit signed number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
int factor = 1 << get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
int factor = 1 << get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
is SELF's operand-dependent value. fields[0] specifies the base
register field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (self->fields[1], code, info->addr.offset.regno, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
<shift> is SELF's operand-dependent value. fields[0] specifies the
base register field, fields[1] specifies the offset register field and
fields[2] is a single-bit field that selects SXTW over UXTW. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
insert_field (self->fields[2], code, 0, 0);
else
insert_field (self->fields[2], code, 1, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
5-bit unsigned number and where <shift> is SELF's operand-dependent value.
fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
int factor = 1 << get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
where <modifier> is fixed by the instruction and where <msz> is a
2-bit unsigned number. fields[0] specifies the base register field
and fields[1] specifies the offset register field. */
-static bfd_boolean
+static bool
aarch64_ext_sve_addr_zz (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_field (self->fields[1], code, info->addr.offset.regno, 0);
insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
}
/* Encode an SVE ADD/SUB immediate. */
-bfd_boolean
+bool
aarch64_ins_sve_aimm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256);
else
insert_all_fields (self, code, info->imm.value & 0xff);
- return TRUE;
+ return true;
}
/* Encode an SVE CPY/DUP immediate. */
-bfd_boolean
+bool
aarch64_ins_sve_asimm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
array specifies which field to use for Zn. MM is encoded in the
concatenation of imm5 and SVE_tszh, with imm5 being the less
significant part. */
-bfd_boolean
+bool
aarch64_ins_sve_index (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
insert_field (self->fields[0], code, info->reglane.regno, 0);
insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
2, FLD_imm5, FLD_SVE_tszh);
- return TRUE;
+ return true;
}
/* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */
-bfd_boolean
+bool
aarch64_ins_sve_limm_mov (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
/* Encode Zn[MM], where Zn occupies the least-significant part of the field
and where MM occupies the most-significant part. The operand-dependent
value specifies the number of bits in Zn. */
-bfd_boolean
+bool
aarch64_ins_sve_quad_index (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
assert (info->reglane.regno < (1U << reg_bits));
unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
insert_all_fields (self, code, val);
- return TRUE;
+ return true;
}
/* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
to use for Zn. */
-bfd_boolean
+bool
aarch64_ins_sve_reglist (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
insert_field (self->fields[0], code, info->reglist.first_regno, 0);
- return TRUE;
+ return true;
}
/* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
field. */
-bfd_boolean
+bool
aarch64_ins_sve_scale (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
insert_all_fields (self, code, info->imm.value);
insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);
- return TRUE;
+ return true;
}
/* Encode an SVE shift left immediate. */
-bfd_boolean
+bool
aarch64_ins_sve_shlimm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
prev_operand = &inst->operands[info->idx - 1];
esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
insert_all_fields (self, code, 8 * esize + info->imm.value);
- return TRUE;
+ return true;
}
/* Encode an SVE shift right immediate. */
-bfd_boolean
+bool
aarch64_ins_sve_shrimm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
prev_operand = &inst->operands[info->idx - opnd_backshift];
esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
insert_all_fields (self, code, 16 * esize - info->imm.value);
- return TRUE;
+ return true;
}
/* Encode a single-bit immediate that selects between #0.5 and #1.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ins_sve_float_half_one (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[0], code, 0, 0);
else
insert_field (self->fields[0], code, 1, 0);
- return TRUE;
+ return true;
}
/* Encode a single-bit immediate that selects between #0.5 and #2.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ins_sve_float_half_two (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[0], code, 0, 0);
else
insert_field (self->fields[0], code, 1, 0);
- return TRUE;
+ return true;
}
/* Encode a single-bit immediate that selects between #0.0 and #1.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
insert_field (self->fields[0], code, 0, 0);
else
insert_field (self->fields[0], code, 1, 0);
- return TRUE;
+ return true;
}
/* Miscellaneous encoding functions. */
Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
matched operand qualifier sequence in *QLF_SEQ. */
-bfd_boolean
+bool
aarch64_opcode_encode (const aarch64_opcode *opcode,
const aarch64_inst *inst_ori, aarch64_insn *code,
aarch64_opnd_qualifier_t *qlf_seq,
if (operand_has_inserter (opnd)
&& !aarch64_insert_operand (opnd, info, &inst->value, inst,
mismatch_detail))
- return FALSE;
+ return false;
}
/* Call opcode encoders indicated by flags. */
/* Run a verifier if the instruction has one set. */
if (opcode->verifier)
{
- enum err_type result = opcode->verifier (inst, *code, 0, TRUE,
+ enum err_type result = opcode->verifier (inst, *code, 0, true,
mismatch_detail, insn_sequence);
switch (result)
{
case ERR_UND:
case ERR_UNP:
case ERR_NYI:
- return FALSE;
+ return false;
default:
break;
}
/* Always run constrain verifiers, this is needed because constrains need to
maintain a global state. Regardless if the instruction has the flag set
or not. */
- enum err_type result = verify_constraints (inst, *code, 0, TRUE,
+ enum err_type result = verify_constraints (inst, *code, 0, true,
mismatch_detail, insn_sequence);
switch (result)
{
case ERR_UND:
case ERR_UNP:
case ERR_NYI:
- return FALSE;
+ return false;
default:
break;
}
*code = inst->value;
- return TRUE;
+ return true;
}
/* Switch-table-based high-level operand inserter. */
-bfd_boolean aarch64_insert_operand (const aarch64_operand *,
- const aarch64_opnd_info *, aarch64_insn *,
- const aarch64_inst *,
- aarch64_operand_error *);
+bool aarch64_insert_operand (const aarch64_operand *,
+ const aarch64_opnd_info *, aarch64_insn *,
+ const aarch64_inst *, aarch64_operand_error *);
/* Operand inserters. */
#define AARCH64_DECL_OPD_INSERTER(x) \
- bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
- aarch64_insn *, const aarch64_inst *, \
- aarch64_operand_error *)
+ bool aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
+ aarch64_insn *, const aarch64_inst *, \
+ aarch64_operand_error *)
AARCH64_DECL_OPD_INSERTER (ins_none);
AARCH64_DECL_OPD_INSERTER (ins_regno);
return aarch64_opcode_table + value;
}
-bfd_boolean
+bool
aarch64_extract_operand (const aarch64_operand *self,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst,
/* Operand extractors. */
-bfd_boolean
+bool
aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info ATTRIBUTE_UNUSED,
const aarch64_insn code ATTRIBUTE_UNUSED,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
info->reg.regno = extract_field (self->fields[0], code, 0);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
const aarch64_insn code ATTRIBUTE_UNUSED,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
assert (info->idx == 1
|| info->idx ==3);
info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
- return TRUE;
+ return true;
}
/* e.g. IC <ic_op>{, <Xt>}. */
-bfd_boolean
+bool
aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
not. */
info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
- return TRUE;
+ return true;
}
/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
-bfd_boolean
+bool
aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
while (++pos <= 3 && (value & 0x1) == 0)
value >>= 1;
if (pos > 3)
- return FALSE;
+ return false;
info->qualifier = get_sreg_qualifier_from_value (pos);
info->reglane.index = (unsigned) (value >> 1);
}
info->reglane.regno &= 0x1f;
break;
default:
- return FALSE;
+ return false;
}
}
else if (inst->opcode->iclass == cryptosm3)
info->reglane.index = extract_field (FLD_H, code, 0);
break;
default:
- return FALSE;
+ return false;
}
if (inst->opcode->op == OP_FCMLA_ELEM
{
/* Complex operand takes two elements. */
if (info->reglane.index & 1)
- return FALSE;
+ return false;
info->reglane.index /= 2;
}
}
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->reglist.first_regno = extract_field (self->fields[0], code, 0);
/* len */
info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
- return TRUE;
+ return true;
}
/* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
-bfd_boolean
+bool
aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
value = extract_field (FLD_opcode, code, 0);
/* PR 21595: Check for a bogus value. */
if (value >= ARRAY_SIZE (data))
- return FALSE;
+ return false;
if (expected_num != data[value].num_elements || data[value].is_reserved)
- return FALSE;
+ return false;
info->reglist.num_regs = data[value].num_regs;
- return TRUE;
+ return true;
}
/* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
lanes instructions. */
-bfd_boolean
+bool
aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
info->reglist.num_regs = 2;
- return TRUE;
+ return true;
}
/* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
load/store single element instructions. */
-bfd_boolean
+bool
aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
case 0x1:
if (QSsize & 0x1)
/* UND. */
- return FALSE;
+ return false;
info->qualifier = AARCH64_OPND_QLF_S_H;
/* Index encoded in "Q:S:size<1>". */
info->reglist.index = QSsize >> 1;
case 0x2:
if ((QSsize >> 1) & 0x1)
/* UND. */
- return FALSE;
+ return false;
if ((QSsize & 0x1) == 0)
{
info->qualifier = AARCH64_OPND_QLF_S_S;
{
if (extract_field (FLD_S, code, 0))
/* UND */
- return FALSE;
+ return false;
info->qualifier = AARCH64_OPND_QLF_S_D;
/* Index encoded in "Q". */
info->reglist.index = QSsize >> 3;
}
break;
default:
- return FALSE;
+ return false;
}
info->reglist.has_index = 1;
info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
- return TRUE;
+ return true;
}
/* Decode fields immh:immb and/or Q for e.g.
SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
or SSHR <V><d>, <V><n>, #<shift>. */
-bfd_boolean
+bool
aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
immh = extract_field (FLD_immh, code, 0);
if (immh == 0)
- return FALSE;
+ return false;
imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
pos = 4;
/* Get highest set bit in immh. */
1xxx (UInt(immh:immb)-64) */
info->imm.value = imm - (8 << pos);
- return TRUE;
+ return true;
}
/* Decode shift immediate for e.g. sshr (imm). */
-bfd_boolean
+bool
aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
case 0: imm = 8; break;
case 1: imm = 16; break;
case 2: imm = 32; break;
- default: return FALSE;
+ default: return false;
}
info->imm.value = imm;
- return TRUE;
+ return true;
}
/* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
value in the field(s) will be extracted as unsigned immediate value. */
-bfd_boolean
+bool
aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
imm <<= 12;
info->imm.value = imm;
- return TRUE;
+ return true;
}
/* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
-bfd_boolean
+bool
aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_ext_imm (self, info, code, inst, errors);
info->shifter.kind = AARCH64_MOD_LSL;
info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
- return TRUE;
+ return true;
}
/* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
-bfd_boolean
+bool
aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
const aarch64_insn code,
case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
- default: assert (0); return FALSE;
+ default: assert (0); return false;
}
/* 00: 0; 01: 8; 10:16; 11:24. */
info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
break;
default:
assert (0);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Decode an 8-bit floating-point immediate. */
-bfd_boolean
+bool
aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
info->imm.value = extract_all_fields (self, code);
info->imm.is_fp = 1;
- return TRUE;
+ return true;
}
/* Decode a 1-bit rotate immediate (#90 or #270). */
-bfd_boolean
+bool
aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
uint64_t rot = extract_field (self->fields[0], code, 0);
assert (rot < 2U);
info->imm.value = rot * 180 + 90;
- return TRUE;
+ return true;
}
/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
-bfd_boolean
+bool
aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
uint64_t rot = extract_field (self->fields[0], code, 0);
assert (rot < 4U);
info->imm.value = rot * 90;
- return TRUE;
+ return true;
}
/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
-bfd_boolean
+bool
aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
info->imm.value = 64- extract_field (FLD_scale, code, 0);
- return TRUE;
+ return true;
}
/* Decode arithmetic immediate for e.g.
SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
-bfd_boolean
+bool
aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* shift */
value = extract_field (FLD_shift, code, 0);
if (value >= 2)
- return FALSE;
+ return false;
info->shifter.amount = value ? 12 : 0;
/* imm12 (unsigned) */
info->imm.value = extract_field (FLD_imm12, code, 0);
- return TRUE;
+ return true;
}
/* Return true if VALUE is a valid logical immediate encoding, storing the
decoded value in *RESULT if so. ESIZE is the number of bytes in the
decoded immediate. */
-static bfd_boolean
+static bool
decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
{
uint64_t imm, mask;
case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
- default: return FALSE;
+ default: return false;
}
mask = (1ull << simd_size) - 1;
/* Top bits are IGNORED. */
}
if (simd_size > esize * 8)
- return FALSE;
+ return false;
/* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
if (S == simd_size - 1)
- return FALSE;
+ return false;
/* S+1 consecutive bits to 1. */
/* NOTE: S can't be 63 due to detection above. */
imm = (1ull << (S + 1)) - 1;
*result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
- return TRUE;
+ return true;
}
/* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
-bfd_boolean
+bool
aarch64_ext_limm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
}
/* Decode a logical immediate for the BIC alias of AND (etc.). */
-bfd_boolean
+bool
aarch64_ext_inv_limm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
aarch64_operand_error *errors)
{
if (!aarch64_ext_limm (self, info, code, inst, errors))
- return FALSE;
+ return false;
info->imm.value = ~info->imm.value;
- return TRUE;
+ return true;
}
/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
-bfd_boolean
+bool
aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
const aarch64_insn code, const aarch64_inst *inst,
case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
- default: return FALSE;
+ default: return false;
}
info->qualifier = qualifier;
}
/* opc1:size */
value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
if (value > 0x4)
- return FALSE;
+ return false;
info->qualifier = get_sreg_qualifier_from_value (value);
}
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
-bfd_boolean
+bool
aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
{
/* Rn */
info->addr.base_regno = extract_field (FLD_Rn, code, 0);
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
-bfd_boolean
+bool
aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst,
info->addr.writeback = 1;
info->addr.preind = 1;
}
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-bfd_boolean
+bool
aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst,
/* option */
value = extract_field (FLD_option, code, 0);
info->shifter.kind =
- aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
+ aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
/* Fix-up the shifter kind; although the table-driven approach is
efficient, it is slightly inflexible, thus needing this fix-up. */
if (info->shifter.kind == AARCH64_MOD_UXTX)
info->shifter.amount_present = 1;
}
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
-bfd_boolean
+bool
aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
info->addr.postind = 1;
}
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
-bfd_boolean
+bool
aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->addr.base_regno = extract_field (self->fields[0], code, 0);
/* uimm12 */
info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
-bfd_boolean
+bool
aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->addr.writeback = 1;
info->addr.preind = 1;
}
- return TRUE;
+ return true;
}
/* Decode the address operand for e.g.
LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
-bfd_boolean
+bool
aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst,
info->addr.offset.is_reg = 1;
info->addr.writeback = 1;
- return TRUE;
+ return true;
}
/* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
-bfd_boolean
+bool
aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* cond */
value = extract_field (FLD_cond, code, 0);
info->cond = get_cond_from_value (value);
- return TRUE;
+ return true;
}
/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
-bfd_boolean
+bool
aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
info->sysreg.flags = F_REG_WRITE;
}
- return TRUE;
+ return true;
}
/* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
-bfd_boolean
+bool
aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
- return TRUE;
+ return true;
/* Reserved value in <pstatefield>. */
- return FALSE;
+ return false;
}
/* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
-bfd_boolean
+bool
aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
aarch64_sys_regs_sr[]. */
value = value & ~(0x7);
break;
- default: assert (0); return FALSE;
+ default: assert (0); return false;
}
for (i = 0; sysins_ops[i].name != NULL; ++i)
info->sysins_op->name,
(unsigned)info->sysins_op->value,
aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
-bfd_boolean
+bool
aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
{
/* CRm */
info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
- return TRUE;
+ return true;
}
/* Decode the memory barrier option operand for DSB <option>nXS|#<imm>. */
-bfd_boolean
+bool
aarch64_ext_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
/* For the DSB nXS barrier variant immediate is encoded in 2-bit field. */
aarch64_insn field = extract_field (FLD_CRm_dsb_nxs, code, 0);
info->barrier = aarch64_barrier_dsb_nxs_options + field;
- return TRUE;
+ return true;
}
/* Decode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
-bfd_boolean
+bool
aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
/* prfop in Rt */
info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
- return TRUE;
+ return true;
}
/* Decode the hint number for an alias taking an operand. Set info->hint_option
to the matching name/value pair in aarch64_hint_options. */
-bfd_boolean
+bool
aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
{
info->hint_option = &(aarch64_hint_options[i]);
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Decode the extended register operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
-bfd_boolean
+bool
aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
/* option */
value = extract_field (FLD_option, code, 0);
info->shifter.kind =
- aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
+ aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
/* imm3 */
info->shifter.amount = extract_field (FLD_imm3, code, 0);
|| info->shifter.kind == AARCH64_MOD_SXTX))
info->qualifier = AARCH64_OPND_QLF_X;
- return TRUE;
+ return true;
}
/* Decode the shifted register operand for e.g.
SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
-bfd_boolean
+bool
aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
/* shift */
value = extract_field (FLD_shift, code, 0);
info->shifter.kind =
- aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
+ aarch64_get_operand_modifier_from_value (value, false /* extend_p */);
if (info->shifter.kind == AARCH64_MOD_ROR
&& inst->opcode->iclass != log_shift)
/* ROR is not available for the shifted register operand in arithmetic
instructions. */
- return FALSE;
+ return false;
/* imm6 */
info->shifter.amount = extract_field (FLD_imm6, code, 0);
/* This makes the constraint checking happy. */
info->shifter.operator_present = 1;
- return TRUE;
+ return true;
}
/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
where <offset> is given by the OFFSET parameter and where <factor> is
1 plus SELF's operand-dependent value. fields[0] specifies the field
that holds <base>. */
-static bfd_boolean
+static bool
aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
int64_t offset)
{
info->addr.base_regno = extract_field (self->fields[0], code, 0);
info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
- info->addr.offset.is_reg = FALSE;
- info->addr.writeback = FALSE;
- info->addr.preind = TRUE;
+ info->addr.offset.is_reg = false;
+ info->addr.writeback = false;
+ info->addr.preind = true;
if (offset != 0)
info->shifter.kind = AARCH64_MOD_MUL_VL;
info->shifter.amount = 1;
info->shifter.operator_present = (info->addr.offset.imm != 0);
- info->shifter.amount_present = FALSE;
- return TRUE;
+ info->shifter.amount_present = false;
+ return true;
}
/* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
where <simm4> is a 4-bit signed value and where <factor> is 1 plus
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm4> is encoded in the SVE_imm4 field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
where <simm6> is a 6-bit signed value and where <factor> is 1 plus
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm6> is encoded in the SVE_imm6 field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
SELF's operand-dependent value. fields[0] specifies the field that
holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
and imm3 fields, with imm3 being the less-significant part. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
aarch64_opnd_info *info,
aarch64_insn code,
/* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
is given by the OFFSET parameter and where <shift> is SELF's operand-
dependent value. fields[0] specifies the base register field <base>. */
-static bfd_boolean
+static bool
aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
int64_t offset)
{
info->addr.base_regno = extract_field (self->fields[0], code, 0);
info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
- info->addr.offset.is_reg = FALSE;
- info->addr.writeback = FALSE;
- info->addr.preind = TRUE;
- info->shifter.operator_present = FALSE;
- info->shifter.amount_present = FALSE;
- return TRUE;
+ info->addr.offset.is_reg = false;
+ info->addr.writeback = false;
+ info->addr.preind = true;
+ info->shifter.operator_present = false;
+ info->shifter.amount_present = false;
+ return true;
}
/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
is a 4-bit signed number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
is SELF's operand-dependent value. fields[0] specifies the base
register field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
index_regno = extract_field (self->fields[1], code, 0);
if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
- return FALSE;
+ return false;
info->addr.base_regno = extract_field (self->fields[0], code, 0);
info->addr.offset.regno = index_regno;
- info->addr.offset.is_reg = TRUE;
- info->addr.writeback = FALSE;
- info->addr.preind = TRUE;
+ info->addr.offset.is_reg = true;
+ info->addr.writeback = false;
+ info->addr.preind = true;
info->shifter.kind = AARCH64_MOD_LSL;
info->shifter.amount = get_operand_specific_data (self);
info->shifter.operator_present = (info->shifter.amount != 0);
info->shifter.amount_present = (info->shifter.amount != 0);
- return TRUE;
+ return true;
}
/* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
<shift> is SELF's operand-dependent value. fields[0] specifies the
base register field, fields[1] specifies the offset register field and
fields[2] is a single-bit field that selects SXTW over UXTW. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
info->addr.base_regno = extract_field (self->fields[0], code, 0);
info->addr.offset.regno = extract_field (self->fields[1], code, 0);
- info->addr.offset.is_reg = TRUE;
- info->addr.writeback = FALSE;
- info->addr.preind = TRUE;
+ info->addr.offset.is_reg = true;
+ info->addr.writeback = false;
+ info->addr.preind = true;
if (extract_field (self->fields[2], code, 0))
info->shifter.kind = AARCH64_MOD_SXTW;
else
info->shifter.kind = AARCH64_MOD_UXTW;
info->shifter.amount = get_operand_specific_data (self);
- info->shifter.operator_present = TRUE;
+ info->shifter.operator_present = true;
info->shifter.amount_present = (info->shifter.amount != 0);
- return TRUE;
+ return true;
}
/* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
5-bit unsigned number and where <shift> is SELF's operand-dependent value.
fields[0] specifies the base register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
number. fields[0] specifies the base register field and fields[1]
specifies the offset register field. */
-static bfd_boolean
+static bool
aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
aarch64_insn code, enum aarch64_modifier_kind kind)
{
info->addr.base_regno = extract_field (self->fields[0], code, 0);
info->addr.offset.regno = extract_field (self->fields[1], code, 0);
- info->addr.offset.is_reg = TRUE;
- info->addr.writeback = FALSE;
- info->addr.preind = TRUE;
+ info->addr.offset.is_reg = true;
+ info->addr.writeback = false;
+ info->addr.preind = true;
info->shifter.kind = kind;
info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
info->shifter.operator_present = (kind != AARCH64_MOD_LSL
|| info->shifter.amount != 0);
info->shifter.amount_present = (info->shifter.amount != 0);
- return TRUE;
+ return true;
}
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
field and fields[1] specifies the offset register field. */
-bfd_boolean
+bool
aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
/* Finish decoding an SVE arithmetic immediate, given that INFO already
has the raw field value and that the low 8 bits decode to VALUE. */
-static bfd_boolean
+static bool
decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
{
info->shifter.kind = AARCH64_MOD_LSL;
info->shifter.operator_present = (info->shifter.amount != 0);
info->shifter.amount_present = (info->shifter.amount != 0);
info->imm.value = value;
- return TRUE;
+ return true;
}
/* Decode an SVE ADD/SUB immediate. */
-bfd_boolean
+bool
aarch64_ext_sve_aimm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
}
/* Decode an SVE CPY/DUP immediate. */
-bfd_boolean
+bool
aarch64_ext_sve_asimm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
/* Decode a single-bit immediate that selects between #0.5 and #1.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ext_sve_float_half_one (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->imm.value = 0x3f800000;
else
info->imm.value = 0x3f000000;
- info->imm.is_fp = TRUE;
- return TRUE;
+ info->imm.is_fp = true;
+ return true;
}
/* Decode a single-bit immediate that selects between #0.5 and #2.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ext_sve_float_half_two (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->imm.value = 0x40000000;
else
info->imm.value = 0x3f000000;
- info->imm.is_fp = TRUE;
- return TRUE;
+ info->imm.is_fp = true;
+ return true;
}
/* Decode a single-bit immediate that selects between #0.0 and #1.0.
The fields array specifies which field to use. */
-bfd_boolean
+bool
aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
info->imm.value = 0x3f800000;
else
info->imm.value = 0x0;
- info->imm.is_fp = TRUE;
- return TRUE;
+ info->imm.is_fp = true;
+ return true;
}
/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
array specifies which field to use for Zn. MM is encoded in the
concatenation of imm5 and SVE_tszh, with imm5 being the less
significant part. */
-bfd_boolean
+bool
aarch64_ext_sve_index (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
while ((val & 1) == 0)
val /= 2;
info->reglane.index = val / 2;
- return TRUE;
+ return true;
}
/* Decode a logical immediate for the MOV alias of SVE DUPM. */
-bfd_boolean
+bool
aarch64_ext_sve_limm_mov (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst,
/* Decode Zn[MM], where Zn occupies the least-significant part of the field
and where MM occupies the most-significant part. The operand-dependent
value specifies the number of bits in Zn. */
-bfd_boolean
+bool
aarch64_ext_sve_quad_index (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
unsigned int val = extract_all_fields (self, code);
info->reglane.regno = val & ((1 << reg_bits) - 1);
info->reglane.index = val >> reg_bits;
- return TRUE;
+ return true;
}
/* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
to use for Zn. The opcode-dependent value specifies the number
of registers in the list. */
-bfd_boolean
+bool
aarch64_ext_sve_reglist (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
{
info->reglist.first_regno = extract_field (self->fields[0], code, 0);
info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
- return TRUE;
+ return true;
}
/* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
field. */
-bfd_boolean
+bool
aarch64_ext_sve_scale (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst, aarch64_operand_error *errors)
int val;
if (!aarch64_ext_imm (self, info, code, inst, errors))
- return FALSE;
+ return false;
val = extract_field (FLD_SVE_imm4, code, 0);
info->shifter.kind = AARCH64_MOD_MUL;
info->shifter.amount = val + 1;
info->shifter.operator_present = (val != 0);
info->shifter.amount_present = (val != 0);
- return TRUE;
+ return true;
}
/* Return the top set bit in VALUE, which is expected to be relatively
}
/* Decode an SVE shift-left immediate. */
-bfd_boolean
+bool
aarch64_ext_sve_shlimm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst, aarch64_operand_error *errors)
{
if (!aarch64_ext_imm (self, info, code, inst, errors)
|| info->imm.value == 0)
- return FALSE;
+ return false;
info->imm.value -= get_top_bit (info->imm.value);
- return TRUE;
+ return true;
}
/* Decode an SVE shift-right immediate. */
-bfd_boolean
+bool
aarch64_ext_sve_shrimm (const aarch64_operand *self,
aarch64_opnd_info *info, const aarch64_insn code,
const aarch64_inst *inst, aarch64_operand_error *errors)
{
if (!aarch64_ext_imm (self, info, code, inst, errors)
|| info->imm.value == 0)
- return FALSE;
+ return false;
info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
- return TRUE;
+ return true;
}
\f
/* Bitfields that are commonly used to encode certain operands' information
}
}
-static bfd_boolean
+static bool
aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
aarch64_inst *, int, aarch64_operand_error *errors);
and fill in the operand qualifiers accordingly. Return true if no
problems are found. */
-static bfd_boolean
+static bool
aarch64_decode_variant_using_iclass (aarch64_inst *inst)
{
int i, variant;
case sve_index:
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
if ((i & 31) == 0)
- return FALSE;
+ return false;
while ((i & 1) == 0)
{
i >>= 1;
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
sve_shift:
if (i == 0)
- return FALSE;
+ return false;
while (i != 1)
{
i >>= 1;
case sve_size_bhs:
variant = extract_field (FLD_size, inst->value, 0);
if (variant >= 3)
- return FALSE;
+ return false;
break;
case sve_size_bhsd:
case sve_size_hsd:
i = extract_field (FLD_size, inst->value, 0);
if (i < 1)
- return FALSE;
+ return false;
variant = i - 1;
break;
case sve_size_hsd2:
i = extract_field (FLD_SVE_size, inst->value, 0);
if (i < 1)
- return FALSE;
+ return false;
variant = i - 1;
break;
case sve_shift_tsz_bhsd:
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
if (i == 0)
- return FALSE;
+ return false;
while (i != 1)
{
i >>= 1;
case sve_size_tsz_bhs:
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
if (i == 0)
- return FALSE;
+ return false;
while (i != 1)
{
if (i & 1)
- return FALSE;
+ return false;
i >>= 1;
variant += 1;
}
case sve_shift_tsz_hsd:
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
if (i == 0)
- return FALSE;
+ return false;
while (i != 1)
{
i >>= 1;
default:
/* No mapping between instruction class and qualifiers. */
- return TRUE;
+ return true;
}
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
- return TRUE;
+ return true;
}
/* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
fails, which meanes that CODE is not an instruction of OPCODE; otherwise
determined and used to disassemble CODE; this is done just before the
return. */
-static bfd_boolean
+static bool
aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
aarch64_inst *inst, int noaliases_p,
aarch64_operand_error *errors)
/* If the opcode has a verifier, then check it now. */
if (opcode->verifier
- && opcode->verifier (inst, code, 0, FALSE, errors, NULL) != ERR_OK)
+ && opcode->verifier (inst, code, 0, false, errors, NULL) != ERR_OK)
{
DEBUG_TRACE ("operand verifier FAIL");
goto decode_fail;
if (!noaliases_p)
determine_disassembling_preference (inst, errors);
DEBUG_TRACE ("SUCCESS");
- return TRUE;
+ return true;
}
else
{
}
decode_fail:
- return FALSE;
+ return false;
}
\f
/* This does some user-friendly fix-up to *INST. It is currently focus on
enum err_type
aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
- bfd_boolean noaliases_p,
+ bool noaliases_p,
aarch64_operand_error *errors)
{
const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
static void
print_operands (bfd_vma pc, const aarch64_opcode *opcode,
const aarch64_opnd_info *opnds, struct disassemble_info *info,
- bfd_boolean *has_notes)
+ bool *has_notes)
{
char *notes = NULL;
int i, pcrel_p, num_printed;
if (notes && !no_notes)
{
- *has_notes = TRUE;
+ *has_notes = true;
(*info->fprintf_func) (info->stream, " // note: %s", notes);
}
}
struct disassemble_info *info,
aarch64_operand_error *mismatch_details)
{
- bfd_boolean has_notes = FALSE;
+ bool has_notes = false;
print_mnemonic_name (inst, info);
print_operands (pc, inst->opcode, inst->operands, info, &has_notes);
/* Always run constraint verifiers, this is needed because constraints need to
maintain a global state regardless of whether the instruction has the flag
set or not. */
- enum err_type result = verify_constraints (inst, code, pc, FALSE,
+ enum err_type result = verify_constraints (inst, code, pc, false,
mismatch_details, &insn_sequence);
switch (result)
{
/* Disallow mapping symbols ($x, $d etc) from
being displayed in symbol relative addresses. */
-bfd_boolean
+bool
aarch64_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
if (n >= info->symtab_size)
- return FALSE;
+ return false;
as = info->symtab[n];
if (bfd_asymbol_flavour (as) != bfd_target_elf_flavour)
- return FALSE;
+ return false;
es = (elf_symbol_type *) as;
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
if (type == STT_FUNC)
{
*map_type = MAP_INSN;
- return TRUE;
+ return true;
}
/* Check for mapping symbols. */
&& (name[2] == '\0' || name[2] == '.'))
{
*map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Set the feature bits in arch_variant in order to get the correct disassembly
int status;
void (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
aarch64_operand_error *);
- bfd_boolean found = FALSE;
+ bool found = false;
unsigned int size = 4;
unsigned long data;
aarch64_operand_error errors;
- static bfd_boolean set_features;
+ static bool set_features;
if (info->disassembler_options)
{
if (!set_features)
{
select_aarch64_variant (info->mach);
- set_features = TRUE;
+ set_features = true;
}
/* Aarch64 instructions are always little-endian */
{
int last_sym = -1;
bfd_vma addr, section_vma = 0;
- bfd_boolean can_use_search_opt_p;
+ bool can_use_search_opt_p;
int n;
if (pc <= last_mapping_addr)
if (get_sym_code_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
}
}
if (get_sym_code_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
break;
}
}
/* Switch-table-based high-level operand extractor. */
-bfd_boolean
+bool
aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
const aarch64_insn, const aarch64_inst *,
aarch64_operand_error *);
/* Operand extractors. */
#define AARCH64_DECL_OPD_EXTRACTOR(x) \
- bfd_boolean aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
- const aarch64_insn, const aarch64_inst *, \
- aarch64_operand_error *)
+ bool aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
+ const aarch64_insn, const aarch64_inst *, \
+ aarch64_operand_error *)
AARCH64_DECL_OPD_EXTRACTOR (ext_none);
AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
printf ("Enter print_operand_inserter\n");
printf ("\n");
- printf ("bfd_boolean\n");
+ printf ("bool\n");
printf ("aarch64_insert_operand (const aarch64_operand *self,\n\
const aarch64_opnd_info *info,\n\
aarch64_insn *code, const aarch64_inst *inst,\n\
printf ("Enter print_operand_extractor\n");
printf ("\n");
- printf ("bfd_boolean\n");
+ printf ("bool\n");
printf ("aarch64_extract_operand (const aarch64_operand *self,\n\
aarch64_opnd_info *info,\n\
aarch64_insn code, const aarch64_inst *inst,\n\
#include "aarch64-opc.h"
#ifdef DEBUG_AARCH64
-int debug_dump = FALSE;
+int debug_dump = false;
#endif /* DEBUG_AARCH64 */
/* The enumeration strings associated with each value of a 5-bit SVE
/* Helper functions to determine which operand to be used to encode/decode
the size:Q fields for AdvSIMD instructions. */
-static inline bfd_boolean
+static inline bool
vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
{
return (qualifier >= AARCH64_OPND_QLF_V_8B
&& qualifier <= AARCH64_OPND_QLF_V_1Q);
}
-static inline bfd_boolean
+static inline bool
fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
{
return (qualifier >= AARCH64_OPND_QLF_S_B
enum aarch64_modifier_kind
aarch64_get_operand_modifier_from_value (aarch64_insn value,
- bfd_boolean extend_p)
+ bool extend_p)
{
if (extend_p)
return AARCH64_MOD_UXTB + value;
return AARCH64_MOD_LSL - value;
}
-bfd_boolean
+bool
aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
{
return kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX;
}
-static inline bfd_boolean
+static inline bool
aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
{
return kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL;
{0, 0, 0, "retrieving", 0},
};
-static inline bfd_boolean
+static inline bool
operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
{
return aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT;
}
-static inline bfd_boolean
+static inline bool
qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
{
return aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE;
/* This function checks if the given instruction INSN is a destructive
instruction based on the usage of the registers. It does not recognize
unary destructive instructions. */
-bfd_boolean
+bool
aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
{
int i = 0;
const enum aarch64_opnd *opnds = opcode->operands;
if (opnds[0] == AARCH64_OPND_NIL)
- return FALSE;
+ return false;
while (opnds[++i] != AARCH64_OPND_NIL)
if (opnds[i] == opnds[0])
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* TODO improve this, we can have an extra field at the runtime to
succeeds. */
static int
-match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
+match_operands_qualifier (aarch64_inst *inst, bool update_p)
{
int i, nops;
aarch64_opnd_qualifier_seq_t qualifiers;
nops = aarch64_num_of_operands (inst->opcode);
for (i = 0; i < nops; ++i)
if (inst->operands[i].qualifier != qualifiers[i])
- return FALSE;
+ return false;
}
/* Update the qualifiers. */
If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
amount will be returned in *SHIFT_AMOUNT. */
-bfd_boolean
+bool
aarch64_wide_constant_p (uint64_t value, int is32, unsigned int *shift_amount)
{
int amount;
permitted. */
if (value >> 32 != 0 && value >> 32 != 0xffffffff)
/* Immediate out of range. */
- return FALSE;
+ return false;
value &= 0xffffffff;
}
if (amount == -1)
{
- DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
- return FALSE;
+ DEBUG_TRACE ("exit false with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
+ return false;
}
if (shift_amount != NULL)
*shift_amount = amount;
- DEBUG_TRACE ("exit TRUE with amount %d", amount);
+ DEBUG_TRACE ("exit true with amount %d", amount);
- return TRUE;
+ return true;
}
/* Build the accepted values for immediate logical SIMD instructions.
If ENCODING is not NULL, on the return of TRUE, the standard encoding for
VALUE will be returned in *ENCODING. */
-bfd_boolean
+bool
aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
{
simd_imm_encoding imm_enc;
const simd_imm_encoding *imm_encoding;
- static bfd_boolean initialized = FALSE;
+ static bool initialized = false;
uint64_t upper;
int i;
if (!initialized)
{
build_immediate_table ();
- initialized = TRUE;
+ initialized = true;
}
/* Allow all zeros or all ones in top bits, so that
constant expressions like ~1 are permitted. */
upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
if ((value & ~upper) != value && (value | upper) != value)
- return FALSE;
+ return false;
/* Replicate to a full 64-bit value. */
value &= ~upper;
sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
if (imm_encoding == NULL)
{
- DEBUG_TRACE ("exit with FALSE");
- return FALSE;
+ DEBUG_TRACE ("exit with false");
+ return false;
}
if (encoding != NULL)
*encoding = imm_encoding->encoding;
- DEBUG_TRACE ("exit with TRUE");
- return TRUE;
+ DEBUG_TRACE ("exit with true");
+ return true;
}
/* If 64-bit immediate IMM is in the format of
constraint checking will carried out by operand_general_constraint_met_p,
which has be to called after this in order to get all of the operands'
qualifiers established. */
- if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
+ if (match_operands_qualifier (inst, true /* update_p */) == 0)
{
DEBUG_TRACE ("FAIL on operand qualifier matching");
if (mismatch_detail)
const char *base, const char *offset)
{
char tb[16]; /* Temporary buffer. */
- bfd_boolean print_extend_p = TRUE;
- bfd_boolean print_amount_p = TRUE;
+ bool print_extend_p = true;
+ bool print_amount_p = true;
const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
{
/* Not print the shift/extend amount when the amount is zero and
when it is not the special case of 8-bit load/store instruction. */
- print_amount_p = FALSE;
+ print_amount_p = false;
/* Likewise, no need to print the shift operator LSL in such a
situation. */
if (opnd->shifter.kind == AARCH64_MOD_LSL)
- print_extend_p = FALSE;
+ print_extend_p = false;
}
/* Prepare for the extend/shift. */
{
const aarch64_sys_reg *sr = aarch64_sys_regs + i;
- bfd_boolean exact_match
+ bool exact_match
= (!(sr->flags & (F_REG_READ | F_REG_WRITE))
|| (sr->flags & opnd->sysreg.flags) == opnd->sysreg.flags)
&& AARCH64_CPU_HAS_FEATURE (features, sr->features);
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};
-bfd_boolean
+bool
aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
{
return (reg_flags & F_DEPRECATED) != 0;
{ 0, CPENC (0,0,0,0,0), 0, 0 },
};
-bfd_boolean
+bool
aarch64_pstatefield_supported_p (const aarch64_feature_set features,
const aarch64_sys_reg *reg)
{
if (!(reg->flags & F_ARCHEXT))
- return TRUE;
+ return true;
return AARCH64_CPU_HAS_ALL_FEATURES (features, reg->features);
}
{ 0, CPENS(0,0,0,0), 0 }
};
-bfd_boolean
+bool
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
{
return (sys_ins_reg->flags & F_HASXT) != 0;
}
-extern bfd_boolean
+extern bool
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
const char *reg_name,
aarch64_insn reg_value,
{
const char *suffix = strrchr (reg_name, '_');
if (suffix && !strcmp (suffix, "_el3"))
- return FALSE;
+ return false;
}
if (!(reg_flags & F_ARCHEXT))
- return TRUE;
+ return true;
if (reg_features
&& AARCH64_CPU_HAS_ALL_FEATURES (features, reg_features))
- return TRUE;
+ return true;
/* ARMv8.4 TLB instructions. */
if ((reg_value == CPENS (0, C8, C1, 0)
|| reg_value == CPENS (6, C8, C5, 1)
|| reg_value == CPENS (6, C8, C5, 5))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
- return TRUE;
+ return true;
/* DC CVAP. Values are from aarch64_sys_regs_dc. */
if (reg_value == CPENS (3, C7, C12, 1)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
- return TRUE;
+ return true;
/* DC CVADP. Values are from aarch64_sys_regs_dc. */
if (reg_value == CPENS (3, C7, C13, 1)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
- return TRUE;
+ return true;
/* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
if ((reg_value == CPENS (0, C7, C6, 3)
|| reg_value == CPENS (3, C7, C14, 5)
|| reg_value == CPENS (3, C7, C4, 4))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
- return TRUE;
+ return true;
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
if ((reg_value == CPENS (0, C7, C9, 0)
|| reg_value == CPENS (0, C7, C9, 1))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
- return TRUE;
+ return true;
/* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
if (reg_value == CPENS (3, C7, C3, 0)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
#undef C0
static enum err_type
verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
- bfd_boolean encoding ATTRIBUTE_UNUSED,
+ bool encoding ATTRIBUTE_UNUSED,
aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
{
static enum err_type
verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
- bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
+ bfd_vma pc ATTRIBUTE_UNUSED, bool encoding,
aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
{
verify_constraints (const struct aarch64_inst *inst,
const aarch64_insn insn ATTRIBUTE_UNUSED,
bfd_vma pc,
- bfd_boolean encoding,
+ bool encoding,
aarch64_operand_error *mismatch_detail,
aarch64_instr_sequence *insn_sequence)
{
mismatch_detail->error = _("instruction opens new dependency "
"sequence without ending previous one");
mismatch_detail->index = -1;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
}
mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
mismatch_detail->error = _("previous `movprfx' sequence not closed");
mismatch_detail->index = -1;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
/* Reset the sequence. */
init_insn_sequence (NULL, insn_sequence);
mismatch_detail->error = _("SVE instruction expected after "
"`movprfx'");
mismatch_detail->index = -1;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
mismatch_detail->error = _("SVE `movprfx' compatible instruction "
"expected");
mismatch_detail->index = -1;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
aarch64_opnd_info blk_pred, inst_pred;
memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
- bfd_boolean predicated = FALSE;
+ bool predicated = false;
assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
/* Determine if the movprfx instruction used is predicated or not. */
if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
{
- predicated = TRUE;
+ predicated = true;
blk_pred = insn_sequence->instr->operands[1];
}
mismatch_detail->error = _("predicated instruction expected "
"after `movprfx'");
mismatch_detail->index = -1;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
mismatch_detail->error = _("merging predicate expected due "
"to preceding `movprfx'");
mismatch_detail->index = inst_pred_idx;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
"from that in preceding "
"`movprfx'");
mismatch_detail->index = inst_pred_idx;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
"`movprfx' not used in current "
"instruction");
mismatch_detail->index = 0;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
mismatch_detail->error = _("output register of preceding "
"`movprfx' expected as output");
mismatch_detail->index = 0;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
mismatch_detail->error = _("output register of preceding "
"`movprfx' used as input");
mismatch_detail->index = last_op_usage;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
mismatch_detail->error = _("register size not compatible with "
"previous `movprfx'");
mismatch_detail->index = 0;
- mismatch_detail->non_fatal = TRUE;
+ mismatch_detail->non_fatal = true;
res = ERR_VFI;
goto done;
}
(with any element size, not just ESIZE) and if using DUPM would
therefore be OK. ESIZE is the number of bytes in the immediate. */
-bfd_boolean
+bool
aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
{
int64_t svalue = uvalue;
uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
- return FALSE;
+ return false;
if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
{
svalue = (int32_t) uvalue;
{
svalue = (int16_t) uvalue;
if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
- return FALSE;
+ return false;
}
}
if ((svalue & 0xff) == 0)
enum err_type
verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
- bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
+ bool, aarch64_operand_error *, aarch64_instr_sequence*);
/* Operand flags. */
#define HINT_FLAG(val) (val >> 8)
#define HINT_VAL(val) (val & 0xff)
-static inline bfd_boolean
+static inline bool
operand_has_inserter (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_HAS_INSERTER) != 0;
}
-static inline bfd_boolean
+static inline bool
operand_has_extractor (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
}
-static inline bfd_boolean
+static inline bool
operand_need_sign_extension (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_SEXT) != 0;
}
-static inline bfd_boolean
+static inline bool
operand_need_shift_by_two (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
}
-static inline bfd_boolean
+static inline bool
operand_need_shift_by_four (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
}
-static inline bfd_boolean
+static inline bool
operand_maybe_stack_pointer (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_MAYBE_SP) != 0;
aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
enum aarch64_modifier_kind
-aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
+aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
-bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);
-bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
+bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
+bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
int aarch64_shrink_expanded_imm8 (uint64_t);
/* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
unsigned insn_len;
/* TRUE if we have limm. */
- bfd_boolean limm_p;
+ bool limm_p;
/* LIMM value, if exists. */
unsigned limm;
static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
/* True if we want to print using only hex numbers. */
-static bfd_boolean print_hex = FALSE;
+static bool print_hex = false;
/* Macros section. */
/* Functions implementation. */
/* Initialize private data. */
-static bfd_boolean
+static bool
init_arc_disasm_info (struct disassemble_info *info)
{
struct arc_disassemble_info *arc_infop
= calloc (sizeof (*arc_infop), 1);
if (arc_infop == NULL)
- return FALSE;
+ return false;
info->private_data = arc_infop;
- return TRUE;
+ return true;
}
/* Add a new element to the decode list. */
/* Return TRUE if we need to skip the opcode from being
disassembled. */
-static bfd_boolean
+static bool
skip_this_opcode (const struct arc_opcode *opcode)
{
linkclass t = decodelist;
&& (OPCODE_32BIT_INSN (opcode->opcode) != 0x06
/* Can be an APEX extensions. */
&& OPCODE_32BIT_INSN (opcode->opcode) != 0x07))
- return FALSE;
+ return false;
/* or not a known truble class. */
switch (opcode->insn_class)
case MPY:
break;
default:
- return FALSE;
+ return false;
}
while (t != NULL)
{
if ((t->insn_class == opcode->insn_class)
&& (t->subclass == opcode->subclass))
- return FALSE;
+ return false;
t = t->nxt;
}
- return TRUE;
+ return true;
}
static bfd_vma
return value;
}
-static bfd_boolean
+static bool
special_flag_p (const char *opname,
const char *flgname)
{
break; /* End of the array. */
if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Find opcode from ARC_TABLE given the instruction described by INSN and
unsigned long long insn,
unsigned int insn_len,
unsigned isa_mask,
- bfd_boolean *has_limm,
- bfd_boolean overlaps)
+ bool *has_limm,
+ bool overlaps)
{
unsigned int i = 0;
const struct arc_opcode *opcode = NULL;
const struct arc_opcode *t_op = NULL;
const unsigned char *opidx;
const unsigned char *flgidx;
- bfd_boolean warn_p = FALSE;
+ bool warn_p = false;
do
{
- bfd_boolean invalid = FALSE;
+ bool invalid = false;
opcode = &arc_table[i++];
if ((insn & opcode->mask) != opcode->opcode)
continue;
- *has_limm = FALSE;
+ *has_limm = false;
/* Possible candidate, check the operands. */
for (opidx = opcode->operands; *opidx; opidx++)
if ((value == 0x3E && insn_len == 4)
|| (value == limmind && insn_len == 2))
{
- invalid = TRUE;
+ invalid = true;
break;
}
}
if (operand->flags & ARC_OPERAND_LIMM
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
- *has_limm = TRUE;
+ *has_limm = true;
}
/* Check the flags. */
if (!foundA && foundB)
{
- invalid = TRUE;
+ invalid = true;
break;
}
}
if (insn_len == 4
&& overlaps)
{
- warn_p = TRUE;
+ warn_p = true;
t_op = opcode;
if (skip_this_opcode (opcode))
continue;
that calls to OPERAND_ITERATOR_NEXT will iterate over the opcode's
operands. */
-static bfd_boolean
+static bool
find_format (bfd_vma memaddr,
unsigned long long insn,
unsigned int * insn_len,
struct arc_operand_iterator * iter)
{
const struct arc_opcode *opcode = NULL;
- bfd_boolean needs_limm = FALSE;
+ bool needs_limm = false;
const extInstruction_t *einsn, *i;
unsigned limm = 0;
struct arc_disassemble_info *arc_infop = info->private_data;
_("An error occurred while generating the "
"extension instruction operations"));
*opcode_result = NULL;
- return FALSE;
+ return false;
}
opcode = find_format_from_table (info, opcode, insn, *insn_len,
- isa_mask, &needs_limm, FALSE);
+ isa_mask, &needs_limm, false);
}
}
/* Then, try finding the first match in the opcode table. */
if (opcode == NULL)
opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
- isa_mask, &needs_limm, TRUE);
+ isa_mask, &needs_limm, true);
if (opcode != NULL && needs_limm)
{
arc_infop->limm = limm;
arc_infop->limm_p = needs_limm;
- return TRUE;
+ return true;
}
static void
else
{
if (operand->extract)
- value = (*operand->extract) (insn, (bfd_boolean *) NULL);
+ value = (*operand->extract) (insn, (bool *) NULL);
else
{
if (operand->flags & ARC_OPERAND_ALIGNED32)
into VALUE. If there is no operand returned then OPERAND and VALUE are
unchanged. */
-static bfd_boolean
+static bool
operand_iterator_next (struct arc_operand_iterator *iter,
const struct arc_operand **operand,
int *value)
if (*iter->opidx == 0)
{
*operand = NULL;
- return FALSE;
+ return false;
}
*operand = &arc_operands[*iter->opidx];
*value = extract_operand_value (*operand, iter->insn, iter->limm);
iter->opidx++;
- return TRUE;
+ return true;
}
/* Helper for parsing the options. */
add_to_decodelist (FLOAT, CVT);
}
else if (startswith (option, "hex"))
- print_hex = TRUE;
+ print_hex = true;
else
/* xgettext:c-format */
opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
unsigned long long insn = 0;
unsigned isa_mask = ARC_OPCODE_NONE;
const struct arc_opcode *opcode;
- bfd_boolean need_comma;
- bfd_boolean open_braket;
+ bool need_comma;
+ bool open_braket;
int size;
const struct arc_operand *operand;
int value, vpcl;
struct arc_operand_iterator iter;
struct arc_disassemble_info *arc_infop;
- bfd_boolean rpcl = FALSE, rset = FALSE;
+ bool rpcl = false, rset = false;
if (info->disassembler_options)
{
info->target2 = 0;
/* FIXME to be moved in dissasemble_init_for_target. */
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
/* Find the first match in the opcode table. */
if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
if (opcode->operands[0] != 0)
(*info->fprintf_func) (info->stream, "\t");
- need_comma = FALSE;
- open_braket = FALSE;
+ need_comma = false;
+ open_braket = false;
arc_infop->operands_count = 0;
/* Now extract and print the operands. */
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
{
(*info->fprintf_func) (info->stream, "]");
- open_braket = FALSE;
+ open_braket = false;
continue;
}
if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
{
(*info->fprintf_func) (info->stream, "[");
- open_braket = TRUE;
- need_comma = FALSE;
+ open_braket = true;
+ need_comma = false;
continue;
}
- need_comma = TRUE;
+ need_comma = true;
if (operand->flags & ARC_OPERAND_PCREL)
{
- rpcl = TRUE;
+ rpcl = true;
vpcl = value;
- rset = TRUE;
+ rset = true;
info->target = (bfd_vma) (memaddr & ~3) + value;
}
else if (!(operand->flags & ARC_OPERAND_IR))
{
vpcl = value;
- rset = TRUE;
+ rset = true;
}
/* Print the operand as directed by the flags. */
(*info->fprintf_func) (info->stream, "%s", rname);
}
if (value == 63)
- rpcl = TRUE;
+ rpcl = true;
else
- rpcl = FALSE;
+ rpcl = false;
}
else if (operand->flags & ARC_OPERAND_LIMM)
{
const char *addrtype = get_addrtype (value);
(*info->fprintf_func) (info->stream, "%s", addrtype);
/* A colon follow an address type. */
- need_comma = FALSE;
+ need_comma = false;
}
else
{
switch (value)
{
case 0:
- need_comma = FALSE;
+ need_comma = false;
break;
case 1:
(*info->fprintf_func) (info->stream, "r13");
regnames[13 + value - 1]);
break;
}
- rpcl = FALSE;
- rset = FALSE;
+ rpcl = false;
+ rset = false;
}
else
{
/* There was an error when disassembling, for example memory read error. */
if (disasm_func (addr, info) < 0)
{
- insn->valid = FALSE;
+ insn->valid = false;
return;
}
/* Quick exit if memory at this address is not an instruction. */
if (info->insn_type == dis_noninsn)
{
- insn->valid = FALSE;
+ insn->valid = false;
return;
}
- insn->valid = TRUE;
+ insn->valid = true;
opcode = (const struct arc_opcode *) arc_infop->opcode;
insn->insn_class = opcode->insn_class;
bfd_vma address;
/* Whether this is a valid instruction. */
- bfd_boolean valid;
+ bool valid;
insn_class_t insn_class;
insn = 00100bbb00101111FBBB111110001001. */
static unsigned long long
insert_limm (unsigned long long insn ATTRIBUTE_UNUSED,
- long long int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
return insn;
#define EXTRACT_LIMM
/* mask = 00000000000000000000000000000000. */
static ATTRIBUTE_UNUSED int
-extract_limm (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_limm (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000111111000000. */
static long long int
extract_uimm6_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000111111222222. */
static long long int
extract_simm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000011100000000. */
static ATTRIBUTE_UNUSED int
extract_simm3_5_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
#define EXTRACT_LIMM_S
/* mask = 0000000000000000. */
static ATTRIBUTE_UNUSED int
-extract_limm_s (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_limm_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000000011111. */
static long long int
extract_uimm7_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000001111111. */
static long long int
extract_uimm7_9_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000000000111. */
static long long int
extract_uimm3_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000111111111. */
static long long int
extract_simm11_a32_7_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000002220111. */
static long long int
extract_uimm6_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000000011111. */
static long long int
extract_uimm5_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000111111102000000000000000. */
static long long int
extract_simm9_a16_8 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 00000000000000000000111111000000. */
static long long int
extract_uimm6_8 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000111111111102222222222000000. */
static long long int
extract_simm21_a16_5 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 00000111111111102222222222003333. */
static long long int
extract_simm25_a16_5 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000111111111. */
static long long int
extract_simm10_a16_7_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000000111111. */
static long long int
extract_simm7_a16_10_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 00000111111111002222222222000000. */
static long long int
extract_simm21_a32_5 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 00000111111111002222222222003333. */
static long long int
extract_simm25_a32_5 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000011111111111. */
static long long int
extract_simm13_a32_5_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000001111111. */
static long long int
extract_simm8_a16_9_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 00000000000000000000000111000000. */
static long long int
extract_uimm3_23 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000001111111111. */
static long long int
extract_uimm10_6_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000002200011110. */
static long long int
extract_uimm6_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000111111112000000000000000. */
static long long int
extract_simm9_8 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000011111111. */
static long long int
extract_uimm10_a32_8_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000000111111111. */
static long long int
extract_simm9_7_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000000011111. */
static long long int
extract_uimm6_a16_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000020000011000. */
static long long int
extract_uimm5_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000022222200111. */
static long long int
extract_simm11_a32_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000022220111. */
static long long int
extract_uimm7_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000011111000000. */
static long long int
extract_uimm6_a16_21 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000022200011110. */
static long long int
extract_uimm7_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000111111000000. */
static long long int
extract_uimm7_a16_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000111111222222. */
static long long int
extract_simm13_a16_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000000011111111. */
static long long int
extract_uimm8_8_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 0000011111100000. */
static long long int
extract_uimm6_5_s (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
/* mask = 00000000000000000000000000000000. */
static ATTRIBUTE_UNUSED int
extract_uimm6_axx_ (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned value = 0;
}
static long long
-extract_rb (unsigned long long insn,
- bfd_boolean * invalid)
+extract_rb (unsigned long long insn,
+ bool *invalid)
{
int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
if (value == 0x3e && invalid)
- *invalid = TRUE; /* A limm operand, it should be extracted in a
+ *invalid = true; /* A limm operand, it should be extracted in a
different way. */
return value;
}
static long long
-extract_rhv1 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_rhv1 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
}
static long long
-extract_rhv2 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_rhv2 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
static long long
extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 0;
}
static long long
extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool* invalid ATTRIBUTE_UNUSED)
{
return 1;
}
static long long
extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 2;
}
static long long
extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 3;
}
static long long
extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 28;
}
static long long
extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 26;
}
static long long
extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 63;
}
static long long
extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 31;
}
static long long
extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 29;
}
static long long
extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 30;
}
}
static long long
-extract_ras (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_ras (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = insn & 0x07;
}
static long long
-extract_rbs (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_rbs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 8) & 0x07;
}
static long long
-extract_rcs (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_rcs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 5) & 0x07;
}
static long long
-extract_simm3s (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_simm3s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 8) & 0x07;
}
static long long
-extract_rrange (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_rrange (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn >> 1) & 0x0F;
}
}
static long long
-extract_fpel (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_fpel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0100) ? 27 : -1;
}
}
static long long
-extract_blinkel (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_blinkel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0200) ? 31 : -1;
}
}
static long long
-extract_pclel (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_pclel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0400) ? 63 : -1;
}
/* mask = 00000000000000000000111111000000. */
static long long
-extract_w6 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_w6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
/* mask = 0000011100022000. */
static long long
-extract_g_s (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_g_s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
int signbit = 1 << (6 - 1);
} \
\
static long long \
-extract_nps_3bit_reg_at_##OFFSET##_##NAME \
- (unsigned long long insn, \
- bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+extract_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
{ \
int value = (insn >> (OFFSET)) & 0x07; \
if (value > 3) \
}
static long long
-extract_nps_bitop_size_2b (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_bitop_size_2b (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return 1 << ((insn >> 10) & 0x3);
}
}
static long long
-extract_nps_bitop_uimm8 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_bitop_uimm8 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
}
}
static long long
-extract_nps_rflt_uimm6 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_rflt_uimm6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn >> 6) & 0x3f;
}
}
static long long
-extract_nps_dst_pos_and_size (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_dst_pos_and_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x1f);
}
}
static long long
-extract_nps_cmem_uimm16 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_cmem_uimm16 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
}
}
static long long
-extract_nps_imm_offset (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 10) & 0x7) * 16;
}
}
static long long
-extract_nps_imm_entry (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_imm_entry (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int imm_entry = ((insn >> 2) & 0x7);
return (1 << (imm_entry + 4));
}
static long long
-extract_nps_size_16bit (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_size_16bit (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
}
} \
\
static long long \
-extract_nps_##NAME##_pos (unsigned long long insn, \
- bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+extract_nps_##NAME##_pos (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
{ \
return ((insn >> SHIFT) & 0x3) * 8; \
}
} \
\
static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
{ \
return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
}
MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
static long long
-extract_nps_qcmp_m3 (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_qcmp_m3 (unsigned long long insn,
+ bool *invalid)
{
int m3 = (insn >> 5) & 0xf;
if (m3 == 0xf)
- *invalid = TRUE;
+ *invalid = true;
return m3;
}
static long long
-extract_nps_qcmp_m2 (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_qcmp_m2 (unsigned long long insn,
+ bool *invalid)
{
- bfd_boolean tmp_invalid = FALSE;
+ bool tmp_invalid = false;
int m2 = (insn >> 15) & 0x1;
int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
if (m2 == 0 && m3 == 0xf)
- *invalid = TRUE;
+ *invalid = true;
return m2;
}
static long long
-extract_nps_qcmp_m1 (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_qcmp_m1 (unsigned long long insn,
+ bool *invalid)
{
- bfd_boolean tmp_invalid = FALSE;
+ bool tmp_invalid = false;
int m1 = (insn >> 14) & 0x1;
int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
if (m1 == 0 && m2 == 0 && m3 == 0xf)
- *invalid = TRUE;
+ *invalid = true;
return m1;
}
}
static long long
-extract_nps_calc_entry_size (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_calc_entry_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
unsigned entry_size = (insn >> 8) & 0xf;
return 1 << entry_size;
}
static long long
-extract_nps_bitop_mod4 (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_bitop_mod4 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
}
}
static long long
-extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ bool *invalid)
{
if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
- *invalid = TRUE;
+ *invalid = true;
return ((insn >> 37) & 0x1f);
}
}
static long long
-extract_nps_bitop_ins_ext (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_bitop_ins_ext (unsigned long long insn,
+ bool *invalid)
{
int value = (insn >> 20) & 0x1f;
if (value > 28)
- *invalid = TRUE;
+ *invalid = true;
return value;
}
} \
\
static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
{ \
int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
if (value == 0) \
}
static long long
-extract_nps_min_hofs (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_min_hofs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 6) & 0xF;
return value * 16;
} \
\
static long long \
-extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
- bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
+ bool *invalid ATTRIBUTE_UNUSED) \
{ \
return ARC_NPS400_ADDRTYPE_##VALUE; \
}
static long long
-extract_nps_rbdouble_64 (unsigned long long insn,
- bfd_boolean * invalid)
+extract_nps_rbdouble_64 (unsigned long long insn,
+ bool *invalid)
{
int value1 = (insn >> 43) & 0x1F;
int value2 = (insn >> 48) & 0x1F;
if (value1 != value2)
- *invalid = TRUE;
+ *invalid = true;
return value1;
}
}
static long long int
-extract_nps_misc_imm_offset (unsigned long long insn,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+extract_nps_misc_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
{
return ((insn >> 8) & 0x1f) * 4;
}
static long long int
extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+ bool *invalid ATTRIBUTE_UNUSED)
{
int value = 0;
struct vpt_block
{
/* Are we in a vpt block. */
- bfd_boolean in_vpt_block;
+ bool in_vpt_block;
/* Next predicate state if in vpt block. */
enum vpt_pred_state next_pred_state;
static struct vpt_block vpt_block_state =
{
- FALSE,
+ false,
PRED_NONE,
0,
0,
#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
#define arm_regnames regnames[regname_selected].reg_names
-static bfd_boolean force_thumb = FALSE;
+static bool force_thumb = false;
static uint16_t cde_coprocs = 0;
/* Current IT instruction state. This contains the same state as the IT
static void
mark_outside_vpt_block (void)
{
- vpt_block_state.in_vpt_block = FALSE;
+ vpt_block_state.in_vpt_block = false;
vpt_block_state.next_pred_state = PRED_NONE;
vpt_block_state.predicate_mask = 0;
vpt_block_state.current_insn_num = 0;
static void
mark_inside_vpt_block (long given)
{
- vpt_block_state.in_vpt_block = TRUE;
+ vpt_block_state.in_vpt_block = true;
vpt_block_state.next_pred_state = PRED_THEN;
vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
vpt_block_state.current_insn_num = 0;
static void
arm_decode_shift (long given, fprintf_ftype func, void *stream,
- bfd_boolean print_shift)
+ bool print_shift)
{
func (stream, "%s", arm_regnames[given & 0xf]);
/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
-static bfd_boolean
+static bool
is_mve_okay_in_it (enum mve_instructions matched_insn)
{
switch (matched_insn)
case MVE_SRSHR:
case MVE_SQSHLL:
case MVE_SQSHL:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
is_mve_architecture (struct disassemble_info *info)
{
struct arm_private_data *private_data = info->private_data;
if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
&& !ARM_CPU_IS_ANY (allowed_arches))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_vpt_instruction (long given)
{
/* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
if ((given & 0x0040e000) == 0)
- return FALSE;
+ return false;
/* VPT floating point T1 variant. */
if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
|| ((given & 0xff811f50) == 0xfe011f40)
/* VPST vector T variant. */
|| ((given & 0xffbf1fff) == 0xfe310f4d))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
This helps us decode instructions that change mnemonic depending on specific
operand values/encodings. */
-static bfd_boolean
+static bool
is_mve_encoding_conflict (unsigned long given,
enum mve_instructions matched_insn)
{
{
case MVE_VPST:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VPT_FP_T1:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if ((arm_decode_field (given, 12, 12) == 0)
&& (arm_decode_field (given, 0, 0) == 1))
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VPT_FP_T2:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if (arm_decode_field (given, 0, 3) == 0xd)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VPT_VEC_T1:
case MVE_VPT_VEC_T2:
case MVE_VPT_VEC_T5:
case MVE_VPT_VEC_T6:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if (arm_decode_field (given, 20, 21) == 3)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VCMP_FP_T1:
if ((arm_decode_field (given, 12, 12) == 0)
&& (arm_decode_field (given, 0, 0) == 1))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VCMP_FP_T2:
if (arm_decode_field (given, 0, 3) == 0xd)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VQADD_T2:
case MVE_VQSUB_T2:
case MVE_VCMP_VEC_T5:
case MVE_VCMP_VEC_T6:
if (arm_decode_field (given, 20, 21) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VLD2:
case MVE_VLD4:
case MVE_VST2:
case MVE_VST4:
if (arm_decode_field (given, 7, 8) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VSTRB_T1:
case MVE_VSTRH_T2:
if ((arm_decode_field (given, 24, 24) == 0)
&& (arm_decode_field (given, 21, 21) == 0))
{
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 7, 8) == 3))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VSTRB_T5:
case MVE_VSTRH_T6:
if ((arm_decode_field (given, 24, 24) == 0)
&& (arm_decode_field (given, 21, 21) == 0))
{
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCVT_FP_FIX_VEC:
return (arm_decode_field (given, 16, 21) & 0x38) == 0;
unsigned long cmode = arm_decode_field (given, 8, 11);
if ((cmode & 1) == 0)
- return TRUE;
+ return true;
else if ((cmode & 0xc) == 0xc)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
case MVE_VMVN_IMM:
unsigned long cmode = arm_decode_field (given, 8, 11);
if (cmode == 0xe)
- return TRUE;
+ return true;
else if ((cmode & 0x9) == 1)
- return TRUE;
+ return true;
else if ((cmode & 0xd) == 9)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
case MVE_VMOV_IMM_TO_VEC:
if ((arm_decode_field (given, 5, 5) == 1)
&& (arm_decode_field (given, 8, 11) != 0xe))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VMOVL:
{
unsigned long size = arm_decode_field (given, 19, 20);
if ((size == 0) || (size == 3))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
case MVE_VMAXA:
case MVE_VQMOVUN:
case MVE_VQMOVN:
if (arm_decode_field (given, 18, 19) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VMLSLDAV:
case MVE_VRMLSLDAVH:
case MVE_VMLALDAV:
case MVE_VADDLV:
if (arm_decode_field (given, 20, 22) == 7)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VRMLALDAVH:
if ((arm_decode_field (given, 20, 22) & 6) == 6)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VDWDUP:
case MVE_VIWDUP:
if ((arm_decode_field (given, 20, 21) == 3)
|| (arm_decode_field (given, 1, 3) == 7))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VSHLL_T1:
unsigned long sz = arm_decode_field (given, 19, 20);
if ((sz == 1) || (sz == 2))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
case MVE_VQSHL_T2:
case MVE_VQSHLU_T3:
case MVE_VSLI:
case MVE_VSRI:
if (arm_decode_field (given, 19, 21) == 0)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VCTP:
if (arm_decode_field (given, 16, 19) == 0xf)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_ASRLI:
case MVE_ASRL:
case MVE_UQSHLL:
case MVE_URSHRL:
if (arm_decode_field (given, 9, 11) == 0x7)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_CSINC:
case MVE_CSINV:
rn = arm_decode_field (given, 16, 19);
/* CSET/CSETM. */
if (rm == 0xf && rn == 0xf)
- return TRUE;
+ return true;
/* CINC/CINV. */
else if (rn == rm && rn != 0xf)
- return TRUE;
+ return true;
}
/* Fall through. */
case MVE_CSEL:
case MVE_CSNEG:
if (arm_decode_field (given, 0, 3) == 0xd)
- return TRUE;
+ return true;
/* CNEG. */
else if (matched_insn == MVE_CSNEG)
if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
- return TRUE;
- return FALSE;
+ return true;
+ return false;
default:
case MVE_VADD_FP_T1:
case MVE_VADD_FP_T2:
case MVE_VADD_VEC_T1:
- return FALSE;
+ return false;
}
}
Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
this encoding is undefined. */
-static bfd_boolean
+static bool
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
enum mve_undefined *undefined_code)
{
if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VQADD_T1:
case MVE_VQSUB_T1:
if (arm_decode_field (given, 20, 21) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRB_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRH_T2:
if (arm_decode_field (given, 7, 8) <= 1)
{
*undefined_code = UNDEF_SIZE_LE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRB_T1:
if ((arm_decode_field (given, 7, 8) == 0))
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_T2:
if ((arm_decode_field (given, 7, 8) <= 1))
{
*undefined_code = UNDEF_SIZE_LE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRB_GATHER_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 28, 28) == 0)
&& (arm_decode_field (given, 7, 8) == 0))
{
*undefined_code = UNDEF_NOT_UNS_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRH_GATHER_T2:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 28, 28) == 0)
&& (arm_decode_field (given, 7, 8) == 1))
{
*undefined_code = UNDEF_NOT_UNS_SIZE_1;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 7, 8) == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRW_GATHER_T3:
if (arm_decode_field (given, 7, 8) != 2)
{
*undefined_code = UNDEF_SIZE_NOT_2;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 28, 28) == 0)
{
*undefined_code = UNDEF_NOT_UNSIGNED;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRD_GATHER_T4:
if (arm_decode_field (given, 7, 8) != 3)
{
*undefined_code = UNDEF_SIZE_NOT_3;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 28, 28) == 0)
{
*undefined_code = UNDEF_NOT_UNSIGNED;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRB_SCATTER_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_SCATTER_T2:
{
if (size == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if (size == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VSTRW_SCATTER_T3:
if (arm_decode_field (given, 7, 8) != 2)
{
*undefined_code = UNDEF_SIZE_NOT_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRD_SCATTER_T4:
if (arm_decode_field (given, 7, 8) != 3)
{
*undefined_code = UNDEF_SIZE_NOT_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCVT_FP_FIX_VEC:
{
if ((imm6 & 0x20) == 0)
{
*undefined_code = UNDEF_VCVT_IMM6;
- return TRUE;
+ return true;
}
if ((arm_decode_field (given, 9, 9) == 0)
&& ((imm6 & 0x30) == 0x20))
{
*undefined_code = UNDEF_VCVT_FSI_IMM6;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VNEG_FP:
if (size == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else if (size == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VMOV_VEC_LANE_TO_GP:
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_U_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else if (op2 == 2)
{
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
case MVE_VMOV_GP_TO_VEC_LANE:
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
case MVE_VMOV_VEC_TO_VEC:
if ((arm_decode_field (given, 5, 5) == 1)
|| (arm_decode_field (given, 22, 22) == 1))
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VMOV_IMM_TO_VEC:
if (arm_decode_field (given, 5, 5) == 0)
if (((cmode & 9) == 1) || ((cmode & 5) == 1))
{
*undefined_code = UNDEF_OP_0_BAD_CMODE;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
case MVE_VSHLL_T2:
case MVE_VMOVN:
if (arm_decode_field (given, 18, 19) == 2)
{
*undefined_code = UNDEF_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VRMLALDAVH:
case MVE_VMLADAV_T1:
&& (arm_decode_field (given, 12, 12) == 1))
{
*undefined_code = UNDEF_XCHG_UNS;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VQSHRN:
case MVE_VQSHRUN:
{
unsigned long sz = arm_decode_field (given, 19, 20);
if (sz == 1)
- return FALSE;
+ return false;
else if ((sz & 2) == 2)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE;
- return TRUE;
+ return true;
}
}
break;
{
unsigned long sz = arm_decode_field (given, 19, 21);
if ((sz & 7) == 1)
- return FALSE;
+ return false;
else if ((sz & 6) == 2)
- return FALSE;
+ return false;
else if ((sz & 4) == 4)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE;
- return TRUE;
+ return true;
}
}
if (arm_decode_field (given, 19, 20) == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VABS_VEC:
if (arm_decode_field (given, 18, 19) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VQNEG:
case MVE_VQABS:
if (arm_decode_field (given, 18, 19) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VREV16:
if (arm_decode_field (given, 18, 19) == 0)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE_NOT_0;
- return TRUE;
+ return true;
}
case MVE_VREV32:
if ((size & 2) == 2)
{
*undefined_code = UNDEF_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VREV64:
if (arm_decode_field (given, 18, 19) != 3)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
default:
- return FALSE;
+ return false;
}
}
Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
why this encoding is unpredictable. */
-static bfd_boolean
+static bool
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
enum mve_unpredictable *unpredictable_code)
{
&& (arm_decode_field (given, 5, 5) == 1))
{
*unpredictable_code = UNPRED_FCA_0_FCB_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VPT_VEC_T4:
case MVE_VPT_VEC_T5:
if (arm_decode_field (given, 0, 3) == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VDUP:
{
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VQADD_T2:
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VLD2:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
{
*unpredictable_code = UNPRED_Q_GT_6;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLD4:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
{
*unpredictable_code = UNPRED_Q_GT_4;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLDRB_T5:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
else if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLDRB_GATHER_T1:
if (arm_decode_field (given, 0, 0) == 1)
{
*unpredictable_code = UNPRED_OS;
- return TRUE;
+ return true;
}
/* fall through. */
if (qd == qm)
{
*unpredictable_code = UNPRED_Q_REGS_EQUAL;
- return TRUE;
+ return true;
}
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VLDRW_GATHER_T5:
if (qd == qm)
{
*unpredictable_code = UNPRED_Q_REGS_EQUAL;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VSTRB_SCATTER_T1:
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 0, 0) == 1)
{
*unpredictable_code = UNPRED_OS;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_SCATTER_T2:
case MVE_VSTRW_SCATTER_T3:
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VMOV2_VEC_LANE_TO_GP:
case MVE_VMOV2_GP_TO_VEC_LANE:
if ((rt == 0xd) || (rt2 == 0xd))
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if ((rt == 0xf) || (rt2 == 0xf))
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else if (rt == rt2)
{
*unpredictable_code = UNPRED_GP_REGS_EQUAL;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VMAXV:
if (rda == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (rda == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VMULL_INT:
if ((Qd == Qn) || (Qd == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
case MVE_VCMUL_FP:
if ((Qd == Qn) || (Qd == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
case MVE_VQDMULL_T2:
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field (given, 28, 28) == 1)
if (Qd == Qn)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
case MVE_VMLSLDAV:
if (arm_decode_field (given, 20, 22) == 6)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VDWDUP:
case MVE_VIWDUP:
if (arm_decode_field (given, 1, 3) == 6)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCADD_VEC:
case MVE_VHCADD:
if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VCADD_FP:
if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VCMLA_FP:
if ((Qda == Qn) || (Qda == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
if (arm_decode_field (given, 16, 19) == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VREV64:
{
if (qd == qm)
{
*unpredictable_code = UNPRED_Q_REGS_EQUAL;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_LSLL:
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
default:
- return FALSE;
+ return false;
}
}
Return TRUE if the instuction matched, FALSE if this is not a
recognised coprocessor instruction. */
-static bfd_boolean
+static bool
print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
bfd_vma pc,
struct disassemble_info *info,
long given,
- bfd_boolean thumb)
+ bool thumb)
{
const struct sopcode32 *insn;
void *stream = info->stream;
for (insn = opcodes; insn->assembler; insn++)
{
unsigned long u_reg = 16;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c;
|| insn->value == 0xfc000000) /* stc2 */
{
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Armv8.1-M Mainline FP & MVE instructions. */
if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
case 'C':
{
- bfd_boolean single = ((given >> 8) & 1) == 0;
+ bool single = ((given >> 8) & 1) == 0;
char reg_prefix = single ? 's' : 'd';
int Dreg = (given >> 22) & 0x1;
int Vdreg = (given >> 12) & 0xf;
case 'u':
if (cond != COND_UNCOND)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'c':
if (cond != COND_UNCOND && cp_num == 9)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'b':
{
case 'R':
if (value == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
if (c[1] == 'u')
++ c;
if (u_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
u_reg = value;
}
func (stream, "%s", arm_regnames[value]);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
print_insn_coprocessor (bfd_vma pc,
struct disassemble_info *info,
long given,
- bfd_boolean thumb)
+ bool thumb)
{
return print_insn_coprocessor_1 (coprocessor_opcodes,
pc, info, given, thumb);
}
-static bfd_boolean
+static bool
print_insn_generic_coprocessor (bfd_vma pc,
struct disassemble_info *info,
long given,
- bfd_boolean thumb)
+ bool thumb)
{
return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
pc, info, given, thumb);
else
{
func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
- arm_decode_shift (given, func, stream, TRUE);
+ arm_decode_shift (given, func, stream, true);
}
func (stream, "]%s",
{
func (stream, "], %s",
NEGATIVE_BIT_SET ? "-" : "");
- arm_decode_shift (given, func, stream, TRUE);
+ arm_decode_shift (given, func, stream, true);
}
}
if (NEGATIVE_BIT_SET)
/* Print one cde instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
recognised cde instruction. */
-static bfd_boolean
-print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
+static bool
+print_insn_cde (struct disassemble_info *info, long given, bool thumb)
{
const struct cdeopcode32 *insn;
void *stream = info->stream;
if ((given & insn->mask) == insn->value)
{
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
const char *c;
for (c = insn->assembler; *c; c++)
{
case 'S':
if (value > 10)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'R':
if (value == 13)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
func (stream, "%s", arm_regnames[value]);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
Return TRUE if the instuction matched, FALSE if this is not a
recognised neon instruction. */
-static bfd_boolean
-print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+static bool
+print_insn_neon (struct disassemble_info *info, long given, bool thumb)
{
const struct opcode32 *insn;
void *stream = info->stream;
;
/* vdup is also a valid neon instruction. */
else if ((given & 0xff900f5f) != 0xee800b10)
- return FALSE;
+ return false;
}
for (insn = neon_opcodes; insn->assembler; insn++)
if ((given & cond_mask) == cond_value)
{
signed long value_in_comment = 0;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
const char *c;
for (c = insn->assembler; *c; c++)
case 'u':
if (thumb && ifthen_state)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'c':
{
int amask = (1 << size) - 1;
if ((idx_align & (1 << size)) != 0)
- return FALSE;
+ return false;
if (size > 0)
{
if ((idx_align & amask) == amask)
align = 8 << size;
else if ((idx_align & amask) != 0)
- return FALSE;
+ return false;
}
}
break;
case 2:
if (size == 2 && (idx_align & 2) != 0)
- return FALSE;
+ return false;
align = (idx_align & 1) ? 16 << size : 0;
break;
case 3:
if ((size == 2 && (idx_align & 3) != 0)
|| (idx_align & 1) != 0)
- return FALSE;
+ return false;
break;
case 4:
if (size == 2)
{
if ((idx_align & 3) == 3)
- return FALSE;
+ return false;
align = (idx_align & 3) * 64;
}
else
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Print one mve instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
recognised mve instruction. */
-static bfd_boolean
+static bool
print_insn_mve (struct disassemble_info *info, long given)
{
const struct mopcode32 *insn;
&& !is_mve_encoding_conflict (given, insn->mve_op))
{
signed long value_in_comment = 0;
- bfd_boolean is_unpredictable = FALSE;
- bfd_boolean is_undefined = FALSE;
+ bool is_unpredictable = false;
+ bool is_undefined = false;
const char *c;
enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
enum mve_undefined undefined_cond = UNDEF_NONE;
There are a few exceptions; check for them. */
if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
{
- is_unpredictable = TRUE;
+ is_unpredictable = true;
unpredictable_cond = UNPRED_IT_BLOCK;
}
else if (is_mve_unpredictable (given, insn->mve_op,
&unpredictable_cond))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
- is_undefined = TRUE;
+ is_undefined = true;
/* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
i.e "VMOV Qd, Qm". */
{
case 'Z':
if (value == 13)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
else if (value == 15)
func (stream, "zr");
else
case 'S':
if (value == 13 || value == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
else
func (stream, "%s", arm_regnames[value]);
break;
else if (vpt_block_state.in_vpt_block)
update_vpt_block_state ();
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
fprintf_ftype func = info->fprintf_func;
struct arm_private_data *private_data = info->private_data;
- if (print_insn_coprocessor (pc, info, given, FALSE))
+ if (print_insn_coprocessor (pc, info, given, false))
return;
- if (print_insn_neon (info, given, FALSE))
+ if (print_insn_neon (info, given, false))
return;
- if (print_insn_generic_coprocessor (pc, info, given, FALSE))
+ if (print_insn_generic_coprocessor (pc, info, given, false))
return;
for (insn = arm_opcodes; insn->assembler; insn++)
{
unsigned long u_reg = 16;
unsigned long U_reg = 16;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c;
{
if (*c == '%')
{
- bfd_boolean allow_unpredictable = FALSE;
+ bool allow_unpredictable = false;
switch (*++c)
{
break;
case 'S':
- allow_unpredictable = TRUE;
+ allow_unpredictable = true;
/* Fall through. */
case 's':
if ((given & 0x004f0000) == 0x004f0000)
func (stream, "[pc], #%s%d",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
if (! allow_unpredictable)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
}
else
if (! allow_unpredictable
&& WRITEBACK_BIT_SET
&& ((given & 0xf) == ((given >> 12) & 0xf)))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
func (stream, "]%s",
destination of the load/store is unpredictable. */
if (! allow_unpredictable
&& (given & 0xf) == ((given >> 12) & 0xf))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
if (! allow_unpredictable)
/* Specifying the PC register as the post-indexed
registers is also unpredictable. */
|| (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
}
}
}
func (stream, "}");
if (! started)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
break;
case 'q':
- arm_decode_shift (given, func, stream, FALSE);
+ arm_decode_shift (given, func, stream, false);
break;
case 'o':
value_in_comment = a;
}
else
- arm_decode_shift (given, func, stream, TRUE);
+ arm_decode_shift (given, func, stream, true);
break;
case 'p':
arm_ext_v6))
func (stream, "p");
else
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
break;
{
case 'R':
if (value == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
case 'T':
++ c;
if (u_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
u_reg = value;
}
if (c[1] == 'U')
++ c;
if (U_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
U_reg = value;
}
func (stream, "%s", arm_regnames[value]);
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
- bfd_boolean is_mve = is_mve_architecture (info);
+ bool is_mve = is_mve_architecture (info);
- if (print_insn_coprocessor (pc, info, given, TRUE))
+ if (print_insn_coprocessor (pc, info, given, true))
return;
- if (!is_mve && print_insn_neon (info, given, TRUE))
+ if (!is_mve && print_insn_neon (info, given, true))
return;
if (is_mve && print_insn_mve (info, given))
return;
- if (print_insn_cde (info, given, TRUE))
+ if (print_insn_cde (info, given, true))
return;
- if (print_insn_generic_coprocessor (pc, info, given, TRUE))
+ if (print_insn_generic_coprocessor (pc, info, given, true))
return;
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
- bfd_boolean is_clrm = FALSE;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_clrm = false;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c = insn->assembler;
unsigned int op = (given & 0x00000f00) >> 8;
unsigned int i12 = (given & 0x00000fff);
unsigned int i8 = (given & 0x000000ff);
- bfd_boolean writeback = FALSE, postind = FALSE;
+ bool writeback = false, postind = false;
bfd_vma offset = 0;
func (stream, "[%s", arm_regnames[Rn]);
case 0xF: /* 8-bit + preindex with wb. */
offset = i8;
- writeback = TRUE;
+ writeback = true;
break;
case 0xD: /* 8-bit - preindex with wb. */
offset = -i8;
- writeback = TRUE;
+ writeback = true;
break;
case 0xB: /* 8-bit + postindex. */
offset = i8;
- postind = TRUE;
+ postind = true;
break;
case 0x9: /* 8-bit - postindex. */
offset = -i8;
- postind = TRUE;
+ postind = true;
break;
default:
break;
case 'n':
- is_clrm = TRUE;
+ is_clrm = true;
/* Fall through. */
case 'm':
{
case 'S':
if (val == 13)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'R':
if (val == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
func (stream, "%s", arm_regnames[val]);
Also disallow private symbol, with __tagsym$$ prefix,
from ARM RVCT toolchain being displayed. */
-bfd_boolean
+bool
arm_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
return;
}
-static bfd_boolean
+static bool
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
enum map_type *map_symbol);
static void
find_ifthen_state (bfd_vma pc,
struct disassemble_info *info,
- bfd_boolean little)
+ bool little)
{
unsigned char b[2];
unsigned int insn;
if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
{
enum map_type type = MAP_ARM;
- bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
+ bool found = mapping_symbol_for_insn (addr, info, &type);
if (!found || (found && type == MAP_THUMB))
{
*map_type = ((name[1] == 'a') ? MAP_ARM
: (name[1] == 't') ? MAP_THUMB
: MAP_DATA);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
{
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
return is_mapping_symbol (info, n, map_type);
}
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
es = *(elf_symbol_type **)(info->symtab + n);
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
*map_type = MAP_THUMB;
else
*map_type = MAP_ARM;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Search the mapping symbol state for instruction at pc. This is only
Return TRUE if the mapping state can be determined, and map_symbol
will be updated accordingly. Otherwise, return FALSE. */
-static bfd_boolean
+static bool
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
enum map_type *map_symbol)
{
bfd_vma addr, section_vma = 0;
int n, last_sym = -1;
- bfd_boolean found = FALSE;
- bfd_boolean can_use_search_opt_p = FALSE;
+ bool found = false;
+ bool can_use_search_opt_p = false;
/* Default to DATA. A text section is required by the ABI to contain an
INSN mapping symbol at the start. A data section has no such
if (info->private_data == NULL
|| bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
- return FALSE;
+ return false;
private_data = info->private_data;
if (get_map_sym_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
}
}
if (get_map_sym_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
break;
}
}
if (n >= 0 && get_sym_code_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
}
}
the relevant number of data bytes exist. */
static int
-print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
{
unsigned char b[4];
unsigned long given;
- int status;
- int is_thumb = FALSE;
- int is_data = FALSE;
- int little_code;
+ int status;
+ int is_thumb = false;
+ int is_data = false;
+ int little_code;
unsigned int size = 4;
- void (*printer) (bfd_vma, struct disassemble_info *, long);
- bfd_boolean found = FALSE;
+ void (*printer) (bfd_vma, struct disassemble_info *, long);
+ bool found = false;
struct arm_private_data *private_data;
/* Clear instruction information field. */
}
if (force_thumb)
- is_thumb = TRUE;
+ is_thumb = true;
if (is_data)
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
&& (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
info->endian_code = BFD_ENDIAN_LITTLE;
- return print_insn (pc, info, FALSE);
+ return print_insn (pc, info, false);
}
int
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
{
- return print_insn (pc, info, TRUE);
+ return print_insn (pc, info, true);
}
const disasm_options_and_args_t *
struct private
{
TIword iw0;
- bfd_boolean comment, parallel;
+ bool comment, parallel;
};
typedef enum
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (opc == 1)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (opc == 2)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (opc == 3)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (opc == 4)
{
OUTS (outf, ");\t\t/* bit");
OUTS (outf, imm7d (src));
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (opc == 5)
{
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (op == 1)
{
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else
return 0;
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (op == 1)
{
OUTS (outf, ";\t\t/* (");
OUTS (outf, imm7d (src));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else
return 0;
else if (op == 2 || op == 3)
OUTS (outf, "4");
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
return 2;
}
OUTS (outf, " */");
- priv->comment = TRUE;
+ priv->comment = true;
}
if (S == 1 || Z == 1)
{
OUTS (outf, "(");
OUTS (outf, imm32 (*pval));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
return 4;
}
OUTS (outf, ";\t\t/* (");
OUTS (outf, uimm16s4d (framesize));
OUTS (outf, ") */");
- priv->comment = TRUE;
+ priv->comment = true;
}
else if (R == 1)
OUTS (outf, "UNLINK");
struct private priv;
int count;
- priv.parallel = FALSE;
- priv.comment = FALSE;
+ priv.parallel = false;
+ priv.comment = false;
outf->private_data = &priv;
count = _print_insn_bfin (pc, outf);
if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
&& ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
{
- bfd_boolean legal = TRUE;
+ bool legal = true;
int len;
- priv.parallel = TRUE;
+ priv.parallel = true;
OUTS (outf, " || ");
len = _print_insn_bfin (pc + 4, outf);
if (len == -1)
return -1;
OUTS (outf, " || ");
if (len != 2)
- legal = FALSE;
+ legal = false;
len = _print_insn_bfin (pc + 6, outf);
if (len == -1)
return -1;
if (len != 2)
- legal = FALSE;
+ legal = false;
if (legal)
count = 8;
else
{
OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
- priv.comment = TRUE;
+ priv.comment = true;
count = 0;
}
}
{
/* Whether to print something less confusing if we find something
matching a switch-construct. */
- bfd_boolean trace_case;
+ bool trace_case;
/* Whether this code is flagged as crisv32. FIXME: Should be an enum
that includes "compatible". */
/* Parse disassembler options and store state in info. FIXME: For the
time being, we abuse static variables. */
-static bfd_boolean
+static bool
cris_parse_disassembler_options (disassemble_info *info,
enum cris_disass_family distype)
{
info->private_data = calloc (1, sizeof (struct cris_disasm_data));
disdata = (struct cris_disasm_data *) info->private_data;
if (disdata == NULL)
- return FALSE;
+ return false;
/* Default true. */
disdata->trace_case
|| (strcmp (info->disassembler_options, "nocase") != 0));
disdata->distype = distype;
- return TRUE;
+ return true;
}
static const struct cris_spec_reg *
format_reg (struct cris_disasm_data *disdata,
int regno,
char *outbuffer_start,
- bfd_boolean with_reg_prefix)
+ bool with_reg_prefix)
{
char *outbuffer = outbuffer_start;
static char *
format_sup_reg (unsigned int regno,
char *outbuffer_start,
- bfd_boolean with_reg_prefix)
+ bool with_reg_prefix)
{
char *outbuffer = outbuffer_start;
int i;
const struct cris_opcode *prefix_opcodep,
unsigned int prefix_insn,
unsigned char *prefix_buffer,
- bfd_boolean with_reg_prefix)
+ bool with_reg_prefix)
{
/* Get a buffer of somewhat reasonable size where we store
intermediate parts of the insn. */
static int
print_insn_cris_generic (bfd_vma memaddr,
disassemble_info *info,
- bfd_boolean with_reg_prefix)
+ bool with_reg_prefix)
{
int nbytes;
unsigned int insn;
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v0_v10))
return -1;
- return print_insn_cris_generic (vma, info, TRUE);
+ return print_insn_cris_generic (vma, info, true);
}
/* Disassemble, prefixing register names with `$'. CRIS v32. */
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v32))
return -1;
- return print_insn_cris_generic (vma, info, TRUE);
+ return print_insn_cris_generic (vma, info, true);
}
/* Disassemble, prefixing register names with `$'.
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
return -1;
- return print_insn_cris_generic (vma, info, TRUE);
+ return print_insn_cris_generic (vma, info, true);
}
/* Disassemble, no prefixes on register names. CRIS v0..v10. */
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v0_v10))
return -1;
- return print_insn_cris_generic (vma, info, FALSE);
+ return print_insn_cris_generic (vma, info, false);
}
/* Disassemble, no prefixes on register names. CRIS v32. */
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v32))
return -1;
- return print_insn_cris_generic (vma, info, FALSE);
+ return print_insn_cris_generic (vma, info, false);
}
/* Disassemble, no prefixes on register names.
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
return -1;
- return print_insn_cris_generic (vma, info, FALSE);
+ return print_insn_cris_generic (vma, info, false);
}
/* Return a disassembler-function that prints registers with a `$' prefix,
&& (name[2] == 0 || name[2] == '.'))
{
*sym_type = ((name[1] == 't') ? CUR_TEXT : CUR_DATA);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static int
return NULL;
}
-static bfd_boolean
+static bool
is_extern_symbol (struct disassemble_info *info, int addr)
{
unsigned int rel_count = 0;
struct reloc_cache_entry *pt = info->section->relocation;
for (; rel_count < info->section->reloc_count; rel_count++, pt++)
if ((long unsigned int)addr == pt->address)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
}
- return FALSE;
+ return false;
}
/* Suppress printing of mapping symbols emitted by the assembler to mark
the beginning of code and data sequences. */
-bfd_boolean
+bool
csky_symbol_is_valid (asymbol *sym,
struct disassemble_info *info ATTRIBUTE_UNUSED)
{
const char *name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
return name && *name != '$';
}
case OPRND_TYPE_PSR_BITS_LIST:
{
struct psrbit const *bits;
- int first_oprnd = TRUE;
+ int first_oprnd = true;
int i = 0;
if (IS_CSKY_V1 (mach_flag))
{
strcat (str, ", ");
strcat (str, bits[i].name);
value &= ~bits[i].value;
- first_oprnd = FALSE;
+ first_oprnd = false;
}
i++;
}
int status;
char str[256];
unsigned long given;
- int is_data = FALSE;
+ int is_data = false;
void (*printer) (bfd_vma, struct disassemble_info *, long);
unsigned int size = 4;
signed int relax;
/* Worker function to call when this instruction needs special assembler
handling. */
- bfd_boolean (*work)(void);
+ bool (*work) (void);
};
/* The following are the opcodes used in relax/fix process. */
/* Just return TRUE. */
-bfd_boolean
+bool
generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED,
struct disassemble_info *info ATTRIBUTE_UNUSED)
{
- return TRUE;
+ return true;
}
disassembler_ftype
disassembler (enum bfd_architecture a,
- bfd_boolean big ATTRIBUTE_UNUSED,
+ bool big ATTRIBUTE_UNUSED,
unsigned long mach ATTRIBUTE_UNUSED,
bfd *abfd ATTRIBUTE_UNUSED)
{
#ifdef ARCH_aarch64
case bfd_arch_aarch64:
info->symbol_is_valid = aarch64_symbol_is_valid;
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
break;
#endif
#ifdef ARCH_arm
case bfd_arch_arm:
info->symbol_is_valid = arm_symbol_is_valid;
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
break;
#endif
#ifdef ARCH_csky
case bfd_arch_csky:
info->symbol_is_valid = csky_symbol_is_valid;
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
break;
#endif
#endif
#ifdef ARCH_metag
case bfd_arch_metag:
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
break;
#endif
#ifdef ARCH_m32c
#endif
#ifdef ARCH_pru
case bfd_arch_pru:
- info->disassembler_needs_relocs = TRUE;
+ info->disassembler_needs_relocs = true;
break;
#endif
#ifdef ARCH_powerpc
/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
development tree. */
-bfd_boolean
+bool
frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
- return TRUE;
+ return true;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
- return TRUE;
+ return true;
break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */
-bfd_boolean
+bool
frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
- return FALSE;
+ return false;
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
/* Returns TRUE if {MAJOR,MACH} supports media insns. */
-bfd_boolean
+bool
frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
- return TRUE;
+ return true;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
- return TRUE;
+ return true;
break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
- return TRUE;
+ return true;
break;
}
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_branch_insn (const CGEN_INSN *insn)
{
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_float_insn (const CGEN_INSN *insn)
{
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
frv_is_media_insn (const CGEN_INSN *insn)
{
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
- return TRUE;
+ return true;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
- return TRUE;
+ return true;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* This table represents the allowable packing for vliw insns for the fr400.
/* Return TRUE if unit1 is a match for unit2.
Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
*_allowed_vliw tables above. */
-static bfd_boolean
+static bool
match_unit (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
{
unit1 = vliw->unit_mapping[unit1];
if (unit1 == unit2)
- return TRUE;
+ return true;
if (unit1 < unit2)
- return FALSE;
+ return false;
switch (unit1)
{
/* The 01 versions of these units are within 2 enums of the 0 or 1
versions. */
if (unit1 - unit2 <= 2)
- return TRUE;
+ return true;
break;
case UNIT_IALL:
case UNIT_FMALL:
/* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
versions. */
if (unit1 - unit2 <= 5)
- return TRUE;
+ return true;
break;
default:
break;
}
- return FALSE;
+ return false;
}
/* Return TRUE if the vliws match, FALSE otherwise. */
-static bfd_boolean
+static bool
match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
{
int i;
for (i = 0; i < vliw_size; ++i)
if ((*vliw1)[i] != (*vliw2)[i])
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Find the next vliw vliw in the table that can accomodate the new insn.
/* Look for the given major insn type in the given vliw.
Returns TRUE if found, FALSE otherwise. */
-static bfd_boolean
+static bool
find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Check for constraints between the insns in the vliw due to major insn
types. */
-static bfd_boolean
+static bool
fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
/* In the cpu file, all media insns are represented as being allowed in
default:
break;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
CGEN_ATTR_VALUE_ENUM_TYPE other_major;
/* (M4, M5) and (M4, M6) are allowed. */
if (other_major == FR450_MAJOR_M_4)
if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
- return TRUE;
+ return true;
/* Otherwise, instructions in even-numbered media categories cannot be
executed in parallel with other media instructions. */
|| other_major == FR450_MAJOR_M_6);
default:
- return TRUE;
+ return true;
}
}
-static bfd_boolean
+static bool
find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
- return TRUE;
+ return true;
- return FALSE; /* Not found. */
+ return false; /* Not found. */
}
-static bfd_boolean
+static bool
find_major_in_slot (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
CGEN_ATTR_VALUE_ENUM_TYPE slot)
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_find_media_in_vliw (FRV_VLIW *vliw)
{
int i;
|| CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
continue;
- return TRUE; /* Found one. */
+ return true; /* Found one. */
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_find_float_in_vliw (FRV_VLIW *vliw)
{
int i;
if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
continue;
- return TRUE; /* Found one. */
+ return true; /* Found one. */
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
fr550_check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
const CGEN_INSN *insn)
default:
break;
}
- return TRUE; /* All OK. */
+ return true; /* All OK. */
}
-static bfd_boolean
+static bool
fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
{
/* TODO: A table might be faster for some of the more complex instances
case FR500_MAJOR_F_4:
case FR500_MAJOR_F_8:
case FR500_MAJOR_M_8:
- return TRUE; /* OK */
+ return true; /* OK */
case FR500_MAJOR_I_2:
/* Cannot coexist with I-3 insn. */
return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
abort ();
break;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_ENUM_TYPE major,
const CGEN_INSN *insn)
return 1;
}
-bfd_boolean
+bool
spr_valid (long regno)
{
- if (regno < 0) return FALSE;
- if (regno <= 4095) return TRUE;
- return FALSE;
+ if (regno < 0) return false;
+ if (regno <= 4095) return true;
+ return false;
}
/* -- */
/* The hash functions are recorded here to help keep assembler code out of
const CGEN_INSN * insn[FRV_VLIW_SIZE];
} FRV_VLIW;
-bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-bfd_boolean frv_is_branch_insn (const CGEN_INSN *);
-bfd_boolean frv_is_float_insn (const CGEN_INSN *);
-bfd_boolean frv_is_media_insn (const CGEN_INSN *);
-void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
-bfd_boolean spr_valid (long);
+bool frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bool frv_is_branch_insn (const CGEN_INSN *);
+bool frv_is_float_insn (const CGEN_INSN *);
+bool frv_is_media_insn (const CGEN_INSN *);
+void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
+int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
+bool spr_valid (long);
/* -- */
/* Enum declaration for frv instruction types. */
typedef enum cgen_insn_type {
int dispregno[3] = { 0, 0, 0 };
int cst[3] = { 0, 0, 0 };
int cstlen[3] = { 0, 0, 0 };
- static bfd_boolean init = 0;
+ static bool init = 0;
const struct h8_instruction *qi;
char const **pregnames = mach != 0 ? lregnames : wregnames;
int status;
#define NOTRACK_PREFIX (0x3e | 0x100)
/* Remember if the current op is a jump instruction. */
-static bfd_boolean op_is_jump = FALSE;
+static bool op_is_jump = false;
static int
ckprefix (void)
}
/* Reset jump operation indicator. */
- op_is_jump = FALSE;
+ op_is_jump = false;
{
int jump_detection = 0;
/* Determine if this is a jump or branch. */
if ((jump_detection & 0x3) == 0x3)
{
- op_is_jump = TRUE;
+ op_is_jump = true;
if (jump_detection & 0x4)
the_info->insn_type = dis_condbranch;
else
|| bytemode == v_bndmk_mode
|| bytemode == bnd_mode
|| bytemode == bnd_swap_mode);
- bfd_boolean check_gather = FALSE;
+ bool check_gather = false;
const char **indexes64 = names64;
const char **indexes32 = names32;
A similar case exists for the movem instructions where the register
mask is interpreted differently for different EAs. */
-static bfd_boolean
+static bool
m68k_valid_ea (char code, int val)
{
int mode, mask;
static void
lookup_reg_list (char *reg_buf, size_t buf_len, unsigned int reg_unit,
unsigned int reg_no, unsigned int rmask,
- bfd_boolean is_fpu_64bit)
+ bool is_fpu_64bit)
{
const char *regs[MGET_MSET_MAX_REGS];
size_t used_regs = 1, i, remaining;
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
char buf[OPERAND_WIDTH];
char addr_buf[ADDR_WIDTH];
unsigned int reg_unit, reg_no;
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
- bfd_boolean is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
+ bool is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
+ bool is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
char buf[OPERAND_WIDTH];
char addr_buf[ADDR_WIDTH];
unsigned int reg_unit, reg_no;
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
- bfd_boolean is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
- bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
+ bool is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
char buf[OPERAND_WIDTH];
char addr_buf[ADDR_WIDTH];
char reg_buf[REG_WIDTH];
unsigned int unit_bit = (insn_word >> 24) & 0x1;
unsigned int ca = (insn_word >> 5) & 0x1;
unsigned int se = (insn_word >> 1) & 0x1;
- bfd_boolean is_quickrot = template->arg_type & GP_ARGS_QR;
+ bool is_quickrot = template->arg_type & GP_ARGS_QR;
enum metag_unit base_unit;
enum metag_unit dest_unit;
const char *dest_reg;
unsigned int p = (insn_word >> 6) & 0x1;
unsigned int d = (insn_word >> 5) & 0x1;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src_reg;
const char *cc_flags;
char buf[OPERAND_WIDTH * 2];
char data_buf[REG_WIDTH];
char fpu_buf[REG_WIDTH];
- bfd_boolean to_fpu = MAJOR_OPCODE (insn_word) == OPC_GET;
- bfd_boolean is_mmovl = MINOR_OPCODE (insn_word) & 0x1;
+ bool to_fpu = MAJOR_OPCODE (insn_word) == OPC_GET;
+ bool is_mmovl = MINOR_OPCODE (insn_word) & 0x1;
unsigned int rmask = (insn_word >> 7) & RMASK_MASK;
unsigned int fpu_no, data_no, data_unit;
else
data_unit = UNIT_D0;
- lookup_reg_list (data_buf, REG_WIDTH, data_unit, data_no, rmask, FALSE);
+ lookup_reg_list (data_buf, REG_WIDTH, data_unit, data_no, rmask, false);
lookup_reg_list (fpu_buf, REG_WIDTH, UNIT_FX, fpu_no,
convert_fx_rmask (rmask), is_mmovl);
unsigned int d = (insn_word >> 5) & 0x1;
unsigned int q = (insn_word >> 7) & 0x1;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src_reg;
const char *cc_flags;
unsigned int d = (insn_word >> 5) & 0x1;
unsigned int src1_no, src2_no, dest_no;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src1_reg;
const char *src2_reg;
unsigned int z = (insn_word >> 12) & 0x1;
unsigned int src_no, dest_no;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src_reg;
const char *cc_flags;
unsigned int xl = (insn_word >> 7) & 0x1;
unsigned int src_no, dest_no, fraction_bits;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src_reg;
const char *cc_flags;
unsigned int d = (insn_word >> 5) & 0x1;
unsigned int src1_no, src2_no, dest_no;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ bool show_cond = cc != COND_A && cc != COND_NV;
const char *dest_reg;
const char *src1_reg;
const char *src2_reg;
{
char buf[OPERAND_WIDTH];
char prefix_buf[10];
- bfd_boolean is_muz = (MINOR_OPCODE (insn_word) == 0x6 &&
- ((insn_word >> 4) & 0x1));
- bfd_boolean is_mac = (MINOR_OPCODE (insn_word) == 0x6 &&
- (insn_word & 0x1f) == 0);
- bfd_boolean is_maw = (MINOR_OPCODE (insn_word) == 0x6 &&
- ((insn_word >> 3) & 0x1));
+ bool is_muz = MINOR_OPCODE (insn_word) == 0x6 && ((insn_word >> 4) & 0x1);
+ bool is_mac = MINOR_OPCODE (insn_word) == 0x6 && (insn_word & 0x1f) == 0;
+ bool is_maw = MINOR_OPCODE (insn_word) == 0x6 && ((insn_word >> 3) & 0x1);
unsigned int o3o = insn_word & 0x1;
unsigned int q = is_muz && ((insn_word >> 1) & 0x1);
unsigned int n = (insn_word >> 7) & 0x1;
unsigned int p = (insn_word >> 6) & 0x1;
unsigned int d = (insn_word >> 5) & 0x1;
unsigned int cc = (insn_word >> 1) & CC_MASK;
- bfd_boolean show_cond = (MINOR_OPCODE (insn_word) == 0x5 && cc != COND_A &&
- cc != COND_NV);
+ bool show_cond = (MINOR_OPCODE (insn_word) == 0x5 && cc != COND_A
+ && cc != COND_NV);
unsigned int src1_no, src2_no, dest_no;
const char *dest_reg;
const char *src1_reg;
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
char buf[OPERAND_WIDTH];
char addr_buf[ADDR_WIDTH];
unsigned int part;
/* Return the name of the DSP RAM register for NUM and UNIT. */
static const char *
-lookup_dspram_name (unsigned int num, unsigned int unit, bfd_boolean load)
+lookup_dspram_name (unsigned int num, unsigned int unit, bool load)
{
size_t i, nentries;
number in a DSP instruction. SOURCE indicates whether this
register is a source or destination operand. */
static const char *
-lookup_any_reg_name (unsigned int unit, unsigned int num, bfd_boolean source)
+lookup_any_reg_name (unsigned int unit, unsigned int num, bool source)
{
/* A register with the top bit set (5th bit) indicates a DSPRAM
register. */
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_get = (template->meta_opcode & 0x100);
+ bool is_get = (template->meta_opcode & 0x100);
char buf[OPERAND_WIDTH];
char addr_buf[ADDR_WIDTH];
char prefix[DSP_PREFIX_WIDTH];
unsigned int part;
const char *reg_name[2];
- bfd_boolean is_high = FALSE;
- bfd_boolean is_dual = (insn_word & 0x4);
- bfd_boolean is_template = (insn_word & 0x2);
+ bool is_high = false;
+ bool is_dual = (insn_word & 0x4);
+ bool is_template = (insn_word & 0x2);
const char *base_reg = "?";
unsigned int addr_unit, base_no, unit;
char buf[OPERAND_WIDTH];
char prefix[DSP_PREFIX_WIDTH];
unsigned int offset[4];
- bfd_boolean is_half = (MINOR_OPCODE (insn_word) == 0x5);
- bfd_boolean daop_only = (MINOR_OPCODE (insn_word) == 0x3);
+ bool is_half = (MINOR_OPCODE (insn_word) == 0x5);
+ bool daop_only = (MINOR_OPCODE (insn_word) == 0x3);
offset[0] = ((insn_word >> 19) & REG_MASK);
offset[1] = ((insn_word >> 14) & REG_MASK);
static void
decode_template_definition(unsigned int insn_word, char *buf, size_t len)
{
- bfd_boolean load = ((insn_word >> 13) & 0x1);
- bfd_boolean dspram = (((insn_word >> 17) & 0x3) == 0x3);
+ bool load = ((insn_word >> 13) & 0x1);
+ bool dspram = (((insn_word >> 17) & 0x3) == 0x3);
const char *template[1];
unsigned int tidx = ((insn_word >> 9) & TEMPLATE_REGS_MASK);
enum metag_unit au, ram_unit;
}
else
{
- bfd_boolean im = (((insn_word >> 18) & 0x1) != 0);
+ bool im = (((insn_word >> 18) & 0x1) != 0);
au = (((insn_word >> 23) & 0x1) == 0) ? UNIT_A0 : UNIT_A1;
addr_reg_nums[0] = ((insn_word >> 19) & DSP_REG_MASK);
const insn_template *template,
disassemble_info *outf)
{
- bfd_boolean is_dual = FALSE;
+ bool is_dual = false;
unsigned int data_unit = (((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0);
const char *reg_names[3];
unsigned int reg_nums[3];
- bfd_boolean ac = ((insn_word >> 7) & 0x1);
+ bool ac = ((insn_word >> 7) & 0x1);
char buf[OPERAND_WIDTH];
char prefix[DSP_PREFIX_WIDTH];
size_t len;
- bfd_boolean is_mod = FALSE;
- bfd_boolean is_overflow = FALSE;
+ bool is_mod = false;
+ bool is_overflow = false;
unsigned int reg_brackets[3];
- bfd_boolean is_w_mx = FALSE;
- bfd_boolean is_b_mx = FALSE;
- bfd_boolean imm = FALSE;
- bfd_boolean is_quickrot64 = FALSE;
- bfd_boolean conditional = FALSE;
+ bool is_w_mx = false;
+ bool is_b_mx = false;
+ bool imm = false;
+ bool is_quickrot64 = false;
+ bool conditional = false;
const char *cc_flags = NULL;
- bfd_boolean is_unsigned = FALSE;
+ bool is_unsigned = false;
memset (reg_brackets, 0, sizeof (reg_brackets));
if (template->arg_type & DSP_ARGS_1)
{
- bfd_boolean is_template = FALSE;
+ bool is_template = false;
const char *addr_reg = NULL;
- bfd_boolean qr = FALSE;
- bfd_boolean is_acc_add = FALSE;
- bfd_boolean is_acc_sub = FALSE;
- bfd_boolean is_acc_zero = FALSE;
- bfd_boolean is_split8 = (template->arg_type & DSP_ARGS_SPLIT8);
+ bool qr = false;
+ bool is_acc_add = false;
+ bool is_acc_sub = false;
+ bool is_acc_zero = false;
+ bool is_split8 = (template->arg_type & DSP_ARGS_SPLIT8);
/* Read DU bit. */
data_unit = ((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0;
is_acc_sub = ((insn_word & 0x84) == 0x84);
}
else
- reg_names[0] = lookup_any_reg_name (data_unit, 0, FALSE);
+ reg_names[0] = lookup_any_reg_name (data_unit, 0, false);
/* These are dummy arguments anyway so the register
number does not matter. */
- reg_names[1] = lookup_any_reg_name (data_unit, 0, TRUE);
+ reg_names[1] = lookup_any_reg_name (data_unit, 0, true);
/* De.r,Dx.r,De.r|ACe.r */
if ((template->arg_type & DSP_ARGS_ACC2) &&
aunit = (data_unit == UNIT_D0) ? UNIT_A0 : UNIT_A1;
addr_reg = lookup_reg_name (aunit, reg_no + 2);
- qr = TRUE;
+ qr = true;
}
- reg_names[2] = lookup_any_reg_name (data_unit, 0, TRUE);
+ reg_names[2] = lookup_any_reg_name (data_unit, 0, true);
}
}
}
else
{
- bfd_boolean o2r = (insn_word & 0x1);
+ bool o2r = (insn_word & 0x1);
/* De.r|ACe.r,Dx.r,De.r */
if ((template->arg_type & DSP_ARGS_DACC) &&
else
{
reg_names[0] = lookup_any_reg_name (data_unit,
- reg_nums[0], FALSE);
+ reg_nums[0], false);
if (reg_nums[0] > 15)
reg_brackets[0] = 1;
}
if (imm)
{
- reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[0], TRUE);
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[0], true);
if (reg_brackets[0])
reg_brackets[1] = 1;
}
else
{
- reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], TRUE);
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], true);
if (reg_nums[1] > 15)
reg_brackets[1] = 1;
aunit = (data_unit == UNIT_D0) ? UNIT_A0 : UNIT_A1;
addr_reg = lookup_reg_name (aunit, reg_no + 2);
- qr = TRUE;
+ qr = true;
}
if (o2r)
else
{
reg_names[2] = lookup_any_reg_name (data_unit,
- reg_nums[2], TRUE);
+ reg_nums[2], true);
if (reg_nums[2] > 15)
reg_brackets[2] = 1;
}
}
else if (template->arg_type & DSP_ARGS_2) /* Group 2. */
{
- bfd_boolean is_template;
- bfd_boolean o2r = FALSE;
+ bool is_template;
+ bool o2r = false;
int major = MAJOR_OPCODE (template->meta_opcode);
- bfd_boolean is_neg_or_mov = (major == OPC_ADD || major == OPC_SUB);
- bfd_boolean is_cmp_tst = ((major == OPC_CMP) &&
- ((insn_word & 0x0000002c) == 0));
- bfd_boolean is_fpu_mov = template->insn_type == INSN_DSP_FPU;
- bfd_boolean to_fpu = (template->meta_opcode >> 7) & 0x1;
+ bool is_neg_or_mov = (major == OPC_ADD || major == OPC_SUB);
+ bool is_cmp_tst = major == OPC_CMP && (insn_word & 0x0000002c) == 0;
+ bool is_fpu_mov = template->insn_type == INSN_DSP_FPU;
+ bool to_fpu = (template->meta_opcode >> 7) & 0x1;
if (major == OPC_9)
imm = (insn_word & 0x2);
}
else
{
- reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], TRUE);
+ reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], true);
if (reg_nums[0] > 15)
reg_brackets[0] = 1;
}
else
{
reg_names[1] = lookup_any_reg_name (data_unit,
- reg_nums[1], TRUE);
+ reg_nums[1], true);
if (reg_nums[1] > 15)
reg_brackets[1] = 1;
}
{
/* If both the C and CA bits are set, then the Rd register can
be in any unit. Figure out which unit from the Ud field. */
- bfd_boolean all_units = (((insn_word) & 0x04000020) == 0x04000020);
+ bool all_units = (((insn_word) & 0x04000020) == 0x04000020);
enum metag_unit ud_unit = ((insn_word >> 1) & UNIT_MASK);
enum metag_unit ram_unit, acc_unit;
- bfd_boolean round = FALSE;
- bfd_boolean clamp9 = FALSE;
- bfd_boolean clamp8 = FALSE;
- bfd_boolean is_template = ((insn_word & 0x04000002) == 0x2);
+ bool round = false;
+ bool clamp9 = false;
+ bool clamp8 = false;
+ bool is_template = ((insn_word & 0x04000002) == 0x2);
imm = ((insn_word >> 25) & 0x1);
ac = (insn_word & 0x1);
reg_names[0] = lookup_reg_name (data_unit, reg_nums[0]);
else
{
- reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], FALSE);
+ reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], false);
if (reg_nums[0] > 15)
reg_brackets[0] = 1;
}
}
else
{
- reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], TRUE);
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], true);
if (reg_nums[1] > 15)
reg_brackets[1] = 1;
}
{
reg_nums[2] = ((insn_word >> 9) & REG_MASK);
- reg_names[2] = lookup_any_reg_name (data_unit, reg_nums[2], TRUE);
+ reg_names[2] = lookup_any_reg_name (data_unit, reg_nums[2], true);
if (reg_nums[2] > 15)
reg_brackets[2] = 1;
if (is_template)
{
- bfd_boolean load = ((insn_word >> 13) & 0x1);
- bfd_boolean dspram = (((insn_word >> 17) & 0x3) == 0x3);
+ bool load = ((insn_word >> 13) & 0x1);
+ bool dspram = (((insn_word >> 17) & 0x3) == 0x3);
const char *tname[1];
unsigned int tidx = ((insn_word >> 9) & TEMPLATE_REGS_MASK);
enum metag_unit au;
}
else
{
- bfd_boolean im = (((insn_word >> 18) & 0x1) != 0);
+ bool im = (((insn_word >> 18) & 0x1) != 0);
au = (((insn_word >> 23) & 0x1) == 0) ? UNIT_A0 : UNIT_A1;
addr_reg_nums[0] = ((insn_word >> 19) & DSP_REG_MASK);
int
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
{
- fprintf_ftype print_func = info->fprintf_func;
- void * stream = info->stream;
- unsigned long inst, prev_inst;
- struct op_code_struct * op, *pop;
- int immval = 0;
- bfd_boolean immfound = FALSE;
- static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */
- static int prev_insn_vma = -1; /* Init the prev insn vma. */
- int curr_insn_vma = info->buffer_vma;
- struct string_buf buf;
+ fprintf_ftype print_func = info->fprintf_func;
+ void *stream = info->stream;
+ unsigned long inst, prev_inst;
+ struct op_code_struct *op, *pop;
+ int immval = 0;
+ bool immfound = false;
+ static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */
+ static int prev_insn_vma = -1; /* Init the prev insn vma. */
+ int curr_insn_vma = info->buffer_vma;
+ struct string_buf buf;
buf.which = 0;
info->bytes_per_chunk = 4;
if (pop->instr == imm)
{
immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
- immfound = TRUE;
+ immfound = true;
}
else
{
immval = 0;
- immfound = FALSE;
+ immfound = false;
}
}
}
enum microblaze_instr
get_insn_microblaze (long inst,
- bfd_boolean *isunsignedimm,
+ bool *isunsignedimm,
enum microblaze_instr_type *insn_type,
short *delay_slots)
{
struct op_code_struct * op;
- *isunsignedimm = FALSE;
+ *isunsignedimm = false;
/* Just a linear search of the table. */
for (op = opcodes; op->name != 0; op ++)
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed)
{
enum microblaze_instr op;
- bfd_boolean t1;
+ bool t1;
enum microblaze_instr_type t2;
short t3;
}
unsigned long
-microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
+microblaze_get_target_address (long inst, bool immfound, int immval,
long pcval, long r1val, long r2val,
- bfd_boolean *targetvalid,
- bfd_boolean *unconditionalbranch)
+ bool *targetvalid,
+ bool *unconditionalbranch)
{
struct op_code_struct * op;
long targetaddr = 0;
- *unconditionalbranch = FALSE;
+ *unconditionalbranch = false;
/* Just a linear search of the table. */
for (op = opcodes; op->name != 0; op ++)
if (op->bit_sequence == (inst & op->opcode_mask))
if (op->name == 0)
{
- *targetvalid = FALSE;
+ *targetvalid = false;
}
else if (op->instr_type == branch_inst)
{
switch (op->inst_type)
{
case INST_TYPE_R2:
- *unconditionalbranch = TRUE;
+ *unconditionalbranch = true;
/* Fall through. */
case INST_TYPE_RD_R2:
case INST_TYPE_R1_R2:
targetaddr = r2val;
- *targetvalid = TRUE;
+ *targetvalid = true;
if (op->inst_offset_type == INST_PC_OFFSET)
targetaddr += pcval;
break;
case INST_TYPE_IMM:
- *unconditionalbranch = TRUE;
+ *unconditionalbranch = true;
/* Fall through. */
case INST_TYPE_RD_IMM:
case INST_TYPE_R1_IMM:
}
if (op->inst_offset_type == INST_PC_OFFSET)
targetaddr += pcval;
- *targetvalid = TRUE;
+ *targetvalid = true;
break;
default:
- *targetvalid = FALSE;
+ *targetvalid = false;
break;
}
}
targetaddr |= 0xFFFF0000;
}
targetaddr += r1val;
- *targetvalid = TRUE;
+ *targetvalid = true;
}
else
- *targetvalid = FALSE;
+ *targetvalid = false;
return targetaddr;
}
extern enum microblaze_instr microblaze_decode_insn (long, int *, int *,
int *, int *);
-extern unsigned long microblaze_get_target_address (long, bfd_boolean, int,
- long, long, long, bfd_boolean *, bfd_boolean *);
-
-extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *,
+extern unsigned long microblaze_get_target_address (long, bool, int,
+ long, long, long,
+ bool *, bool *);
+extern enum microblaze_instr get_insn_microblaze (long, bool *,
enum microblaze_instr_type *,
short *);
case 'y': MAPPED_REG (0, 0, GP, reg_31_map);
case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
- case 'A': INT_ADJ (7, 0, 63, 2, FALSE); /* (-64 .. 63) << 2 */
- case 'B': MAPPED_INT (3, 1, int_b_map, FALSE);
- case 'C': MAPPED_INT (4, 0, int_c_map, TRUE);
+ case 'A': INT_ADJ (7, 0, 63, 2, false); /* (-64 .. 63) << 2 */
+ case 'B': MAPPED_INT (3, 1, int_b_map, false);
+ case 'C': MAPPED_INT (4, 0, int_c_map, true);
case 'D': BRANCH (10, 0, 1);
case 'E': BRANCH (7, 0, 1);
case 'F': HINT (4, 0);
- case 'G': INT_ADJ (4, 0, 14, 0, FALSE); /* (-1 .. 14) */
- case 'H': INT_ADJ (4, 0, 15, 1, FALSE); /* (0 .. 15) << 1 */
- case 'I': INT_ADJ (7, 0, 126, 0, FALSE); /* (-1 .. 126) */
- case 'J': INT_ADJ (4, 0, 15, 2, FALSE); /* (0 .. 15) << 2 */
- case 'L': INT_ADJ (4, 0, 15, 0, FALSE); /* (0 .. 15) */
- case 'M': INT_ADJ (3, 1, 8, 0, FALSE); /* (1 .. 8) */
+ case 'G': INT_ADJ (4, 0, 14, 0, false); /* (-1 .. 14) */
+ case 'H': INT_ADJ (4, 0, 15, 1, false); /* (0 .. 15) << 1 */
+ case 'I': INT_ADJ (7, 0, 126, 0, false); /* (-1 .. 126) */
+ case 'J': INT_ADJ (4, 0, 15, 2, false); /* (0 .. 15) << 2 */
+ case 'L': INT_ADJ (4, 0, 15, 0, false); /* (0 .. 15) */
+ case 'M': INT_ADJ (3, 1, 8, 0, false); /* (1 .. 8) */
case 'N': SPECIAL (2, 4, LWM_SWM_LIST);
case 'O': HINT (4, 0);
- case 'P': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
- case 'Q': INT_ADJ (23, 0, 4194303, 2, FALSE);
+ case 'P': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */
+ case 'Q': INT_ADJ (23, 0, 4194303, 2, false);
/* (-4194304 .. 4194303) */
- case 'U': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
- case 'W': INT_ADJ (6, 1, 63, 2, FALSE); /* (0 .. 63) << 2 */
+ case 'U': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */
+ case 'W': INT_ADJ (6, 1, 63, 2, false); /* (0 .. 63) << 2 */
case 'X': SINT (4, 1);
case 'Y': SPECIAL (9, 1, ADDIUSP_INT);
case 'Z': UINT (0, 0); /* 0 only */
switch (p[1])
{
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
- case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */
- case 'C': MSB (5, 11, 1, FALSE, 32); /* (1 .. 32), 32-bit op */
+ case 'B': MSB (5, 11, 1, true, 32); /* (1 .. 32), 32-bit op */
+ case 'C': MSB (5, 11, 1, false, 32); /* (1 .. 32), 32-bit op */
case 'E': BIT (5, 6, 32); /* (32 .. 63) */
- case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */
- case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
- case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
+ case 'F': MSB (5, 11, 33, true, 64); /* (33 .. 64), 64-bit op */
+ case 'G': MSB (5, 11, 33, false, 64); /* (33 .. 64), 64-bit op */
+ case 'H': MSB (5, 11, 1, false, 64); /* (1 .. 32), 64-bit op */
case 'J': HINT (10, 16);
- case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
- case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
- case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
- case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */
+ case 'T': INT_ADJ (10, 16, 511, 0, false); /* (-512 .. 511) << 0 */
+ case 'U': INT_ADJ (10, 16, 511, 1, false); /* (-512 .. 511) << 1 */
+ case 'V': INT_ADJ (10, 16, 511, 2, false); /* (-512 .. 511) << 2 */
+ case 'W': INT_ADJ (10, 16, 511, 3, false); /* (-512 .. 511) << 3 */
case 'd': REG (5, 6, MSA);
case 'e': REG (5, 11, MSA);
/* Parse an ASE disassembler option and set the corresponding global
ASE flag(s). Return TRUE if successful, FALSE otherwise. */
-static bfd_boolean
+static bool
parse_mips_ase_option (const char *option)
{
if (startswith (option, "msa"))
|| (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5
|| (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)
mips_ase |= ASE_MSA64;
- return TRUE;
+ return true;
}
if (startswith (option, "virt"))
|| mips_isa & ISA_MIPS64R5
|| mips_isa & ISA_MIPS64R6)
mips_ase |= ASE_VIRT64;
- return TRUE;
+ return true;
}
if (startswith (option, "xpa"))
{
mips_ase |= ASE_XPA;
- return TRUE;
+ return true;
}
if (startswith (option, "ginv"))
{
mips_ase |= ASE_GINV;
- return TRUE;
+ return true;
}
if (startswith (option, "loongson-mmi"))
{
mips_ase |= ASE_LOONGSON_MMI;
- return TRUE;
+ return true;
}
if (startswith (option, "loongson-cam"))
{
mips_ase |= ASE_LOONGSON_CAM;
- return TRUE;
+ return true;
}
/* Put here for match ext2 frist */
if (startswith (option, "loongson-ext2"))
{
mips_ase |= ASE_LOONGSON_EXT2;
- return TRUE;
+ return true;
}
if (startswith (option, "loongson-ext"))
{
mips_ase |= ASE_LOONGSON_EXT;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static void
/* Validate the arguments for INSN, which is described by OPCODE.
Use DECODE_OPERAND to get the encoding of each operand. */
-static bfd_boolean
+static bool
validate_insn_args (const struct mips_opcode *opcode,
const struct mips_operand *(*decode_operand) (const char *),
unsigned int insn)
reg2 = uval >> 5;
if (reg1 != reg2 || reg1 == 0)
- return FALSE;
+ return false;
}
break;
prev_op = (const struct mips_check_prev_operand *) operand;
if (!prev_op->zero_ok && uval == 0)
- return FALSE;
+ return false;
if (((prev_op->less_than_ok && uval < state.last_regno)
|| (prev_op->greater_than_ok && uval > state.last_regno)
|| (prev_op->equal_ok && uval == state.last_regno)))
break;
- return FALSE;
+ return false;
}
case OP_NON_ZERO_REG:
{
if (uval == 0)
- return FALSE;
+ return false;
}
break;
++s;
}
}
- return TRUE;
+ return true;
}
/* Print the arguments for INSN, which is described by OPCODE.
static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op;
- static bfd_boolean init = 0;
+ static bool init = 0;
void *is = info->stream;
/* Build a hash table to shorten the search time. */
struct mips_print_arg_state *state,
const struct mips_opcode *opcode,
char type, bfd_vma memaddr,
- unsigned insn, bfd_boolean use_extend,
- unsigned extend, bfd_boolean is_offset)
+ unsigned insn, bool use_extend,
+ unsigned extend, bool is_offset)
{
const fprintf_ftype infprintf = info->fprintf_func;
void *is = info->stream;
break;
default:
- operand = decode_mips16_operand (type, FALSE);
+ operand = decode_mips16_operand (type, false);
if (!operand)
{
/* xgettext:c-format */
ext_size = 0;
if (use_extend)
{
- ext_operand = decode_mips16_operand (type, TRUE);
+ ext_operand = decode_mips16_operand (type, true);
if (ext_operand != operand
|| (operand->type == OP_INT && operand->lsb == 0
&& mips_opcode_32bit_p (opcode)))
This word is data and depending on the value it may interfere with
disassembly of further PLT entries. We make use of the fact PLT
symbols are marked BSF_SYNTHETIC. */
-static bfd_boolean
+static bool
is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
{
if (info->symbols
&& info->symbols[0]
&& (info->symbols[0]->flags & BSF_SYNTHETIC)
&& addr == bfd_asymbol_value (info->symbols[0]) + 12)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Whether none, a 32-bit or a 16-bit instruction match has been done. */
const struct mips_opcode *op, *opend;
struct mips_print_arg_state state;
void *is = info->stream;
- bfd_boolean have_second;
- bfd_boolean extend_only;
+ bool have_second;
+ bool extend_only;
unsigned int second;
unsigned int first;
unsigned int full;
return -1;
}
- extend_only = FALSE;
+ extend_only = false;
if (info->endian == BFD_ENDIAN_BIG)
first = bfd_getb16 (buffer);
status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
if (status == 0)
{
- have_second = TRUE;
+ have_second = true;
if (info->endian == BFD_ENDIAN_BIG)
second = bfd_getb16 (buffer);
else
}
else
{
- have_second = FALSE;
+ have_second = false;
second = 0;
full = first;
}
if (op->pinfo2 & INSN2_SHORT_ONLY)
{
match = MATCH_NONE;
- extend_only = TRUE;
+ extend_only = true;
}
else
match = MATCH_FULL;
const struct mips_operand *operand;
unsigned int reg, sel;
- operand = decode_mips16_operand (*s, TRUE);
+ operand = decode_mips16_operand (*s, true);
reg = mips_extract_operand (operand, (first << 16) | second);
s += 2;
- operand = decode_mips16_operand (*s, TRUE);
+ operand = decode_mips16_operand (*s, true);
sel = mips_extract_operand (operand, (first << 16) | second);
/* CP0 register including 'sel' code for mftc0, to be
{
case MATCH_FULL:
print_mips16_insn_arg (info, &state, op, *s, memaddr + 2,
- second, TRUE, first, s[1] == '(');
+ second, true, first, s[1] == '(');
break;
case MATCH_SHORT:
print_mips16_insn_arg (info, &state, op, *s, memaddr,
- first, FALSE, 0, s[1] == '(');
+ first, false, 0, s[1] == '(');
break;
case MATCH_NONE: /* Stop the compiler complaining. */
break;
have been derived from function symbols defined elsewhere or could
define data). Otherwise, return 0. */
-static bfd_boolean
-is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p)
+static bool
+is_compressed_mode_p (struct disassemble_info *info, bool micromips_p)
{
int i;
int l;
#endif
#if SYMTAB_AVAILABLE
- if (is_compressed_mode_p (info, TRUE))
+ if (is_compressed_mode_p (info, true))
return print_insn_micromips (memaddr, info);
- if (is_compressed_mode_p (info, FALSE))
+ if (is_compressed_mode_p (info, false))
return print_insn_mips16 (memaddr, info);
#endif
INT_BIAS(SIZE, LSB, MAX_VAL, 0, SHIFT, PRINT_HEX)
#define UINT(SIZE, LSB) \
- INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, FALSE)
+ INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, false)
#define SINT(SIZE, LSB) \
- INT_ADJ(SIZE, LSB, (1 << ((SIZE) - 1)) - 1, 0, FALSE)
+ INT_ADJ(SIZE, LSB, (1 << ((SIZE) - 1)) - 1, 0, false)
#define HINT(SIZE, LSB) \
- INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, TRUE)
+ INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, true)
#define BIT(SIZE, LSB, BIAS) \
{ \
static const struct mips_int_operand op = { \
- { OP_INT, SIZE, LSB }, (1 << (SIZE)) - 1, BIAS, 0, TRUE \
+ { OP_INT, SIZE, LSB }, (1 << (SIZE)) - 1, BIAS, 0, true \
}; \
return &op.root; \
}
{ \
static const struct mips_pcrel_operand op = { \
{ { OP_PCREL, SIZE, LSB }, \
- (1 << ((SIZE) - (IS_SIGNED))) - 1, 0, SHIFT, TRUE }, \
+ (1 << ((SIZE) - (IS_SIGNED))) - 1, 0, SHIFT, true }, \
ALIGN_LOG2, INCLUDE_ISA_BIT, FLIP_ISA_BIT \
}; \
return &op.root.root; \
}
#define JUMP(SIZE, LSB, SHIFT) \
- PCREL (SIZE, LSB, FALSE, SHIFT, SIZE + SHIFT, TRUE, FALSE)
+ PCREL (SIZE, LSB, false, SHIFT, SIZE + SHIFT, true, false)
#define JALX(SIZE, LSB, SHIFT) \
- PCREL (SIZE, LSB, FALSE, SHIFT, SIZE + SHIFT, TRUE, TRUE)
+ PCREL (SIZE, LSB, false, SHIFT, SIZE + SHIFT, true, true)
#define BRANCH(SIZE, LSB, SHIFT) \
- PCREL (SIZE, LSB, TRUE, SHIFT, 0, TRUE, FALSE)
+ PCREL (SIZE, LSB, true, SHIFT, 0, true, false)
#define SPECIAL(SIZE, LSB, TYPE) \
{ \
case '-':
switch (p[1])
{
- case 'a': INT_ADJ (19, 0, 262143, 2, FALSE);
- case 'b': INT_ADJ (18, 0, 131071, 3, FALSE);
+ case 'a': INT_ADJ (19, 0, 262143, 2, false);
+ case 'b': INT_ADJ (18, 0, 131071, 3, false);
case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
case 'm': SPECIAL (20, 6, SAVE_RESTORE_LIST);
case 's': SPECIAL (5, 21, NON_ZERO_REG);
case 't': SPECIAL (5, 16, NON_ZERO_REG);
- case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
- case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
- case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
- case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
- case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE);
- case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
- case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
+ case 'u': PREV_CHECK (5, 16, true, false, false, false);
+ case 'v': PREV_CHECK (5, 16, true, true, false, false);
+ case 'w': PREV_CHECK (5, 16, false, true, true, true);
+ case 'x': PREV_CHECK (5, 21, true, false, false, true);
+ case 'y': PREV_CHECK (5, 21, false, true, false, false);
+ case 'A': PCREL (19, 0, true, 2, 2, false, false);
+ case 'B': PCREL (18, 0, true, 3, 3, false, false);
}
break;
case '0': REG (5, 16, VI);
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
- case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */
- case 'C': MSB (5, 11, 1, FALSE, 32); /* (1 .. 32), 32-bit op */
+ case 'B': MSB (5, 11, 1, true, 32); /* (1 .. 32), 32-bit op */
+ case 'C': MSB (5, 11, 1, false, 32); /* (1 .. 32), 32-bit op */
case 'E': BIT (5, 6, 32); /* (32 .. 63) */
- case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */
- case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
- case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
+ case 'F': MSB (5, 11, 33, true, 64); /* (33 .. 64), 64-bit op */
+ case 'G': MSB (5, 11, 33, false, 64); /* (33 .. 64), 64-bit op */
+ case 'H': MSB (5, 11, 1, false, 64); /* (1 .. 32), 64-bit op */
case 'I': UINT (2, 6);
case 'J': HINT (10, 11);
case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX);
case 'P': BIT (5, 6, 32); /* (32 .. 63) */
case 'Q': SINT (10, 6);
case 'R': SPECIAL (0, 0, PC);
- case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */
- case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
- case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
- case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
- case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */
+ case 'S': MSB (5, 11, 0, false, 63); /* (0 .. 31), 64-bit op */
+ case 'T': INT_ADJ (10, 16, 511, 0, false); /* (-512 .. 511) << 0 */
+ case 'U': INT_ADJ (10, 16, 511, 1, false); /* (-512 .. 511) << 1 */
+ case 'V': INT_ADJ (10, 16, 511, 2, false); /* (-512 .. 511) << 2 */
+ case 'W': INT_ADJ (10, 16, 511, 3, false); /* (-512 .. 511) << 3 */
case 'X': BIT (5, 16, 32); /* (32 .. 63) */
case 'Z': REG (5, 0, FP);
case 'a': SINT (8, 6);
case 'b': SINT (8, 3);
- case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */
+ case 'c': INT_ADJ (9, 6, 255, 4, false); /* (-256 .. 255) << 4 */
case 'd': REG (5, 6, MSA);
case 'e': REG (5, 11, MSA);
- case 'f': INT_ADJ (15, 6, 32767, 3, TRUE);
+ case 'f': INT_ADJ (15, 6, 32767, 3, true);
case 'g': SINT (5, 6);
case 'h': REG (5, 16, MSA);
case 'i': JALX (26, 0, 2);
case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */
case 'q': REG (0, 0, R5900_Q);
case 'r': REG (0, 0, R5900_R);
- case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */
+ case 's': MSB (5, 11, 0, false, 31); /* (0 .. 31) */
case 't': REG (5, 16, COPRO);
case 'u': SPECIAL (3, 16, IMM_INDEX);
case 'v': SPECIAL (2, 16, IMM_INDEX);
The extended forms all have an lsb of 0. */
const struct mips_operand *
-decode_mips16_operand (char type, bfd_boolean extended_p)
+decode_mips16_operand (char type, bool extended_p)
{
switch (type)
{
case 'a': JUMP (26, 0, 2);
case 'b': BIT (5, 22, 0); /* (0 .. 31) */
- case 'c': MSB (5, 16, 1, TRUE, 32); /* (1 .. 32) */
- case 'd': MSB (5, 16, 1, FALSE, 32); /* (1 .. 32) */
+ case 'c': MSB (5, 16, 1, true, 32); /* (1 .. 32) */
+ case 'd': MSB (5, 16, 1, false, 32); /* (1 .. 32) */
case 'e': HINT (11, 0);
case 'i': JALX (26, 0, 2);
case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
- case 'n': INT_BIAS (2, 0, 3, 1, 0, FALSE); /* (1 .. 4) */
- case 'o': INT_ADJ (5, 16, 31, 4, FALSE); /* (0 .. 31) << 4 */
+ case 'n': INT_BIAS (2, 0, 3, 1, 0, false); /* (1 .. 4) */
+ case 'o': INT_ADJ (5, 16, 31, 4, false); /* (0 .. 31) << 4 */
case 'r': MAPPED_REG (3, 16, GP, reg_m16_map);
case 's': HINT (3, 24);
case 'u': HINT (16, 0);
case '5': SINT (16, 0);
case '8': SINT (16, 0);
- case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
- case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
+ case 'A': PCREL (16, 0, true, 0, 2, false, false);
+ case 'B': PCREL (16, 0, true, 0, 3, false, false);
case 'C': SINT (16, 0);
case 'D': SINT (16, 0);
- case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
+ case 'E': PCREL (16, 0, true, 0, 2, false, false);
case 'F': SINT (15, 0);
case 'H': SINT (16, 0);
case 'K': SINT (16, 0);
else
switch (type)
{
- case '<': INT_ADJ (3, 2, 8, 0, FALSE);
- case '[': INT_ADJ (3, 2, 8, 0, FALSE);
- case ']': INT_ADJ (3, 8, 8, 0, FALSE);
+ case '<': INT_ADJ (3, 2, 8, 0, false);
+ case '[': INT_ADJ (3, 2, 8, 0, false);
+ case ']': INT_ADJ (3, 8, 8, 0, false);
case '5': UINT (5, 0);
case '8': UINT (8, 0);
- case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
- case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
- case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
- case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
- case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
+ case 'A': PCREL (8, 0, false, 2, 2, false, false);
+ case 'B': PCREL (5, 0, false, 3, 3, false, false);
+ case 'C': INT_ADJ (8, 0, 255, 3, false); /* (0 .. 255) << 3 */
+ case 'D': INT_ADJ (5, 0, 31, 3, false); /* (0 .. 31) << 3 */
+ case 'E': PCREL (5, 0, false, 2, 2, false, false);
case 'F': SINT (4, 0);
- case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
- case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
+ case 'H': INT_ADJ (5, 0, 31, 1, false); /* (0 .. 31) << 1 */
+ case 'K': INT_ADJ (8, 0, 127, 3, false); /* (-128 .. 127) << 3 */
case 'U': UINT (8, 0);
- case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
- case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
+ case 'V': INT_ADJ (8, 0, 255, 2, false); /* (0 .. 255) << 2 */
+ case 'W': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */
case 'j': SINT (5, 0);
case 'k': SINT (8, 0);
/* Initialize a target-specific array in INFO. */
-static bfd_boolean
+static bool
initialize_mmix_dis_info (struct disassemble_info *info)
{
struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info));
long i;
if (minfop == NULL)
- return FALSE;
+ return false;
memset (minfop, 0, sizeof (*minfop));
{
FATAL_DEBUG;
free (minfop);
- return FALSE;
+ return false;
}
nsyms = bfd_canonicalize_symtab (abfd, syms);
minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name;
info->private_data = (void *) minfop;
- return TRUE;
+ return true;
}
/* A table indexed by the first byte is constructed as we disassemble each
#define PS(x) (0xffff & (x))
-static bfd_boolean
+static bool
msp430dis_read_two_bytes (bfd_vma addr,
disassemble_info * info,
bfd_byte * buffer,
status = info->read_memory_func (addr, buffer, 2, info);
if (status == 0)
- return TRUE;
+ return true;
/* PR 20150: A status of EIO means that there were no more bytes left
to read in the current section. This can happen when disassembling
sprintf (comm, _("Error: read from memory failed"));
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
msp430dis_opcode_unsigned (bfd_vma addr,
disassemble_info * info,
unsigned short * return_val,
if (msp430dis_read_two_bytes (addr, info, buffer, comm))
{
* return_val = bfd_getl16 (buffer);
- return TRUE;
+ return true;
}
else
{
* return_val = 0;
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
msp430dis_opcode_signed (bfd_vma addr,
disassemble_info * info,
signed int * return_val,
if (status & 0x8000)
status |= -1U << 16;
* return_val = status;
- return TRUE;
+ return true;
}
else
{
* return_val = 0;
- return FALSE;
+ return false;
}
}
int n;
int last_symbol_index = -1;
bfd_vma addr;
- int is_data = FALSE;
- bfd_boolean found = FALSE;
+ int is_data = false;
+ bool found = false;
struct nds32_private_data *private_data;
unsigned int size;
enum map_type mapping_type = MAP_CODE;
if (get_mapping_symbol_type (info, n, &mapping_type))
{
last_symbol_index = n;
- found = TRUE;
+ found = true;
}
}
/* Ignore disassembling unnecessary name. */
-static bfd_boolean
+static bool
nds32_symbol_is_valid (asymbol *sym,
struct disassemble_info *info ATTRIBUTE_UNUSED)
{
const char *name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
/* Mapping symbol is invalid. */
if (name[0] == '$')
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
static void
if (name[1] == 'c')
{
*map_type = MAP_CODE;
- return TRUE;
+ return true;
}
else if (name[1] == 'd' && name[2] == '0')
{
*map_type = MAP_DATA0;
- return TRUE;
+ return true;
}
else if (name[1] == 'd' && name[2] == '1')
{
*map_type = MAP_DATA1;
- return TRUE;
+ return true;
}
else if (name[1] == 'd' && name[2] == '2')
{
*map_type = MAP_DATA2;
- return TRUE;
+ return true;
}
else if (name[1] == 'd' && name[2] == '3')
{
*map_type = MAP_DATA3;
- return TRUE;
+ return true;
}
else if (name[1] == 'd' && name[2] == '4')
{
*map_type = MAP_DATA4;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static int
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL
&& info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
return is_mapping_symbol (info, n, map_type);
}
return _NFP_ERR_CONT;
}
-static bfd_boolean
+static bool
nfp_me_is_imm_opnd10 (unsigned int opnd)
{
return _BF (opnd, 9, 8) == 0x3;
}
-static bfd_boolean
+static bool
nfp_me_is_imm_opnd8 (unsigned int opnd)
{
return _BTST (opnd, 5);
/* Print an unrestricted/10-bit operand.
This can mostly be generic across NFP families at the moment. */
-static bfd_boolean
+static bool
nfp_me_print_opnd10 (unsigned int opnd, char bank, int num_ctx, int lmem_ext,
struct disassemble_info *dinfo)
{
else
{
dinfo->fprintf_func (dinfo->stream, "<opnd:0x%x>", opnd);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Print a restricted/8-bit operand.
This can mostly be generic across NFP families at the moment. */
-static bfd_boolean
+static bool
nfp_me_print_opnd8 (unsigned int opnd, char bank, int num_ctx, int lmem_ext,
unsigned int imm8_msb, struct disassemble_info *dinfo)
{
else
{
dinfo->fprintf_func (dinfo->stream, "<opnd:0x%x>", opnd);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
static int
unsigned int shift = _BF (instr, 32, 28);
char dst_bank = 'A' + _BTST (instr, 36);
unsigned int nocc = _BTST (instr, 40);
- bfd_boolean err = FALSE;
+ bool err = false;
if (swap)
{
char dst_bank = 'A' + _BTST (instr, 36);
unsigned int nocc = _BTST (instr, 40);
int do_close_bracket = 1;
- bfd_boolean err = FALSE;
+ bool err = false;
if (swap)
{
if (!nfp_me27_28_crc_op[_BF (srcA, 7, 5)])
{
dinfo->fprintf_func (dinfo->stream, _(", <invalid CRC operator>, "));
- err = TRUE;
+ err = true;
}
else
{
if (!nfp_me27_28_alu_op[op])
{
dinfo->fprintf_func (dinfo->stream, ", <operator:0x%x>, ", op);
- err = TRUE;
+ err = true;
}
else
{
unsigned int wd = _BTST (instr, 30);
unsigned int inv = _BTST (instr, 31);
unsigned int byte_shift = _BF (instr, 34, 33);
- bfd_boolean err = FALSE;
+ bool err = false;
if (nfp_me_is_imm_opnd10 (srcB))
{
unsigned int src = _BF (instr, 17, 10);
unsigned int sc = _BF (instr, 9, 8);
unsigned int dst = _BF (instr, 7, 0);
- bfd_boolean err = FALSE;
+ bool err = false;
if (swap)
{
unsigned int csr_num = _BF (instr, 32, 22);
unsigned int src = srcA;
char src_bank = 'A';
- bfd_boolean err = FALSE;
+ bool err = false;
if (nfp_me_is_imm_opnd10 (srcA) && !nfp_me_is_imm_opnd10 (srcB))
{
unsigned int eq = _BTST (instr, 19);
unsigned int defer = _BF (instr, 21, 20);
unsigned int br_addr = _BFS (instr, 40, 40, 13) | _BF (instr, 34, 22);
- bfd_boolean err = FALSE;
+ bool err = false;
if (eq)
dinfo->fprintf_func (dinfo->stream, "br=byte[");
unsigned int b = _BTST (instr, 18);
unsigned int defer = _BF (instr, 21, 20);
unsigned int br_addr = _BFS (instr, 40, 40, 13) | _BF (instr, 34, 22);
- bfd_boolean err = FALSE;
+ bool err = false;
if (b)
dinfo->fprintf_func (dinfo->stream, "br_bset[");
unsigned int srcB = _BF (instr, 19, 10);
unsigned int defer = _BF (instr, 21, 20);
unsigned int imm = _BF (instr, 30, 22);
- bfd_boolean err = FALSE;
+ bool err = false;
if (nfp_me_is_imm_opnd10 (srcA))
imm = (imm << 8) | nfp_me_imm_opnd10 (srcA);
unsigned int swap = _BTST (instr, 30);
unsigned int mtype = _BF (instr, 32, 31);
unsigned int nocc = _BTST (instr, 40);
- bfd_boolean err = FALSE;
+ bool err = false;
if (swap)
{
if (!s)
{
s = "<invalid mul_step>";
- err = TRUE;
+ err = true;
}
dinfo->fprintf_func (dinfo->stream, "_%s", s);
}
unsigned int indref = _BTST (instr, 41);
unsigned int mode = _BF (instr, 44, 42);
- bfd_boolean err = FALSE;
+ bool err = false;
int cpp_target = -1;
int cpp_action = -1;
const char *mnemonic = NULL;
unsigned int indref = _BTST (instr, 41);
unsigned int mode = _BF (instr, 44, 42);
- bfd_boolean err = FALSE;
+ bool err = false;
int cpp_target = -1;
int cpp_action = -1;
const char *mnemonic = NULL;
gpr_wrboth, num_ctx, dinfo);
}
-static bfd_boolean
+static bool
init_nfp3200_priv (nfp_priv_data * priv, struct disassemble_info *dinfo)
{
Elf_Internal_Shdr *sec = NULL;
if (!dinfo->section)
/* No section info, will use default values. */
- return TRUE;
+ return true;
sec_cnt = elf_numsections (dinfo->section->owner);
if (sec_idx == sec_cnt)
{
dinfo->fprintf_func (dinfo->stream, _("File has no ME-Config section."));
- return FALSE;
+ return false;
}
for (roff = 0; (bfd_size_type) roff < sec->sh_size;
{
dinfo->fprintf_func (dinfo->stream,
_("File has invalid ME-Config section."));
- return FALSE;
+ return false;
}
mecfg = &priv->mecfgs[isl][menum][1];
if (!bfd_get_section_contents (dinfo->section->owner, sec->bfd_section,
buffer, roff, sizeof (buffer)))
- return FALSE;
+ return false;
mecfg_ent.ctx_enables = bfd_getl32 (buffer + offsetof (Elf_Nfp_MeConfig,
ctx_enables));
mecfg->scs_cnt = _BTST (mecfg_ent.misc_control, 2);
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
init_nfp6000_mecsr_sec (nfp_priv_data * priv, Elf_Internal_Shdr * sec,
int is_for_text, struct disassemble_info *dinfo)
{
size_t isl, menum;
if (sec->sh_entsize != sizeof (ireg))
- return FALSE;
+ return false;
isl = SHI_NFP_IREG_ISLAND (sec->sh_info);
if (!bfd_get_section_contents (dinfo->section->owner, sec->bfd_section,
buffer, ireg_off, sizeof (buffer)))
- return FALSE;
+ return false;
ireg.cpp_offset_lo = bfd_getl32 (buffer
+ offsetof (Elf_Nfp_InitRegEntry, cpp_offset_lo));
}
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
init_nfp6000_priv (nfp_priv_data * priv, struct disassemble_info *dinfo)
{
int mecfg_orders[64][2];
if (!dinfo->section)
/* No section info, will use default values. */
- return TRUE;
+ return true;
sec_cnt = elf_numsections (dinfo->section->owner);
{
dinfo->fprintf_func (dinfo->stream,
_("Error processing section %u "), sec_idx);
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
static int
init_nfp_priv (struct disassemble_info *dinfo)
{
nfp_priv_data *priv;
- int ret = FALSE;
+ int ret = false;
if (dinfo->private_data)
return (nfp_priv_data *) dinfo->private_data;
nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
const struct nios2_opcode *nop;
- bfd_boolean init;
+ bool init;
} nios2_disassembler_state;
static nios2_disassembler_state
#define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
-static bfd_boolean
+static bool
ppc_symbol_is_valid (asymbol *sym,
struct disassemble_info *info ATTRIBUTE_UNUSED)
{
elf_symbol_type * est;
if (sym == NULL)
- return FALSE;
+ return false;
est = elf_symbol_from (sym);
&& ELF_ST_VISIBILITY (est->internal_elf_sym.st_other) == STV_HIDDEN
&& ELF_ST_BIND (est->internal_elf_sym.st_info) == STB_LOCAL
&& ELF_ST_TYPE (est->internal_elf_sym.st_info) == STT_NOTYPE)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Calculate opcode table indices to speed up disassembly,
/* Determine whether the optional operand(s) should be printed. */
-static bfd_boolean
+static bool
skip_optional_operands (const unsigned char *opindex,
uint64_t insn, ppc_cpu_t dialect)
{
{
operand = &powerpc_operands[*opindex];
if ((operand->flags & PPC_OPERAND_NEXT) != 0)
- return FALSE;
+ return false;
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
{
/* Negative count is used as a flag to extract function. */
if (operand_value_powerpc (operand, insn, dialect)
!= ppc_optional_operand_value (operand, insn, dialect,
num_optional))
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
/* Find a match for INSN in the opcode table, given machine DIALECT. */
{
uint64_t table_opcd = opcode->opcode;
uint64_t table_mask = opcode->mask;
- bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
+ bool table_op_is_short = PPC_OP_SE_VLE(table_mask);
uint64_t insn2;
const unsigned char *opindex;
const struct powerpc_operand *operand;
need_7spaces = 7,
need_paren
} op_separator;
- bfd_boolean skip_optional;
+ bool skip_optional;
int blanks;
(*info->fprintf_func) (info->stream, "%s", opcode->name);
/* Now extract and print the operands. */
op_separator = blanks;
- skip_optional = FALSE;
+ skip_optional = false;
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
int64_t value;
no_aliases = 0;
}
-static bfd_boolean
+static bool
parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
static void
case 'E':
{
static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */
- static bfd_boolean init_csr = FALSE;
+ static bool init_csr = false;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
if (!init_csr)
riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
{
const struct riscv_opcode *op;
- static bfd_boolean init = 0;
+ static bool init = 0;
static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
struct riscv_private_data *pd;
int insnlen;
/* Prevent use of the fake labels that are generated as part of the DWARF
and for relaxable relocations in the assembler. */
-bfd_boolean
+bool
riscv_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
#ifdef BFD64
/* s3_s7: opcodes and export prototypes. */
extern int
-s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
+s7_print_insn (bfd_vma pc, struct disassemble_info *info, bool little);
struct score_opcode
{
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
static int
-s3_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+s3_print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
{
unsigned char b[6];
bfd_vma given, given_h, given_l, given_16, given_32, given_48;
print_insn_big_score (bfd_vma pc, struct disassemble_info *info)
{
if (score_get_arch (info) == bfd_mach_score3)
- return s3_print_insn (pc, info, FALSE);
+ return s3_print_insn (pc, info, false);
else
- return s7_print_insn (pc, info, FALSE);
+ return s7_print_insn (pc, info, false);
}
int
print_insn_little_score (bfd_vma pc, struct disassemble_info *info)
{
if (score_get_arch (info) == bfd_mach_score3)
- return s3_print_insn (pc, info, TRUE);
+ return s3_print_insn (pc, info, true);
else
- return s7_print_insn (pc, info, TRUE);
+ return s7_print_insn (pc, info, true);
}
#else /* not BFD64 */
int
/* s3_s7: opcodes and export prototypes. */
int
-s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
+s7_print_insn (bfd_vma pc, struct disassemble_info *info, bool little);
/* Print one instruction from PC on INFO->STREAM.
Return the size of the instruction. */
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
int
-s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+s7_print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
{
unsigned char b[4];
unsigned long given;
long ridparity;
int status;
- bfd_boolean insn_pce_p = FALSE;
- bfd_boolean insn_16_p = FALSE;
+ bool insn_pce_p = false;
+ bool insn_16_p = false;
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
- insn_16_p = TRUE;
+ insn_16_p = true;
}
else
{
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
- insn_16_p = TRUE;
+ insn_16_p = true;
}
}
if ((given & 0x80008000) == 0x80008000)
{
- insn_pce_p = FALSE;
- insn_16_p = FALSE;
+ insn_pce_p = false;
+ insn_16_p = false;
}
else if ((given & 0x8000) == 0x8000)
- insn_pce_p = TRUE;
+ insn_pce_p = true;
else
- insn_16_p = TRUE;
+ insn_16_p = true;
/* 16 bit instruction. */
if (insn_16_p)
#define OPCODES_SIGSETJMP(buf) setjmp(buf)
#define OPCODES_SIGLONGJMP(buf,val) longjmp((buf), (val))
#endif
+
+#define POISON_BFD_BOOLEAN 1
/* FP points to a fetch packet. Return whether it is header-based; if
it is, fill in HEADER. */
-static bfd_boolean
+static bool
tic6x_check_fetch_packet_header (unsigned char *fp,
tic6x_fetch_packet_header *header,
struct disassemble_info *info)
header->br = 0;
header->sat = 0;
for (i = 0; i < 7; i++)
- header->word_compact[i] = FALSE;
+ header->word_compact[i] = false;
for (i = 0; i < 14; i++)
- header->p_bits[i] = FALSE;
- return FALSE;
+ header->p_bits[i] = false;
+ return false;
}
for (i = 0; i < 7; i++)
for (i = 0; i < 14; i++)
header->p_bits[i] = (header->header & (1u << i)) != 0;
- return TRUE;
+ return true;
}
/* Disassemble the instruction at ADDR and print it using
unsigned char fp[32];
unsigned int opcode;
tic6x_opcode_id opcode_id;
- bfd_boolean fetch_packet_header_based;
+ bool fetch_packet_header_based;
tic6x_fetch_packet_header header;
unsigned int num_bits;
- bfd_boolean bad_offset = FALSE;
+ bool bad_offset = false;
fp_offset = addr & 0x1f;
fp_addr = addr - fp_offset;
if (fetch_packet_header_based)
{
if (fp_offset & 0x1)
- bad_offset = TRUE;
+ bad_offset = true;
if ((fp_offset & 0x3) && (fp_offset >= 28
|| !header.word_compact[fp_offset >> 2]))
- bad_offset = TRUE;
+ bad_offset = true;
if (fp_offset == 28)
{
info->bytes_per_chunk = 4;
{
num_bits = 32;
if (fp_offset & 0x3)
- bad_offset = TRUE;
+ bad_offset = true;
}
if (bad_offset)
const tic6x_insn_format *const fmt
= &tic6x_insn_format_table[opc->format];
const tic6x_insn_field *creg_field;
- bfd_boolean p_bit;
+ bool p_bit;
const char *parallel;
const char *cond = "";
const char *func_unit;
separating commas and trailing NUL). */
char operands[TIC6X_MAX_OPERANDS][24] = { { 0 } };
bfd_vma operands_addresses[TIC6X_MAX_OPERANDS] = { 0 };
- bfd_boolean operands_text[TIC6X_MAX_OPERANDS] = { FALSE };
- bfd_boolean operands_pcrel[TIC6X_MAX_OPERANDS] = { FALSE };
+ bool operands_text[TIC6X_MAX_OPERANDS] = { false };
+ bool operands_pcrel[TIC6X_MAX_OPERANDS] = { false };
unsigned int fix;
unsigned int num_operands;
unsigned int op_num;
- bfd_boolean fixed_ok;
- bfd_boolean operands_ok;
- bfd_boolean have_t = FALSE;
+ bool fixed_ok;
+ bool operands_ok;
+ bool have_t = false;
if (opc->flags & TIC6X_FLAG_MACRO)
continue;
const tic6x_insn_field *cc_field;
unsigned int s_value = 0;
unsigned int z_value = 0;
- bfd_boolean cond_known = FALSE;
+ bool cond_known = false;
static const char *const conds[2][2] =
{
{ "[a0] ", "[!a0] " },
cc_value = tic6x_field_bits (opcode, cc_field);
s_value = (cc_value & 0x2) >> 1;
z_value = (cc_value & 0x1);
- cond_known = TRUE;
+ cond_known = true;
}
else
{
}
z_value = tic6x_field_bits (opcode, z_field);
- cond_known = TRUE;
+ cond_known = true;
}
if (!cond_known)
/* All fixed fields must have matching values; all fields with
restricted ranges must have values within those ranges. */
- fixed_ok = TRUE;
+ fixed_ok = true;
for (fix = 0; fix < opc->num_fixed_fields; fix++)
{
unsigned int field_bits;
if (field_bits < opc->fixed_fields[fix].min_val
|| field_bits > opc->fixed_fields[fix].max_val)
{
- fixed_ok = FALSE;
+ fixed_ok = false;
break;
}
}
status = info->read_memory_func (fp_addr - 32, fp_prev, 32, info);
if (status)
/* No previous instruction to be parallel with. */
- p_bit = FALSE;
+ p_bit = false;
else
{
- bfd_boolean prev_header_based;
+ bool prev_header_based;
tic6x_fetch_packet_header prev_header;
prev_header_based
unsigned int fld_num;
char func_unit_char;
const char *data_str;
- bfd_boolean have_areg = FALSE;
- bfd_boolean have_cross = FALSE;
+ bool have_areg = false;
+ bool have_cross = false;
func_unit_side = (opc->flags & TIC6X_FLAG_SIDE_B_ONLY) ? 2 : 0;
func_unit_cross = 0;
opcode, fld_num);
abort ();
}
- have_cross = TRUE;
+ have_cross = true;
func_unit_cross = fld_val;
break;
case tic6x_coding_rside:
/* If the format has a t field, use it for src/dst register side. */
- have_t = TRUE;
+ have_t = true;
t_val = fld_val;
func_unit_data_side = (t_val ? 2 : 1);
break;
case tic6x_coding_areg:
- have_areg = TRUE;
+ have_areg = true;
break;
default:
/* For each operand there must be one or more fields set based
on that operand, that can together be used to derive the
operand value. */
- operands_ok = TRUE;
+ operands_ok = true;
num_operands = opc->num_operands;
for (op_num = 0; op_num < num_operands; op_num++)
{
unsigned int fld_num;
unsigned int mem_base_reg = 0;
- bfd_boolean mem_base_reg_known = FALSE;
- bfd_boolean mem_base_reg_known_long = FALSE;
+ bool mem_base_reg_known = false;
+ bool mem_base_reg_known_long = false;
unsigned int mem_offset = 0;
- bfd_boolean mem_offset_known = FALSE;
- bfd_boolean mem_offset_known_long = FALSE;
+ bool mem_offset_known = false;
+ bool mem_offset_known_long = false;
unsigned int mem_mode = 0;
- bfd_boolean mem_mode_known = FALSE;
+ bool mem_mode_known = false;
unsigned int mem_scaled = 0;
- bfd_boolean mem_scaled_known = FALSE;
+ bool mem_scaled_known = false;
unsigned int crlo = 0;
- bfd_boolean crlo_known = FALSE;
+ bool crlo_known = false;
unsigned int crhi = 0;
- bfd_boolean crhi_known = FALSE;
- bfd_boolean spmask_skip_operand = FALSE;
+ bool crhi_known = false;
+ bool spmask_skip_operand = false;
unsigned int fcyc_bits = 0;
- bfd_boolean prev_sploop_found = FALSE;
+ bool prev_sploop_found = false;
switch (opc->operand_info[op_num].form)
{
case tic6x_operand_b15reg:
/* Fully determined by the functional unit. */
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "b15");
continue;
case tic6x_operand_zreg:
/* Fully determined by the functional unit. */
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%c0",
(func_unit_side == 2 ? 'b' : 'a'));
continue;
case tic6x_operand_retreg:
/* Fully determined by the functional unit. */
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%c3",
(func_unit_side == 2 ? 'b' : 'a'));
continue;
case tic6x_operand_irp:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "irp");
continue;
case tic6x_operand_nrp:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "nrp");
continue;
case tic6x_operand_ilc:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "ilc");
continue;
case tic6x_operand_hw_const_minus_1:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "-1");
continue;
case tic6x_operand_hw_const_0:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "0");
continue;
case tic6x_operand_hw_const_1:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "1");
continue;
case tic6x_operand_hw_const_5:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "5");
continue;
case tic6x_operand_hw_const_16:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "16");
continue;
case tic6x_operand_hw_const_24:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "24");
continue;
case tic6x_operand_hw_const_31:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "31");
continue;
{
case tic6x_operand_asm_const:
case tic6x_operand_link_const:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%u", fld_val);
break;
case tic6x_operand_mem_long:
mem_offset = fld_val;
- mem_offset_known_long = TRUE;
+ mem_offset_known_long = true;
break;
default:
break;
case tic6x_coding_lcst_high16:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%u", fld_val << 16);
break;
case tic6x_coding_scst_l3i:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
if (fld_val == 0)
{
signed_fld_val = 8;
break;
case tic6x_coding_scst:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
signed_fld_val = (signed int) fld_val;
signed_fld_val ^= (1 << (tic6x_field_width (field) - 1));
signed_fld_val -= (1 << (tic6x_field_width (field) - 1));
break;
case tic6x_coding_ucst_minus_one:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%u", fld_val + 1);
break;
signed_fld_val *= 2;
else
signed_fld_val *= 4;
- operands_pcrel[op_num] = TRUE;
+ operands_pcrel[op_num] = true;
operands_addresses[op_num] = fp_addr + signed_fld_val;
break;
case tic6x_coding_regpair_msb:
if (opc->operand_info[op_num].form != tic6x_operand_regpair)
abort ();
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%c%u:%c%u",
(func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1),
(func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1) - 1);
break;
case tic6x_coding_pcrel_half_unsigned:
- operands_pcrel[op_num] = TRUE;
+ operands_pcrel[op_num] = true;
operands_addresses[op_num] = fp_addr + 2 * fld_val;
break;
printf ("opcode %x: operand treg but missing t field\n", opcode);
abort ();
}
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = t_val ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
break;
case tic6x_operand_reg:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = (func_unit_side == 2) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
break;
case tic6x_operand_reg_nors:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = (func_unit_side == 2) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u", reg_side, fld_val);
break;
case tic6x_operand_reg_bside:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "b%u", reg_base + fld_val);
break;
case tic6x_operand_reg_bside_nors:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "b%u", fld_val);
break;
case tic6x_operand_xreg:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = ((func_unit_side == 2) ^ func_unit_cross) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
break;
case tic6x_operand_dreg:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = (func_unit_data_side == 2) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
break;
case tic6x_operand_regpair:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
if (fld_val & 1)
- operands_ok = FALSE;
+ operands_ok = false;
reg_side = (func_unit_side == 2) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u:%c%u",
reg_side, reg_base + fld_val + 1,
break;
case tic6x_operand_xregpair:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
if (fld_val & 1)
- operands_ok = FALSE;
+ operands_ok = false;
reg_side = ((func_unit_side == 2) ^ func_unit_cross) ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u:%c%u",
reg_side, reg_base + fld_val + 1,
printf ("opcode %x: operand tregpair but missing t field\n", opcode);
abort ();
}
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
if (fld_val & 1)
- operands_ok = FALSE;
+ operands_ok = false;
reg_side = t_val ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u:%c%u",
reg_side, reg_base + fld_val + 1,
break;
case tic6x_operand_dregpair:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
if (fld_val & 1)
- operands_ok = FALSE;
+ operands_ok = false;
reg_side = (func_unit_data_side) == 2 ? 'b' : 'a';
snprintf (operands[op_num], 24, "%c%u:%c%u",
reg_side, reg_base + fld_val + 1,
break;
case tic6x_operand_mem_deref:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
reg_side = func_unit_side == 2 ? 'b' : 'a';
snprintf (operands[op_num], 24, "*%c%u", reg_side, reg_base + fld_val);
break;
case tic6x_operand_mem_short:
case tic6x_operand_mem_ndw:
mem_base_reg = fld_val;
- mem_base_reg_known = TRUE;
+ mem_base_reg_known = true;
break;
default:
abort ();
}
mem_base_reg = 0x4 | fld_val;
- mem_base_reg_known = TRUE;
+ mem_base_reg_known = true;
break;
default:
switch (opc->operand_info[op_num].form)
{
case tic6x_operand_areg:
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "b%u",
fld_val ? 15u : 14u);
break;
case tic6x_operand_mem_long:
mem_base_reg = fld_val ? 15u : 14u;
- mem_base_reg_known_long = TRUE;
+ mem_base_reg_known_long = true;
break;
default:
case tic6x_coding_mem_offset_noscale:
case tic6x_coding_mem_offset:
mem_offset = fld_val;
- mem_offset_known = TRUE;
+ mem_offset_known = true;
if (num_bits == 16)
{
- mem_mode_known = TRUE;
+ mem_mode_known = true;
mem_mode = TIC6X_INSN16_MEM_MODE_VAL (opc->flags);
- mem_scaled_known = TRUE;
- mem_scaled = TRUE;
+ mem_scaled_known = true;
+ mem_scaled = true;
if (opc->flags & TIC6X_FLAG_INSN16_B15PTR)
{
- mem_base_reg_known = TRUE;
+ mem_base_reg_known = true;
mem_base_reg = 15;
}
if ( enc->coding_method == tic6x_coding_mem_offset_noscale
|| enc->coding_method == tic6x_coding_mem_offset_noscale )
- mem_scaled = FALSE;
+ mem_scaled = false;
}
break;
case tic6x_coding_mem_mode:
mem_mode = fld_val;
- mem_mode_known = TRUE;
+ mem_mode_known = true;
break;
case tic6x_coding_scaled:
mem_scaled = fld_val;
- mem_scaled_known = TRUE;
+ mem_scaled_known = true;
break;
case tic6x_coding_crlo:
crlo = fld_val;
- crlo_known = TRUE;
+ crlo_known = true;
break;
case tic6x_coding_crhi:
crhi = fld_val;
- crhi_known = TRUE;
+ crhi_known = true;
break;
case tic6x_coding_fstg:
{
bfd_vma search_fp_addr = fp_addr;
bfd_vma search_fp_offset = fp_offset;
- bfd_boolean search_fp_header_based
+ bool search_fp_header_based
= fetch_packet_header_based;
tic6x_fetch_packet_header search_fp_header = header;
unsigned char search_fp[32];
|| ((search_opcode & 0x003ffffe)
== 0x0003e000)))
{
- prev_sploop_found = TRUE;
+ prev_sploop_found = true;
sploop_ii = ((search_opcode >> 23) & 0x1f) + 1;
}
else if (search_num_bits == 16
&& (search_opcode & 0x3c7e) == 0x0c66)
{
- prev_sploop_found = TRUE;
+ prev_sploop_found = true;
sploop_ii
= (((search_opcode >> 7) & 0x7)
| ((search_opcode >> 11) & 0x8)) + 1;
else if (sploop_ii <= 14)
fcyc_bits = 4;
else
- prev_sploop_found = FALSE;
+ prev_sploop_found = false;
}
if (prev_sploop_found)
break;
}
if (!prev_sploop_found)
{
- operands_ok = FALSE;
- operands_text[op_num] = TRUE;
+ operands_ok = false;
+ operands_text[op_num] = true;
break;
}
if (fcyc_bits > tic6x_field_width(field))
int i, t;
for (t = 0, i = fcyc_bits; i < 6; i++)
t = (t << 1) | ((fld_val >> i) & 1);
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%u", t);
}
else
{
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%u",
fld_val & ((1 << fcyc_bits) - 1));
}
case tic6x_coding_spmask:
if (fld_val == 0)
- spmask_skip_operand = TRUE;
+ spmask_skip_operand = true;
else
{
char *p;
unsigned int i;
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
p = operands[op_num];
for (i = 0; i < 8; i++)
if (fld_val & (1 << i))
printf ("opcode %x: long access but operands already known ?\n", opcode);
abort ();
}
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "*+b%u(%u)", mem_base_reg,
mem_offset * opc->operand_info[op_num].size);
}
{
char side;
char base[4];
- bfd_boolean offset_is_reg;
- bfd_boolean offset_scaled;
+ bool offset_is_reg;
+ bool offset_scaled;
char offset[4];
char offsetp[6];
== tic6x_operand_mem_ndw)
offset_scaled = mem_scaled != 0;
else
- offset_scaled = TRUE;
+ offset_scaled = true;
}
else
{
}
else
{
- offset_scaled = FALSE;
+ offset_scaled = false;
snprintf (offset, 4, "%u",
(mem_offset
* opc->operand_info[op_num].size));
else
snprintf (offsetp, 6, "(%s)", offset);
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
switch (mem_mode & ~4u)
{
case 0:
case 2:
case 3:
- operands_ok = FALSE;
+ operands_ok = false;
break;
case 8:
}
if (crid == tic6x_ctrl_max)
{
- operands_text[op_num] = TRUE;
- operands_ok = FALSE;
+ operands_text[op_num] = true;
+ operands_ok = false;
}
else
{
- operands_text[op_num] = TRUE;
+ operands_text[op_num] = true;
snprintf (operands[op_num], 24, "%s",
tic6x_ctrl_table[crid].name);
}
int bytes_read,
bfd_vma memaddr,
struct disassemble_info * info,
- bfd_boolean noerror,
+ bool noerror,
int *invalid)
{
unsigned long value;
*opindex_ptr != 0;
opindex_ptr++, opnum++)
{
- bfd_boolean square = FALSE;
+ bool square = false;
long value;
int flag;
char *prefix;
if (opnum == 1 && opnum == memop)
{
info->fprintf_func (info->stream, "%s[", prefix);
- square = TRUE;
+ square = true;
}
else if ( (strcmp ("stc.w", op->name) == 0
|| strcmp ("cache", op->name) == 0
&& opnum == 2 && opnum == memop)
{
info->fprintf_func (info->stream, ", [");
- square = TRUE;
+ square = true;
}
else if ( (strcmp (op->name, "pushsp") == 0
|| strcmp (op->name, "popsp") == 0
&& opnum == memop)
{
info->fprintf_func (info->stream, "%s[", prefix);
- square = TRUE;
+ square = true;
}
else if (opnum == 2
&& ( op->opcode == 0x00e407e0 /* clr1 */
))
{
info->fprintf_func (info->stream, ", %s[", prefix);
- square = TRUE;
+ square = true;
}
else if (opnum > 1)
info->fprintf_func (info->stream, ", %s", prefix);
entry addresses, which can be useful to disassemble ROM images, since
there's no symbol table. Returns TRUE upon success, FALSE otherwise. */
-static bfd_boolean
+static bool
parse_disassembler_options (const char *options)
{
const char * entry_switch = "entry:";
}
if (entry_addr == NULL)
- return FALSE;
+ return false;
entry_addr[entry_addr_occupied_slots] = bfd_scan_vma (options, NULL, 0);
entry_addr_occupied_slots ++;
}
- return TRUE;
+ return true;
}
#if 0 /* FIXME: Ideally the disassembler should have target specific
table at all. Forced entry points can be given by supplying several
-M options to objdump: -M entry:0xffbb7730. */
-static bfd_boolean
+static bool
is_function_entry (struct disassemble_info *info, bfd_vma addr)
{
unsigned int i;
&& info->symbols[0]
&& (info->symbols[0]->flags & (BSF_FUNCTION | BSF_SYNTHETIC))
&& addr == bfd_asymbol_value (info->symbols[0]))
- return TRUE;
+ return true;
/* Check for forced function entry address. */
for (i = entry_addr_occupied_slots; i--;)
if (entry_addr[i] == addr)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Check if the given address is the last longword of a PLT entry.
This longword is data and depending on the value it may interfere
with disassembly of further PLT entries. We make use of the fact
PLT symbols are marked BSF_SYNTHETIC. */
-static bfd_boolean
+static bool
is_plt_tail (struct disassemble_info *info, bfd_vma addr)
{
if (info->symbols
&& info->symbols[0]
&& (info->symbols[0]->flags & BSF_SYNTHETIC)
&& addr == bfd_asymbol_value (info->symbols[0]) + 8)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
static int
int
print_insn_vax (bfd_vma memaddr, disassemble_info *info)
{
- static bfd_boolean parsed_disassembler_options = FALSE;
+ static bool parsed_disassembler_options = false;
const struct vot *votp;
const char *argp;
unsigned char *arg;
parse_disassembler_options (info->disassembler_options);
/* To avoid repeated parsing of these options. */
- parsed_disassembler_options = TRUE;
+ parsed_disassembler_options = true;
}
if (OPCODES_SIGSETJMP (priv.bailout) != 0)
struct wasm32_private_data
{
- bfd_boolean print_registers;
- bfd_boolean print_well_known_globals;
+ bool print_registers;
+ bool print_well_known_globals;
/* Limit valid symbols to those with a given prefix. */
const char *section_prefix;
while (opts != NULL)
{
if (startswith (opts, "registers"))
- private->print_registers = TRUE;
+ private->print_registers = true;
else if (startswith (opts, "globals"))
- private->print_well_known_globals = TRUE;
+ private->print_well_known_globals = true;
opts = strchr (opts, ',');
if (opts)
are unhelpful to print, and arguments to a "call" insn, which we
want to be in a section matching a given prefix. */
-static bfd_boolean
+static bool
wasm32_symbol_is_valid (asymbol *sym,
struct disassemble_info *info)
{
struct wasm32_private_data *private_data = info->private_data;
if (sym == NULL)
- return FALSE;
+ return false;
if (strcmp(sym->section->name, "*ABS*") == 0)
- return FALSE;
+ return false;
if (private_data && private_data->section_prefix != NULL
&& strncmp (sym->section->name, private_data->section_prefix,
strlen (private_data->section_prefix)))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Initialize the disassembler structures for INFO. */
{
static struct wasm32_private_data private;
- private.print_registers = FALSE;
- private.print_well_known_globals = FALSE;
+ private.print_registers = false;
+ private.print_well_known_globals = false;
private.section_prefix = NULL;
info->private_data = &private;
wasm_read_leb128 (). */
static uint64_t
-wasm_read_leb128 (bfd_vma pc,
- struct disassemble_info * info,
- bfd_boolean * error_return,
- unsigned int * length_return,
- bfd_boolean sign)
+wasm_read_leb128 (bfd_vma pc,
+ struct disassemble_info *info,
+ bool *error_return,
+ unsigned int *length_return,
+ bool sign)
{
uint64_t result = 0;
unsigned int num_read = 0;
uint64_t val;
int len;
unsigned int bytes_read;
- bfd_boolean error;
+ bool error;
if (info->read_memory_func (pc, buffer, 1, info))
return -1;
if (op->clas == wasm_typed)
{
- val = wasm_read_leb128 (pc + len, info, &error, &bytes_read, FALSE);
+ val = wasm_read_leb128 (pc + len, info, &error, &bytes_read, false);
if (error)
return -1;
len += bytes_read;
{
uint32_t target_count, i;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
target_count = val;
if (error || target_count != val || target_count == (uint32_t) -1)
return -1;
{
uint32_t target;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
target = val;
if (error || target != val)
return -1;
{
uint32_t depth;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
depth = val;
if (error || depth != val)
return -1;
case wasm_constant_i32:
case wasm_constant_i64:
- val = wasm_read_leb128 (pc + len, info, &error, &bytes_read, TRUE);
+ val = wasm_read_leb128 (pc + len, info, &error, &bytes_read, true);
if (error)
return -1;
len += bytes_read;
{
uint32_t function_index;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
function_index = val;
if (error || function_index != val)
return -1;
{
uint32_t type_index, xtra_index;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
type_index = val;
if (error || type_index != val)
return -1;
len += bytes_read;
prin (stream, " %u", type_index);
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
xtra_index = val;
if (error || xtra_index != val)
return -1;
{
uint32_t local_index;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
local_index = val;
if (error || local_index != val)
return -1;
{
uint32_t reserved_size;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
reserved_size = val;
if (error || reserved_size != val)
return -1;
{
uint32_t flags, offset;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
flags = val;
if (error || flags != val)
return -1;
len += bytes_read;
val = wasm_read_leb128 (pc + len, info, &error, &bytes_read,
- FALSE);
+ false);
offset = val;
if (error || offset != val)
return -1;
priv.insn_table_entry_count =
xtensa_read_table_entries (abfd, section,
&priv.insn_table_entries,
- XTENSA_PROP_SEC_NAME, FALSE);
+ XTENSA_PROP_SEC_NAME, false);
if (priv.insn_table_entry_count == 0)
{
free (priv.insn_table_entries);
priv.insn_table_entry_count =
xtensa_read_table_entries (abfd, section,
&priv.insn_table_entries,
- XTENSA_INSN_SEC_NAME, FALSE);
+ XTENSA_INSN_SEC_NAME, false);
}
priv.insn_table_cur_idx = 0;
xtensa_coalesce_insn_tables (&priv);
projects / thirdparty / binutils-gdb.git / commitdiff
