1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 /* Middle-to-low level generation of rtx code and insns.
23 This file contains support functions for creating rtl expressions
24 and manipulating them in the doubly-linked chain of insns.
26 The patterns of the insns are created by machine-dependent
27 routines in insn-emit.c, which is generated automatically from
28 the machine description. These routines make the individual rtx's
29 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
30 which are automatically generated from rtl.def; what is machine
31 dependent is the kind of rtx's they make and what arguments they
36 #include "coretypes.h"
44 #include "stringpool.h"
45 #include "insn-config.h"
49 #include "diagnostic-core.h"
51 #include "fold-const.h"
59 #include "stor-layout.h"
62 #include "rtx-vector-builder.h"
64 #include "gimple-ssa.h"
67 struct target_rtl default_target_rtl
;
69 struct target_rtl
*this_target_rtl
= &default_target_rtl
;
72 #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx)
74 /* Commonly used modes. */
76 scalar_int_mode byte_mode
; /* Mode whose width is BITS_PER_UNIT. */
77 scalar_int_mode word_mode
; /* Mode whose width is BITS_PER_WORD. */
78 scalar_int_mode ptr_mode
; /* Mode whose width is POINTER_SIZE. */
80 /* Datastructures maintained for currently processed function in RTL form. */
82 struct rtl_data x_rtl
;
84 /* Indexed by pseudo register number, gives the rtx for that pseudo.
85 Allocated in parallel with regno_pointer_align.
86 FIXME: We could put it into emit_status struct, but gengtype is not able to deal
87 with length attribute nested in top level structures. */
91 /* This is *not* reset after each function. It gives each CODE_LABEL
92 in the entire compilation a unique label number. */
94 static GTY(()) int label_num
= 1;
96 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
97 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
98 record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX
99 is set only for MODE_INT and MODE_VECTOR_INT modes. */
101 rtx const_tiny_rtx
[4][(int) MAX_MACHINE_MODE
];
105 REAL_VALUE_TYPE dconst0
;
106 REAL_VALUE_TYPE dconst1
;
107 REAL_VALUE_TYPE dconst2
;
108 REAL_VALUE_TYPE dconstm1
;
109 REAL_VALUE_TYPE dconsthalf
;
111 /* Record fixed-point constant 0 and 1. */
112 FIXED_VALUE_TYPE fconst0
[MAX_FCONST0
];
113 FIXED_VALUE_TYPE fconst1
[MAX_FCONST1
];
115 /* We make one copy of (const_int C) where C is in
116 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
117 to save space during the compilation and simplify comparisons of
120 rtx const_int_rtx
[MAX_SAVED_CONST_INT
* 2 + 1];
122 /* Standard pieces of rtx, to be substituted directly into things. */
125 rtx simple_return_rtx
;
128 /* Marker used for denoting an INSN, which should never be accessed (i.e.,
129 this pointer should normally never be dereferenced), but is required to be
130 distinct from NULL_RTX. Currently used by peephole2 pass. */
131 rtx_insn
*invalid_insn_rtx
;
133 /* A hash table storing CONST_INTs whose absolute value is greater
134 than MAX_SAVED_CONST_INT. */
136 struct const_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
138 typedef HOST_WIDE_INT compare_type
;
140 static hashval_t
hash (rtx i
);
141 static bool equal (rtx i
, HOST_WIDE_INT h
);
144 static GTY ((cache
)) hash_table
<const_int_hasher
> *const_int_htab
;
146 struct const_wide_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
148 static hashval_t
hash (rtx x
);
149 static bool equal (rtx x
, rtx y
);
152 static GTY ((cache
)) hash_table
<const_wide_int_hasher
> *const_wide_int_htab
;
154 struct const_poly_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
156 typedef std::pair
<machine_mode
, poly_wide_int_ref
> compare_type
;
158 static hashval_t
hash (rtx x
);
159 static bool equal (rtx x
, const compare_type
&y
);
162 static GTY ((cache
)) hash_table
<const_poly_int_hasher
> *const_poly_int_htab
;
164 /* A hash table storing register attribute structures. */
165 struct reg_attr_hasher
: ggc_cache_ptr_hash
<reg_attrs
>
167 static hashval_t
hash (reg_attrs
*x
);
168 static bool equal (reg_attrs
*a
, reg_attrs
*b
);
171 static GTY ((cache
)) hash_table
<reg_attr_hasher
> *reg_attrs_htab
;
173 /* A hash table storing all CONST_DOUBLEs. */
174 struct const_double_hasher
: ggc_cache_ptr_hash
<rtx_def
>
176 static hashval_t
hash (rtx x
);
177 static bool equal (rtx x
, rtx y
);
180 static GTY ((cache
)) hash_table
<const_double_hasher
> *const_double_htab
;
182 /* A hash table storing all CONST_FIXEDs. */
183 struct const_fixed_hasher
: ggc_cache_ptr_hash
<rtx_def
>
185 static hashval_t
hash (rtx x
);
186 static bool equal (rtx x
, rtx y
);
189 static GTY ((cache
)) hash_table
<const_fixed_hasher
> *const_fixed_htab
;
191 #define cur_insn_uid (crtl->emit.x_cur_insn_uid)
192 #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid)
193 #define first_label_num (crtl->emit.x_first_label_num)
195 static void set_used_decls (tree
);
196 static void mark_label_nuses (rtx
);
197 #if TARGET_SUPPORTS_WIDE_INT
198 static rtx
lookup_const_wide_int (rtx
);
200 static rtx
lookup_const_double (rtx
);
201 static rtx
lookup_const_fixed (rtx
);
202 static rtx
gen_const_vector (machine_mode
, int);
203 static void copy_rtx_if_shared_1 (rtx
*orig
);
205 /* Probability of the conditional branch currently proceeded by try_split. */
206 profile_probability split_branch_probability
;
208 /* Returns a hash code for X (which is a really a CONST_INT). */
211 const_int_hasher::hash (rtx x
)
213 return (hashval_t
) INTVAL (x
);
216 /* Returns nonzero if the value represented by X (which is really a
217 CONST_INT) is the same as that given by Y (which is really a
221 const_int_hasher::equal (rtx x
, HOST_WIDE_INT y
)
223 return (INTVAL (x
) == y
);
226 #if TARGET_SUPPORTS_WIDE_INT
227 /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */
230 const_wide_int_hasher::hash (rtx x
)
233 unsigned HOST_WIDE_INT hash
= 0;
236 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
237 hash
+= CONST_WIDE_INT_ELT (xr
, i
);
239 return (hashval_t
) hash
;
242 /* Returns nonzero if the value represented by X (which is really a
243 CONST_WIDE_INT) is the same as that given by Y (which is really a
247 const_wide_int_hasher::equal (rtx x
, rtx y
)
252 if (CONST_WIDE_INT_NUNITS (xr
) != CONST_WIDE_INT_NUNITS (yr
))
255 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
256 if (CONST_WIDE_INT_ELT (xr
, i
) != CONST_WIDE_INT_ELT (yr
, i
))
263 /* Returns a hash code for CONST_POLY_INT X. */
266 const_poly_int_hasher::hash (rtx x
)
269 h
.add_int (GET_MODE (x
));
270 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
271 h
.add_wide_int (CONST_POLY_INT_COEFFS (x
)[i
]);
275 /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */
278 const_poly_int_hasher::equal (rtx x
, const compare_type
&y
)
280 if (GET_MODE (x
) != y
.first
)
282 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
283 if (CONST_POLY_INT_COEFFS (x
)[i
] != y
.second
.coeffs
[i
])
288 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
290 const_double_hasher::hash (rtx x
)
292 const_rtx
const value
= x
;
295 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (value
) == VOIDmode
)
296 h
= CONST_DOUBLE_LOW (value
) ^ CONST_DOUBLE_HIGH (value
);
299 h
= real_hash (CONST_DOUBLE_REAL_VALUE (value
));
300 /* MODE is used in the comparison, so it should be in the hash. */
301 h
^= GET_MODE (value
);
306 /* Returns nonzero if the value represented by X (really a ...)
307 is the same as that represented by Y (really a ...) */
309 const_double_hasher::equal (rtx x
, rtx y
)
311 const_rtx
const a
= x
, b
= y
;
313 if (GET_MODE (a
) != GET_MODE (b
))
315 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (a
) == VOIDmode
)
316 return (CONST_DOUBLE_LOW (a
) == CONST_DOUBLE_LOW (b
)
317 && CONST_DOUBLE_HIGH (a
) == CONST_DOUBLE_HIGH (b
));
319 return real_identical (CONST_DOUBLE_REAL_VALUE (a
),
320 CONST_DOUBLE_REAL_VALUE (b
));
323 /* Returns a hash code for X (which is really a CONST_FIXED). */
326 const_fixed_hasher::hash (rtx x
)
328 const_rtx
const value
= x
;
331 h
= fixed_hash (CONST_FIXED_VALUE (value
));
332 /* MODE is used in the comparison, so it should be in the hash. */
333 h
^= GET_MODE (value
);
337 /* Returns nonzero if the value represented by X is the same as that
341 const_fixed_hasher::equal (rtx x
, rtx y
)
343 const_rtx
const a
= x
, b
= y
;
345 if (GET_MODE (a
) != GET_MODE (b
))
347 return fixed_identical (CONST_FIXED_VALUE (a
), CONST_FIXED_VALUE (b
));
350 /* Return true if the given memory attributes are equal. */
353 mem_attrs_eq_p (const class mem_attrs
*p
, const class mem_attrs
*q
)
359 return (p
->alias
== q
->alias
360 && p
->offset_known_p
== q
->offset_known_p
361 && (!p
->offset_known_p
|| known_eq (p
->offset
, q
->offset
))
362 && p
->size_known_p
== q
->size_known_p
363 && (!p
->size_known_p
|| known_eq (p
->size
, q
->size
))
364 && p
->align
== q
->align
365 && p
->addrspace
== q
->addrspace
366 && (p
->expr
== q
->expr
367 || (p
->expr
!= NULL_TREE
&& q
->expr
!= NULL_TREE
368 && operand_equal_p (p
->expr
, q
->expr
, 0))));
371 /* Set MEM's memory attributes so that they are the same as ATTRS. */
374 set_mem_attrs (rtx mem
, mem_attrs
*attrs
)
376 /* If everything is the default, we can just clear the attributes. */
377 if (mem_attrs_eq_p (attrs
, mode_mem_attrs
[(int) GET_MODE (mem
)]))
384 || !mem_attrs_eq_p (attrs
, MEM_ATTRS (mem
)))
386 MEM_ATTRS (mem
) = ggc_alloc
<mem_attrs
> ();
387 memcpy (MEM_ATTRS (mem
), attrs
, sizeof (mem_attrs
));
391 /* Returns a hash code for X (which is a really a reg_attrs *). */
394 reg_attr_hasher::hash (reg_attrs
*x
)
396 const reg_attrs
*const p
= x
;
400 h
.add_poly_hwi (p
->offset
);
404 /* Returns nonzero if the value represented by X is the same as that given by
408 reg_attr_hasher::equal (reg_attrs
*x
, reg_attrs
*y
)
410 const reg_attrs
*const p
= x
;
411 const reg_attrs
*const q
= y
;
413 return (p
->decl
== q
->decl
&& known_eq (p
->offset
, q
->offset
));
415 /* Allocate a new reg_attrs structure and insert it into the hash table if
416 one identical to it is not already in the table. We are doing this for
420 get_reg_attrs (tree decl
, poly_int64 offset
)
424 /* If everything is the default, we can just return zero. */
425 if (decl
== 0 && known_eq (offset
, 0))
429 attrs
.offset
= offset
;
431 reg_attrs
**slot
= reg_attrs_htab
->find_slot (&attrs
, INSERT
);
434 *slot
= ggc_alloc
<reg_attrs
> ();
435 memcpy (*slot
, &attrs
, sizeof (reg_attrs
));
443 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
444 and to block register equivalences to be seen across this insn. */
449 rtx x
= gen_rtx_ASM_INPUT (VOIDmode
, "");
450 MEM_VOLATILE_P (x
) = true;
456 /* Set the mode and register number of X to MODE and REGNO. */
459 set_mode_and_regno (rtx x
, machine_mode mode
, unsigned int regno
)
461 unsigned int nregs
= (HARD_REGISTER_NUM_P (regno
)
462 ? hard_regno_nregs (regno
, mode
)
464 PUT_MODE_RAW (x
, mode
);
465 set_regno_raw (x
, regno
, nregs
);
468 /* Initialize a fresh REG rtx with mode MODE and register REGNO. */
471 init_raw_REG (rtx x
, machine_mode mode
, unsigned int regno
)
473 set_mode_and_regno (x
, mode
, regno
);
474 REG_ATTRS (x
) = NULL
;
475 ORIGINAL_REGNO (x
) = regno
;
479 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
480 don't attempt to share with the various global pieces of rtl (such as
481 frame_pointer_rtx). */
484 gen_raw_REG (machine_mode mode
, unsigned int regno
)
486 rtx x
= rtx_alloc (REG MEM_STAT_INFO
);
487 init_raw_REG (x
, mode
, regno
);
491 /* There are some RTL codes that require special attention; the generation
492 functions do the raw handling. If you add to this list, modify
493 special_rtx in gengenrtl.c as well. */
496 gen_rtx_EXPR_LIST (machine_mode mode
, rtx expr
, rtx expr_list
)
498 return as_a
<rtx_expr_list
*> (gen_rtx_fmt_ee (EXPR_LIST
, mode
, expr
,
503 gen_rtx_INSN_LIST (machine_mode mode
, rtx insn
, rtx insn_list
)
505 return as_a
<rtx_insn_list
*> (gen_rtx_fmt_ue (INSN_LIST
, mode
, insn
,
510 gen_rtx_INSN (machine_mode mode
, rtx_insn
*prev_insn
, rtx_insn
*next_insn
,
511 basic_block bb
, rtx pattern
, int location
, int code
,
514 return as_a
<rtx_insn
*> (gen_rtx_fmt_uuBeiie (INSN
, mode
,
515 prev_insn
, next_insn
,
516 bb
, pattern
, location
, code
,
521 gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED
, HOST_WIDE_INT arg
)
523 if (arg
>= - MAX_SAVED_CONST_INT
&& arg
<= MAX_SAVED_CONST_INT
)
524 return const_int_rtx
[arg
+ MAX_SAVED_CONST_INT
];
526 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
527 if (const_true_rtx
&& arg
== STORE_FLAG_VALUE
)
528 return const_true_rtx
;
531 /* Look up the CONST_INT in the hash table. */
532 rtx
*slot
= const_int_htab
->find_slot_with_hash (arg
, (hashval_t
) arg
,
535 *slot
= gen_rtx_raw_CONST_INT (VOIDmode
, arg
);
541 gen_int_mode (poly_int64 c
, machine_mode mode
)
543 c
= trunc_int_for_mode (c
, mode
);
544 if (c
.is_constant ())
545 return GEN_INT (c
.coeffs
[0]);
546 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
547 return immed_wide_int_const (poly_wide_int::from (c
, prec
, SIGNED
), mode
);
550 /* CONST_DOUBLEs might be created from pairs of integers, or from
551 REAL_VALUE_TYPEs. Also, their length is known only at run time,
552 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
554 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
555 hash table. If so, return its counterpart; otherwise add it
556 to the hash table and return it. */
558 lookup_const_double (rtx real
)
560 rtx
*slot
= const_double_htab
->find_slot (real
, INSERT
);
567 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
568 VALUE in mode MODE. */
570 const_double_from_real_value (REAL_VALUE_TYPE value
, machine_mode mode
)
572 rtx real
= rtx_alloc (CONST_DOUBLE
);
573 PUT_MODE (real
, mode
);
577 return lookup_const_double (real
);
580 /* Determine whether FIXED, a CONST_FIXED, already exists in the
581 hash table. If so, return its counterpart; otherwise add it
582 to the hash table and return it. */
585 lookup_const_fixed (rtx fixed
)
587 rtx
*slot
= const_fixed_htab
->find_slot (fixed
, INSERT
);
594 /* Return a CONST_FIXED rtx for a fixed-point value specified by
595 VALUE in mode MODE. */
598 const_fixed_from_fixed_value (FIXED_VALUE_TYPE value
, machine_mode mode
)
600 rtx fixed
= rtx_alloc (CONST_FIXED
);
601 PUT_MODE (fixed
, mode
);
605 return lookup_const_fixed (fixed
);
608 #if TARGET_SUPPORTS_WIDE_INT == 0
609 /* Constructs double_int from rtx CST. */
612 rtx_to_double_int (const_rtx cst
)
616 if (CONST_INT_P (cst
))
617 r
= double_int::from_shwi (INTVAL (cst
));
618 else if (CONST_DOUBLE_AS_INT_P (cst
))
620 r
.low
= CONST_DOUBLE_LOW (cst
);
621 r
.high
= CONST_DOUBLE_HIGH (cst
);
630 #if TARGET_SUPPORTS_WIDE_INT
631 /* Determine whether CONST_WIDE_INT WINT already exists in the hash table.
632 If so, return its counterpart; otherwise add it to the hash table and
636 lookup_const_wide_int (rtx wint
)
638 rtx
*slot
= const_wide_int_htab
->find_slot (wint
, INSERT
);
646 /* Return an rtx constant for V, given that the constant has mode MODE.
647 The returned rtx will be a CONST_INT if V fits, otherwise it will be
648 a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT
649 (if TARGET_SUPPORTS_WIDE_INT). */
652 immed_wide_int_const_1 (const wide_int_ref
&v
, machine_mode mode
)
654 unsigned int len
= v
.get_len ();
655 /* Not scalar_int_mode because we also allow pointer bound modes. */
656 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
658 /* Allow truncation but not extension since we do not know if the
659 number is signed or unsigned. */
660 gcc_assert (prec
<= v
.get_precision ());
662 if (len
< 2 || prec
<= HOST_BITS_PER_WIDE_INT
)
663 return gen_int_mode (v
.elt (0), mode
);
665 #if TARGET_SUPPORTS_WIDE_INT
669 unsigned int blocks_needed
670 = (prec
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
;
672 if (len
> blocks_needed
)
675 value
= const_wide_int_alloc (len
);
677 /* It is so tempting to just put the mode in here. Must control
679 PUT_MODE (value
, VOIDmode
);
680 CWI_PUT_NUM_ELEM (value
, len
);
682 for (i
= 0; i
< len
; i
++)
683 CONST_WIDE_INT_ELT (value
, i
) = v
.elt (i
);
685 return lookup_const_wide_int (value
);
688 return immed_double_const (v
.elt (0), v
.elt (1), mode
);
692 #if TARGET_SUPPORTS_WIDE_INT == 0
693 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
694 of ints: I0 is the low-order word and I1 is the high-order word.
695 For values that are larger than HOST_BITS_PER_DOUBLE_INT, the
696 implied upper bits are copies of the high bit of i1. The value
697 itself is neither signed nor unsigned. Do not use this routine for
698 non-integer modes; convert to REAL_VALUE_TYPE and use
699 const_double_from_real_value. */
702 immed_double_const (HOST_WIDE_INT i0
, HOST_WIDE_INT i1
, machine_mode mode
)
707 /* There are the following cases (note that there are no modes with
708 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT):
710 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
712 2) If the value of the integer fits into HOST_WIDE_INT anyway
713 (i.e., i1 consists only from copies of the sign bit, and sign
714 of i0 and i1 are the same), then we return a CONST_INT for i0.
715 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
717 if (is_a
<scalar_mode
> (mode
, &smode
)
718 && GET_MODE_BITSIZE (smode
) <= HOST_BITS_PER_WIDE_INT
)
719 return gen_int_mode (i0
, mode
);
721 /* If this integer fits in one word, return a CONST_INT. */
722 if ((i1
== 0 && i0
>= 0) || (i1
== ~0 && i0
< 0))
725 /* We use VOIDmode for integers. */
726 value
= rtx_alloc (CONST_DOUBLE
);
727 PUT_MODE (value
, VOIDmode
);
729 CONST_DOUBLE_LOW (value
) = i0
;
730 CONST_DOUBLE_HIGH (value
) = i1
;
732 for (i
= 2; i
< (sizeof CONST_DOUBLE_FORMAT
- 1); i
++)
733 XWINT (value
, i
) = 0;
735 return lookup_const_double (value
);
739 /* Return an rtx representation of C in mode MODE. */
742 immed_wide_int_const (const poly_wide_int_ref
&c
, machine_mode mode
)
744 if (c
.is_constant ())
745 return immed_wide_int_const_1 (c
.coeffs
[0], mode
);
747 /* Not scalar_int_mode because we also allow pointer bound modes. */
748 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
750 /* Allow truncation but not extension since we do not know if the
751 number is signed or unsigned. */
752 gcc_assert (prec
<= c
.coeffs
[0].get_precision ());
753 poly_wide_int newc
= poly_wide_int::from (c
, prec
, SIGNED
);
755 /* See whether we already have an rtx for this constant. */
758 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
759 h
.add_wide_int (newc
.coeffs
[i
]);
760 const_poly_int_hasher::compare_type
typed_value (mode
, newc
);
761 rtx
*slot
= const_poly_int_htab
->find_slot_with_hash (typed_value
,
767 /* Create a new rtx. There's a choice to be made here between installing
768 the actual mode of the rtx or leaving it as VOIDmode (for consistency
769 with CONST_INT). In practice the handling of the codes is different
770 enough that we get no benefit from using VOIDmode, and various places
771 assume that VOIDmode implies CONST_INT. Using the real mode seems like
772 the right long-term direction anyway. */
773 typedef trailing_wide_ints
<NUM_POLY_INT_COEFFS
> twi
;
774 size_t extra_size
= twi::extra_size (prec
);
775 x
= rtx_alloc_v (CONST_POLY_INT
,
776 sizeof (struct const_poly_int_def
) + extra_size
);
778 CONST_POLY_INT_COEFFS (x
).set_precision (prec
);
779 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
780 CONST_POLY_INT_COEFFS (x
)[i
] = newc
.coeffs
[i
];
787 gen_rtx_REG (machine_mode mode
, unsigned int regno
)
789 /* In case the MD file explicitly references the frame pointer, have
790 all such references point to the same frame pointer. This is
791 used during frame pointer elimination to distinguish the explicit
792 references to these registers from pseudos that happened to be
795 If we have eliminated the frame pointer or arg pointer, we will
796 be using it as a normal register, for example as a spill
797 register. In such cases, we might be accessing it in a mode that
798 is not Pmode and therefore cannot use the pre-allocated rtx.
800 Also don't do this when we are making new REGs in reload, since
801 we don't want to get confused with the real pointers. */
803 if (mode
== Pmode
&& !reload_in_progress
&& !lra_in_progress
)
805 if (regno
== FRAME_POINTER_REGNUM
806 && (!reload_completed
|| frame_pointer_needed
))
807 return frame_pointer_rtx
;
809 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
810 && regno
== HARD_FRAME_POINTER_REGNUM
811 && (!reload_completed
|| frame_pointer_needed
))
812 return hard_frame_pointer_rtx
;
813 #if !HARD_FRAME_POINTER_IS_ARG_POINTER
814 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
815 && regno
== ARG_POINTER_REGNUM
)
816 return arg_pointer_rtx
;
818 #ifdef RETURN_ADDRESS_POINTER_REGNUM
819 if (regno
== RETURN_ADDRESS_POINTER_REGNUM
)
820 return return_address_pointer_rtx
;
822 if (regno
== (unsigned) PIC_OFFSET_TABLE_REGNUM
823 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
824 && fixed_regs
[PIC_OFFSET_TABLE_REGNUM
])
825 return pic_offset_table_rtx
;
826 if (regno
== STACK_POINTER_REGNUM
)
827 return stack_pointer_rtx
;
831 /* If the per-function register table has been set up, try to re-use
832 an existing entry in that table to avoid useless generation of RTL.
834 This code is disabled for now until we can fix the various backends
835 which depend on having non-shared hard registers in some cases. Long
836 term we want to re-enable this code as it can significantly cut down
837 on the amount of useless RTL that gets generated.
839 We'll also need to fix some code that runs after reload that wants to
840 set ORIGINAL_REGNO. */
845 && regno
< FIRST_PSEUDO_REGISTER
846 && reg_raw_mode
[regno
] == mode
)
847 return regno_reg_rtx
[regno
];
850 return gen_raw_REG (mode
, regno
);
854 gen_rtx_MEM (machine_mode mode
, rtx addr
)
856 rtx rt
= gen_rtx_raw_MEM (mode
, addr
);
858 /* This field is not cleared by the mere allocation of the rtx, so
865 /* Generate a memory referring to non-trapping constant memory. */
868 gen_const_mem (machine_mode mode
, rtx addr
)
870 rtx mem
= gen_rtx_MEM (mode
, addr
);
871 MEM_READONLY_P (mem
) = 1;
872 MEM_NOTRAP_P (mem
) = 1;
876 /* Generate a MEM referring to fixed portions of the frame, e.g., register
880 gen_frame_mem (machine_mode mode
, rtx addr
)
882 rtx mem
= gen_rtx_MEM (mode
, addr
);
883 MEM_NOTRAP_P (mem
) = 1;
884 set_mem_alias_set (mem
, get_frame_alias_set ());
888 /* Generate a MEM referring to a temporary use of the stack, not part
889 of the fixed stack frame. For example, something which is pushed
890 by a target splitter. */
892 gen_tmp_stack_mem (machine_mode mode
, rtx addr
)
894 rtx mem
= gen_rtx_MEM (mode
, addr
);
895 MEM_NOTRAP_P (mem
) = 1;
896 if (!cfun
->calls_alloca
)
897 set_mem_alias_set (mem
, get_frame_alias_set ());
901 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
902 this construct would be valid, and false otherwise. */
905 validate_subreg (machine_mode omode
, machine_mode imode
,
906 const_rtx reg
, poly_uint64 offset
)
908 poly_uint64 isize
= GET_MODE_SIZE (imode
);
909 poly_uint64 osize
= GET_MODE_SIZE (omode
);
911 /* The sizes must be ordered, so that we know whether the subreg
912 is partial, paradoxical or complete. */
913 if (!ordered_p (isize
, osize
))
916 /* All subregs must be aligned. */
917 if (!multiple_p (offset
, osize
))
920 /* The subreg offset cannot be outside the inner object. */
921 if (maybe_ge (offset
, isize
))
924 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (imode
);
926 /* ??? This should not be here. Temporarily continue to allow word_mode
927 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
928 Generally, backends are doing something sketchy but it'll take time to
930 if (omode
== word_mode
)
932 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
933 is the culprit here, and not the backends. */
934 else if (known_ge (osize
, regsize
) && known_ge (isize
, osize
))
936 /* Allow component subregs of complex and vector. Though given the below
937 extraction rules, it's not always clear what that means. */
938 else if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
939 && GET_MODE_INNER (imode
) == omode
)
941 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
942 i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This
943 surely isn't the cleanest way to represent this. It's questionable
944 if this ought to be represented at all -- why can't this all be hidden
945 in post-reload splitters that make arbitrarily mode changes to the
946 registers themselves. */
947 else if (VECTOR_MODE_P (omode
)
948 && GET_MODE_INNER (omode
) == GET_MODE_INNER (imode
))
950 /* Subregs involving floating point modes are not allowed to
951 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
952 (subreg:SI (reg:DF) 0) isn't. */
953 else if (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))
955 if (! (known_eq (isize
, osize
)
956 /* LRA can use subreg to store a floating point value in
957 an integer mode. Although the floating point and the
958 integer modes need the same number of hard registers,
959 the size of floating point mode can be less than the
960 integer mode. LRA also uses subregs for a register
961 should be used in different mode in on insn. */
966 /* Paradoxical subregs must have offset zero. */
967 if (maybe_gt (osize
, isize
))
968 return known_eq (offset
, 0U);
970 /* This is a normal subreg. Verify that the offset is representable. */
972 /* For hard registers, we already have most of these rules collected in
973 subreg_offset_representable_p. */
974 if (reg
&& REG_P (reg
) && HARD_REGISTER_P (reg
))
976 unsigned int regno
= REGNO (reg
);
978 if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
979 && GET_MODE_INNER (imode
) == omode
)
981 else if (!REG_CAN_CHANGE_MODE_P (regno
, imode
, omode
))
984 return subreg_offset_representable_p (regno
, imode
, offset
, omode
);
987 /* The outer size must be ordered wrt the register size, otherwise
988 we wouldn't know at compile time how many registers the outer
990 if (!ordered_p (osize
, regsize
))
993 /* For pseudo registers, we want most of the same checks. Namely:
995 Assume that the pseudo register will be allocated to hard registers
996 that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE,
997 the remainder must correspond to the lowpart of the containing hard
998 register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset,
999 otherwise it is at the lowest offset.
1001 Given that we've already checked the mode and offset alignment,
1002 we only have to check subblock subregs here. */
1003 if (maybe_lt (osize
, regsize
)
1004 && ! (lra_in_progress
&& (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))))
1006 /* It is invalid for the target to pick a register size for a mode
1007 that isn't ordered wrt to the size of that mode. */
1008 poly_uint64 block_size
= ordered_min (isize
, regsize
);
1009 unsigned int start_reg
;
1010 poly_uint64 offset_within_reg
;
1011 if (!can_div_trunc_p (offset
, block_size
, &start_reg
, &offset_within_reg
)
1012 || (BYTES_BIG_ENDIAN
1013 ? maybe_ne (offset_within_reg
, block_size
- osize
)
1014 : maybe_ne (offset_within_reg
, 0U)))
1021 gen_rtx_SUBREG (machine_mode mode
, rtx reg
, poly_uint64 offset
)
1023 gcc_assert (validate_subreg (mode
, GET_MODE (reg
), reg
, offset
));
1024 return gen_rtx_raw_SUBREG (mode
, reg
, offset
);
1027 /* Generate a SUBREG representing the least-significant part of REG if MODE
1028 is smaller than mode of REG, otherwise paradoxical SUBREG. */
1031 gen_lowpart_SUBREG (machine_mode mode
, rtx reg
)
1033 machine_mode inmode
;
1035 inmode
= GET_MODE (reg
);
1036 if (inmode
== VOIDmode
)
1038 return gen_rtx_SUBREG (mode
, reg
,
1039 subreg_lowpart_offset (mode
, inmode
));
1043 gen_rtx_VAR_LOCATION (machine_mode mode
, tree decl
, rtx loc
,
1044 enum var_init_status status
)
1046 rtx x
= gen_rtx_fmt_te (VAR_LOCATION
, mode
, decl
, loc
);
1047 PAT_VAR_LOCATION_STATUS (x
) = status
;
1052 /* Create an rtvec and stores within it the RTXen passed in the arguments. */
1055 gen_rtvec (int n
, ...)
1063 /* Don't allocate an empty rtvec... */
1070 rt_val
= rtvec_alloc (n
);
1072 for (i
= 0; i
< n
; i
++)
1073 rt_val
->elem
[i
] = va_arg (p
, rtx
);
1080 gen_rtvec_v (int n
, rtx
*argp
)
1085 /* Don't allocate an empty rtvec... */
1089 rt_val
= rtvec_alloc (n
);
1091 for (i
= 0; i
< n
; i
++)
1092 rt_val
->elem
[i
] = *argp
++;
1098 gen_rtvec_v (int n
, rtx_insn
**argp
)
1103 /* Don't allocate an empty rtvec... */
1107 rt_val
= rtvec_alloc (n
);
1109 for (i
= 0; i
< n
; i
++)
1110 rt_val
->elem
[i
] = *argp
++;
1116 /* Return the number of bytes between the start of an OUTER_MODE
1117 in-memory value and the start of an INNER_MODE in-memory value,
1118 given that the former is a lowpart of the latter. It may be a
1119 paradoxical lowpart, in which case the offset will be negative
1120 on big-endian targets. */
1123 byte_lowpart_offset (machine_mode outer_mode
,
1124 machine_mode inner_mode
)
1126 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1127 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1129 return subreg_lowpart_offset (outer_mode
, inner_mode
);
1132 /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET)
1133 from address X. For paradoxical big-endian subregs this is a
1134 negative value, otherwise it's the same as OFFSET. */
1137 subreg_memory_offset (machine_mode outer_mode
, machine_mode inner_mode
,
1140 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1142 gcc_assert (known_eq (offset
, 0U));
1143 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1148 /* As above, but return the offset that existing subreg X would have
1149 if SUBREG_REG (X) were stored in memory. The only significant thing
1150 about the current SUBREG_REG is its mode. */
1153 subreg_memory_offset (const_rtx x
)
1155 return subreg_memory_offset (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
1159 /* Generate a REG rtx for a new pseudo register of mode MODE.
1160 This pseudo is assigned the next sequential register number. */
1163 gen_reg_rtx (machine_mode mode
)
1166 unsigned int align
= GET_MODE_ALIGNMENT (mode
);
1168 gcc_assert (can_create_pseudo_p ());
1170 /* If a virtual register with bigger mode alignment is generated,
1171 increase stack alignment estimation because it might be spilled
1173 if (SUPPORTS_STACK_ALIGNMENT
1174 && crtl
->stack_alignment_estimated
< align
1175 && !crtl
->stack_realign_processed
)
1177 unsigned int min_align
= MINIMUM_ALIGNMENT (NULL
, mode
, align
);
1178 if (crtl
->stack_alignment_estimated
< min_align
)
1179 crtl
->stack_alignment_estimated
= min_align
;
1182 if (generating_concat_p
1183 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1184 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
))
1186 /* For complex modes, don't make a single pseudo.
1187 Instead, make a CONCAT of two pseudos.
1188 This allows noncontiguous allocation of the real and imaginary parts,
1189 which makes much better code. Besides, allocating DCmode
1190 pseudos overstrains reload on some machines like the 386. */
1191 rtx realpart
, imagpart
;
1192 machine_mode partmode
= GET_MODE_INNER (mode
);
1194 realpart
= gen_reg_rtx (partmode
);
1195 imagpart
= gen_reg_rtx (partmode
);
1196 return gen_rtx_CONCAT (mode
, realpart
, imagpart
);
1199 /* Do not call gen_reg_rtx with uninitialized crtl. */
1200 gcc_assert (crtl
->emit
.regno_pointer_align_length
);
1202 crtl
->emit
.ensure_regno_capacity ();
1203 gcc_assert (reg_rtx_no
< crtl
->emit
.regno_pointer_align_length
);
1205 val
= gen_raw_REG (mode
, reg_rtx_no
);
1206 regno_reg_rtx
[reg_rtx_no
++] = val
;
1210 /* Make sure m_regno_pointer_align, and regno_reg_rtx are large
1211 enough to have elements in the range 0 <= idx <= reg_rtx_no. */
1214 emit_status::ensure_regno_capacity ()
1216 int old_size
= regno_pointer_align_length
;
1218 if (reg_rtx_no
< old_size
)
1221 int new_size
= old_size
* 2;
1222 while (reg_rtx_no
>= new_size
)
1225 char *tmp
= XRESIZEVEC (char, regno_pointer_align
, new_size
);
1226 memset (tmp
+ old_size
, 0, new_size
- old_size
);
1227 regno_pointer_align
= (unsigned char *) tmp
;
1229 rtx
*new1
= GGC_RESIZEVEC (rtx
, regno_reg_rtx
, new_size
);
1230 memset (new1
+ old_size
, 0, (new_size
- old_size
) * sizeof (rtx
));
1231 regno_reg_rtx
= new1
;
1233 crtl
->emit
.regno_pointer_align_length
= new_size
;
1236 /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */
1239 reg_is_parm_p (rtx reg
)
1243 gcc_assert (REG_P (reg
));
1244 decl
= REG_EXPR (reg
);
1245 return (decl
&& TREE_CODE (decl
) == PARM_DECL
);
1248 /* Update NEW with the same attributes as REG, but with OFFSET added
1249 to the REG_OFFSET. */
1252 update_reg_offset (rtx new_rtx
, rtx reg
, poly_int64 offset
)
1254 REG_ATTRS (new_rtx
) = get_reg_attrs (REG_EXPR (reg
),
1255 REG_OFFSET (reg
) + offset
);
1258 /* Generate a register with same attributes as REG, but with OFFSET
1259 added to the REG_OFFSET. */
1262 gen_rtx_REG_offset (rtx reg
, machine_mode mode
, unsigned int regno
,
1265 rtx new_rtx
= gen_rtx_REG (mode
, regno
);
1267 update_reg_offset (new_rtx
, reg
, offset
);
1271 /* Generate a new pseudo-register with the same attributes as REG, but
1272 with OFFSET added to the REG_OFFSET. */
1275 gen_reg_rtx_offset (rtx reg
, machine_mode mode
, int offset
)
1277 rtx new_rtx
= gen_reg_rtx (mode
);
1279 update_reg_offset (new_rtx
, reg
, offset
);
1283 /* Adjust REG in-place so that it has mode MODE. It is assumed that the
1284 new register is a (possibly paradoxical) lowpart of the old one. */
1287 adjust_reg_mode (rtx reg
, machine_mode mode
)
1289 update_reg_offset (reg
, reg
, byte_lowpart_offset (mode
, GET_MODE (reg
)));
1290 PUT_MODE (reg
, mode
);
1293 /* Copy REG's attributes from X, if X has any attributes. If REG and X
1294 have different modes, REG is a (possibly paradoxical) lowpart of X. */
1297 set_reg_attrs_from_value (rtx reg
, rtx x
)
1300 bool can_be_reg_pointer
= true;
1302 /* Don't call mark_reg_pointer for incompatible pointer sign
1304 while (GET_CODE (x
) == SIGN_EXTEND
1305 || GET_CODE (x
) == ZERO_EXTEND
1306 || GET_CODE (x
) == TRUNCATE
1307 || (GET_CODE (x
) == SUBREG
&& subreg_lowpart_p (x
)))
1309 #if defined(POINTERS_EXTEND_UNSIGNED)
1310 if (((GET_CODE (x
) == SIGN_EXTEND
&& POINTERS_EXTEND_UNSIGNED
)
1311 || (GET_CODE (x
) == ZERO_EXTEND
&& ! POINTERS_EXTEND_UNSIGNED
)
1312 || (paradoxical_subreg_p (x
)
1313 && ! (SUBREG_PROMOTED_VAR_P (x
)
1314 && SUBREG_CHECK_PROMOTED_SIGN (x
,
1315 POINTERS_EXTEND_UNSIGNED
))))
1316 && !targetm
.have_ptr_extend ())
1317 can_be_reg_pointer
= false;
1322 /* Hard registers can be reused for multiple purposes within the same
1323 function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN
1324 on them is wrong. */
1325 if (HARD_REGISTER_P (reg
))
1328 offset
= byte_lowpart_offset (GET_MODE (reg
), GET_MODE (x
));
1331 if (MEM_OFFSET_KNOWN_P (x
))
1332 REG_ATTRS (reg
) = get_reg_attrs (MEM_EXPR (x
),
1333 MEM_OFFSET (x
) + offset
);
1334 if (can_be_reg_pointer
&& MEM_POINTER (x
))
1335 mark_reg_pointer (reg
, 0);
1340 update_reg_offset (reg
, x
, offset
);
1341 if (can_be_reg_pointer
&& REG_POINTER (x
))
1342 mark_reg_pointer (reg
, REGNO_POINTER_ALIGN (REGNO (x
)));
1346 /* Generate a REG rtx for a new pseudo register, copying the mode
1347 and attributes from X. */
1350 gen_reg_rtx_and_attrs (rtx x
)
1352 rtx reg
= gen_reg_rtx (GET_MODE (x
));
1353 set_reg_attrs_from_value (reg
, x
);
1357 /* Set the register attributes for registers contained in PARM_RTX.
1358 Use needed values from memory attributes of MEM. */
1361 set_reg_attrs_for_parm (rtx parm_rtx
, rtx mem
)
1363 if (REG_P (parm_rtx
))
1364 set_reg_attrs_from_value (parm_rtx
, mem
);
1365 else if (GET_CODE (parm_rtx
) == PARALLEL
)
1367 /* Check for a NULL entry in the first slot, used to indicate that the
1368 parameter goes both on the stack and in registers. */
1369 int i
= XEXP (XVECEXP (parm_rtx
, 0, 0), 0) ? 0 : 1;
1370 for (; i
< XVECLEN (parm_rtx
, 0); i
++)
1372 rtx x
= XVECEXP (parm_rtx
, 0, i
);
1373 if (REG_P (XEXP (x
, 0)))
1374 REG_ATTRS (XEXP (x
, 0))
1375 = get_reg_attrs (MEM_EXPR (mem
),
1376 INTVAL (XEXP (x
, 1)));
1381 /* Set the REG_ATTRS for registers in value X, given that X represents
1385 set_reg_attrs_for_decl_rtl (tree t
, rtx x
)
1390 if (GET_CODE (x
) == SUBREG
)
1392 gcc_assert (subreg_lowpart_p (x
));
1397 = get_reg_attrs (t
, byte_lowpart_offset (GET_MODE (x
),
1400 : TYPE_MODE (TREE_TYPE (tdecl
))));
1401 if (GET_CODE (x
) == CONCAT
)
1403 if (REG_P (XEXP (x
, 0)))
1404 REG_ATTRS (XEXP (x
, 0)) = get_reg_attrs (t
, 0);
1405 if (REG_P (XEXP (x
, 1)))
1406 REG_ATTRS (XEXP (x
, 1))
1407 = get_reg_attrs (t
, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x
, 0))));
1409 if (GET_CODE (x
) == PARALLEL
)
1413 /* Check for a NULL entry, used to indicate that the parameter goes
1414 both on the stack and in registers. */
1415 if (XEXP (XVECEXP (x
, 0, 0), 0))
1420 for (i
= start
; i
< XVECLEN (x
, 0); i
++)
1422 rtx y
= XVECEXP (x
, 0, i
);
1423 if (REG_P (XEXP (y
, 0)))
1424 REG_ATTRS (XEXP (y
, 0)) = get_reg_attrs (t
, INTVAL (XEXP (y
, 1)));
1429 /* Assign the RTX X to declaration T. */
1432 set_decl_rtl (tree t
, rtx x
)
1434 DECL_WRTL_CHECK (t
)->decl_with_rtl
.rtl
= x
;
1436 set_reg_attrs_for_decl_rtl (t
, x
);
1439 /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true
1440 if the ABI requires the parameter to be passed by reference. */
1443 set_decl_incoming_rtl (tree t
, rtx x
, bool by_reference_p
)
1445 DECL_INCOMING_RTL (t
) = x
;
1446 if (x
&& !by_reference_p
)
1447 set_reg_attrs_for_decl_rtl (t
, x
);
1450 /* Identify REG (which may be a CONCAT) as a user register. */
1453 mark_user_reg (rtx reg
)
1455 if (GET_CODE (reg
) == CONCAT
)
1457 REG_USERVAR_P (XEXP (reg
, 0)) = 1;
1458 REG_USERVAR_P (XEXP (reg
, 1)) = 1;
1462 gcc_assert (REG_P (reg
));
1463 REG_USERVAR_P (reg
) = 1;
1467 /* Identify REG as a probable pointer register and show its alignment
1468 as ALIGN, if nonzero. */
1471 mark_reg_pointer (rtx reg
, int align
)
1473 if (! REG_POINTER (reg
))
1475 REG_POINTER (reg
) = 1;
1478 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1480 else if (align
&& align
< REGNO_POINTER_ALIGN (REGNO (reg
)))
1481 /* We can no-longer be sure just how aligned this pointer is. */
1482 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1485 /* Return 1 plus largest pseudo reg number used in the current function. */
1493 /* Return 1 + the largest label number used so far in the current function. */
1496 max_label_num (void)
1501 /* Return first label number used in this function (if any were used). */
1504 get_first_label_num (void)
1506 return first_label_num
;
1509 /* If the rtx for label was created during the expansion of a nested
1510 function, then first_label_num won't include this label number.
1511 Fix this now so that array indices work later. */
1514 maybe_set_first_label_num (rtx_code_label
*x
)
1516 if (CODE_LABEL_NUMBER (x
) < first_label_num
)
1517 first_label_num
= CODE_LABEL_NUMBER (x
);
1520 /* For use by the RTL function loader, when mingling with normal
1522 Ensure that label_num is greater than the label num of X, to avoid
1523 duplicate labels in the generated assembler. */
1526 maybe_set_max_label_num (rtx_code_label
*x
)
1528 if (CODE_LABEL_NUMBER (x
) >= label_num
)
1529 label_num
= CODE_LABEL_NUMBER (x
) + 1;
1533 /* Return a value representing some low-order bits of X, where the number
1534 of low-order bits is given by MODE. Note that no conversion is done
1535 between floating-point and fixed-point values, rather, the bit
1536 representation is returned.
1538 This function handles the cases in common between gen_lowpart, below,
1539 and two variants in cse.c and combine.c. These are the cases that can
1540 be safely handled at all points in the compilation.
1542 If this is not a case we can handle, return 0. */
1545 gen_lowpart_common (machine_mode mode
, rtx x
)
1547 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1548 machine_mode innermode
;
1550 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1551 so we have to make one up. Yuk. */
1552 innermode
= GET_MODE (x
);
1554 && known_le (msize
* BITS_PER_UNIT
,
1555 (unsigned HOST_WIDE_INT
) HOST_BITS_PER_WIDE_INT
))
1556 innermode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1557 else if (innermode
== VOIDmode
)
1558 innermode
= int_mode_for_size (HOST_BITS_PER_DOUBLE_INT
, 0).require ();
1560 gcc_assert (innermode
!= VOIDmode
&& innermode
!= BLKmode
);
1562 if (innermode
== mode
)
1565 /* The size of the outer and inner modes must be ordered. */
1566 poly_uint64 xsize
= GET_MODE_SIZE (innermode
);
1567 if (!ordered_p (msize
, xsize
))
1570 if (SCALAR_FLOAT_MODE_P (mode
))
1572 /* Don't allow paradoxical FLOAT_MODE subregs. */
1573 if (maybe_gt (msize
, xsize
))
1578 /* MODE must occupy no more of the underlying registers than X. */
1579 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (innermode
);
1580 unsigned int mregs
, xregs
;
1581 if (!can_div_away_from_zero_p (msize
, regsize
, &mregs
)
1582 || !can_div_away_from_zero_p (xsize
, regsize
, &xregs
)
1587 scalar_int_mode int_mode
, int_innermode
, from_mode
;
1588 if ((GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
1589 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1590 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
1591 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &from_mode
))
1593 /* If we are getting the low-order part of something that has been
1594 sign- or zero-extended, we can either just use the object being
1595 extended or make a narrower extension. If we want an even smaller
1596 piece than the size of the object being extended, call ourselves
1599 This case is used mostly by combine and cse. */
1601 if (from_mode
== int_mode
)
1603 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (from_mode
))
1604 return gen_lowpart_common (int_mode
, XEXP (x
, 0));
1605 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (int_innermode
))
1606 return gen_rtx_fmt_e (GET_CODE (x
), int_mode
, XEXP (x
, 0));
1608 else if (GET_CODE (x
) == SUBREG
|| REG_P (x
)
1609 || GET_CODE (x
) == CONCAT
|| GET_CODE (x
) == CONST_VECTOR
1610 || CONST_DOUBLE_AS_FLOAT_P (x
) || CONST_SCALAR_INT_P (x
)
1611 || CONST_POLY_INT_P (x
))
1612 return lowpart_subreg (mode
, x
, innermode
);
1614 /* Otherwise, we can't do this. */
1619 gen_highpart (machine_mode mode
, rtx x
)
1621 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1624 /* This case loses if X is a subreg. To catch bugs early,
1625 complain if an invalid MODE is used even in other cases. */
1626 gcc_assert (known_le (msize
, (unsigned int) UNITS_PER_WORD
)
1627 || known_eq (msize
, GET_MODE_UNIT_SIZE (GET_MODE (x
))));
1629 result
= simplify_gen_subreg (mode
, x
, GET_MODE (x
),
1630 subreg_highpart_offset (mode
, GET_MODE (x
)));
1631 gcc_assert (result
);
1633 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1634 the target if we have a MEM. gen_highpart must return a valid operand,
1635 emitting code if necessary to do so. */
1638 result
= validize_mem (result
);
1639 gcc_assert (result
);
1645 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1646 be VOIDmode constant. */
1648 gen_highpart_mode (machine_mode outermode
, machine_mode innermode
, rtx exp
)
1650 if (GET_MODE (exp
) != VOIDmode
)
1652 gcc_assert (GET_MODE (exp
) == innermode
);
1653 return gen_highpart (outermode
, exp
);
1655 return simplify_gen_subreg (outermode
, exp
, innermode
,
1656 subreg_highpart_offset (outermode
, innermode
));
1659 /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has
1660 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1663 subreg_size_lowpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1665 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
1666 if (maybe_gt (outer_bytes
, inner_bytes
))
1667 /* Paradoxical subregs always have a SUBREG_BYTE of 0. */
1670 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1671 return inner_bytes
- outer_bytes
;
1672 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1675 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
, 0);
1678 /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has
1679 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1682 subreg_size_highpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1684 gcc_assert (known_ge (inner_bytes
, outer_bytes
));
1686 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1688 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1689 return inner_bytes
- outer_bytes
;
1691 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
,
1692 (inner_bytes
- outer_bytes
)
1696 /* Return 1 iff X, assumed to be a SUBREG,
1697 refers to the least significant part of its containing reg.
1698 If X is not a SUBREG, always return 1 (it is its own low part!). */
1701 subreg_lowpart_p (const_rtx x
)
1703 if (GET_CODE (x
) != SUBREG
)
1705 else if (GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
1708 return known_eq (subreg_lowpart_offset (GET_MODE (x
),
1709 GET_MODE (SUBREG_REG (x
))),
1713 /* Return subword OFFSET of operand OP.
1714 The word number, OFFSET, is interpreted as the word number starting
1715 at the low-order address. OFFSET 0 is the low-order word if not
1716 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1718 If we cannot extract the required word, we return zero. Otherwise,
1719 an rtx corresponding to the requested word will be returned.
1721 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1722 reload has completed, a valid address will always be returned. After
1723 reload, if a valid address cannot be returned, we return zero.
1725 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1726 it is the responsibility of the caller.
1728 MODE is the mode of OP in case it is a CONST_INT.
1730 ??? This is still rather broken for some cases. The problem for the
1731 moment is that all callers of this thing provide no 'goal mode' to
1732 tell us to work with. This exists because all callers were written
1733 in a word based SUBREG world.
1734 Now use of this function can be deprecated by simplify_subreg in most
1739 operand_subword (rtx op
, poly_uint64 offset
, int validate_address
,
1742 if (mode
== VOIDmode
)
1743 mode
= GET_MODE (op
);
1745 gcc_assert (mode
!= VOIDmode
);
1747 /* If OP is narrower than a word, fail. */
1749 && maybe_lt (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
1752 /* If we want a word outside OP, return zero. */
1754 && maybe_gt ((offset
+ 1) * UNITS_PER_WORD
, GET_MODE_SIZE (mode
)))
1757 /* Form a new MEM at the requested address. */
1760 rtx new_rtx
= adjust_address_nv (op
, word_mode
, offset
* UNITS_PER_WORD
);
1762 if (! validate_address
)
1765 else if (reload_completed
)
1767 if (! strict_memory_address_addr_space_p (word_mode
,
1769 MEM_ADDR_SPACE (op
)))
1773 return replace_equiv_address (new_rtx
, XEXP (new_rtx
, 0));
1776 /* Rest can be handled by simplify_subreg. */
1777 return simplify_gen_subreg (word_mode
, op
, mode
, (offset
* UNITS_PER_WORD
));
1780 /* Similar to `operand_subword', but never return 0. If we can't
1781 extract the required subword, put OP into a register and try again.
1782 The second attempt must succeed. We always validate the address in
1785 MODE is the mode of OP, in case it is CONST_INT. */
1788 operand_subword_force (rtx op
, poly_uint64 offset
, machine_mode mode
)
1790 rtx result
= operand_subword (op
, offset
, 1, mode
);
1795 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
1797 /* If this is a register which cannot be accessed by words, copy it
1798 to a pseudo register. */
1800 op
= copy_to_reg (op
);
1802 op
= force_reg (mode
, op
);
1805 result
= operand_subword (op
, offset
, 1, mode
);
1806 gcc_assert (result
);
1811 mem_attrs::mem_attrs ()
1817 addrspace (ADDR_SPACE_GENERIC
),
1818 offset_known_p (false),
1819 size_known_p (false)
1822 /* Returns 1 if both MEM_EXPR can be considered equal
1826 mem_expr_equal_p (const_tree expr1
, const_tree expr2
)
1831 if (! expr1
|| ! expr2
)
1834 if (TREE_CODE (expr1
) != TREE_CODE (expr2
))
1837 return operand_equal_p (expr1
, expr2
, 0);
1840 /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN
1841 bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or
1845 get_mem_align_offset (rtx mem
, unsigned int align
)
1850 /* This function can't use
1851 if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem)
1852 || (MAX (MEM_ALIGN (mem),
1853 MAX (align, get_object_alignment (MEM_EXPR (mem))))
1857 return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1);
1859 - COMPONENT_REFs in MEM_EXPR can have NULL first operand,
1860 for <variable>. get_inner_reference doesn't handle it and
1861 even if it did, the alignment in that case needs to be determined
1862 from DECL_FIELD_CONTEXT's TYPE_ALIGN.
1863 - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR
1864 isn't sufficiently aligned, the object it is in might be. */
1865 gcc_assert (MEM_P (mem
));
1866 expr
= MEM_EXPR (mem
);
1867 if (expr
== NULL_TREE
|| !MEM_OFFSET_KNOWN_P (mem
))
1870 offset
= MEM_OFFSET (mem
);
1873 if (DECL_ALIGN (expr
) < align
)
1876 else if (INDIRECT_REF_P (expr
))
1878 if (TYPE_ALIGN (TREE_TYPE (expr
)) < (unsigned int) align
)
1881 else if (TREE_CODE (expr
) == COMPONENT_REF
)
1885 tree inner
= TREE_OPERAND (expr
, 0);
1886 tree field
= TREE_OPERAND (expr
, 1);
1887 tree byte_offset
= component_ref_field_offset (expr
);
1888 tree bit_offset
= DECL_FIELD_BIT_OFFSET (field
);
1890 poly_uint64 suboffset
;
1892 || !poly_int_tree_p (byte_offset
, &suboffset
)
1893 || !tree_fits_uhwi_p (bit_offset
))
1896 offset
+= suboffset
;
1897 offset
+= tree_to_uhwi (bit_offset
) / BITS_PER_UNIT
;
1899 if (inner
== NULL_TREE
)
1901 if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field
))
1902 < (unsigned int) align
)
1906 else if (DECL_P (inner
))
1908 if (DECL_ALIGN (inner
) < align
)
1912 else if (TREE_CODE (inner
) != COMPONENT_REF
)
1920 HOST_WIDE_INT misalign
;
1921 if (!known_misalignment (offset
, align
/ BITS_PER_UNIT
, &misalign
))
1926 /* Given REF (a MEM) and T, either the type of X or the expression
1927 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1928 if we are making a new object of this type. BITPOS is nonzero if
1929 there is an offset outstanding on T that will be applied later. */
1932 set_mem_attributes_minus_bitpos (rtx ref
, tree t
, int objectp
,
1935 poly_int64 apply_bitpos
= 0;
1937 class mem_attrs attrs
, *defattrs
, *refattrs
;
1940 /* It can happen that type_for_mode was given a mode for which there
1941 is no language-level type. In which case it returns NULL, which
1946 type
= TYPE_P (t
) ? t
: TREE_TYPE (t
);
1947 if (type
== error_mark_node
)
1950 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1951 wrong answer, as it assumes that DECL_RTL already has the right alias
1952 info. Callers should not set DECL_RTL until after the call to
1953 set_mem_attributes. */
1954 gcc_assert (!DECL_P (t
) || ref
!= DECL_RTL_IF_SET (t
));
1956 /* Get the alias set from the expression or type (perhaps using a
1957 front-end routine) and use it. */
1958 attrs
.alias
= get_alias_set (t
);
1960 MEM_VOLATILE_P (ref
) |= TYPE_VOLATILE (type
);
1961 MEM_POINTER (ref
) = POINTER_TYPE_P (type
);
1963 /* Default values from pre-existing memory attributes if present. */
1964 refattrs
= MEM_ATTRS (ref
);
1967 /* ??? Can this ever happen? Calling this routine on a MEM that
1968 already carries memory attributes should probably be invalid. */
1969 attrs
.expr
= refattrs
->expr
;
1970 attrs
.offset_known_p
= refattrs
->offset_known_p
;
1971 attrs
.offset
= refattrs
->offset
;
1972 attrs
.size_known_p
= refattrs
->size_known_p
;
1973 attrs
.size
= refattrs
->size
;
1974 attrs
.align
= refattrs
->align
;
1977 /* Otherwise, default values from the mode of the MEM reference. */
1980 defattrs
= mode_mem_attrs
[(int) GET_MODE (ref
)];
1981 gcc_assert (!defattrs
->expr
);
1982 gcc_assert (!defattrs
->offset_known_p
);
1984 /* Respect mode size. */
1985 attrs
.size_known_p
= defattrs
->size_known_p
;
1986 attrs
.size
= defattrs
->size
;
1987 /* ??? Is this really necessary? We probably should always get
1988 the size from the type below. */
1990 /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type;
1991 if T is an object, always compute the object alignment below. */
1993 attrs
.align
= defattrs
->align
;
1995 attrs
.align
= BITS_PER_UNIT
;
1996 /* ??? If T is a type, respecting mode alignment may *also* be wrong
1997 e.g. if the type carries an alignment attribute. Should we be
1998 able to simply always use TYPE_ALIGN? */
2001 /* We can set the alignment from the type if we are making an object or if
2002 this is an INDIRECT_REF. */
2003 if (objectp
|| TREE_CODE (t
) == INDIRECT_REF
)
2004 attrs
.align
= MAX (attrs
.align
, TYPE_ALIGN (type
));
2006 /* If the size is known, we can set that. */
2007 tree new_size
= TYPE_SIZE_UNIT (type
);
2009 /* The address-space is that of the type. */
2010 as
= TYPE_ADDR_SPACE (type
);
2012 /* If T is not a type, we may be able to deduce some more information about
2018 if (TREE_THIS_VOLATILE (t
))
2019 MEM_VOLATILE_P (ref
) = 1;
2021 /* Now remove any conversions: they don't change what the underlying
2022 object is. Likewise for SAVE_EXPR. */
2023 while (CONVERT_EXPR_P (t
)
2024 || TREE_CODE (t
) == VIEW_CONVERT_EXPR
2025 || TREE_CODE (t
) == SAVE_EXPR
)
2026 t
= TREE_OPERAND (t
, 0);
2028 /* Note whether this expression can trap. */
2029 MEM_NOTRAP_P (ref
) = !tree_could_trap_p (t
);
2031 base
= get_base_address (t
);
2035 && TREE_READONLY (base
)
2036 && (TREE_STATIC (base
) || DECL_EXTERNAL (base
))
2037 && !TREE_THIS_VOLATILE (base
))
2038 MEM_READONLY_P (ref
) = 1;
2040 /* Mark static const strings readonly as well. */
2041 if (TREE_CODE (base
) == STRING_CST
2042 && TREE_READONLY (base
)
2043 && TREE_STATIC (base
))
2044 MEM_READONLY_P (ref
) = 1;
2046 /* Address-space information is on the base object. */
2047 if (TREE_CODE (base
) == MEM_REF
2048 || TREE_CODE (base
) == TARGET_MEM_REF
)
2049 as
= TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base
,
2052 as
= TYPE_ADDR_SPACE (TREE_TYPE (base
));
2055 /* If this expression uses it's parent's alias set, mark it such
2056 that we won't change it. */
2057 if (component_uses_parent_alias_set_from (t
) != NULL_TREE
)
2058 MEM_KEEP_ALIAS_SET_P (ref
) = 1;
2060 /* If this is a decl, set the attributes of the MEM from it. */
2064 attrs
.offset_known_p
= true;
2066 apply_bitpos
= bitpos
;
2067 new_size
= DECL_SIZE_UNIT (t
);
2070 /* ??? If we end up with a constant here do record a MEM_EXPR. */
2071 else if (CONSTANT_CLASS_P (t
))
2074 /* If this is a field reference, record it. */
2075 else if (TREE_CODE (t
) == COMPONENT_REF
)
2078 attrs
.offset_known_p
= true;
2080 apply_bitpos
= bitpos
;
2081 if (DECL_BIT_FIELD (TREE_OPERAND (t
, 1)))
2082 new_size
= DECL_SIZE_UNIT (TREE_OPERAND (t
, 1));
2085 /* If this is an array reference, look for an outer field reference. */
2086 else if (TREE_CODE (t
) == ARRAY_REF
)
2088 tree off_tree
= size_zero_node
;
2089 /* We can't modify t, because we use it at the end of the
2095 tree index
= TREE_OPERAND (t2
, 1);
2096 tree low_bound
= array_ref_low_bound (t2
);
2097 tree unit_size
= array_ref_element_size (t2
);
2099 /* We assume all arrays have sizes that are a multiple of a byte.
2100 First subtract the lower bound, if any, in the type of the
2101 index, then convert to sizetype and multiply by the size of
2102 the array element. */
2103 if (! integer_zerop (low_bound
))
2104 index
= fold_build2 (MINUS_EXPR
, TREE_TYPE (index
),
2107 off_tree
= size_binop (PLUS_EXPR
,
2108 size_binop (MULT_EXPR
,
2109 fold_convert (sizetype
,
2113 t2
= TREE_OPERAND (t2
, 0);
2115 while (TREE_CODE (t2
) == ARRAY_REF
);
2118 || (TREE_CODE (t2
) == COMPONENT_REF
2119 /* For trailing arrays t2 doesn't have a size that
2120 covers all valid accesses. */
2121 && ! array_at_struct_end_p (t
)))
2124 attrs
.offset_known_p
= false;
2125 if (poly_int_tree_p (off_tree
, &attrs
.offset
))
2127 attrs
.offset_known_p
= true;
2128 apply_bitpos
= bitpos
;
2131 /* Else do not record a MEM_EXPR. */
2134 /* If this is an indirect reference, record it. */
2135 else if (TREE_CODE (t
) == MEM_REF
2136 || TREE_CODE (t
) == TARGET_MEM_REF
)
2139 attrs
.offset_known_p
= true;
2141 apply_bitpos
= bitpos
;
2144 /* If this is a reference based on a partitioned decl replace the
2145 base with a MEM_REF of the pointer representative we created
2146 during stack slot partitioning. */
2149 && ! is_global_var (base
)
2150 && cfun
->gimple_df
->decls_to_pointers
!= NULL
)
2152 tree
*namep
= cfun
->gimple_df
->decls_to_pointers
->get (base
);
2155 attrs
.expr
= unshare_expr (attrs
.expr
);
2156 tree
*orig_base
= &attrs
.expr
;
2157 while (handled_component_p (*orig_base
))
2158 orig_base
= &TREE_OPERAND (*orig_base
, 0);
2159 tree aptrt
= reference_alias_ptr_type (*orig_base
);
2160 *orig_base
= build2 (MEM_REF
, TREE_TYPE (*orig_base
), *namep
,
2161 build_int_cst (aptrt
, 0));
2165 /* Compute the alignment. */
2166 unsigned int obj_align
;
2167 unsigned HOST_WIDE_INT obj_bitpos
;
2168 get_object_alignment_1 (t
, &obj_align
, &obj_bitpos
);
2169 unsigned int diff_align
= known_alignment (obj_bitpos
- bitpos
);
2170 if (diff_align
!= 0)
2171 obj_align
= MIN (obj_align
, diff_align
);
2172 attrs
.align
= MAX (attrs
.align
, obj_align
);
2175 poly_uint64 const_size
;
2176 if (poly_int_tree_p (new_size
, &const_size
))
2178 attrs
.size_known_p
= true;
2179 attrs
.size
= const_size
;
2182 /* If we modified OFFSET based on T, then subtract the outstanding
2183 bit position offset. Similarly, increase the size of the accessed
2184 object to contain the negative offset. */
2185 if (maybe_ne (apply_bitpos
, 0))
2187 gcc_assert (attrs
.offset_known_p
);
2188 poly_int64 bytepos
= bits_to_bytes_round_down (apply_bitpos
);
2189 attrs
.offset
-= bytepos
;
2190 if (attrs
.size_known_p
)
2191 attrs
.size
+= bytepos
;
2194 /* Now set the attributes we computed above. */
2195 attrs
.addrspace
= as
;
2196 set_mem_attrs (ref
, &attrs
);
2200 set_mem_attributes (rtx ref
, tree t
, int objectp
)
2202 set_mem_attributes_minus_bitpos (ref
, t
, objectp
, 0);
2205 /* Set the alias set of MEM to SET. */
2208 set_mem_alias_set (rtx mem
, alias_set_type set
)
2210 /* If the new and old alias sets don't conflict, something is wrong. */
2211 gcc_checking_assert (alias_sets_conflict_p (set
, MEM_ALIAS_SET (mem
)));
2212 mem_attrs
attrs (*get_mem_attrs (mem
));
2214 set_mem_attrs (mem
, &attrs
);
2217 /* Set the address space of MEM to ADDRSPACE (target-defined). */
2220 set_mem_addr_space (rtx mem
, addr_space_t addrspace
)
2222 mem_attrs
attrs (*get_mem_attrs (mem
));
2223 attrs
.addrspace
= addrspace
;
2224 set_mem_attrs (mem
, &attrs
);
2227 /* Set the alignment of MEM to ALIGN bits. */
2230 set_mem_align (rtx mem
, unsigned int align
)
2232 mem_attrs
attrs (*get_mem_attrs (mem
));
2233 attrs
.align
= align
;
2234 set_mem_attrs (mem
, &attrs
);
2237 /* Set the expr for MEM to EXPR. */
2240 set_mem_expr (rtx mem
, tree expr
)
2242 mem_attrs
attrs (*get_mem_attrs (mem
));
2244 set_mem_attrs (mem
, &attrs
);
2247 /* Set the offset of MEM to OFFSET. */
2250 set_mem_offset (rtx mem
, poly_int64 offset
)
2252 mem_attrs
attrs (*get_mem_attrs (mem
));
2253 attrs
.offset_known_p
= true;
2254 attrs
.offset
= offset
;
2255 set_mem_attrs (mem
, &attrs
);
2258 /* Clear the offset of MEM. */
2261 clear_mem_offset (rtx mem
)
2263 mem_attrs
attrs (*get_mem_attrs (mem
));
2264 attrs
.offset_known_p
= false;
2265 set_mem_attrs (mem
, &attrs
);
2268 /* Set the size of MEM to SIZE. */
2271 set_mem_size (rtx mem
, poly_int64 size
)
2273 mem_attrs
attrs (*get_mem_attrs (mem
));
2274 attrs
.size_known_p
= true;
2276 set_mem_attrs (mem
, &attrs
);
2279 /* Clear the size of MEM. */
2282 clear_mem_size (rtx mem
)
2284 mem_attrs
attrs (*get_mem_attrs (mem
));
2285 attrs
.size_known_p
= false;
2286 set_mem_attrs (mem
, &attrs
);
2289 /* Return a memory reference like MEMREF, but with its mode changed to MODE
2290 and its address changed to ADDR. (VOIDmode means don't change the mode.
2291 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
2292 returned memory location is required to be valid. INPLACE is true if any
2293 changes can be made directly to MEMREF or false if MEMREF must be treated
2296 The memory attributes are not changed. */
2299 change_address_1 (rtx memref
, machine_mode mode
, rtx addr
, int validate
,
2305 gcc_assert (MEM_P (memref
));
2306 as
= MEM_ADDR_SPACE (memref
);
2307 if (mode
== VOIDmode
)
2308 mode
= GET_MODE (memref
);
2310 addr
= XEXP (memref
, 0);
2311 if (mode
== GET_MODE (memref
) && addr
== XEXP (memref
, 0)
2312 && (!validate
|| memory_address_addr_space_p (mode
, addr
, as
)))
2315 /* Don't validate address for LRA. LRA can make the address valid
2316 by itself in most efficient way. */
2317 if (validate
&& !lra_in_progress
)
2319 if (reload_in_progress
|| reload_completed
)
2320 gcc_assert (memory_address_addr_space_p (mode
, addr
, as
));
2322 addr
= memory_address_addr_space (mode
, addr
, as
);
2325 if (rtx_equal_p (addr
, XEXP (memref
, 0)) && mode
== GET_MODE (memref
))
2330 XEXP (memref
, 0) = addr
;
2334 new_rtx
= gen_rtx_MEM (mode
, addr
);
2335 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2339 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
2340 way we are changing MEMREF, so we only preserve the alias set. */
2343 change_address (rtx memref
, machine_mode mode
, rtx addr
)
2345 rtx new_rtx
= change_address_1 (memref
, mode
, addr
, 1, false);
2346 machine_mode mmode
= GET_MODE (new_rtx
);
2347 class mem_attrs
*defattrs
;
2349 mem_attrs
attrs (*get_mem_attrs (memref
));
2350 defattrs
= mode_mem_attrs
[(int) mmode
];
2351 attrs
.expr
= NULL_TREE
;
2352 attrs
.offset_known_p
= false;
2353 attrs
.size_known_p
= defattrs
->size_known_p
;
2354 attrs
.size
= defattrs
->size
;
2355 attrs
.align
= defattrs
->align
;
2357 /* If there are no changes, just return the original memory reference. */
2358 if (new_rtx
== memref
)
2360 if (mem_attrs_eq_p (get_mem_attrs (memref
), &attrs
))
2363 new_rtx
= gen_rtx_MEM (mmode
, XEXP (memref
, 0));
2364 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2367 set_mem_attrs (new_rtx
, &attrs
);
2371 /* Return a memory reference like MEMREF, but with its mode changed
2372 to MODE and its address offset by OFFSET bytes. If VALIDATE is
2373 nonzero, the memory address is forced to be valid.
2374 If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS
2375 and the caller is responsible for adjusting MEMREF base register.
2376 If ADJUST_OBJECT is zero, the underlying object associated with the
2377 memory reference is left unchanged and the caller is responsible for
2378 dealing with it. Otherwise, if the new memory reference is outside
2379 the underlying object, even partially, then the object is dropped.
2380 SIZE, if nonzero, is the size of an access in cases where MODE
2381 has no inherent size. */
2384 adjust_address_1 (rtx memref
, machine_mode mode
, poly_int64 offset
,
2385 int validate
, int adjust_address
, int adjust_object
,
2388 rtx addr
= XEXP (memref
, 0);
2390 scalar_int_mode address_mode
;
2391 class mem_attrs
attrs (*get_mem_attrs (memref
)), *defattrs
;
2392 unsigned HOST_WIDE_INT max_align
;
2393 #ifdef POINTERS_EXTEND_UNSIGNED
2394 scalar_int_mode pointer_mode
2395 = targetm
.addr_space
.pointer_mode (attrs
.addrspace
);
2398 /* VOIDmode means no mode change for change_address_1. */
2399 if (mode
== VOIDmode
)
2400 mode
= GET_MODE (memref
);
2402 /* Take the size of non-BLKmode accesses from the mode. */
2403 defattrs
= mode_mem_attrs
[(int) mode
];
2404 if (defattrs
->size_known_p
)
2405 size
= defattrs
->size
;
2407 /* If there are no changes, just return the original memory reference. */
2408 if (mode
== GET_MODE (memref
)
2409 && known_eq (offset
, 0)
2410 && (known_eq (size
, 0)
2411 || (attrs
.size_known_p
&& known_eq (attrs
.size
, size
)))
2412 && (!validate
|| memory_address_addr_space_p (mode
, addr
,
2416 /* ??? Prefer to create garbage instead of creating shared rtl.
2417 This may happen even if offset is nonzero -- consider
2418 (plus (plus reg reg) const_int) -- so do this always. */
2419 addr
= copy_rtx (addr
);
2421 /* Convert a possibly large offset to a signed value within the
2422 range of the target address space. */
2423 address_mode
= get_address_mode (memref
);
2424 offset
= trunc_int_for_mode (offset
, address_mode
);
2428 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
2429 object, we can merge it into the LO_SUM. */
2430 if (GET_MODE (memref
) != BLKmode
2431 && GET_CODE (addr
) == LO_SUM
2432 && known_in_range_p (offset
,
2433 0, (GET_MODE_ALIGNMENT (GET_MODE (memref
))
2435 addr
= gen_rtx_LO_SUM (address_mode
, XEXP (addr
, 0),
2436 plus_constant (address_mode
,
2437 XEXP (addr
, 1), offset
));
2438 #ifdef POINTERS_EXTEND_UNSIGNED
2439 /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid
2440 in that mode, we merge it into the ZERO_EXTEND. We take advantage of
2441 the fact that pointers are not allowed to overflow. */
2442 else if (POINTERS_EXTEND_UNSIGNED
> 0
2443 && GET_CODE (addr
) == ZERO_EXTEND
2444 && GET_MODE (XEXP (addr
, 0)) == pointer_mode
2445 && known_eq (trunc_int_for_mode (offset
, pointer_mode
), offset
))
2446 addr
= gen_rtx_ZERO_EXTEND (address_mode
,
2447 plus_constant (pointer_mode
,
2448 XEXP (addr
, 0), offset
));
2451 addr
= plus_constant (address_mode
, addr
, offset
);
2454 new_rtx
= change_address_1 (memref
, mode
, addr
, validate
, false);
2456 /* If the address is a REG, change_address_1 rightfully returns memref,
2457 but this would destroy memref's MEM_ATTRS. */
2458 if (new_rtx
== memref
&& maybe_ne (offset
, 0))
2459 new_rtx
= copy_rtx (new_rtx
);
2461 /* Conservatively drop the object if we don't know where we start from. */
2462 if (adjust_object
&& (!attrs
.offset_known_p
|| !attrs
.size_known_p
))
2464 attrs
.expr
= NULL_TREE
;
2468 /* Compute the new values of the memory attributes due to this adjustment.
2469 We add the offsets and update the alignment. */
2470 if (attrs
.offset_known_p
)
2472 attrs
.offset
+= offset
;
2474 /* Drop the object if the new left end is not within its bounds. */
2475 if (adjust_object
&& maybe_lt (attrs
.offset
, 0))
2477 attrs
.expr
= NULL_TREE
;
2482 /* Compute the new alignment by taking the MIN of the alignment and the
2483 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
2485 if (maybe_ne (offset
, 0))
2487 max_align
= known_alignment (offset
) * BITS_PER_UNIT
;
2488 attrs
.align
= MIN (attrs
.align
, max_align
);
2491 if (maybe_ne (size
, 0))
2493 /* Drop the object if the new right end is not within its bounds. */
2494 if (adjust_object
&& maybe_gt (offset
+ size
, attrs
.size
))
2496 attrs
.expr
= NULL_TREE
;
2499 attrs
.size_known_p
= true;
2502 else if (attrs
.size_known_p
)
2504 gcc_assert (!adjust_object
);
2505 attrs
.size
-= offset
;
2506 /* ??? The store_by_pieces machinery generates negative sizes,
2507 so don't assert for that here. */
2510 set_mem_attrs (new_rtx
, &attrs
);
2515 /* Return a memory reference like MEMREF, but with its mode changed
2516 to MODE and its address changed to ADDR, which is assumed to be
2517 MEMREF offset by OFFSET bytes. If VALIDATE is
2518 nonzero, the memory address is forced to be valid. */
2521 adjust_automodify_address_1 (rtx memref
, machine_mode mode
, rtx addr
,
2522 poly_int64 offset
, int validate
)
2524 memref
= change_address_1 (memref
, VOIDmode
, addr
, validate
, false);
2525 return adjust_address_1 (memref
, mode
, offset
, validate
, 0, 0, 0);
2528 /* Return a memory reference like MEMREF, but whose address is changed by
2529 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
2530 known to be in OFFSET (possibly 1). */
2533 offset_address (rtx memref
, rtx offset
, unsigned HOST_WIDE_INT pow2
)
2535 rtx new_rtx
, addr
= XEXP (memref
, 0);
2536 machine_mode address_mode
;
2537 class mem_attrs
*defattrs
;
2539 mem_attrs
attrs (*get_mem_attrs (memref
));
2540 address_mode
= get_address_mode (memref
);
2541 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2543 /* At this point we don't know _why_ the address is invalid. It
2544 could have secondary memory references, multiplies or anything.
2546 However, if we did go and rearrange things, we can wind up not
2547 being able to recognize the magic around pic_offset_table_rtx.
2548 This stuff is fragile, and is yet another example of why it is
2549 bad to expose PIC machinery too early. */
2550 if (! memory_address_addr_space_p (GET_MODE (memref
), new_rtx
,
2552 && GET_CODE (addr
) == PLUS
2553 && XEXP (addr
, 0) == pic_offset_table_rtx
)
2555 addr
= force_reg (GET_MODE (addr
), addr
);
2556 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2559 update_temp_slot_address (XEXP (memref
, 0), new_rtx
);
2560 new_rtx
= change_address_1 (memref
, VOIDmode
, new_rtx
, 1, false);
2562 /* If there are no changes, just return the original memory reference. */
2563 if (new_rtx
== memref
)
2566 /* Update the alignment to reflect the offset. Reset the offset, which
2568 defattrs
= mode_mem_attrs
[(int) GET_MODE (new_rtx
)];
2569 attrs
.offset_known_p
= false;
2570 attrs
.size_known_p
= defattrs
->size_known_p
;
2571 attrs
.size
= defattrs
->size
;
2572 attrs
.align
= MIN (attrs
.align
, pow2
* BITS_PER_UNIT
);
2573 set_mem_attrs (new_rtx
, &attrs
);
2577 /* Return a memory reference like MEMREF, but with its address changed to
2578 ADDR. The caller is asserting that the actual piece of memory pointed
2579 to is the same, just the form of the address is being changed, such as
2580 by putting something into a register. INPLACE is true if any changes
2581 can be made directly to MEMREF or false if MEMREF must be treated as
2585 replace_equiv_address (rtx memref
, rtx addr
, bool inplace
)
2587 /* change_address_1 copies the memory attribute structure without change
2588 and that's exactly what we want here. */
2589 update_temp_slot_address (XEXP (memref
, 0), addr
);
2590 return change_address_1 (memref
, VOIDmode
, addr
, 1, inplace
);
2593 /* Likewise, but the reference is not required to be valid. */
2596 replace_equiv_address_nv (rtx memref
, rtx addr
, bool inplace
)
2598 return change_address_1 (memref
, VOIDmode
, addr
, 0, inplace
);
2601 /* Return a memory reference like MEMREF, but with its mode widened to
2602 MODE and offset by OFFSET. This would be used by targets that e.g.
2603 cannot issue QImode memory operations and have to use SImode memory
2604 operations plus masking logic. */
2607 widen_memory_access (rtx memref
, machine_mode mode
, poly_int64 offset
)
2609 rtx new_rtx
= adjust_address_1 (memref
, mode
, offset
, 1, 1, 0, 0);
2610 poly_uint64 size
= GET_MODE_SIZE (mode
);
2612 /* If there are no changes, just return the original memory reference. */
2613 if (new_rtx
== memref
)
2616 mem_attrs
attrs (*get_mem_attrs (new_rtx
));
2618 /* If we don't know what offset we were at within the expression, then
2619 we can't know if we've overstepped the bounds. */
2620 if (! attrs
.offset_known_p
)
2621 attrs
.expr
= NULL_TREE
;
2625 if (TREE_CODE (attrs
.expr
) == COMPONENT_REF
)
2627 tree field
= TREE_OPERAND (attrs
.expr
, 1);
2628 tree offset
= component_ref_field_offset (attrs
.expr
);
2630 if (! DECL_SIZE_UNIT (field
))
2632 attrs
.expr
= NULL_TREE
;
2636 /* Is the field at least as large as the access? If so, ok,
2637 otherwise strip back to the containing structure. */
2638 if (poly_int_tree_p (DECL_SIZE_UNIT (field
))
2639 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field
)), size
)
2640 && known_ge (attrs
.offset
, 0))
2643 poly_uint64 suboffset
;
2644 if (!poly_int_tree_p (offset
, &suboffset
))
2646 attrs
.expr
= NULL_TREE
;
2650 attrs
.expr
= TREE_OPERAND (attrs
.expr
, 0);
2651 attrs
.offset
+= suboffset
;
2652 attrs
.offset
+= (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field
))
2655 /* Similarly for the decl. */
2656 else if (DECL_P (attrs
.expr
)
2657 && DECL_SIZE_UNIT (attrs
.expr
)
2658 && poly_int_tree_p (DECL_SIZE_UNIT (attrs
.expr
))
2659 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs
.expr
)),
2661 && known_ge (attrs
.offset
, 0))
2665 /* The widened memory access overflows the expression, which means
2666 that it could alias another expression. Zap it. */
2667 attrs
.expr
= NULL_TREE
;
2673 attrs
.offset_known_p
= false;
2675 /* The widened memory may alias other stuff, so zap the alias set. */
2676 /* ??? Maybe use get_alias_set on any remaining expression. */
2678 attrs
.size_known_p
= true;
2680 set_mem_attrs (new_rtx
, &attrs
);
2684 /* A fake decl that is used as the MEM_EXPR of spill slots. */
2685 static GTY(()) tree spill_slot_decl
;
2688 get_spill_slot_decl (bool force_build_p
)
2690 tree d
= spill_slot_decl
;
2693 if (d
|| !force_build_p
)
2696 d
= build_decl (DECL_SOURCE_LOCATION (current_function_decl
),
2697 VAR_DECL
, get_identifier ("%sfp"), void_type_node
);
2698 DECL_ARTIFICIAL (d
) = 1;
2699 DECL_IGNORED_P (d
) = 1;
2701 spill_slot_decl
= d
;
2703 rd
= gen_rtx_MEM (BLKmode
, frame_pointer_rtx
);
2704 MEM_NOTRAP_P (rd
) = 1;
2705 mem_attrs
attrs (*mode_mem_attrs
[(int) BLKmode
]);
2706 attrs
.alias
= new_alias_set ();
2708 set_mem_attrs (rd
, &attrs
);
2709 SET_DECL_RTL (d
, rd
);
2714 /* Given MEM, a result from assign_stack_local, fill in the memory
2715 attributes as appropriate for a register allocator spill slot.
2716 These slots are not aliasable by other memory. We arrange for
2717 them all to use a single MEM_EXPR, so that the aliasing code can
2718 work properly in the case of shared spill slots. */
2721 set_mem_attrs_for_spill (rtx mem
)
2725 mem_attrs
attrs (*get_mem_attrs (mem
));
2726 attrs
.expr
= get_spill_slot_decl (true);
2727 attrs
.alias
= MEM_ALIAS_SET (DECL_RTL (attrs
.expr
));
2728 attrs
.addrspace
= ADDR_SPACE_GENERIC
;
2730 /* We expect the incoming memory to be of the form:
2731 (mem:MODE (plus (reg sfp) (const_int offset)))
2732 with perhaps the plus missing for offset = 0. */
2733 addr
= XEXP (mem
, 0);
2734 attrs
.offset_known_p
= true;
2735 strip_offset (addr
, &attrs
.offset
);
2737 set_mem_attrs (mem
, &attrs
);
2738 MEM_NOTRAP_P (mem
) = 1;
2741 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2744 gen_label_rtx (void)
2746 return as_a
<rtx_code_label
*> (
2747 gen_rtx_CODE_LABEL (VOIDmode
, NULL_RTX
, NULL_RTX
,
2748 NULL
, label_num
++, NULL
));
2751 /* For procedure integration. */
2753 /* Install new pointers to the first and last insns in the chain.
2754 Also, set cur_insn_uid to one higher than the last in use.
2755 Used for an inline-procedure after copying the insn chain. */
2758 set_new_first_and_last_insn (rtx_insn
*first
, rtx_insn
*last
)
2762 set_first_insn (first
);
2763 set_last_insn (last
);
2766 if (param_min_nondebug_insn_uid
|| MAY_HAVE_DEBUG_INSNS
)
2768 int debug_count
= 0;
2770 cur_insn_uid
= param_min_nondebug_insn_uid
- 1;
2771 cur_debug_insn_uid
= 0;
2773 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2774 if (INSN_UID (insn
) < param_min_nondebug_insn_uid
)
2775 cur_debug_insn_uid
= MAX (cur_debug_insn_uid
, INSN_UID (insn
));
2778 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2779 if (DEBUG_INSN_P (insn
))
2784 cur_debug_insn_uid
= param_min_nondebug_insn_uid
+ debug_count
;
2786 cur_debug_insn_uid
++;
2789 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2790 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2795 /* Go through all the RTL insn bodies and copy any invalid shared
2796 structure. This routine should only be called once. */
2799 unshare_all_rtl_1 (rtx_insn
*insn
)
2801 /* Unshare just about everything else. */
2802 unshare_all_rtl_in_chain (insn
);
2804 /* Make sure the addresses of stack slots found outside the insn chain
2805 (such as, in DECL_RTL of a variable) are not shared
2806 with the insn chain.
2808 This special care is necessary when the stack slot MEM does not
2809 actually appear in the insn chain. If it does appear, its address
2810 is unshared from all else at that point. */
2813 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2814 (*stack_slot_list
)[i
] = copy_rtx_if_shared (temp
);
2817 /* Go through all the RTL insn bodies and copy any invalid shared
2818 structure, again. This is a fairly expensive thing to do so it
2819 should be done sparingly. */
2822 unshare_all_rtl_again (rtx_insn
*insn
)
2827 for (p
= insn
; p
; p
= NEXT_INSN (p
))
2830 reset_used_flags (PATTERN (p
));
2831 reset_used_flags (REG_NOTES (p
));
2833 reset_used_flags (CALL_INSN_FUNCTION_USAGE (p
));
2836 /* Make sure that virtual stack slots are not shared. */
2837 set_used_decls (DECL_INITIAL (cfun
->decl
));
2839 /* Make sure that virtual parameters are not shared. */
2840 for (decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2841 set_used_flags (DECL_RTL (decl
));
2845 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2846 reset_used_flags (temp
);
2848 unshare_all_rtl_1 (insn
);
2852 unshare_all_rtl (void)
2854 unshare_all_rtl_1 (get_insns ());
2856 for (tree decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2858 if (DECL_RTL_SET_P (decl
))
2859 SET_DECL_RTL (decl
, copy_rtx_if_shared (DECL_RTL (decl
)));
2860 DECL_INCOMING_RTL (decl
) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl
));
2867 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2868 Recursively does the same for subexpressions. */
2871 verify_rtx_sharing (rtx orig
, rtx insn
)
2876 const char *format_ptr
;
2881 code
= GET_CODE (x
);
2883 /* These types may be freely shared. */
2899 /* SCRATCH must be shared because they represent distinct values. */
2902 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
2903 clobbers or clobbers of hard registers that originated as pseudos.
2904 This is needed to allow safe register renaming. */
2905 if (REG_P (XEXP (x
, 0))
2906 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
2907 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
2912 if (shared_const_p (orig
))
2917 /* A MEM is allowed to be shared if its address is constant. */
2918 if (CONSTANT_ADDRESS_P (XEXP (x
, 0))
2919 || reload_completed
|| reload_in_progress
)
2928 /* This rtx may not be shared. If it has already been seen,
2929 replace it with a copy of itself. */
2930 if (flag_checking
&& RTX_FLAG (x
, used
))
2932 error ("invalid rtl sharing found in the insn");
2934 error ("shared rtx");
2936 internal_error ("internal consistency failure");
2938 gcc_assert (!RTX_FLAG (x
, used
));
2940 RTX_FLAG (x
, used
) = 1;
2942 /* Now scan the subexpressions recursively. */
2944 format_ptr
= GET_RTX_FORMAT (code
);
2946 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
2948 switch (*format_ptr
++)
2951 verify_rtx_sharing (XEXP (x
, i
), insn
);
2955 if (XVEC (x
, i
) != NULL
)
2958 int len
= XVECLEN (x
, i
);
2960 for (j
= 0; j
< len
; j
++)
2962 /* We allow sharing of ASM_OPERANDS inside single
2964 if (j
&& GET_CODE (XVECEXP (x
, i
, j
)) == SET
2965 && (GET_CODE (SET_SRC (XVECEXP (x
, i
, j
)))
2967 verify_rtx_sharing (SET_DEST (XVECEXP (x
, i
, j
)), insn
);
2969 verify_rtx_sharing (XVECEXP (x
, i
, j
), insn
);
2978 /* Reset used-flags for INSN. */
2981 reset_insn_used_flags (rtx insn
)
2983 gcc_assert (INSN_P (insn
));
2984 reset_used_flags (PATTERN (insn
));
2985 reset_used_flags (REG_NOTES (insn
));
2987 reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn
));
2990 /* Go through all the RTL insn bodies and clear all the USED bits. */
2993 reset_all_used_flags (void)
2997 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
3000 rtx pat
= PATTERN (p
);
3001 if (GET_CODE (pat
) != SEQUENCE
)
3002 reset_insn_used_flags (p
);
3005 gcc_assert (REG_NOTES (p
) == NULL
);
3006 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
3008 rtx insn
= XVECEXP (pat
, 0, i
);
3010 reset_insn_used_flags (insn
);
3016 /* Verify sharing in INSN. */
3019 verify_insn_sharing (rtx insn
)
3021 gcc_assert (INSN_P (insn
));
3022 verify_rtx_sharing (PATTERN (insn
), insn
);
3023 verify_rtx_sharing (REG_NOTES (insn
), insn
);
3025 verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn
), insn
);
3028 /* Go through all the RTL insn bodies and check that there is no unexpected
3029 sharing in between the subexpressions. */
3032 verify_rtl_sharing (void)
3036 timevar_push (TV_VERIFY_RTL_SHARING
);
3038 reset_all_used_flags ();
3040 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
3043 rtx pat
= PATTERN (p
);
3044 if (GET_CODE (pat
) != SEQUENCE
)
3045 verify_insn_sharing (p
);
3047 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
3049 rtx insn
= XVECEXP (pat
, 0, i
);
3051 verify_insn_sharing (insn
);
3055 reset_all_used_flags ();
3057 timevar_pop (TV_VERIFY_RTL_SHARING
);
3060 /* Go through all the RTL insn bodies and copy any invalid shared structure.
3061 Assumes the mark bits are cleared at entry. */
3064 unshare_all_rtl_in_chain (rtx_insn
*insn
)
3066 for (; insn
; insn
= NEXT_INSN (insn
))
3069 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
3070 REG_NOTES (insn
) = copy_rtx_if_shared (REG_NOTES (insn
));
3072 CALL_INSN_FUNCTION_USAGE (insn
)
3073 = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn
));
3077 /* Go through all virtual stack slots of a function and mark them as
3078 shared. We never replace the DECL_RTLs themselves with a copy,
3079 but expressions mentioned into a DECL_RTL cannot be shared with
3080 expressions in the instruction stream.
3082 Note that reload may convert pseudo registers into memories in-place.
3083 Pseudo registers are always shared, but MEMs never are. Thus if we
3084 reset the used flags on MEMs in the instruction stream, we must set
3085 them again on MEMs that appear in DECL_RTLs. */
3088 set_used_decls (tree blk
)
3093 for (t
= BLOCK_VARS (blk
); t
; t
= DECL_CHAIN (t
))
3094 if (DECL_RTL_SET_P (t
))
3095 set_used_flags (DECL_RTL (t
));
3097 /* Now process sub-blocks. */
3098 for (t
= BLOCK_SUBBLOCKS (blk
); t
; t
= BLOCK_CHAIN (t
))
3102 /* Mark ORIG as in use, and return a copy of it if it was already in use.
3103 Recursively does the same for subexpressions. Uses
3104 copy_rtx_if_shared_1 to reduce stack space. */
3107 copy_rtx_if_shared (rtx orig
)
3109 copy_rtx_if_shared_1 (&orig
);
3113 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
3114 use. Recursively does the same for subexpressions. */
3117 copy_rtx_if_shared_1 (rtx
*orig1
)
3123 const char *format_ptr
;
3127 /* Repeat is used to turn tail-recursion into iteration. */
3134 code
= GET_CODE (x
);
3136 /* These types may be freely shared. */
3152 /* SCRATCH must be shared because they represent distinct values. */
3155 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
3156 clobbers or clobbers of hard registers that originated as pseudos.
3157 This is needed to allow safe register renaming. */
3158 if (REG_P (XEXP (x
, 0))
3159 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
3160 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
3165 if (shared_const_p (x
))
3175 /* The chain of insns is not being copied. */
3182 /* This rtx may not be shared. If it has already been seen,
3183 replace it with a copy of itself. */
3185 if (RTX_FLAG (x
, used
))
3187 x
= shallow_copy_rtx (x
);
3190 RTX_FLAG (x
, used
) = 1;
3192 /* Now scan the subexpressions recursively.
3193 We can store any replaced subexpressions directly into X
3194 since we know X is not shared! Any vectors in X
3195 must be copied if X was copied. */
3197 format_ptr
= GET_RTX_FORMAT (code
);
3198 length
= GET_RTX_LENGTH (code
);
3201 for (i
= 0; i
< length
; i
++)
3203 switch (*format_ptr
++)
3207 copy_rtx_if_shared_1 (last_ptr
);
3208 last_ptr
= &XEXP (x
, i
);
3212 if (XVEC (x
, i
) != NULL
)
3215 int len
= XVECLEN (x
, i
);
3217 /* Copy the vector iff I copied the rtx and the length
3219 if (copied
&& len
> 0)
3220 XVEC (x
, i
) = gen_rtvec_v (len
, XVEC (x
, i
)->elem
);
3222 /* Call recursively on all inside the vector. */
3223 for (j
= 0; j
< len
; j
++)
3226 copy_rtx_if_shared_1 (last_ptr
);
3227 last_ptr
= &XVECEXP (x
, i
, j
);
3242 /* Set the USED bit in X and its non-shareable subparts to FLAG. */
3245 mark_used_flags (rtx x
, int flag
)
3249 const char *format_ptr
;
3252 /* Repeat is used to turn tail-recursion into iteration. */
3257 code
= GET_CODE (x
);
3259 /* These types may be freely shared so we needn't do any resetting
3283 /* The chain of insns is not being copied. */
3290 RTX_FLAG (x
, used
) = flag
;
3292 format_ptr
= GET_RTX_FORMAT (code
);
3293 length
= GET_RTX_LENGTH (code
);
3295 for (i
= 0; i
< length
; i
++)
3297 switch (*format_ptr
++)
3305 mark_used_flags (XEXP (x
, i
), flag
);
3309 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3310 mark_used_flags (XVECEXP (x
, i
, j
), flag
);
3316 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
3317 to look for shared sub-parts. */
3320 reset_used_flags (rtx x
)
3322 mark_used_flags (x
, 0);
3325 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
3326 to look for shared sub-parts. */
3329 set_used_flags (rtx x
)
3331 mark_used_flags (x
, 1);
3334 /* Copy X if necessary so that it won't be altered by changes in OTHER.
3335 Return X or the rtx for the pseudo reg the value of X was copied into.
3336 OTHER must be valid as a SET_DEST. */
3339 make_safe_from (rtx x
, rtx other
)
3342 switch (GET_CODE (other
))
3345 other
= SUBREG_REG (other
);
3347 case STRICT_LOW_PART
:
3350 other
= XEXP (other
, 0);
3359 && GET_CODE (x
) != SUBREG
)
3361 && (REGNO (other
) < FIRST_PSEUDO_REGISTER
3362 || reg_mentioned_p (other
, x
))))
3364 rtx temp
= gen_reg_rtx (GET_MODE (x
));
3365 emit_move_insn (temp
, x
);
3371 /* Emission of insns (adding them to the doubly-linked list). */
3373 /* Return the last insn emitted, even if it is in a sequence now pushed. */
3376 get_last_insn_anywhere (void)
3378 struct sequence_stack
*seq
;
3379 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
3385 /* Return the first nonnote insn emitted in current sequence or current
3386 function. This routine looks inside SEQUENCEs. */
3389 get_first_nonnote_insn (void)
3391 rtx_insn
*insn
= get_insns ();
3396 for (insn
= next_insn (insn
);
3397 insn
&& NOTE_P (insn
);
3398 insn
= next_insn (insn
))
3402 if (NONJUMP_INSN_P (insn
)
3403 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3404 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3411 /* Return the last nonnote insn emitted in current sequence or current
3412 function. This routine looks inside SEQUENCEs. */
3415 get_last_nonnote_insn (void)
3417 rtx_insn
*insn
= get_last_insn ();
3422 for (insn
= previous_insn (insn
);
3423 insn
&& NOTE_P (insn
);
3424 insn
= previous_insn (insn
))
3428 if (NONJUMP_INSN_P (insn
))
3429 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3430 insn
= seq
->insn (seq
->len () - 1);
3437 /* Return the number of actual (non-debug) insns emitted in this
3441 get_max_insn_count (void)
3443 int n
= cur_insn_uid
;
3445 /* The table size must be stable across -g, to avoid codegen
3446 differences due to debug insns, and not be affected by
3447 -fmin-insn-uid, to avoid excessive table size and to simplify
3448 debugging of -fcompare-debug failures. */
3449 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
3450 n
-= cur_debug_insn_uid
;
3452 n
-= param_min_nondebug_insn_uid
;
3458 /* Return the next insn. If it is a SEQUENCE, return the first insn
3462 next_insn (rtx_insn
*insn
)
3466 insn
= NEXT_INSN (insn
);
3467 if (insn
&& NONJUMP_INSN_P (insn
)
3468 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3469 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3475 /* Return the previous insn. If it is a SEQUENCE, return the last insn
3479 previous_insn (rtx_insn
*insn
)
3483 insn
= PREV_INSN (insn
);
3484 if (insn
&& NONJUMP_INSN_P (insn
))
3485 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3486 insn
= seq
->insn (seq
->len () - 1);
3492 /* Return the next insn after INSN that is not a NOTE. This routine does not
3493 look inside SEQUENCEs. */
3496 next_nonnote_insn (rtx_insn
*insn
)
3500 insn
= NEXT_INSN (insn
);
3501 if (insn
== 0 || !NOTE_P (insn
))
3508 /* Return the next insn after INSN that is not a DEBUG_INSN. This
3509 routine does not look inside SEQUENCEs. */
3512 next_nondebug_insn (rtx_insn
*insn
)
3516 insn
= NEXT_INSN (insn
);
3517 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3524 /* Return the previous insn before INSN that is not a NOTE. This routine does
3525 not look inside SEQUENCEs. */
3528 prev_nonnote_insn (rtx_insn
*insn
)
3532 insn
= PREV_INSN (insn
);
3533 if (insn
== 0 || !NOTE_P (insn
))
3540 /* Return the previous insn before INSN that is not a DEBUG_INSN.
3541 This routine does not look inside SEQUENCEs. */
3544 prev_nondebug_insn (rtx_insn
*insn
)
3548 insn
= PREV_INSN (insn
);
3549 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3556 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN.
3557 This routine does not look inside SEQUENCEs. */
3560 next_nonnote_nondebug_insn (rtx_insn
*insn
)
3564 insn
= NEXT_INSN (insn
);
3565 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3572 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN,
3573 but stop the search before we enter another basic block. This
3574 routine does not look inside SEQUENCEs. */
3577 next_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3581 insn
= NEXT_INSN (insn
);
3584 if (DEBUG_INSN_P (insn
))
3588 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3595 /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN.
3596 This routine does not look inside SEQUENCEs. */
3599 prev_nonnote_nondebug_insn (rtx_insn
*insn
)
3603 insn
= PREV_INSN (insn
);
3604 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3611 /* Return the previous insn before INSN that is not a NOTE nor
3612 DEBUG_INSN, but stop the search before we enter another basic
3613 block. This routine does not look inside SEQUENCEs. */
3616 prev_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3620 insn
= PREV_INSN (insn
);
3623 if (DEBUG_INSN_P (insn
))
3627 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3634 /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN;
3635 or 0, if there is none. This routine does not look inside
3639 next_real_insn (rtx_insn
*insn
)
3643 insn
= NEXT_INSN (insn
);
3644 if (insn
== 0 || INSN_P (insn
))
3651 /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN;
3652 or 0, if there is none. This routine does not look inside
3656 prev_real_insn (rtx_insn
*insn
)
3660 insn
= PREV_INSN (insn
);
3661 if (insn
== 0 || INSN_P (insn
))
3668 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
3669 or 0, if there is none. This routine does not look inside
3673 next_real_nondebug_insn (rtx uncast_insn
)
3675 rtx_insn
*insn
= safe_as_a
<rtx_insn
*> (uncast_insn
);
3679 insn
= NEXT_INSN (insn
);
3680 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3687 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
3688 or 0, if there is none. This routine does not look inside
3692 prev_real_nondebug_insn (rtx_insn
*insn
)
3696 insn
= PREV_INSN (insn
);
3697 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3704 /* Return the last CALL_INSN in the current list, or 0 if there is none.
3705 This routine does not look inside SEQUENCEs. */
3708 last_call_insn (void)
3712 for (insn
= get_last_insn ();
3713 insn
&& !CALL_P (insn
);
3714 insn
= PREV_INSN (insn
))
3717 return safe_as_a
<rtx_call_insn
*> (insn
);
3720 /* Find the next insn after INSN that really does something. This routine
3721 does not look inside SEQUENCEs. After reload this also skips over
3722 standalone USE and CLOBBER insn. */
3725 active_insn_p (const rtx_insn
*insn
)
3727 return (CALL_P (insn
) || JUMP_P (insn
)
3728 || JUMP_TABLE_DATA_P (insn
) /* FIXME */
3729 || (NONJUMP_INSN_P (insn
)
3730 && (! reload_completed
3731 || (GET_CODE (PATTERN (insn
)) != USE
3732 && GET_CODE (PATTERN (insn
)) != CLOBBER
))));
3736 next_active_insn (rtx_insn
*insn
)
3740 insn
= NEXT_INSN (insn
);
3741 if (insn
== 0 || active_insn_p (insn
))
3748 /* Find the last insn before INSN that really does something. This routine
3749 does not look inside SEQUENCEs. After reload this also skips over
3750 standalone USE and CLOBBER insn. */
3753 prev_active_insn (rtx_insn
*insn
)
3757 insn
= PREV_INSN (insn
);
3758 if (insn
== 0 || active_insn_p (insn
))
3765 /* Return the next insn that uses CC0 after INSN, which is assumed to
3766 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3767 applied to the result of this function should yield INSN).
3769 Normally, this is simply the next insn. However, if a REG_CC_USER note
3770 is present, it contains the insn that uses CC0.
3772 Return 0 if we can't find the insn. */
3775 next_cc0_user (rtx_insn
*insn
)
3777 rtx note
= find_reg_note (insn
, REG_CC_USER
, NULL_RTX
);
3780 return safe_as_a
<rtx_insn
*> (XEXP (note
, 0));
3782 insn
= next_nonnote_insn (insn
);
3783 if (insn
&& NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3784 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3786 if (insn
&& INSN_P (insn
) && reg_mentioned_p (cc0_rtx
, PATTERN (insn
)))
3792 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3793 note, it is the previous insn. */
3796 prev_cc0_setter (rtx_insn
*insn
)
3798 rtx note
= find_reg_note (insn
, REG_CC_SETTER
, NULL_RTX
);
3801 return safe_as_a
<rtx_insn
*> (XEXP (note
, 0));
3803 insn
= prev_nonnote_insn (insn
);
3804 gcc_assert (sets_cc0_p (PATTERN (insn
)));
3809 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3812 find_auto_inc (const_rtx x
, const_rtx reg
)
3814 subrtx_iterator::array_type array
;
3815 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
3817 const_rtx x
= *iter
;
3818 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
3819 && rtx_equal_p (reg
, XEXP (x
, 0)))
3825 /* Increment the label uses for all labels present in rtx. */
3828 mark_label_nuses (rtx x
)
3834 code
= GET_CODE (x
);
3835 if (code
== LABEL_REF
&& LABEL_P (label_ref_label (x
)))
3836 LABEL_NUSES (label_ref_label (x
))++;
3838 fmt
= GET_RTX_FORMAT (code
);
3839 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3842 mark_label_nuses (XEXP (x
, i
));
3843 else if (fmt
[i
] == 'E')
3844 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3845 mark_label_nuses (XVECEXP (x
, i
, j
));
3850 /* Try splitting insns that can be split for better scheduling.
3851 PAT is the pattern which might split.
3852 TRIAL is the insn providing PAT.
3853 LAST is nonzero if we should return the last insn of the sequence produced.
3855 If this routine succeeds in splitting, it returns the first or last
3856 replacement insn depending on the value of LAST. Otherwise, it
3857 returns TRIAL. If the insn to be returned can be split, it will be. */
3860 try_split (rtx pat
, rtx_insn
*trial
, int last
)
3862 rtx_insn
*before
, *after
;
3864 rtx_insn
*seq
, *tem
;
3865 profile_probability probability
;
3866 rtx_insn
*insn_last
, *insn
;
3868 rtx_insn
*call_insn
= NULL
;
3870 /* We're not good at redistributing frame information. */
3871 if (RTX_FRAME_RELATED_P (trial
))
3874 if (any_condjump_p (trial
)
3875 && (note
= find_reg_note (trial
, REG_BR_PROB
, 0)))
3876 split_branch_probability
3877 = profile_probability::from_reg_br_prob_note (XINT (note
, 0));
3879 split_branch_probability
= profile_probability::uninitialized ();
3881 probability
= split_branch_probability
;
3883 seq
= split_insns (pat
, trial
);
3885 split_branch_probability
= profile_probability::uninitialized ();
3890 /* Avoid infinite loop if any insn of the result matches
3891 the original pattern. */
3895 if (INSN_P (insn_last
)
3896 && rtx_equal_p (PATTERN (insn_last
), pat
))
3898 if (!NEXT_INSN (insn_last
))
3900 insn_last
= NEXT_INSN (insn_last
);
3903 /* We will be adding the new sequence to the function. The splitters
3904 may have introduced invalid RTL sharing, so unshare the sequence now. */
3905 unshare_all_rtl_in_chain (seq
);
3907 /* Mark labels and copy flags. */
3908 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3913 CROSSING_JUMP_P (insn
) = CROSSING_JUMP_P (trial
);
3914 mark_jump_label (PATTERN (insn
), insn
, 0);
3916 if (probability
.initialized_p ()
3917 && any_condjump_p (insn
)
3918 && !find_reg_note (insn
, REG_BR_PROB
, 0))
3920 /* We can preserve the REG_BR_PROB notes only if exactly
3921 one jump is created, otherwise the machine description
3922 is responsible for this step using
3923 split_branch_probability variable. */
3924 gcc_assert (njumps
== 1);
3925 add_reg_br_prob_note (insn
, probability
);
3930 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3931 in SEQ and copy any additional information across. */
3934 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3937 gcc_assert (call_insn
== NULL_RTX
);
3940 /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the
3941 target may have explicitly specified. */
3942 rtx
*p
= &CALL_INSN_FUNCTION_USAGE (insn
);
3945 *p
= CALL_INSN_FUNCTION_USAGE (trial
);
3947 /* If the old call was a sibling call, the new one must
3949 SIBLING_CALL_P (insn
) = SIBLING_CALL_P (trial
);
3953 /* Copy notes, particularly those related to the CFG. */
3954 for (note
= REG_NOTES (trial
); note
; note
= XEXP (note
, 1))
3956 switch (REG_NOTE_KIND (note
))
3959 copy_reg_eh_region_note_backward (note
, insn_last
, NULL
);
3965 case REG_CALL_NOCF_CHECK
:
3966 case REG_CALL_ARG_LOCATION
:
3967 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3970 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3974 case REG_NON_LOCAL_GOTO
:
3975 case REG_LABEL_TARGET
:
3976 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3979 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3987 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3989 rtx reg
= XEXP (note
, 0);
3990 if (!FIND_REG_INC_NOTE (insn
, reg
)
3991 && find_auto_inc (PATTERN (insn
), reg
))
3992 add_reg_note (insn
, REG_INC
, reg
);
3997 fixup_args_size_notes (NULL
, insn_last
, get_args_size (note
));
4001 gcc_assert (call_insn
!= NULL_RTX
);
4002 add_reg_note (call_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
4010 /* If there are LABELS inside the split insns increment the
4011 usage count so we don't delete the label. */
4015 while (insn
!= NULL_RTX
)
4017 /* JUMP_P insns have already been "marked" above. */
4018 if (NONJUMP_INSN_P (insn
))
4019 mark_label_nuses (PATTERN (insn
));
4021 insn
= PREV_INSN (insn
);
4025 before
= PREV_INSN (trial
);
4026 after
= NEXT_INSN (trial
);
4028 emit_insn_after_setloc (seq
, trial
, INSN_LOCATION (trial
));
4030 delete_insn (trial
);
4032 /* Recursively call try_split for each new insn created; by the
4033 time control returns here that insn will be fully split, so
4034 set LAST and continue from the insn after the one returned.
4035 We can't use next_active_insn here since AFTER may be a note.
4036 Ignore deleted insns, which can be occur if not optimizing. */
4037 for (tem
= NEXT_INSN (before
); tem
!= after
; tem
= NEXT_INSN (tem
))
4038 if (! tem
->deleted () && INSN_P (tem
))
4039 tem
= try_split (PATTERN (tem
), tem
, 1);
4041 /* Return either the first or the last insn, depending on which was
4044 ? (after
? PREV_INSN (after
) : get_last_insn ())
4045 : NEXT_INSN (before
);
4048 /* Make and return an INSN rtx, initializing all its slots.
4049 Store PATTERN in the pattern slots. */
4052 make_insn_raw (rtx pattern
)
4056 insn
= as_a
<rtx_insn
*> (rtx_alloc (INSN
));
4058 INSN_UID (insn
) = cur_insn_uid
++;
4059 PATTERN (insn
) = pattern
;
4060 INSN_CODE (insn
) = -1;
4061 REG_NOTES (insn
) = NULL
;
4062 INSN_LOCATION (insn
) = curr_insn_location ();
4063 BLOCK_FOR_INSN (insn
) = NULL
;
4065 #ifdef ENABLE_RTL_CHECKING
4068 && (returnjump_p (insn
)
4069 || (GET_CODE (insn
) == SET
4070 && SET_DEST (insn
) == pc_rtx
)))
4072 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
4080 /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */
4083 make_debug_insn_raw (rtx pattern
)
4085 rtx_debug_insn
*insn
;
4087 insn
= as_a
<rtx_debug_insn
*> (rtx_alloc (DEBUG_INSN
));
4088 INSN_UID (insn
) = cur_debug_insn_uid
++;
4089 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
4090 INSN_UID (insn
) = cur_insn_uid
++;
4092 PATTERN (insn
) = pattern
;
4093 INSN_CODE (insn
) = -1;
4094 REG_NOTES (insn
) = NULL
;
4095 INSN_LOCATION (insn
) = curr_insn_location ();
4096 BLOCK_FOR_INSN (insn
) = NULL
;
4101 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
4104 make_jump_insn_raw (rtx pattern
)
4106 rtx_jump_insn
*insn
;
4108 insn
= as_a
<rtx_jump_insn
*> (rtx_alloc (JUMP_INSN
));
4109 INSN_UID (insn
) = cur_insn_uid
++;
4111 PATTERN (insn
) = pattern
;
4112 INSN_CODE (insn
) = -1;
4113 REG_NOTES (insn
) = NULL
;
4114 JUMP_LABEL (insn
) = NULL
;
4115 INSN_LOCATION (insn
) = curr_insn_location ();
4116 BLOCK_FOR_INSN (insn
) = NULL
;
4121 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
4124 make_call_insn_raw (rtx pattern
)
4126 rtx_call_insn
*insn
;
4128 insn
= as_a
<rtx_call_insn
*> (rtx_alloc (CALL_INSN
));
4129 INSN_UID (insn
) = cur_insn_uid
++;
4131 PATTERN (insn
) = pattern
;
4132 INSN_CODE (insn
) = -1;
4133 REG_NOTES (insn
) = NULL
;
4134 CALL_INSN_FUNCTION_USAGE (insn
) = NULL
;
4135 INSN_LOCATION (insn
) = curr_insn_location ();
4136 BLOCK_FOR_INSN (insn
) = NULL
;
4141 /* Like `make_insn_raw' but make a NOTE instead of an insn. */
4144 make_note_raw (enum insn_note subtype
)
4146 /* Some notes are never created this way at all. These notes are
4147 only created by patching out insns. */
4148 gcc_assert (subtype
!= NOTE_INSN_DELETED_LABEL
4149 && subtype
!= NOTE_INSN_DELETED_DEBUG_LABEL
);
4151 rtx_note
*note
= as_a
<rtx_note
*> (rtx_alloc (NOTE
));
4152 INSN_UID (note
) = cur_insn_uid
++;
4153 NOTE_KIND (note
) = subtype
;
4154 BLOCK_FOR_INSN (note
) = NULL
;
4155 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
4159 /* Add INSN to the end of the doubly-linked list, between PREV and NEXT.
4160 INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects,
4161 but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */
4164 link_insn_into_chain (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4166 SET_PREV_INSN (insn
) = prev
;
4167 SET_NEXT_INSN (insn
) = next
;
4170 SET_NEXT_INSN (prev
) = insn
;
4171 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4173 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4174 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = insn
;
4179 SET_PREV_INSN (next
) = insn
;
4180 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4182 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4183 SET_PREV_INSN (sequence
->insn (0)) = insn
;
4187 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4189 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (insn
));
4190 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4191 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4195 /* Add INSN to the end of the doubly-linked list.
4196 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
4199 add_insn (rtx_insn
*insn
)
4201 rtx_insn
*prev
= get_last_insn ();
4202 link_insn_into_chain (insn
, prev
, NULL
);
4203 if (get_insns () == NULL
)
4204 set_first_insn (insn
);
4205 set_last_insn (insn
);
4208 /* Add INSN into the doubly-linked list after insn AFTER. */
4211 add_insn_after_nobb (rtx_insn
*insn
, rtx_insn
*after
)
4213 rtx_insn
*next
= NEXT_INSN (after
);
4215 gcc_assert (!optimize
|| !after
->deleted ());
4217 link_insn_into_chain (insn
, after
, next
);
4221 struct sequence_stack
*seq
;
4223 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4224 if (after
== seq
->last
)
4232 /* Add INSN into the doubly-linked list before insn BEFORE. */
4235 add_insn_before_nobb (rtx_insn
*insn
, rtx_insn
*before
)
4237 rtx_insn
*prev
= PREV_INSN (before
);
4239 gcc_assert (!optimize
|| !before
->deleted ());
4241 link_insn_into_chain (insn
, prev
, before
);
4245 struct sequence_stack
*seq
;
4247 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4248 if (before
== seq
->first
)
4258 /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN.
4259 If BB is NULL, an attempt is made to infer the bb from before.
4261 This and the next function should be the only functions called
4262 to insert an insn once delay slots have been filled since only
4263 they know how to update a SEQUENCE. */
4266 add_insn_after (rtx_insn
*insn
, rtx_insn
*after
, basic_block bb
)
4268 add_insn_after_nobb (insn
, after
);
4269 if (!BARRIER_P (after
)
4270 && !BARRIER_P (insn
)
4271 && (bb
= BLOCK_FOR_INSN (after
)))
4273 set_block_for_insn (insn
, bb
);
4275 df_insn_rescan (insn
);
4276 /* Should not happen as first in the BB is always
4277 either NOTE or LABEL. */
4278 if (BB_END (bb
) == after
4279 /* Avoid clobbering of structure when creating new BB. */
4280 && !BARRIER_P (insn
)
4281 && !NOTE_INSN_BASIC_BLOCK_P (insn
))
4286 /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN.
4287 If BB is NULL, an attempt is made to infer the bb from before.
4289 This and the previous function should be the only functions called
4290 to insert an insn once delay slots have been filled since only
4291 they know how to update a SEQUENCE. */
4294 add_insn_before (rtx_insn
*insn
, rtx_insn
*before
, basic_block bb
)
4296 add_insn_before_nobb (insn
, before
);
4299 && !BARRIER_P (before
)
4300 && !BARRIER_P (insn
))
4301 bb
= BLOCK_FOR_INSN (before
);
4305 set_block_for_insn (insn
, bb
);
4307 df_insn_rescan (insn
);
4308 /* Should not happen as first in the BB is always either NOTE or
4310 gcc_assert (BB_HEAD (bb
) != insn
4311 /* Avoid clobbering of structure when creating new BB. */
4313 || NOTE_INSN_BASIC_BLOCK_P (insn
));
4317 /* Replace insn with an deleted instruction note. */
4320 set_insn_deleted (rtx_insn
*insn
)
4323 df_insn_delete (insn
);
4324 PUT_CODE (insn
, NOTE
);
4325 NOTE_KIND (insn
) = NOTE_INSN_DELETED
;
4329 /* Unlink INSN from the insn chain.
4331 This function knows how to handle sequences.
4333 This function does not invalidate data flow information associated with
4334 INSN (i.e. does not call df_insn_delete). That makes this function
4335 usable for only disconnecting an insn from the chain, and re-emit it
4338 To later insert INSN elsewhere in the insn chain via add_insn and
4339 similar functions, PREV_INSN and NEXT_INSN must be nullified by
4340 the caller. Nullifying them here breaks many insn chain walks.
4342 To really delete an insn and related DF information, use delete_insn. */
4345 remove_insn (rtx_insn
*insn
)
4347 rtx_insn
*next
= NEXT_INSN (insn
);
4348 rtx_insn
*prev
= PREV_INSN (insn
);
4353 SET_NEXT_INSN (prev
) = next
;
4354 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4356 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4357 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4362 struct sequence_stack
*seq
;
4364 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4365 if (insn
== seq
->first
)
4376 SET_PREV_INSN (next
) = prev
;
4377 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4379 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4380 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4385 struct sequence_stack
*seq
;
4387 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4388 if (insn
== seq
->last
)
4397 /* Fix up basic block boundaries, if necessary. */
4398 if (!BARRIER_P (insn
)
4399 && (bb
= BLOCK_FOR_INSN (insn
)))
4401 if (BB_HEAD (bb
) == insn
)
4403 /* Never ever delete the basic block note without deleting whole
4405 gcc_assert (!NOTE_P (insn
));
4406 BB_HEAD (bb
) = next
;
4408 if (BB_END (bb
) == insn
)
4413 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
4416 add_function_usage_to (rtx call_insn
, rtx call_fusage
)
4418 gcc_assert (call_insn
&& CALL_P (call_insn
));
4420 /* Put the register usage information on the CALL. If there is already
4421 some usage information, put ours at the end. */
4422 if (CALL_INSN_FUNCTION_USAGE (call_insn
))
4426 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); XEXP (link
, 1) != 0;
4427 link
= XEXP (link
, 1))
4430 XEXP (link
, 1) = call_fusage
;
4433 CALL_INSN_FUNCTION_USAGE (call_insn
) = call_fusage
;
4436 /* Delete all insns made since FROM.
4437 FROM becomes the new last instruction. */
4440 delete_insns_since (rtx_insn
*from
)
4445 SET_NEXT_INSN (from
) = 0;
4446 set_last_insn (from
);
4449 /* This function is deprecated, please use sequences instead.
4451 Move a consecutive bunch of insns to a different place in the chain.
4452 The insns to be moved are those between FROM and TO.
4453 They are moved to a new position after the insn AFTER.
4454 AFTER must not be FROM or TO or any insn in between.
4456 This function does not know about SEQUENCEs and hence should not be
4457 called after delay-slot filling has been done. */
4460 reorder_insns_nobb (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4464 for (rtx_insn
*x
= from
; x
!= to
; x
= NEXT_INSN (x
))
4465 gcc_assert (after
!= x
);
4466 gcc_assert (after
!= to
);
4469 /* Splice this bunch out of where it is now. */
4470 if (PREV_INSN (from
))
4471 SET_NEXT_INSN (PREV_INSN (from
)) = NEXT_INSN (to
);
4473 SET_PREV_INSN (NEXT_INSN (to
)) = PREV_INSN (from
);
4474 if (get_last_insn () == to
)
4475 set_last_insn (PREV_INSN (from
));
4476 if (get_insns () == from
)
4477 set_first_insn (NEXT_INSN (to
));
4479 /* Make the new neighbors point to it and it to them. */
4480 if (NEXT_INSN (after
))
4481 SET_PREV_INSN (NEXT_INSN (after
)) = to
;
4483 SET_NEXT_INSN (to
) = NEXT_INSN (after
);
4484 SET_PREV_INSN (from
) = after
;
4485 SET_NEXT_INSN (after
) = from
;
4486 if (after
== get_last_insn ())
4490 /* Same as function above, but take care to update BB boundaries. */
4492 reorder_insns (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4494 rtx_insn
*prev
= PREV_INSN (from
);
4495 basic_block bb
, bb2
;
4497 reorder_insns_nobb (from
, to
, after
);
4499 if (!BARRIER_P (after
)
4500 && (bb
= BLOCK_FOR_INSN (after
)))
4503 df_set_bb_dirty (bb
);
4505 if (!BARRIER_P (from
)
4506 && (bb2
= BLOCK_FOR_INSN (from
)))
4508 if (BB_END (bb2
) == to
)
4509 BB_END (bb2
) = prev
;
4510 df_set_bb_dirty (bb2
);
4513 if (BB_END (bb
) == after
)
4516 for (x
= from
; x
!= NEXT_INSN (to
); x
= NEXT_INSN (x
))
4518 df_insn_change_bb (x
, bb
);
4523 /* Emit insn(s) of given code and pattern
4524 at a specified place within the doubly-linked list.
4526 All of the emit_foo global entry points accept an object
4527 X which is either an insn list or a PATTERN of a single
4530 There are thus a few canonical ways to generate code and
4531 emit it at a specific place in the instruction stream. For
4532 example, consider the instruction named SPOT and the fact that
4533 we would like to emit some instructions before SPOT. We might
4537 ... emit the new instructions ...
4538 insns_head = get_insns ();
4541 emit_insn_before (insns_head, SPOT);
4543 It used to be common to generate SEQUENCE rtl instead, but that
4544 is a relic of the past which no longer occurs. The reason is that
4545 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
4546 generated would almost certainly die right after it was created. */
4549 emit_pattern_before_noloc (rtx x
, rtx_insn
*before
, rtx_insn
*last
,
4551 rtx_insn
*(*make_raw
) (rtx
))
4555 gcc_assert (before
);
4560 switch (GET_CODE (x
))
4569 insn
= as_a
<rtx_insn
*> (x
);
4572 rtx_insn
*next
= NEXT_INSN (insn
);
4573 add_insn_before (insn
, before
, bb
);
4579 #ifdef ENABLE_RTL_CHECKING
4586 last
= (*make_raw
) (x
);
4587 add_insn_before (last
, before
, bb
);
4594 /* Make X be output before the instruction BEFORE. */
4597 emit_insn_before_noloc (rtx x
, rtx_insn
*before
, basic_block bb
)
4599 return emit_pattern_before_noloc (x
, before
, before
, bb
, make_insn_raw
);
4602 /* Make an instruction with body X and code JUMP_INSN
4603 and output it before the instruction BEFORE. */
4606 emit_jump_insn_before_noloc (rtx x
, rtx_insn
*before
)
4608 return as_a
<rtx_jump_insn
*> (
4609 emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4610 make_jump_insn_raw
));
4613 /* Make an instruction with body X and code CALL_INSN
4614 and output it before the instruction BEFORE. */
4617 emit_call_insn_before_noloc (rtx x
, rtx_insn
*before
)
4619 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4620 make_call_insn_raw
);
4623 /* Make an instruction with body X and code DEBUG_INSN
4624 and output it before the instruction BEFORE. */
4627 emit_debug_insn_before_noloc (rtx x
, rtx_insn
*before
)
4629 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4630 make_debug_insn_raw
);
4633 /* Make an insn of code BARRIER
4634 and output it before the insn BEFORE. */
4637 emit_barrier_before (rtx_insn
*before
)
4639 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4641 INSN_UID (insn
) = cur_insn_uid
++;
4643 add_insn_before (insn
, before
, NULL
);
4647 /* Emit the label LABEL before the insn BEFORE. */
4650 emit_label_before (rtx_code_label
*label
, rtx_insn
*before
)
4652 gcc_checking_assert (INSN_UID (label
) == 0);
4653 INSN_UID (label
) = cur_insn_uid
++;
4654 add_insn_before (label
, before
, NULL
);
4658 /* Helper for emit_insn_after, handles lists of instructions
4662 emit_insn_after_1 (rtx_insn
*first
, rtx_insn
*after
, basic_block bb
)
4665 rtx_insn
*after_after
;
4666 if (!bb
&& !BARRIER_P (after
))
4667 bb
= BLOCK_FOR_INSN (after
);
4671 df_set_bb_dirty (bb
);
4672 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4673 if (!BARRIER_P (last
))
4675 set_block_for_insn (last
, bb
);
4676 df_insn_rescan (last
);
4678 if (!BARRIER_P (last
))
4680 set_block_for_insn (last
, bb
);
4681 df_insn_rescan (last
);
4683 if (BB_END (bb
) == after
)
4687 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4690 after_after
= NEXT_INSN (after
);
4692 SET_NEXT_INSN (after
) = first
;
4693 SET_PREV_INSN (first
) = after
;
4694 SET_NEXT_INSN (last
) = after_after
;
4696 SET_PREV_INSN (after_after
) = last
;
4698 if (after
== get_last_insn ())
4699 set_last_insn (last
);
4705 emit_pattern_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
,
4706 rtx_insn
*(*make_raw
)(rtx
))
4708 rtx_insn
*last
= after
;
4715 switch (GET_CODE (x
))
4724 last
= emit_insn_after_1 (as_a
<rtx_insn
*> (x
), after
, bb
);
4727 #ifdef ENABLE_RTL_CHECKING
4734 last
= (*make_raw
) (x
);
4735 add_insn_after (last
, after
, bb
);
4742 /* Make X be output after the insn AFTER and set the BB of insn. If
4743 BB is NULL, an attempt is made to infer the BB from AFTER. */
4746 emit_insn_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
)
4748 return emit_pattern_after_noloc (x
, after
, bb
, make_insn_raw
);
4752 /* Make an insn of code JUMP_INSN with body X
4753 and output it after the insn AFTER. */
4756 emit_jump_insn_after_noloc (rtx x
, rtx_insn
*after
)
4758 return as_a
<rtx_jump_insn
*> (
4759 emit_pattern_after_noloc (x
, after
, NULL
, make_jump_insn_raw
));
4762 /* Make an instruction with body X and code CALL_INSN
4763 and output it after the instruction AFTER. */
4766 emit_call_insn_after_noloc (rtx x
, rtx_insn
*after
)
4768 return emit_pattern_after_noloc (x
, after
, NULL
, make_call_insn_raw
);
4771 /* Make an instruction with body X and code CALL_INSN
4772 and output it after the instruction AFTER. */
4775 emit_debug_insn_after_noloc (rtx x
, rtx_insn
*after
)
4777 return emit_pattern_after_noloc (x
, after
, NULL
, make_debug_insn_raw
);
4780 /* Make an insn of code BARRIER
4781 and output it after the insn AFTER. */
4784 emit_barrier_after (rtx_insn
*after
)
4786 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4788 INSN_UID (insn
) = cur_insn_uid
++;
4790 add_insn_after (insn
, after
, NULL
);
4794 /* Emit the label LABEL after the insn AFTER. */
4797 emit_label_after (rtx_insn
*label
, rtx_insn
*after
)
4799 gcc_checking_assert (INSN_UID (label
) == 0);
4800 INSN_UID (label
) = cur_insn_uid
++;
4801 add_insn_after (label
, after
, NULL
);
4805 /* Notes require a bit of special handling: Some notes need to have their
4806 BLOCK_FOR_INSN set, others should never have it set, and some should
4807 have it set or clear depending on the context. */
4809 /* Return true iff a note of kind SUBTYPE should be emitted with routines
4810 that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the
4811 caller is asked to emit a note before BB_HEAD, or after BB_END. */
4814 note_outside_basic_block_p (enum insn_note subtype
, bool on_bb_boundary_p
)
4818 /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */
4819 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
4822 /* Notes for var tracking and EH region markers can appear between or
4823 inside basic blocks. If the caller is emitting on the basic block
4824 boundary, do not set BLOCK_FOR_INSN on the new note. */
4825 case NOTE_INSN_VAR_LOCATION
:
4826 case NOTE_INSN_EH_REGION_BEG
:
4827 case NOTE_INSN_EH_REGION_END
:
4828 return on_bb_boundary_p
;
4830 /* Otherwise, BLOCK_FOR_INSN must be set. */
4836 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4839 emit_note_after (enum insn_note subtype
, rtx_insn
*after
)
4841 rtx_note
*note
= make_note_raw (subtype
);
4842 basic_block bb
= BARRIER_P (after
) ? NULL
: BLOCK_FOR_INSN (after
);
4843 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_END (bb
) == after
);
4845 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4846 add_insn_after_nobb (note
, after
);
4848 add_insn_after (note
, after
, bb
);
4852 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
4855 emit_note_before (enum insn_note subtype
, rtx_insn
*before
)
4857 rtx_note
*note
= make_note_raw (subtype
);
4858 basic_block bb
= BARRIER_P (before
) ? NULL
: BLOCK_FOR_INSN (before
);
4859 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_HEAD (bb
) == before
);
4861 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4862 add_insn_before_nobb (note
, before
);
4864 add_insn_before (note
, before
, bb
);
4868 /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC.
4869 MAKE_RAW indicates how to turn PATTERN into a real insn. */
4872 emit_pattern_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
,
4873 rtx_insn
*(*make_raw
) (rtx
))
4875 rtx_insn
*last
= emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4877 if (pattern
== NULL_RTX
|| !loc
)
4880 after
= NEXT_INSN (after
);
4883 if (active_insn_p (after
)
4884 && !JUMP_TABLE_DATA_P (after
) /* FIXME */
4885 && !INSN_LOCATION (after
))
4886 INSN_LOCATION (after
) = loc
;
4889 after
= NEXT_INSN (after
);
4894 /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN
4895 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after
4899 emit_pattern_after (rtx pattern
, rtx_insn
*after
, bool skip_debug_insns
,
4900 rtx_insn
*(*make_raw
) (rtx
))
4902 rtx_insn
*prev
= after
;
4904 if (skip_debug_insns
)
4905 while (DEBUG_INSN_P (prev
))
4906 prev
= PREV_INSN (prev
);
4909 return emit_pattern_after_setloc (pattern
, after
, INSN_LOCATION (prev
),
4912 return emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4915 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4917 emit_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4919 return emit_pattern_after_setloc (pattern
, after
, loc
, make_insn_raw
);
4922 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4924 emit_insn_after (rtx pattern
, rtx_insn
*after
)
4926 return emit_pattern_after (pattern
, after
, true, make_insn_raw
);
4929 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4931 emit_jump_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4933 return as_a
<rtx_jump_insn
*> (
4934 emit_pattern_after_setloc (pattern
, after
, loc
, make_jump_insn_raw
));
4937 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4939 emit_jump_insn_after (rtx pattern
, rtx_insn
*after
)
4941 return as_a
<rtx_jump_insn
*> (
4942 emit_pattern_after (pattern
, after
, true, make_jump_insn_raw
));
4945 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4947 emit_call_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4949 return emit_pattern_after_setloc (pattern
, after
, loc
, make_call_insn_raw
);
4952 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4954 emit_call_insn_after (rtx pattern
, rtx_insn
*after
)
4956 return emit_pattern_after (pattern
, after
, true, make_call_insn_raw
);
4959 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4961 emit_debug_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4963 return emit_pattern_after_setloc (pattern
, after
, loc
, make_debug_insn_raw
);
4966 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4968 emit_debug_insn_after (rtx pattern
, rtx_insn
*after
)
4970 return emit_pattern_after (pattern
, after
, false, make_debug_insn_raw
);
4973 /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC.
4974 MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP
4975 indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN,
4979 emit_pattern_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
,
4980 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
4982 rtx_insn
*first
= PREV_INSN (before
);
4983 rtx_insn
*last
= emit_pattern_before_noloc (pattern
, before
,
4984 insnp
? before
: NULL
,
4987 if (pattern
== NULL_RTX
|| !loc
)
4991 first
= get_insns ();
4993 first
= NEXT_INSN (first
);
4996 if (active_insn_p (first
)
4997 && !JUMP_TABLE_DATA_P (first
) /* FIXME */
4998 && !INSN_LOCATION (first
))
4999 INSN_LOCATION (first
) = loc
;
5002 first
= NEXT_INSN (first
);
5007 /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN
5008 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert
5009 before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an
5010 INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */
5013 emit_pattern_before (rtx pattern
, rtx_insn
*before
, bool skip_debug_insns
,
5014 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
5016 rtx_insn
*next
= before
;
5018 if (skip_debug_insns
)
5019 while (DEBUG_INSN_P (next
))
5020 next
= PREV_INSN (next
);
5023 return emit_pattern_before_setloc (pattern
, before
, INSN_LOCATION (next
),
5026 return emit_pattern_before_noloc (pattern
, before
,
5027 insnp
? before
: NULL
,
5031 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5033 emit_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5035 return emit_pattern_before_setloc (pattern
, before
, loc
, true,
5039 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5041 emit_insn_before (rtx pattern
, rtx_insn
*before
)
5043 return emit_pattern_before (pattern
, before
, true, true, make_insn_raw
);
5046 /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5048 emit_jump_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5050 return as_a
<rtx_jump_insn
*> (
5051 emit_pattern_before_setloc (pattern
, before
, loc
, false,
5052 make_jump_insn_raw
));
5055 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5057 emit_jump_insn_before (rtx pattern
, rtx_insn
*before
)
5059 return as_a
<rtx_jump_insn
*> (
5060 emit_pattern_before (pattern
, before
, true, false,
5061 make_jump_insn_raw
));
5064 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5066 emit_call_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5068 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
5069 make_call_insn_raw
);
5072 /* Like emit_call_insn_before_noloc,
5073 but set insn_location according to BEFORE. */
5075 emit_call_insn_before (rtx pattern
, rtx_insn
*before
)
5077 return emit_pattern_before (pattern
, before
, true, false,
5078 make_call_insn_raw
);
5081 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5083 emit_debug_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5085 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
5086 make_debug_insn_raw
);
5089 /* Like emit_debug_insn_before_noloc,
5090 but set insn_location according to BEFORE. */
5092 emit_debug_insn_before (rtx pattern
, rtx_insn
*before
)
5094 return emit_pattern_before (pattern
, before
, false, false,
5095 make_debug_insn_raw
);
5098 /* Take X and emit it at the end of the doubly-linked
5101 Returns the last insn emitted. */
5106 rtx_insn
*last
= get_last_insn ();
5112 switch (GET_CODE (x
))
5121 insn
= as_a
<rtx_insn
*> (x
);
5124 rtx_insn
*next
= NEXT_INSN (insn
);
5131 #ifdef ENABLE_RTL_CHECKING
5132 case JUMP_TABLE_DATA
:
5139 last
= make_insn_raw (x
);
5147 /* Make an insn of code DEBUG_INSN with pattern X
5148 and add it to the end of the doubly-linked list. */
5151 emit_debug_insn (rtx x
)
5153 rtx_insn
*last
= get_last_insn ();
5159 switch (GET_CODE (x
))
5168 insn
= as_a
<rtx_insn
*> (x
);
5171 rtx_insn
*next
= NEXT_INSN (insn
);
5178 #ifdef ENABLE_RTL_CHECKING
5179 case JUMP_TABLE_DATA
:
5186 last
= make_debug_insn_raw (x
);
5194 /* Make an insn of code JUMP_INSN with pattern X
5195 and add it to the end of the doubly-linked list. */
5198 emit_jump_insn (rtx x
)
5200 rtx_insn
*last
= NULL
;
5203 switch (GET_CODE (x
))
5212 insn
= as_a
<rtx_insn
*> (x
);
5215 rtx_insn
*next
= NEXT_INSN (insn
);
5222 #ifdef ENABLE_RTL_CHECKING
5223 case JUMP_TABLE_DATA
:
5230 last
= make_jump_insn_raw (x
);
5238 /* Make an insn of code CALL_INSN with pattern X
5239 and add it to the end of the doubly-linked list. */
5242 emit_call_insn (rtx x
)
5246 switch (GET_CODE (x
))
5255 insn
= emit_insn (x
);
5258 #ifdef ENABLE_RTL_CHECKING
5260 case JUMP_TABLE_DATA
:
5266 insn
= make_call_insn_raw (x
);
5274 /* Add the label LABEL to the end of the doubly-linked list. */
5277 emit_label (rtx uncast_label
)
5279 rtx_code_label
*label
= as_a
<rtx_code_label
*> (uncast_label
);
5281 gcc_checking_assert (INSN_UID (label
) == 0);
5282 INSN_UID (label
) = cur_insn_uid
++;
5287 /* Make an insn of code JUMP_TABLE_DATA
5288 and add it to the end of the doubly-linked list. */
5290 rtx_jump_table_data
*
5291 emit_jump_table_data (rtx table
)
5293 rtx_jump_table_data
*jump_table_data
=
5294 as_a
<rtx_jump_table_data
*> (rtx_alloc (JUMP_TABLE_DATA
));
5295 INSN_UID (jump_table_data
) = cur_insn_uid
++;
5296 PATTERN (jump_table_data
) = table
;
5297 BLOCK_FOR_INSN (jump_table_data
) = NULL
;
5298 add_insn (jump_table_data
);
5299 return jump_table_data
;
5302 /* Make an insn of code BARRIER
5303 and add it to the end of the doubly-linked list. */
5308 rtx_barrier
*barrier
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
5309 INSN_UID (barrier
) = cur_insn_uid
++;
5314 /* Emit a copy of note ORIG. */
5317 emit_note_copy (rtx_note
*orig
)
5319 enum insn_note kind
= (enum insn_note
) NOTE_KIND (orig
);
5320 rtx_note
*note
= make_note_raw (kind
);
5321 NOTE_DATA (note
) = NOTE_DATA (orig
);
5326 /* Make an insn of code NOTE or type NOTE_NO
5327 and add it to the end of the doubly-linked list. */
5330 emit_note (enum insn_note kind
)
5332 rtx_note
*note
= make_note_raw (kind
);
5337 /* Emit a clobber of lvalue X. */
5340 emit_clobber (rtx x
)
5342 /* CONCATs should not appear in the insn stream. */
5343 if (GET_CODE (x
) == CONCAT
)
5345 emit_clobber (XEXP (x
, 0));
5346 return emit_clobber (XEXP (x
, 1));
5348 return emit_insn (gen_rtx_CLOBBER (VOIDmode
, x
));
5351 /* Return a sequence of insns to clobber lvalue X. */
5365 /* Emit a use of rvalue X. */
5370 /* CONCATs should not appear in the insn stream. */
5371 if (GET_CODE (x
) == CONCAT
)
5373 emit_use (XEXP (x
, 0));
5374 return emit_use (XEXP (x
, 1));
5376 return emit_insn (gen_rtx_USE (VOIDmode
, x
));
5379 /* Return a sequence of insns to use rvalue X. */
5393 /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction.
5394 Return the set in INSN that such notes describe, or NULL if the notes
5395 have no meaning for INSN. */
5398 set_for_reg_notes (rtx insn
)
5405 pat
= PATTERN (insn
);
5406 if (GET_CODE (pat
) == PARALLEL
)
5408 /* We do not use single_set because that ignores SETs of unused
5409 registers. REG_EQUAL and REG_EQUIV notes really do require the
5410 PARALLEL to have a single SET. */
5411 if (multiple_sets (insn
))
5413 pat
= XVECEXP (pat
, 0, 0);
5416 if (GET_CODE (pat
) != SET
)
5419 reg
= SET_DEST (pat
);
5421 /* Notes apply to the contents of a STRICT_LOW_PART. */
5422 if (GET_CODE (reg
) == STRICT_LOW_PART
5423 || GET_CODE (reg
) == ZERO_EXTRACT
)
5424 reg
= XEXP (reg
, 0);
5426 /* Check that we have a register. */
5427 if (!(REG_P (reg
) || GET_CODE (reg
) == SUBREG
))
5433 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
5434 note of this type already exists, remove it first. */
5437 set_unique_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
5439 rtx note
= find_reg_note (insn
, kind
, NULL_RTX
);
5445 /* We need to support the REG_EQUAL on USE trick of find_reloads. */
5446 if (!set_for_reg_notes (insn
) && GET_CODE (PATTERN (insn
)) != USE
)
5449 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
5450 It serves no useful purpose and breaks eliminate_regs. */
5451 if (GET_CODE (datum
) == ASM_OPERANDS
)
5454 /* Notes with side effects are dangerous. Even if the side-effect
5455 initially mirrors one in PATTERN (INSN), later optimizations
5456 might alter the way that the final register value is calculated
5457 and so move or alter the side-effect in some way. The note would
5458 then no longer be a valid substitution for SET_SRC. */
5459 if (side_effects_p (datum
))
5468 XEXP (note
, 0) = datum
;
5471 add_reg_note (insn
, kind
, datum
);
5472 note
= REG_NOTES (insn
);
5479 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
5488 /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */
5490 set_dst_reg_note (rtx insn
, enum reg_note kind
, rtx datum
, rtx dst
)
5492 rtx set
= set_for_reg_notes (insn
);
5494 if (set
&& SET_DEST (set
) == dst
)
5495 return set_unique_reg_note (insn
, kind
, datum
);
5499 /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a
5500 following barrier if the instruction needs one and if ALLOW_BARRIER_P
5503 If X is a label, it is simply added into the insn chain. */
5506 emit (rtx x
, bool allow_barrier_p
)
5508 enum rtx_code code
= classify_insn (x
);
5513 return emit_label (x
);
5515 return emit_insn (x
);
5518 rtx_insn
*insn
= emit_jump_insn (x
);
5520 && (any_uncondjump_p (insn
) || GET_CODE (x
) == RETURN
))
5521 return emit_barrier ();
5525 return emit_call_insn (x
);
5527 return emit_debug_insn (x
);
5533 /* Space for free sequence stack entries. */
5534 static GTY ((deletable
)) struct sequence_stack
*free_sequence_stack
;
5536 /* Begin emitting insns to a sequence. If this sequence will contain
5537 something that might cause the compiler to pop arguments to function
5538 calls (because those pops have previously been deferred; see
5539 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
5540 before calling this function. That will ensure that the deferred
5541 pops are not accidentally emitted in the middle of this sequence. */
5544 start_sequence (void)
5546 struct sequence_stack
*tem
;
5548 if (free_sequence_stack
!= NULL
)
5550 tem
= free_sequence_stack
;
5551 free_sequence_stack
= tem
->next
;
5554 tem
= ggc_alloc
<sequence_stack
> ();
5556 tem
->next
= get_current_sequence ()->next
;
5557 tem
->first
= get_insns ();
5558 tem
->last
= get_last_insn ();
5559 get_current_sequence ()->next
= tem
;
5565 /* Set up the insn chain starting with FIRST as the current sequence,
5566 saving the previously current one. See the documentation for
5567 start_sequence for more information about how to use this function. */
5570 push_to_sequence (rtx_insn
*first
)
5576 for (last
= first
; last
&& NEXT_INSN (last
); last
= NEXT_INSN (last
))
5579 set_first_insn (first
);
5580 set_last_insn (last
);
5583 /* Like push_to_sequence, but take the last insn as an argument to avoid
5584 looping through the list. */
5587 push_to_sequence2 (rtx_insn
*first
, rtx_insn
*last
)
5591 set_first_insn (first
);
5592 set_last_insn (last
);
5595 /* Set up the outer-level insn chain
5596 as the current sequence, saving the previously current one. */
5599 push_topmost_sequence (void)
5601 struct sequence_stack
*top
;
5605 top
= get_topmost_sequence ();
5606 set_first_insn (top
->first
);
5607 set_last_insn (top
->last
);
5610 /* After emitting to the outer-level insn chain, update the outer-level
5611 insn chain, and restore the previous saved state. */
5614 pop_topmost_sequence (void)
5616 struct sequence_stack
*top
;
5618 top
= get_topmost_sequence ();
5619 top
->first
= get_insns ();
5620 top
->last
= get_last_insn ();
5625 /* After emitting to a sequence, restore previous saved state.
5627 To get the contents of the sequence just made, you must call
5628 `get_insns' *before* calling here.
5630 If the compiler might have deferred popping arguments while
5631 generating this sequence, and this sequence will not be immediately
5632 inserted into the instruction stream, use do_pending_stack_adjust
5633 before calling get_insns. That will ensure that the deferred
5634 pops are inserted into this sequence, and not into some random
5635 location in the instruction stream. See INHIBIT_DEFER_POP for more
5636 information about deferred popping of arguments. */
5641 struct sequence_stack
*tem
= get_current_sequence ()->next
;
5643 set_first_insn (tem
->first
);
5644 set_last_insn (tem
->last
);
5645 get_current_sequence ()->next
= tem
->next
;
5647 memset (tem
, 0, sizeof (*tem
));
5648 tem
->next
= free_sequence_stack
;
5649 free_sequence_stack
= tem
;
5652 /* Return 1 if currently emitting into a sequence. */
5655 in_sequence_p (void)
5657 return get_current_sequence ()->next
!= 0;
5660 /* Put the various virtual registers into REGNO_REG_RTX. */
5663 init_virtual_regs (void)
5665 regno_reg_rtx
[VIRTUAL_INCOMING_ARGS_REGNUM
] = virtual_incoming_args_rtx
;
5666 regno_reg_rtx
[VIRTUAL_STACK_VARS_REGNUM
] = virtual_stack_vars_rtx
;
5667 regno_reg_rtx
[VIRTUAL_STACK_DYNAMIC_REGNUM
] = virtual_stack_dynamic_rtx
;
5668 regno_reg_rtx
[VIRTUAL_OUTGOING_ARGS_REGNUM
] = virtual_outgoing_args_rtx
;
5669 regno_reg_rtx
[VIRTUAL_CFA_REGNUM
] = virtual_cfa_rtx
;
5670 regno_reg_rtx
[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
]
5671 = virtual_preferred_stack_boundary_rtx
;
5675 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
5676 static rtx copy_insn_scratch_in
[MAX_RECOG_OPERANDS
];
5677 static rtx copy_insn_scratch_out
[MAX_RECOG_OPERANDS
];
5678 static int copy_insn_n_scratches
;
5680 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5681 copied an ASM_OPERANDS.
5682 In that case, it is the original input-operand vector. */
5683 static rtvec orig_asm_operands_vector
;
5685 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5686 copied an ASM_OPERANDS.
5687 In that case, it is the copied input-operand vector. */
5688 static rtvec copy_asm_operands_vector
;
5690 /* Likewise for the constraints vector. */
5691 static rtvec orig_asm_constraints_vector
;
5692 static rtvec copy_asm_constraints_vector
;
5694 /* Recursively create a new copy of an rtx for copy_insn.
5695 This function differs from copy_rtx in that it handles SCRATCHes and
5696 ASM_OPERANDs properly.
5697 Normally, this function is not used directly; use copy_insn as front end.
5698 However, you could first copy an insn pattern with copy_insn and then use
5699 this function afterwards to properly copy any REG_NOTEs containing
5703 copy_insn_1 (rtx orig
)
5708 const char *format_ptr
;
5713 code
= GET_CODE (orig
);
5728 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
5729 clobbers or clobbers of hard registers that originated as pseudos.
5730 This is needed to allow safe register renaming. */
5731 if (REG_P (XEXP (orig
, 0))
5732 && HARD_REGISTER_NUM_P (REGNO (XEXP (orig
, 0)))
5733 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig
, 0))))
5738 for (i
= 0; i
< copy_insn_n_scratches
; i
++)
5739 if (copy_insn_scratch_in
[i
] == orig
)
5740 return copy_insn_scratch_out
[i
];
5744 if (shared_const_p (orig
))
5748 /* A MEM with a constant address is not sharable. The problem is that
5749 the constant address may need to be reloaded. If the mem is shared,
5750 then reloading one copy of this mem will cause all copies to appear
5751 to have been reloaded. */
5757 /* Copy the various flags, fields, and other information. We assume
5758 that all fields need copying, and then clear the fields that should
5759 not be copied. That is the sensible default behavior, and forces
5760 us to explicitly document why we are *not* copying a flag. */
5761 copy
= shallow_copy_rtx (orig
);
5763 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
5766 RTX_FLAG (copy
, jump
) = 0;
5767 RTX_FLAG (copy
, call
) = 0;
5768 RTX_FLAG (copy
, frame_related
) = 0;
5771 format_ptr
= GET_RTX_FORMAT (GET_CODE (copy
));
5773 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (copy
)); i
++)
5774 switch (*format_ptr
++)
5777 if (XEXP (orig
, i
) != NULL
)
5778 XEXP (copy
, i
) = copy_insn_1 (XEXP (orig
, i
));
5783 if (XVEC (orig
, i
) == orig_asm_constraints_vector
)
5784 XVEC (copy
, i
) = copy_asm_constraints_vector
;
5785 else if (XVEC (orig
, i
) == orig_asm_operands_vector
)
5786 XVEC (copy
, i
) = copy_asm_operands_vector
;
5787 else if (XVEC (orig
, i
) != NULL
)
5789 XVEC (copy
, i
) = rtvec_alloc (XVECLEN (orig
, i
));
5790 for (j
= 0; j
< XVECLEN (copy
, i
); j
++)
5791 XVECEXP (copy
, i
, j
) = copy_insn_1 (XVECEXP (orig
, i
, j
));
5803 /* These are left unchanged. */
5810 if (code
== SCRATCH
)
5812 i
= copy_insn_n_scratches
++;
5813 gcc_assert (i
< MAX_RECOG_OPERANDS
);
5814 copy_insn_scratch_in
[i
] = orig
;
5815 copy_insn_scratch_out
[i
] = copy
;
5817 else if (code
== ASM_OPERANDS
)
5819 orig_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (orig
);
5820 copy_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (copy
);
5821 orig_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig
);
5822 copy_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy
);
5828 /* Create a new copy of an rtx.
5829 This function differs from copy_rtx in that it handles SCRATCHes and
5830 ASM_OPERANDs properly.
5831 INSN doesn't really have to be a full INSN; it could be just the
5834 copy_insn (rtx insn
)
5836 copy_insn_n_scratches
= 0;
5837 orig_asm_operands_vector
= 0;
5838 orig_asm_constraints_vector
= 0;
5839 copy_asm_operands_vector
= 0;
5840 copy_asm_constraints_vector
= 0;
5841 return copy_insn_1 (insn
);
5844 /* Return a copy of INSN that can be used in a SEQUENCE delay slot,
5845 on that assumption that INSN itself remains in its original place. */
5848 copy_delay_slot_insn (rtx_insn
*insn
)
5850 /* Copy INSN with its rtx_code, all its notes, location etc. */
5851 insn
= as_a
<rtx_insn
*> (copy_rtx (insn
));
5852 INSN_UID (insn
) = cur_insn_uid
++;
5856 /* Initialize data structures and variables in this file
5857 before generating rtl for each function. */
5862 set_first_insn (NULL
);
5863 set_last_insn (NULL
);
5864 if (param_min_nondebug_insn_uid
)
5865 cur_insn_uid
= param_min_nondebug_insn_uid
;
5868 cur_debug_insn_uid
= 1;
5869 reg_rtx_no
= LAST_VIRTUAL_REGISTER
+ 1;
5870 first_label_num
= label_num
;
5871 get_current_sequence ()->next
= NULL
;
5873 /* Init the tables that describe all the pseudo regs. */
5875 crtl
->emit
.regno_pointer_align_length
= LAST_VIRTUAL_REGISTER
+ 101;
5877 crtl
->emit
.regno_pointer_align
5878 = XCNEWVEC (unsigned char, crtl
->emit
.regno_pointer_align_length
);
5881 = ggc_cleared_vec_alloc
<rtx
> (crtl
->emit
.regno_pointer_align_length
);
5883 /* Put copies of all the hard registers into regno_reg_rtx. */
5884 memcpy (regno_reg_rtx
,
5885 initial_regno_reg_rtx
,
5886 FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
5888 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
5889 init_virtual_regs ();
5891 /* Indicate that the virtual registers and stack locations are
5893 REG_POINTER (stack_pointer_rtx
) = 1;
5894 REG_POINTER (frame_pointer_rtx
) = 1;
5895 REG_POINTER (hard_frame_pointer_rtx
) = 1;
5896 REG_POINTER (arg_pointer_rtx
) = 1;
5898 REG_POINTER (virtual_incoming_args_rtx
) = 1;
5899 REG_POINTER (virtual_stack_vars_rtx
) = 1;
5900 REG_POINTER (virtual_stack_dynamic_rtx
) = 1;
5901 REG_POINTER (virtual_outgoing_args_rtx
) = 1;
5902 REG_POINTER (virtual_cfa_rtx
) = 1;
5904 #ifdef STACK_BOUNDARY
5905 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM
) = STACK_BOUNDARY
;
5906 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5907 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5908 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) = STACK_BOUNDARY
;
5910 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5911 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM
) = STACK_BOUNDARY
;
5912 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM
) = STACK_BOUNDARY
;
5913 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5915 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM
) = BITS_PER_WORD
;
5918 #ifdef INIT_EXPANDERS
5923 /* Return the value of element I of CONST_VECTOR X as a wide_int. */
5926 const_vector_int_elt (const_rtx x
, unsigned int i
)
5928 /* First handle elements that are directly encoded. */
5929 machine_mode elt_mode
= GET_MODE_INNER (GET_MODE (x
));
5930 if (i
< (unsigned int) XVECLEN (x
, 0))
5931 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, i
), elt_mode
);
5933 /* Identify the pattern that contains element I and work out the index of
5934 the last encoded element for that pattern. */
5935 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5936 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5937 unsigned int count
= i
/ npatterns
;
5938 unsigned int pattern
= i
% npatterns
;
5939 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5941 /* If there are no steps, the final encoded value is the right one. */
5942 if (!CONST_VECTOR_STEPPED_P (x
))
5943 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, final_i
), elt_mode
);
5945 /* Otherwise work out the value from the last two encoded elements. */
5946 rtx v1
= CONST_VECTOR_ENCODED_ELT (x
, final_i
- npatterns
);
5947 rtx v2
= CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5948 wide_int diff
= wi::sub (rtx_mode_t (v2
, elt_mode
),
5949 rtx_mode_t (v1
, elt_mode
));
5950 return wi::add (rtx_mode_t (v2
, elt_mode
), (count
- 2) * diff
);
5953 /* Return the value of element I of CONST_VECTOR X. */
5956 const_vector_elt (const_rtx x
, unsigned int i
)
5958 /* First handle elements that are directly encoded. */
5959 if (i
< (unsigned int) XVECLEN (x
, 0))
5960 return CONST_VECTOR_ENCODED_ELT (x
, i
);
5962 /* If there are no steps, the final encoded value is the right one. */
5963 if (!CONST_VECTOR_STEPPED_P (x
))
5965 /* Identify the pattern that contains element I and work out the index of
5966 the last encoded element for that pattern. */
5967 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5968 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5969 unsigned int pattern
= i
% npatterns
;
5970 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5971 return CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5974 /* Otherwise work out the value from the last two encoded elements. */
5975 return immed_wide_int_const (const_vector_int_elt (x
, i
),
5976 GET_MODE_INNER (GET_MODE (x
)));
5979 /* Return true if X is a valid element for a CONST_VECTOR of the given
5983 valid_for_const_vector_p (machine_mode
, rtx x
)
5985 return (CONST_SCALAR_INT_P (x
)
5986 || CONST_DOUBLE_AS_FLOAT_P (x
)
5987 || CONST_FIXED_P (x
));
5990 /* Generate a vector constant of mode MODE in which every element has
5994 gen_const_vec_duplicate (machine_mode mode
, rtx elt
)
5996 rtx_vector_builder
builder (mode
, 1, 1);
5997 builder
.quick_push (elt
);
5998 return builder
.build ();
6001 /* Return a vector rtx of mode MODE in which every element has value X.
6002 The result will be a constant if X is constant. */
6005 gen_vec_duplicate (machine_mode mode
, rtx x
)
6007 if (valid_for_const_vector_p (mode
, x
))
6008 return gen_const_vec_duplicate (mode
, x
);
6009 return gen_rtx_VEC_DUPLICATE (mode
, x
);
6012 /* A subroutine of const_vec_series_p that handles the case in which:
6014 (GET_CODE (X) == CONST_VECTOR
6015 && CONST_VECTOR_NPATTERNS (X) == 1
6016 && !CONST_VECTOR_DUPLICATE_P (X))
6018 is known to hold. */
6021 const_vec_series_p_1 (const_rtx x
, rtx
*base_out
, rtx
*step_out
)
6023 /* Stepped sequences are only defined for integers, to avoid specifying
6024 rounding behavior. */
6025 if (GET_MODE_CLASS (GET_MODE (x
)) != MODE_VECTOR_INT
)
6028 /* A non-duplicated vector with two elements can always be seen as a
6029 series with a nonzero step. Longer vectors must have a stepped
6031 if (maybe_ne (CONST_VECTOR_NUNITS (x
), 2)
6032 && !CONST_VECTOR_STEPPED_P (x
))
6035 /* Calculate the step between the first and second elements. */
6036 scalar_mode inner
= GET_MODE_INNER (GET_MODE (x
));
6037 rtx base
= CONST_VECTOR_ELT (x
, 0);
6038 rtx step
= simplify_binary_operation (MINUS
, inner
,
6039 CONST_VECTOR_ENCODED_ELT (x
, 1), base
);
6040 if (rtx_equal_p (step
, CONST0_RTX (inner
)))
6043 /* If we have a stepped encoding, check that the step between the
6044 second and third elements is the same as STEP. */
6045 if (CONST_VECTOR_STEPPED_P (x
))
6047 rtx diff
= simplify_binary_operation (MINUS
, inner
,
6048 CONST_VECTOR_ENCODED_ELT (x
, 2),
6049 CONST_VECTOR_ENCODED_ELT (x
, 1));
6050 if (!rtx_equal_p (step
, diff
))
6059 /* Generate a vector constant of mode MODE in which element I has
6060 the value BASE + I * STEP. */
6063 gen_const_vec_series (machine_mode mode
, rtx base
, rtx step
)
6065 gcc_assert (valid_for_const_vector_p (mode
, base
)
6066 && valid_for_const_vector_p (mode
, step
));
6068 rtx_vector_builder
builder (mode
, 1, 3);
6069 builder
.quick_push (base
);
6070 for (int i
= 1; i
< 3; ++i
)
6071 builder
.quick_push (simplify_gen_binary (PLUS
, GET_MODE_INNER (mode
),
6072 builder
[i
- 1], step
));
6073 return builder
.build ();
6076 /* Generate a vector of mode MODE in which element I has the value
6077 BASE + I * STEP. The result will be a constant if BASE and STEP
6078 are both constants. */
6081 gen_vec_series (machine_mode mode
, rtx base
, rtx step
)
6083 if (step
== const0_rtx
)
6084 return gen_vec_duplicate (mode
, base
);
6085 if (valid_for_const_vector_p (mode
, base
)
6086 && valid_for_const_vector_p (mode
, step
))
6087 return gen_const_vec_series (mode
, base
, step
);
6088 return gen_rtx_VEC_SERIES (mode
, base
, step
);
6091 /* Generate a new vector constant for mode MODE and constant value
6095 gen_const_vector (machine_mode mode
, int constant
)
6097 machine_mode inner
= GET_MODE_INNER (mode
);
6099 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner
));
6101 rtx el
= const_tiny_rtx
[constant
][(int) inner
];
6104 return gen_const_vec_duplicate (mode
, el
);
6107 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
6108 all elements are zero, and the one vector when all elements are one. */
6110 gen_rtx_CONST_VECTOR (machine_mode mode
, rtvec v
)
6112 gcc_assert (known_eq (GET_MODE_NUNITS (mode
), GET_NUM_ELEM (v
)));
6114 /* If the values are all the same, check to see if we can use one of the
6115 standard constant vectors. */
6116 if (rtvec_all_equal_p (v
))
6117 return gen_const_vec_duplicate (mode
, RTVEC_ELT (v
, 0));
6119 unsigned int nunits
= GET_NUM_ELEM (v
);
6120 rtx_vector_builder
builder (mode
, nunits
, 1);
6121 for (unsigned int i
= 0; i
< nunits
; ++i
)
6122 builder
.quick_push (RTVEC_ELT (v
, i
));
6123 return builder
.build (v
);
6126 /* Initialise global register information required by all functions. */
6129 init_emit_regs (void)
6135 /* Reset register attributes */
6136 reg_attrs_htab
->empty ();
6138 /* We need reg_raw_mode, so initialize the modes now. */
6139 init_reg_modes_target ();
6141 /* Assign register numbers to the globally defined register rtx. */
6142 stack_pointer_rtx
= gen_raw_REG (Pmode
, STACK_POINTER_REGNUM
);
6143 frame_pointer_rtx
= gen_raw_REG (Pmode
, FRAME_POINTER_REGNUM
);
6144 hard_frame_pointer_rtx
= gen_raw_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
6145 arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
6146 virtual_incoming_args_rtx
=
6147 gen_raw_REG (Pmode
, VIRTUAL_INCOMING_ARGS_REGNUM
);
6148 virtual_stack_vars_rtx
=
6149 gen_raw_REG (Pmode
, VIRTUAL_STACK_VARS_REGNUM
);
6150 virtual_stack_dynamic_rtx
=
6151 gen_raw_REG (Pmode
, VIRTUAL_STACK_DYNAMIC_REGNUM
);
6152 virtual_outgoing_args_rtx
=
6153 gen_raw_REG (Pmode
, VIRTUAL_OUTGOING_ARGS_REGNUM
);
6154 virtual_cfa_rtx
= gen_raw_REG (Pmode
, VIRTUAL_CFA_REGNUM
);
6155 virtual_preferred_stack_boundary_rtx
=
6156 gen_raw_REG (Pmode
, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
);
6158 /* Initialize RTL for commonly used hard registers. These are
6159 copied into regno_reg_rtx as we begin to compile each function. */
6160 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6161 initial_regno_reg_rtx
[i
] = gen_raw_REG (reg_raw_mode
[i
], i
);
6163 #ifdef RETURN_ADDRESS_POINTER_REGNUM
6164 return_address_pointer_rtx
6165 = gen_raw_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
);
6168 pic_offset_table_rtx
= NULL_RTX
;
6169 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6170 pic_offset_table_rtx
= gen_raw_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
);
6172 for (i
= 0; i
< (int) MAX_MACHINE_MODE
; i
++)
6174 mode
= (machine_mode
) i
;
6175 attrs
= ggc_cleared_alloc
<mem_attrs
> ();
6176 attrs
->align
= BITS_PER_UNIT
;
6177 attrs
->addrspace
= ADDR_SPACE_GENERIC
;
6178 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
6180 attrs
->size_known_p
= true;
6181 attrs
->size
= GET_MODE_SIZE (mode
);
6182 if (STRICT_ALIGNMENT
)
6183 attrs
->align
= GET_MODE_ALIGNMENT (mode
);
6185 mode_mem_attrs
[i
] = attrs
;
6188 split_branch_probability
= profile_probability::uninitialized ();
6191 /* Initialize global machine_mode variables. */
6194 init_derived_machine_modes (void)
6196 opt_scalar_int_mode mode_iter
, opt_byte_mode
, opt_word_mode
;
6197 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_INT
)
6199 scalar_int_mode mode
= mode_iter
.require ();
6201 if (GET_MODE_BITSIZE (mode
) == BITS_PER_UNIT
6202 && !opt_byte_mode
.exists ())
6203 opt_byte_mode
= mode
;
6205 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
6206 && !opt_word_mode
.exists ())
6207 opt_word_mode
= mode
;
6210 byte_mode
= opt_byte_mode
.require ();
6211 word_mode
= opt_word_mode
.require ();
6212 ptr_mode
= as_a
<scalar_int_mode
>
6213 (mode_for_size (POINTER_SIZE
, GET_MODE_CLASS (Pmode
), 0).require ());
6216 /* Create some permanent unique rtl objects shared between all functions. */
6219 init_emit_once (void)
6223 scalar_float_mode double_mode
;
6224 opt_scalar_mode smode_iter
;
6226 /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
6227 CONST_FIXED, and memory attribute hash tables. */
6228 const_int_htab
= hash_table
<const_int_hasher
>::create_ggc (37);
6230 #if TARGET_SUPPORTS_WIDE_INT
6231 const_wide_int_htab
= hash_table
<const_wide_int_hasher
>::create_ggc (37);
6233 const_double_htab
= hash_table
<const_double_hasher
>::create_ggc (37);
6235 if (NUM_POLY_INT_COEFFS
> 1)
6236 const_poly_int_htab
= hash_table
<const_poly_int_hasher
>::create_ggc (37);
6238 const_fixed_htab
= hash_table
<const_fixed_hasher
>::create_ggc (37);
6240 reg_attrs_htab
= hash_table
<reg_attr_hasher
>::create_ggc (37);
6242 #ifdef INIT_EXPANDERS
6243 /* This is to initialize {init|mark|free}_machine_status before the first
6244 call to push_function_context_to. This is needed by the Chill front
6245 end which calls push_function_context_to before the first call to
6246 init_function_start. */
6250 /* Create the unique rtx's for certain rtx codes and operand values. */
6252 /* Process stack-limiting command-line options. */
6253 if (opt_fstack_limit_symbol_arg
!= NULL
)
6255 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (opt_fstack_limit_symbol_arg
));
6256 if (opt_fstack_limit_register_no
>= 0)
6257 stack_limit_rtx
= gen_rtx_REG (Pmode
, opt_fstack_limit_register_no
);
6259 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
6260 tries to use these variables. */
6261 for (i
= - MAX_SAVED_CONST_INT
; i
<= MAX_SAVED_CONST_INT
; i
++)
6262 const_int_rtx
[i
+ MAX_SAVED_CONST_INT
] =
6263 gen_rtx_raw_CONST_INT (VOIDmode
, (HOST_WIDE_INT
) i
);
6265 if (STORE_FLAG_VALUE
>= - MAX_SAVED_CONST_INT
6266 && STORE_FLAG_VALUE
<= MAX_SAVED_CONST_INT
)
6267 const_true_rtx
= const_int_rtx
[STORE_FLAG_VALUE
+ MAX_SAVED_CONST_INT
];
6269 const_true_rtx
= gen_rtx_CONST_INT (VOIDmode
, STORE_FLAG_VALUE
);
6271 double_mode
= float_mode_for_size (DOUBLE_TYPE_SIZE
).require ();
6273 real_from_integer (&dconst0
, double_mode
, 0, SIGNED
);
6274 real_from_integer (&dconst1
, double_mode
, 1, SIGNED
);
6275 real_from_integer (&dconst2
, double_mode
, 2, SIGNED
);
6280 dconsthalf
= dconst1
;
6281 SET_REAL_EXP (&dconsthalf
, REAL_EXP (&dconsthalf
) - 1);
6283 for (i
= 0; i
< 3; i
++)
6285 const REAL_VALUE_TYPE
*const r
=
6286 (i
== 0 ? &dconst0
: i
== 1 ? &dconst1
: &dconst2
);
6288 FOR_EACH_MODE_IN_CLASS (mode
, MODE_FLOAT
)
6289 const_tiny_rtx
[i
][(int) mode
] =
6290 const_double_from_real_value (*r
, mode
);
6292 FOR_EACH_MODE_IN_CLASS (mode
, MODE_DECIMAL_FLOAT
)
6293 const_tiny_rtx
[i
][(int) mode
] =
6294 const_double_from_real_value (*r
, mode
);
6296 const_tiny_rtx
[i
][(int) VOIDmode
] = GEN_INT (i
);
6298 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6299 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6301 for (mode
= MIN_MODE_PARTIAL_INT
;
6302 mode
<= MAX_MODE_PARTIAL_INT
;
6303 mode
= (machine_mode
)((int)(mode
) + 1))
6304 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6307 const_tiny_rtx
[3][(int) VOIDmode
] = constm1_rtx
;
6309 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6310 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6312 /* For BImode, 1 and -1 are unsigned and signed interpretations
6313 of the same value. */
6314 const_tiny_rtx
[0][(int) BImode
] = const0_rtx
;
6315 const_tiny_rtx
[1][(int) BImode
] = const_true_rtx
;
6316 const_tiny_rtx
[3][(int) BImode
] = const_true_rtx
;
6318 for (mode
= MIN_MODE_PARTIAL_INT
;
6319 mode
<= MAX_MODE_PARTIAL_INT
;
6320 mode
= (machine_mode
)((int)(mode
) + 1))
6321 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6323 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_INT
)
6325 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6326 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6329 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_FLOAT
)
6331 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6332 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6335 /* As for BImode, "all 1" and "all -1" are unsigned and signed
6336 interpretations of the same value. */
6337 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_BOOL
)
6339 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6340 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6341 const_tiny_rtx
[1][(int) mode
] = const_tiny_rtx
[3][(int) mode
];
6344 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_INT
)
6346 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6347 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6348 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6351 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FLOAT
)
6353 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6354 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6357 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_FRACT
)
6359 scalar_mode smode
= smode_iter
.require ();
6360 FCONST0 (smode
).data
.high
= 0;
6361 FCONST0 (smode
).data
.low
= 0;
6362 FCONST0 (smode
).mode
= smode
;
6363 const_tiny_rtx
[0][(int) smode
]
6364 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6367 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UFRACT
)
6369 scalar_mode smode
= smode_iter
.require ();
6370 FCONST0 (smode
).data
.high
= 0;
6371 FCONST0 (smode
).data
.low
= 0;
6372 FCONST0 (smode
).mode
= smode
;
6373 const_tiny_rtx
[0][(int) smode
]
6374 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6377 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_ACCUM
)
6379 scalar_mode smode
= smode_iter
.require ();
6380 FCONST0 (smode
).data
.high
= 0;
6381 FCONST0 (smode
).data
.low
= 0;
6382 FCONST0 (smode
).mode
= smode
;
6383 const_tiny_rtx
[0][(int) smode
]
6384 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6386 /* We store the value 1. */
6387 FCONST1 (smode
).data
.high
= 0;
6388 FCONST1 (smode
).data
.low
= 0;
6389 FCONST1 (smode
).mode
= smode
;
6390 FCONST1 (smode
).data
6391 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6392 HOST_BITS_PER_DOUBLE_INT
,
6393 SIGNED_FIXED_POINT_MODE_P (smode
));
6394 const_tiny_rtx
[1][(int) smode
]
6395 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6398 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UACCUM
)
6400 scalar_mode smode
= smode_iter
.require ();
6401 FCONST0 (smode
).data
.high
= 0;
6402 FCONST0 (smode
).data
.low
= 0;
6403 FCONST0 (smode
).mode
= smode
;
6404 const_tiny_rtx
[0][(int) smode
]
6405 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6407 /* We store the value 1. */
6408 FCONST1 (smode
).data
.high
= 0;
6409 FCONST1 (smode
).data
.low
= 0;
6410 FCONST1 (smode
).mode
= smode
;
6411 FCONST1 (smode
).data
6412 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6413 HOST_BITS_PER_DOUBLE_INT
,
6414 SIGNED_FIXED_POINT_MODE_P (smode
));
6415 const_tiny_rtx
[1][(int) smode
]
6416 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6419 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FRACT
)
6421 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6424 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UFRACT
)
6426 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6429 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_ACCUM
)
6431 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6432 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6435 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UACCUM
)
6437 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6438 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6441 for (i
= (int) CCmode
; i
< (int) MAX_MACHINE_MODE
; ++i
)
6442 if (GET_MODE_CLASS ((machine_mode
) i
) == MODE_CC
)
6443 const_tiny_rtx
[0][i
] = const0_rtx
;
6445 pc_rtx
= gen_rtx_fmt_ (PC
, VOIDmode
);
6446 ret_rtx
= gen_rtx_fmt_ (RETURN
, VOIDmode
);
6447 simple_return_rtx
= gen_rtx_fmt_ (SIMPLE_RETURN
, VOIDmode
);
6448 cc0_rtx
= gen_rtx_fmt_ (CC0
, VOIDmode
);
6449 invalid_insn_rtx
= gen_rtx_INSN (VOIDmode
,
6453 /*pattern=*/NULL_RTX
,
6456 /*reg_notes=*/NULL_RTX
);
6459 /* Produce exact duplicate of insn INSN after AFTER.
6460 Care updating of libcall regions if present. */
6463 emit_copy_of_insn_after (rtx_insn
*insn
, rtx_insn
*after
)
6468 switch (GET_CODE (insn
))
6471 new_rtx
= emit_insn_after (copy_insn (PATTERN (insn
)), after
);
6475 new_rtx
= emit_jump_insn_after (copy_insn (PATTERN (insn
)), after
);
6476 CROSSING_JUMP_P (new_rtx
) = CROSSING_JUMP_P (insn
);
6480 new_rtx
= emit_debug_insn_after (copy_insn (PATTERN (insn
)), after
);
6484 new_rtx
= emit_call_insn_after (copy_insn (PATTERN (insn
)), after
);
6485 if (CALL_INSN_FUNCTION_USAGE (insn
))
6486 CALL_INSN_FUNCTION_USAGE (new_rtx
)
6487 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn
));
6488 SIBLING_CALL_P (new_rtx
) = SIBLING_CALL_P (insn
);
6489 RTL_CONST_CALL_P (new_rtx
) = RTL_CONST_CALL_P (insn
);
6490 RTL_PURE_CALL_P (new_rtx
) = RTL_PURE_CALL_P (insn
);
6491 RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx
)
6492 = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn
);
6499 /* Update LABEL_NUSES. */
6500 mark_jump_label (PATTERN (new_rtx
), new_rtx
, 0);
6502 INSN_LOCATION (new_rtx
) = INSN_LOCATION (insn
);
6504 /* If the old insn is frame related, then so is the new one. This is
6505 primarily needed for IA-64 unwind info which marks epilogue insns,
6506 which may be duplicated by the basic block reordering code. */
6507 RTX_FRAME_RELATED_P (new_rtx
) = RTX_FRAME_RELATED_P (insn
);
6509 /* Locate the end of existing REG_NOTES in NEW_RTX. */
6510 rtx
*ptail
= ®_NOTES (new_rtx
);
6511 while (*ptail
!= NULL_RTX
)
6512 ptail
= &XEXP (*ptail
, 1);
6514 /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label
6515 will make them. REG_LABEL_TARGETs are created there too, but are
6516 supposed to be sticky, so we copy them. */
6517 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
6518 if (REG_NOTE_KIND (link
) != REG_LABEL_OPERAND
)
6520 *ptail
= duplicate_reg_note (link
);
6521 ptail
= &XEXP (*ptail
, 1);
6524 INSN_CODE (new_rtx
) = INSN_CODE (insn
);
6528 static GTY((deletable
)) rtx hard_reg_clobbers
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
6530 gen_hard_reg_clobber (machine_mode mode
, unsigned int regno
)
6532 if (hard_reg_clobbers
[mode
][regno
])
6533 return hard_reg_clobbers
[mode
][regno
];
6535 return (hard_reg_clobbers
[mode
][regno
] =
6536 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (mode
, regno
)));
6539 location_t prologue_location
;
6540 location_t epilogue_location
;
6542 /* Hold current location information and last location information, so the
6543 datastructures are built lazily only when some instructions in given
6544 place are needed. */
6545 static location_t curr_location
;
6547 /* Allocate insn location datastructure. */
6549 insn_locations_init (void)
6551 prologue_location
= epilogue_location
= 0;
6552 curr_location
= UNKNOWN_LOCATION
;
6555 /* At the end of emit stage, clear current location. */
6557 insn_locations_finalize (void)
6559 epilogue_location
= curr_location
;
6560 curr_location
= UNKNOWN_LOCATION
;
6563 /* Set current location. */
6565 set_curr_insn_location (location_t location
)
6567 curr_location
= location
;
6570 /* Get current location. */
6572 curr_insn_location (void)
6574 return curr_location
;
6577 /* Set the location of the insn chain starting at INSN to LOC. */
6579 set_insn_locations (rtx_insn
*insn
, location_t loc
)
6584 INSN_LOCATION (insn
) = loc
;
6585 insn
= NEXT_INSN (insn
);
6589 /* Return lexical scope block insn belongs to. */
6591 insn_scope (const rtx_insn
*insn
)
6593 return LOCATION_BLOCK (INSN_LOCATION (insn
));
6596 /* Return line number of the statement that produced this insn. */
6598 insn_line (const rtx_insn
*insn
)
6600 return LOCATION_LINE (INSN_LOCATION (insn
));
6603 /* Return source file of the statement that produced this insn. */
6605 insn_file (const rtx_insn
*insn
)
6607 return LOCATION_FILE (INSN_LOCATION (insn
));
6610 /* Return expanded location of the statement that produced this insn. */
6612 insn_location (const rtx_insn
*insn
)
6614 return expand_location (INSN_LOCATION (insn
));
6617 /* Return true if memory model MODEL requires a pre-operation (release-style)
6618 barrier or a post-operation (acquire-style) barrier. While not universal,
6619 this function matches behavior of several targets. */
6622 need_atomic_barrier_p (enum memmodel model
, bool pre
)
6624 switch (model
& MEMMODEL_BASE_MASK
)
6626 case MEMMODEL_RELAXED
:
6627 case MEMMODEL_CONSUME
:
6629 case MEMMODEL_RELEASE
:
6631 case MEMMODEL_ACQUIRE
:
6633 case MEMMODEL_ACQ_REL
:
6634 case MEMMODEL_SEQ_CST
:
6641 /* Return a constant shift amount for shifting a value of mode MODE
6645 gen_int_shift_amount (machine_mode
, poly_int64 value
)
6647 /* Use a 64-bit mode, to avoid any truncation.
6649 ??? Perhaps this should be automatically derived from the .md files
6650 instead, or perhaps have a target hook. */
6651 scalar_int_mode shift_mode
= (BITS_PER_UNIT
== 8
6653 : int_mode_for_size (64, 0).require ());
6654 return gen_int_mode (value
, shift_mode
);
6657 /* Initialize fields of rtl_data related to stack alignment. */
6660 rtl_data::init_stack_alignment ()
6662 stack_alignment_needed
= STACK_BOUNDARY
;
6663 max_used_stack_slot_alignment
= STACK_BOUNDARY
;
6664 stack_alignment_estimated
= 0;
6665 preferred_stack_boundary
= STACK_BOUNDARY
;
6669 #include "gt-emit-rtl.h"