RISC-V: Fix for combine bug with shift and AND operations.

[thirdparty/gcc.git] / gcc / testsuite / gcc.target / riscv / shift-and-1.c

/* { dg-do compile } */
/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */

/* Test for <optab>si3_mask.  */
int
sub1 (int i, int j)
{
  return i << (j & 0x1f);
}
/* { dg-final { scan-assembler-not "andi" } } */