]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - arch/x86/kvm/x86.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Use the POWER8 Micro Partition Prefetch Engine in KVM HV on POWER8
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
16a96021
MT		 109static bool backwards_tsc_observed = false;
110
18863bdd
AK		 111#define KVM_NR_SHARED_MSRS 16
112
113struct kvm_shared_msrs_global {
114 int nr;
2bf78fa7 115 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118struct kvm_shared_msrs {
119 struct user_return_notifier urn;
120 bool registered;
2bf78fa7
SY		 121 struct kvm_shared_msr_values {
122 u64 host;
123 u64 curr;
124 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 128static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 129
417bc304 130struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 131 { "pf_fixed", VCPU_STAT(pf_fixed) },
132 { "pf_guest", VCPU_STAT(pf_guest) },
133 { "tlb_flush", VCPU_STAT(tlb_flush) },
134 { "invlpg", VCPU_STAT(invlpg) },
135 { "exits", VCPU_STAT(exits) },
136 { "io_exits", VCPU_STAT(io_exits) },
137 { "mmio_exits", VCPU_STAT(mmio_exits) },
138 { "signal_exits", VCPU_STAT(signal_exits) },
139 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 140 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 141 { "halt_exits", VCPU_STAT(halt_exits) },
142 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 143 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 144 { "request_irq", VCPU_STAT(request_irq_exits) },
145 { "irq_exits", VCPU_STAT(irq_exits) },
146 { "host_state_reload", VCPU_STAT(host_state_reload) },
147 { "efer_reload", VCPU_STAT(efer_reload) },
148 { "fpu_reload", VCPU_STAT(fpu_reload) },
149 { "insn_emulation", VCPU_STAT(insn_emulation) },
150 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 151 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 152 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 153 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
154 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
155 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
156 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
157 { "mmu_flooded", VM_STAT(mmu_flooded) },
158 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 159 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 160 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 161 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 162 { "largepages", VM_STAT(lpages) },
417bc304
HB		 163 { NULL }
164};
165
2acf923e
DC		 166u64 __read_mostly host_xcr0;
167
b6785def 168static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 169
af585b92
GN		 170static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171{
172 int i;
173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
174 vcpu->arch.apf.gfns[i] = ~0;
175}
176
18863bdd
AK		 177static void kvm_on_user_return(struct user_return_notifier *urn)
178{
179 unsigned slot;
18863bdd
AK		 180 struct kvm_shared_msrs *locals
181 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 182 struct kvm_shared_msr_values *values;
18863bdd
AK		 183
184 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 185 values = &locals->values[slot];
186 if (values->host != values->curr) {
187 wrmsrl(shared_msrs_global.msrs[slot], values->host);
188 values->curr = values->host;
18863bdd
AK		 189 }
190 }
191 locals->registered = false;
192 user_return_notifier_unregister(urn);
193}
194
2bf78fa7 195static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 196{
18863bdd 197 u64 value;
013f6a5d
MT		 198 unsigned int cpu = smp_processor_id();
199 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 200
2bf78fa7
SY		 201 /* only read, and nobody should modify it at this time,
202 * so don't need lock */
203 if (slot >= shared_msrs_global.nr) {
204 printk(KERN_ERR "kvm: invalid MSR slot!");
205 return;
206 }
207 rdmsrl_safe(msr, &value);
208 smsr->values[slot].host = value;
209 smsr->values[slot].curr = value;
210}
211
212void kvm_define_shared_msr(unsigned slot, u32 msr)
213{
18863bdd
AK		 214 if (slot >= shared_msrs_global.nr)
215 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 216 shared_msrs_global.msrs[slot] = msr;
217 /* we need ensured the shared_msr_global have been updated */
218 smp_wmb();
18863bdd
AK		 219}
220EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
221
222static void kvm_shared_msr_cpu_online(void)
223{
224 unsigned i;
18863bdd
AK		 225
226 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 227 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 228}
229
d5696725 230void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 231{
013f6a5d
MT		 232 unsigned int cpu = smp_processor_id();
233 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 234
2bf78fa7 235 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 236 return;
2bf78fa7
SY		 237 smsr->values[slot].curr = value;
238 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 239 if (!smsr->registered) {
240 smsr->urn.on_user_return = kvm_on_user_return;
241 user_return_notifier_register(&smsr->urn);
242 smsr->registered = true;
243 }
244}
245EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
246
3548bab5
AK		 247static void drop_user_return_notifiers(void *ignore)
248{
013f6a5d
MT		 249 unsigned int cpu = smp_processor_id();
250 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 251
252 if (smsr->registered)
253 kvm_on_user_return(&smsr->urn);
254}
255
6866b83e
CO		 256u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
257{
8a5a87d9 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
58cb628d
JK		 262int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
263{
264 u64 old_state = vcpu->arch.apic_base &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 new_state = msr_info->data &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
269 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
270
271 if (!msr_info->host_initiated &&
272 ((msr_info->data & reserved_bits) != 0 ||
273 new_state == X2APIC_ENABLE ||
274 (new_state == MSR_IA32_APICBASE_ENABLE &&
275 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
276 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
277 old_state == 0)))
278 return 1;
279
280 kvm_lapic_set_base(vcpu, msr_info->data);
281 return 0;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_set_apic_base);
284
2605fc21 285asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 286{
287 /* Fault while not rebooting. We want the trace. */
288 BUG();
289}
290EXPORT_SYMBOL_GPL(kvm_spurious_fault);
291
3fd28fce
ED		 292#define EXCPT_BENIGN 0
293#define EXCPT_CONTRIBUTORY 1
294#define EXCPT_PF 2
295
296static int exception_class(int vector)
297{
298 switch (vector) {
299 case PF_VECTOR:
300 return EXCPT_PF;
301 case DE_VECTOR:
302 case TS_VECTOR:
303 case NP_VECTOR:
304 case SS_VECTOR:
305 case GP_VECTOR:
306 return EXCPT_CONTRIBUTORY;
307 default:
308 break;
309 }
310 return EXCPT_BENIGN;
311}
312
313static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 314 unsigned nr, bool has_error, u32 error_code,
315 bool reinject)
3fd28fce
ED		 316{
317 u32 prev_nr;
318 int class1, class2;
319
3842d135
AK		 320 kvm_make_request(KVM_REQ_EVENT, vcpu);
321
3fd28fce
ED		 322 if (!vcpu->arch.exception.pending) {
323 queue:
324 vcpu->arch.exception.pending = true;
325 vcpu->arch.exception.has_error_code = has_error;
326 vcpu->arch.exception.nr = nr;
327 vcpu->arch.exception.error_code = error_code;
3f0fd292 328 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 329 return;
330 }
331
332 /* to check exception */
333 prev_nr = vcpu->arch.exception.nr;
334 if (prev_nr == DF_VECTOR) {
335 /* triple fault -> shutdown */
a8eeb04a 336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 337 return;
338 }
339 class1 = exception_class(prev_nr);
340 class2 = exception_class(nr);
341 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
342 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
343 /* generate double fault per SDM Table 5-5 */
344 vcpu->arch.exception.pending = true;
345 vcpu->arch.exception.has_error_code = true;
346 vcpu->arch.exception.nr = DF_VECTOR;
347 vcpu->arch.exception.error_code = 0;
348 } else
349 /* replace previous exception with a new one in a hope
350 that instruction re-execution will regenerate lost
351 exception */
352 goto queue;
353}
354
298101da
AK		 355void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
356{
ce7ddec4 357 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 358}
359EXPORT_SYMBOL_GPL(kvm_queue_exception);
360
ce7ddec4
JR		 361void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
362{
363 kvm_multiple_exception(vcpu, nr, false, 0, true);
364}
365EXPORT_SYMBOL_GPL(kvm_requeue_exception);
366
db8fcefa 367void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 368{
db8fcefa
AP		 369 if (err)
370 kvm_inject_gp(vcpu, 0);
371 else
372 kvm_x86_ops->skip_emulated_instruction(vcpu);
373}
374EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 375
6389ee94 376void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 377{
378 ++vcpu->stat.pf_guest;
6389ee94
AK		 379 vcpu->arch.cr2 = fault->address;
380 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 381}
27d6c865 382EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 383
6389ee94 384void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 385{
6389ee94
AK		 386 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
387 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 388 else
6389ee94 389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 390}
391
3419ffc8
SY		 392void kvm_inject_nmi(struct kvm_vcpu *vcpu)
393{
7460fb4a
AK		 394 atomic_inc(&vcpu->arch.nmi_queued);
395 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 396}
397EXPORT_SYMBOL_GPL(kvm_inject_nmi);
398
298101da
AK		 399void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
400{
ce7ddec4 401 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 402}
403EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
404
ce7ddec4
JR		 405void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
406{
407 kvm_multiple_exception(vcpu, nr, true, error_code, true);
408}
409EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
410
0a79b009
AK		 411/*
412 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
413 * a #GP and return false.
414 */
415bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 416{
0a79b009
AK		 417 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
418 return true;
419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
420 return false;
298101da 421}
0a79b009 422EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 423
ec92fe44
JR		 424/*
425 * This function will be used to read from the physical memory of the currently
426 * running guest. The difference to kvm_read_guest_page is that this function
427 * can read from guest physical or from the guest's guest physical memory.
428 */
429int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
430 gfn_t ngfn, void *data, int offset, int len,
431 u32 access)
432{
433 gfn_t real_gfn;
434 gpa_t ngpa;
435
436 ngpa = gfn_to_gpa(ngfn);
437 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
438 if (real_gfn == UNMAPPED_GVA)
439 return -EFAULT;
440
441 real_gfn = gpa_to_gfn(real_gfn);
442
443 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
444}
445EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
446
3d06b8bf
JR		 447int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
448 void *data, int offset, int len, u32 access)
449{
450 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
451 data, offset, len, access);
452}
453
a03490ed
CO		 454/*
455 * Load the pae pdptrs. Return true is they are all valid.
456 */
ff03a073 457int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 458{
459 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
460 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
461 int i;
462 int ret;
ff03a073 463 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 464
ff03a073
JR		 465 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
466 offset * sizeof(u64), sizeof(pdpte),
467 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 468 if (ret < 0) {
469 ret = 0;
470 goto out;
471 }
472 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 473 if (is_present_gpte(pdpte[i]) &&
20c466b5 474 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 475 ret = 0;
476 goto out;
477 }
478 }
479 ret = 1;
480
ff03a073 481 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail);
484 __set_bit(VCPU_EXREG_PDPTR,
485 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 486out:
a03490ed
CO		 487
488 return ret;
489}
cc4b6871 490EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 491
d835dfec
AK		 492static bool pdptrs_changed(struct kvm_vcpu *vcpu)
493{
ff03a073 494 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 495 bool changed = true;
3d06b8bf
JR		 496 int offset;
497 gfn_t gfn;
d835dfec
AK		 498 int r;
499
500 if (is_long_mode(vcpu) || !is_pae(vcpu))
501 return false;
502
6de4f3ad
AK		 503 if (!test_bit(VCPU_EXREG_PDPTR,
504 (unsigned long *)&vcpu->arch.regs_avail))
505 return true;
506
9f8fe504
AK		 507 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
508 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 509 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
510 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 511 if (r < 0)
512 goto out;
ff03a073 513 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 514out:
d835dfec
AK		 515
516 return changed;
517}
518
49a9b07e 519int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 520{
aad82703
SY		 521 unsigned long old_cr0 = kvm_read_cr0(vcpu);
522 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
523 X86_CR0_CD | X86_CR0_NW;
524
f9a48e6a
AK		 525 cr0 |= X86_CR0_ET;
526
ab344828 527#ifdef CONFIG_X86_64
0f12244f
GN		 528 if (cr0 & 0xffffffff00000000UL)
529 return 1;
ab344828
GN		 530#endif
531
532 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 533
0f12244f
GN		 534 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
535 return 1;
a03490ed 536
0f12244f
GN		 537 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
538 return 1;
a03490ed
CO		 539
540 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
541#ifdef CONFIG_X86_64
f6801dff 542 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 543 int cs_db, cs_l;
544
0f12244f
GN		 545 if (!is_pae(vcpu))
546 return 1;
a03490ed 547 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 548 if (cs_l)
549 return 1;
a03490ed
CO		 550 } else
551#endif
ff03a073 552 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 553 kvm_read_cr3(vcpu)))
0f12244f 554 return 1;
a03490ed
CO		 555 }
556
ad756a16
MJ		 557 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
558 return 1;
559
a03490ed 560 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 561
d170c419 562 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 563 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 564 kvm_async_pf_hash_reset(vcpu);
565 }
e5f3f027 566
aad82703
SY		 567 if ((cr0 ^ old_cr0) & update_bits)
568 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 569 return 0;
570}
2d3ad1f4 571EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 572
2d3ad1f4 573void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 574{
49a9b07e 575 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 578
42bdf991
MT		 579static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
580{
581 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
582 !vcpu->guest_xcr0_loaded) {
583 /* kvm_set_xcr() also depends on this */
584 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
585 vcpu->guest_xcr0_loaded = 1;
586 }
587}
588
589static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
590{
591 if (vcpu->guest_xcr0_loaded) {
592 if (vcpu->arch.xcr0 != host_xcr0)
593 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
594 vcpu->guest_xcr0_loaded = 0;
595 }
596}
597
2acf923e
DC		 598int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599{
56c103ec
LJ		 600 u64 xcr0 = xcr;
601 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 602 u64 valid_bits;
2acf923e
DC		 603
604 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
605 if (index != XCR_XFEATURE_ENABLED_MASK)
606 return 1;
2acf923e
DC		 607 if (!(xcr0 & XSTATE_FP))
608 return 1;
609 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
610 return 1;
46c34cb0
PB		 611
612 /*
613 * Do not allow the guest to set bits that we do not support
614 * saving. However, xcr0 bit 0 is always set, even if the
615 * emulated CPU does not support XSAVE (see fx_init).
616 */
617 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
618 if (xcr0 & ~valid_bits)
2acf923e 619 return 1;
46c34cb0 620
390bd528
LJ		 621 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
622 return 1;
623
42bdf991 624 kvm_put_guest_xcr0(vcpu);
2acf923e 625 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 626
627 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
628 kvm_update_cpuid(vcpu);
2acf923e
DC		 629 return 0;
630}
631
632int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
633{
764bcbc5
Z		 634 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
635 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 636 kvm_inject_gp(vcpu, 0);
637 return 1;
638 }
639 return 0;
640}
641EXPORT_SYMBOL_GPL(kvm_set_xcr);
642
a83b29c6 643int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 644{
fc78f519 645 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 646 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
647 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 648 if (cr4 & CR4_RESERVED_BITS)
649 return 1;
a03490ed 650
2acf923e
DC		 651 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
652 return 1;
653
c68b734f
YW		 654 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
655 return 1;
656
97ec8c06
FW		 657 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
658 return 1;
659
afcbf13f 660 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 661 return 1;
662
a03490ed 663 if (is_long_mode(vcpu)) {
0f12244f
GN		 664 if (!(cr4 & X86_CR4_PAE))
665 return 1;
a2edf57f
AK		 666 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
667 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 668 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
0f12244f
GN		 670 return 1;
671
ad756a16
MJ		 672 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
673 if (!guest_cpuid_has_pcid(vcpu))
674 return 1;
675
676 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
677 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
678 return 1;
679 }
680
5e1746d6 681 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 682 return 1;
a03490ed 683
ad756a16
MJ		 684 if (((cr4 ^ old_cr4) & pdptr_bits) ||
685 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 686 kvm_mmu_reset_context(vcpu);
0f12244f 687
97ec8c06
FW		 688 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
689 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
690
2acf923e 691 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 692 kvm_update_cpuid(vcpu);
2acf923e 693
0f12244f
GN		 694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 697
2390218b 698int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 699{
9f8fe504 700 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 701 kvm_mmu_sync_roots(vcpu);
d835dfec 702 kvm_mmu_flush_tlb(vcpu);
0f12244f 703 return 0;
d835dfec
AK		 704 }
705
a03490ed 706 if (is_long_mode(vcpu)) {
d9f89b88
JK		 707 if (cr3 & CR3_L_MODE_RESERVED_BITS)
708 return 1;
709 } else if (is_pae(vcpu) && is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 711 return 1;
a03490ed 712
0f12244f 713 vcpu->arch.cr3 = cr3;
aff48baa 714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 715 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 716 return 0;
717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 719
eea1cff9 720int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 721{
0f12244f
GN		 722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
a03490ed
CO		 724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
ad312c7c 727 vcpu->arch.cr8 = cr8;
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 731
2d3ad1f4 732unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 733{
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
ad312c7c 737 return vcpu->arch.cr8;
a03490ed 738}
2d3ad1f4 739EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 740
73aaf249
JK		 741static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742{
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745}
746
c8639010
JK		 747static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748{
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 756 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
757 if (dr7 & DR7_BP_EN_MASK)
758 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 759}
760
338dbc97 761static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 762{
763 switch (dr) {
764 case 0 ... 3:
765 vcpu->arch.db[dr] = val;
766 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
767 vcpu->arch.eff_db[dr] = val;
768 break;
769 case 4:
338dbc97
GN		 770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
771 return 1; /* #UD */
020df079
GN		 772 /* fall through */
773 case 6:
338dbc97
GN		 774 if (val & 0xffffffff00000000ULL)
775 return -1; /* #GP */
020df079 776 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 777 kvm_update_dr6(vcpu);
020df079
GN		 778 break;
779 case 5:
338dbc97
GN		 780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 return 1; /* #UD */
020df079
GN		 782 /* fall through */
783 default: /* 7 */
338dbc97
GN		 784 if (val & 0xffffffff00000000ULL)
785 return -1; /* #GP */
020df079 786 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 787 kvm_update_dr7(vcpu);
020df079
GN		 788 break;
789 }
790
791 return 0;
792}
338dbc97
GN		 793
794int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
795{
796 int res;
797
798 res = __kvm_set_dr(vcpu, dr, val);
799 if (res > 0)
800 kvm_queue_exception(vcpu, UD_VECTOR);
801 else if (res < 0)
802 kvm_inject_gp(vcpu, 0);
803
804 return res;
805}
020df079
GN		 806EXPORT_SYMBOL_GPL(kvm_set_dr);
807
338dbc97 808static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 809{
810 switch (dr) {
811 case 0 ... 3:
812 *val = vcpu->arch.db[dr];
813 break;
814 case 4:
338dbc97 815 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 816 return 1;
020df079
GN		 817 /* fall through */
818 case 6:
73aaf249
JK		 819 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
820 *val = vcpu->arch.dr6;
821 else
822 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 823 break;
824 case 5:
338dbc97 825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 826 return 1;
020df079
GN		 827 /* fall through */
828 default: /* 7 */
829 *val = vcpu->arch.dr7;
830 break;
831 }
832
833 return 0;
834}
338dbc97
GN		 835
836int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
837{
838 if (_kvm_get_dr(vcpu, dr, val)) {
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 return 1;
841 }
842 return 0;
843}
020df079
GN		 844EXPORT_SYMBOL_GPL(kvm_get_dr);
845
022cd0e8
AK		 846bool kvm_rdpmc(struct kvm_vcpu *vcpu)
847{
848 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
849 u64 data;
850 int err;
851
852 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
853 if (err)
854 return err;
855 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
856 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
857 return err;
858}
859EXPORT_SYMBOL_GPL(kvm_rdpmc);
860
043405e1
CO		 861/*
862 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
863 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
864 *
865 * This list is modified at module load time to reflect the
e3267cbb
GC		 866 * capabilities of the host cpu. This capabilities test skips MSRs that are
867 * kvm-specific. Those are put in the beginning of the list.
043405e1 868 */
e3267cbb 869
e984097b 870#define KVM_SAVE_MSRS_BEGIN 12
043405e1 871static u32 msrs_to_save[] = {
e3267cbb 872 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 873 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 874 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 875 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 876 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 877 MSR_KVM_PV_EOI_EN,
043405e1 878 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 879 MSR_STAR,
043405e1
CO		 880#ifdef CONFIG_X86_64
881 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
882#endif
b3897a49 883 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 884 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 885};
886
887static unsigned num_msrs_to_save;
888
f1d24831 889static const u32 emulated_msrs[] = {
ba904635 890 MSR_IA32_TSC_ADJUST,
a3e06bbe 891 MSR_IA32_TSCDEADLINE,
043405e1 892 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 893 MSR_IA32_MCG_STATUS,
894 MSR_IA32_MCG_CTL,
043405e1
CO		 895};
896
384bb783 897bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 898{
b69e8cae 899 if (efer & efer_reserved_bits)
384bb783 900 return false;
15c4a640 901
1b2fd70c
AG		 902 if (efer & EFER_FFXSR) {
903 struct kvm_cpuid_entry2 *feat;
904
905 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 906 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 907 return false;
1b2fd70c
AG		 908 }
909
d8017474
AG		 910 if (efer & EFER_SVME) {
911 struct kvm_cpuid_entry2 *feat;
912
913 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 914 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 915 return false;
d8017474
AG		 916 }
917
384bb783
JK		 918 return true;
919}
920EXPORT_SYMBOL_GPL(kvm_valid_efer);
921
922static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
923{
924 u64 old_efer = vcpu->arch.efer;
925
926 if (!kvm_valid_efer(vcpu, efer))
927 return 1;
928
929 if (is_paging(vcpu)
930 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
931 return 1;
932
15c4a640 933 efer &= ~EFER_LMA;
f6801dff 934 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 935
a3d204e2
SY		 936 kvm_x86_ops->set_efer(vcpu, efer);
937
aad82703
SY		 938 /* Update reserved bits */
939 if ((efer ^ old_efer) & EFER_NX)
940 kvm_mmu_reset_context(vcpu);
941
b69e8cae 942 return 0;
15c4a640
CO		 943}
944
f2b4b7dd
JR		 945void kvm_enable_efer_bits(u64 mask)
946{
947 efer_reserved_bits &= ~mask;
948}
949EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
950
951
15c4a640
CO		 952/*
953 * Writes msr value into into the appropriate "register".
954 * Returns 0 on success, non-0 otherwise.
955 * Assumes vcpu_load() was already called.
956 */
8fe8ab46 957int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 958{
8fe8ab46 959 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 960}
961
313a3dc7
CO		 962/*
963 * Adapt set_msr() to msr_io()'s calling convention
964 */
965static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
966{
8fe8ab46
WA		 967 struct msr_data msr;
968
969 msr.data = *data;
970 msr.index = index;
971 msr.host_initiated = true;
972 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 973}
974
16e8d74d
MT		 975#ifdef CONFIG_X86_64
976struct pvclock_gtod_data {
977 seqcount_t seq;
978
979 struct { /* extract of a clocksource struct */
980 int vclock_mode;
981 cycle_t cycle_last;
982 cycle_t mask;
983 u32 mult;
984 u32 shift;
985 } clock;
986
987 /* open coded 'struct timespec' */
988 u64 monotonic_time_snsec;
989 time_t monotonic_time_sec;
990};
991
992static struct pvclock_gtod_data pvclock_gtod_data;
993
994static void update_pvclock_gtod(struct timekeeper *tk)
995{
996 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
997
998 write_seqcount_begin(&vdata->seq);
999
1000 /* copy pvclock gtod data */
1001 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1002 vdata->clock.cycle_last = tk->clock->cycle_last;
1003 vdata->clock.mask = tk->clock->mask;
1004 vdata->clock.mult = tk->mult;
1005 vdata->clock.shift = tk->shift;
1006
1007 vdata->monotonic_time_sec = tk->xtime_sec
1008 + tk->wall_to_monotonic.tv_sec;
1009 vdata->monotonic_time_snsec = tk->xtime_nsec
1010 + (tk->wall_to_monotonic.tv_nsec
1011 << tk->shift);
1012 while (vdata->monotonic_time_snsec >=
1013 (((u64)NSEC_PER_SEC) << tk->shift)) {
1014 vdata->monotonic_time_snsec -=
1015 ((u64)NSEC_PER_SEC) << tk->shift;
1016 vdata->monotonic_time_sec++;
1017 }
1018
1019 write_seqcount_end(&vdata->seq);
1020}
1021#endif
1022
1023
18068523
GOC		 1024static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1025{
9ed3c444
AK		 1026 int version;
1027 int r;
50d0a0f9 1028 struct pvclock_wall_clock wc;
923de3cf 1029 struct timespec boot;
18068523
GOC		 1030
1031 if (!wall_clock)
1032 return;
1033
9ed3c444
AK		 1034 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1035 if (r)
1036 return;
1037
1038 if (version & 1)
1039 ++version; /* first time write, random junk */
1040
1041 ++version;
18068523 1042
18068523
GOC		 1043 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1044
50d0a0f9
GH		 1045 /*
1046 * The guest calculates current wall clock time by adding
34c238a1 1047 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1048 * wall clock specified here. guest system time equals host
1049 * system time for us, thus we must fill in host boot time here.
1050 */
923de3cf 1051 getboottime(&boot);
50d0a0f9 1052
4b648665
BR		 1053 if (kvm->arch.kvmclock_offset) {
1054 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1055 boot = timespec_sub(boot, ts);
1056 }
50d0a0f9
GH		 1057 wc.sec = boot.tv_sec;
1058 wc.nsec = boot.tv_nsec;
1059 wc.version = version;
18068523
GOC		 1060
1061 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1062
1063 version++;
1064 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1065}
1066
50d0a0f9
GH		 1067static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1068{
1069 uint32_t quotient, remainder;
1070
1071 /* Don't try to replace with do_div(), this one calculates
1072 * "(dividend << 32) / divisor" */
1073 __asm__ ( "divl %4"
1074 : "=a" (quotient), "=d" (remainder)
1075 : "0" (0), "1" (dividend), "r" (divisor) );
1076 return quotient;
1077}
1078
5f4e3f88
ZA		 1079static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1080 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1081{
5f4e3f88 1082 uint64_t scaled64;
50d0a0f9
GH		 1083 int32_t shift = 0;
1084 uint64_t tps64;
1085 uint32_t tps32;
1086
5f4e3f88
ZA		 1087 tps64 = base_khz * 1000LL;
1088 scaled64 = scaled_khz * 1000LL;
50933623 1089 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1090 tps64 >>= 1;
1091 shift--;
1092 }
1093
1094 tps32 = (uint32_t)tps64;
50933623
JK		 1095 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1096 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1097 scaled64 >>= 1;
1098 else
1099 tps32 <<= 1;
50d0a0f9
GH		 1100 shift++;
1101 }
1102
5f4e3f88
ZA		 1103 *pshift = shift;
1104 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1105
5f4e3f88
ZA		 1106 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1107 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1108}
1109
759379dd
ZA		 1110static inline u64 get_kernel_ns(void)
1111{
1112 struct timespec ts;
1113
759379dd
ZA		 1114 ktime_get_ts(&ts);
1115 monotonic_to_bootbased(&ts);
1116 return timespec_to_ns(&ts);
50d0a0f9
GH		 1117}
1118
d828199e 1119#ifdef CONFIG_X86_64
16e8d74d 1120static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1121#endif
16e8d74d 1122
c8076604 1123static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1124unsigned long max_tsc_khz;
c8076604 1125
cc578287 1126static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1127{
cc578287
ZA		 1128 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1129 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1130}
1131
cc578287 1132static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1133{
cc578287
ZA		 1134 u64 v = (u64)khz * (1000000 + ppm);
1135 do_div(v, 1000000);
1136 return v;
1e993611
JR		 1137}
1138
cc578287 1139static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1140{
cc578287
ZA		 1141 u32 thresh_lo, thresh_hi;
1142 int use_scaling = 0;
217fc9cf 1143
03ba32ca
MT		 1144 /* tsc_khz can be zero if TSC calibration fails */
1145 if (this_tsc_khz == 0)
1146 return;
1147
c285545f
ZA		 1148 /* Compute a scale to convert nanoseconds in TSC cycles */
1149 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1150 &vcpu->arch.virtual_tsc_shift,
1151 &vcpu->arch.virtual_tsc_mult);
1152 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1153
1154 /*
1155 * Compute the variation in TSC rate which is acceptable
1156 * within the range of tolerance and decide if the
1157 * rate being applied is within that bounds of the hardware
1158 * rate. If so, no scaling or compensation need be done.
1159 */
1160 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1161 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1162 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1163 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1164 use_scaling = 1;
1165 }
1166 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1167}
1168
1169static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1170{
e26101b1 1171 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1172 vcpu->arch.virtual_tsc_mult,
1173 vcpu->arch.virtual_tsc_shift);
e26101b1 1174 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1175 return tsc;
1176}
1177
b48aa97e
MT		 1178void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1179{
1180#ifdef CONFIG_X86_64
1181 bool vcpus_matched;
1182 bool do_request = false;
1183 struct kvm_arch *ka = &vcpu->kvm->arch;
1184 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1185
1186 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1187 atomic_read(&vcpu->kvm->online_vcpus));
1188
1189 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1190 if (!ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (!vcpus_matched && ka->use_master_clock)
1194 do_request = 1;
1195
1196 if (do_request)
1197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1198
1199 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1200 atomic_read(&vcpu->kvm->online_vcpus),
1201 ka->use_master_clock, gtod->clock.vclock_mode);
1202#endif
1203}
1204
ba904635
WA		 1205static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1206{
1207 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1208 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1209}
1210
8fe8ab46 1211void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1212{
1213 struct kvm *kvm = vcpu->kvm;
f38e098f 1214 u64 offset, ns, elapsed;
99e3e30a 1215 unsigned long flags;
02626b6a 1216 s64 usdiff;
b48aa97e 1217 bool matched;
8fe8ab46 1218 u64 data = msr->data;
99e3e30a 1219
038f8c11 1220 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1221 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1222 ns = get_kernel_ns();
f38e098f 1223 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1224
03ba32ca 1225 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1226 int faulted = 0;
1227
03ba32ca
MT		 1228 /* n.b - signed multiplication and division required */
1229 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1230#ifdef CONFIG_X86_64
03ba32ca 1231 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1232#else
03ba32ca 1233 /* do_div() only does unsigned */
8915aa27
MT		 1234 asm("1: idivl %[divisor]\n"
1235 "2: xor %%edx, %%edx\n"
1236 " movl $0, %[faulted]\n"
1237 "3:\n"
1238 ".section .fixup,\"ax\"\n"
1239 "4: movl $1, %[faulted]\n"
1240 " jmp 3b\n"
1241 ".previous\n"
1242
1243 _ASM_EXTABLE(1b, 4b)
1244
1245 : "=A"(usdiff), [faulted] "=r" (faulted)
1246 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1247
5d3cb0f6 1248#endif
03ba32ca
MT		 1249 do_div(elapsed, 1000);
1250 usdiff -= elapsed;
1251 if (usdiff < 0)
1252 usdiff = -usdiff;
8915aa27
MT		 1253
1254 /* idivl overflow => difference is larger than USEC_PER_SEC */
1255 if (faulted)
1256 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1257 } else
1258 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1259
1260 /*
5d3cb0f6
ZA		 1261 * Special case: TSC write with a small delta (1 second) of virtual
1262 * cycle time against real time is interpreted as an attempt to
1263 * synchronize the CPU.
1264 *
1265 * For a reliable TSC, we can match TSC offsets, and for an unstable
1266 * TSC, we add elapsed time in this computation. We could let the
1267 * compensation code attempt to catch up if we fall behind, but
1268 * it's better to try to match offsets from the beginning.
1269 */
02626b6a 1270 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1271 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1272 if (!check_tsc_unstable()) {
e26101b1 1273 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1274 pr_debug("kvm: matched tsc offset for %llu\n", data);
1275 } else {
857e4099 1276 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1277 data += delta;
1278 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1279 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1280 }
b48aa97e 1281 matched = true;
e26101b1
ZA		 1282 } else {
1283 /*
1284 * We split periods of matched TSC writes into generations.
1285 * For each generation, we track the original measured
1286 * nanosecond time, offset, and write, so if TSCs are in
1287 * sync, we can match exact offset, and if not, we can match
4a969980 1288 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1289 *
1290 * These values are tracked in kvm->arch.cur_xxx variables.
1291 */
1292 kvm->arch.cur_tsc_generation++;
1293 kvm->arch.cur_tsc_nsec = ns;
1294 kvm->arch.cur_tsc_write = data;
1295 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1296 matched = false;
e26101b1
ZA		 1297 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1298 kvm->arch.cur_tsc_generation, data);
f38e098f 1299 }
e26101b1
ZA		 1300
1301 /*
1302 * We also track th most recent recorded KHZ, write and time to
1303 * allow the matching interval to be extended at each write.
1304 */
f38e098f
ZA		 1305 kvm->arch.last_tsc_nsec = ns;
1306 kvm->arch.last_tsc_write = data;
5d3cb0f6 1307 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1308
b183aa58 1309 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1310
1311 /* Keep track of which generation this VCPU has synchronized to */
1312 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1313 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1314 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1315
ba904635
WA		 1316 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1317 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1318 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1319 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1320
1321 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1322 if (matched)
1323 kvm->arch.nr_vcpus_matched_tsc++;
1324 else
1325 kvm->arch.nr_vcpus_matched_tsc = 0;
1326
1327 kvm_track_tsc_matching(vcpu);
1328 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1329}
e26101b1 1330
99e3e30a
ZA		 1331EXPORT_SYMBOL_GPL(kvm_write_tsc);
1332
d828199e
MT		 1333#ifdef CONFIG_X86_64
1334
1335static cycle_t read_tsc(void)
1336{
1337 cycle_t ret;
1338 u64 last;
1339
1340 /*
1341 * Empirically, a fence (of type that depends on the CPU)
1342 * before rdtsc is enough to ensure that rdtsc is ordered
1343 * with respect to loads. The various CPU manuals are unclear
1344 * as to whether rdtsc can be reordered with later loads,
1345 * but no one has ever seen it happen.
1346 */
1347 rdtsc_barrier();
1348 ret = (cycle_t)vget_cycles();
1349
1350 last = pvclock_gtod_data.clock.cycle_last;
1351
1352 if (likely(ret >= last))
1353 return ret;
1354
1355 /*
1356 * GCC likes to generate cmov here, but this branch is extremely
1357 * predictable (it's just a funciton of time and the likely is
1358 * very likely) and there's a data dependence, so force GCC
1359 * to generate a branch instead. I don't barrier() because
1360 * we don't actually need a barrier, and if this function
1361 * ever gets inlined it will generate worse code.
1362 */
1363 asm volatile ("");
1364 return last;
1365}
1366
1367static inline u64 vgettsc(cycle_t *cycle_now)
1368{
1369 long v;
1370 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1371
1372 *cycle_now = read_tsc();
1373
1374 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1375 return v * gtod->clock.mult;
1376}
1377
1378static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1379{
1380 unsigned long seq;
1381 u64 ns;
1382 int mode;
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384
1385 ts->tv_nsec = 0;
1386 do {
1387 seq = read_seqcount_begin(&gtod->seq);
1388 mode = gtod->clock.vclock_mode;
1389 ts->tv_sec = gtod->monotonic_time_sec;
1390 ns = gtod->monotonic_time_snsec;
1391 ns += vgettsc(cycle_now);
1392 ns >>= gtod->clock.shift;
1393 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1394 timespec_add_ns(ts, ns);
1395
1396 return mode;
1397}
1398
1399/* returns true if host is using tsc clocksource */
1400static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1401{
1402 struct timespec ts;
1403
1404 /* checked again under seqlock below */
1405 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1406 return false;
1407
1408 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1409 return false;
1410
1411 monotonic_to_bootbased(&ts);
1412 *kernel_ns = timespec_to_ns(&ts);
1413
1414 return true;
1415}
1416#endif
1417
1418/*
1419 *
b48aa97e
MT		 1420 * Assuming a stable TSC across physical CPUS, and a stable TSC
1421 * across virtual CPUs, the following condition is possible.
1422 * Each numbered line represents an event visible to both
d828199e
MT		 1423 * CPUs at the next numbered event.
1424 *
1425 * "timespecX" represents host monotonic time. "tscX" represents
1426 * RDTSC value.
1427 *
1428 * VCPU0 on CPU0 | VCPU1 on CPU1
1429 *
1430 * 1. read timespec0,tsc0
1431 * 2. | timespec1 = timespec0 + N
1432 * | tsc1 = tsc0 + M
1433 * 3. transition to guest | transition to guest
1434 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1435 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1436 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1437 *
1438 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1439 *
1440 * - ret0 < ret1
1441 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1442 * ...
1443 * - 0 < N - M => M < N
1444 *
1445 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1446 * always the case (the difference between two distinct xtime instances
1447 * might be smaller then the difference between corresponding TSC reads,
1448 * when updating guest vcpus pvclock areas).
1449 *
1450 * To avoid that problem, do not allow visibility of distinct
1451 * system_timestamp/tsc_timestamp values simultaneously: use a master
1452 * copy of host monotonic time values. Update that master copy
1453 * in lockstep.
1454 *
b48aa97e 1455 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1456 *
1457 */
1458
1459static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1460{
1461#ifdef CONFIG_X86_64
1462 struct kvm_arch *ka = &kvm->arch;
1463 int vclock_mode;
b48aa97e
MT		 1464 bool host_tsc_clocksource, vcpus_matched;
1465
1466 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1467 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1468
1469 /*
1470 * If the host uses TSC clock, then passthrough TSC as stable
1471 * to the guest.
1472 */
b48aa97e 1473 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1474 &ka->master_kernel_ns,
1475 &ka->master_cycle_now);
1476
16a96021
MT		 1477 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1478 && !backwards_tsc_observed;
b48aa97e 1479
d828199e
MT		 1480 if (ka->use_master_clock)
1481 atomic_set(&kvm_guest_has_master_clock, 1);
1482
1483 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1484 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1485 vcpus_matched);
d828199e
MT		 1486#endif
1487}
1488
2e762ff7
MT		 1489static void kvm_gen_update_masterclock(struct kvm *kvm)
1490{
1491#ifdef CONFIG_X86_64
1492 int i;
1493 struct kvm_vcpu *vcpu;
1494 struct kvm_arch *ka = &kvm->arch;
1495
1496 spin_lock(&ka->pvclock_gtod_sync_lock);
1497 kvm_make_mclock_inprogress_request(kvm);
1498 /* no guest entries from this point */
1499 pvclock_update_vm_gtod_copy(kvm);
1500
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1503
1504 /* guest entries allowed */
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1507
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
1509#endif
1510}
1511
34c238a1 1512static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1513{
d828199e 1514 unsigned long flags, this_tsc_khz;
18068523 1515 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1516 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1517 s64 kernel_ns;
d828199e 1518 u64 tsc_timestamp, host_tsc;
0b79459b 1519 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1520 u8 pvclock_flags;
d828199e
MT		 1521 bool use_master_clock;
1522
1523 kernel_ns = 0;
1524 host_tsc = 0;
18068523 1525
d828199e
MT		 1526 /*
1527 * If the host uses TSC clock, then passthrough TSC as stable
1528 * to the guest.
1529 */
1530 spin_lock(&ka->pvclock_gtod_sync_lock);
1531 use_master_clock = ka->use_master_clock;
1532 if (use_master_clock) {
1533 host_tsc = ka->master_cycle_now;
1534 kernel_ns = ka->master_kernel_ns;
1535 }
1536 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1537
1538 /* Keep irq disabled to prevent changes to the clock */
1539 local_irq_save(flags);
1540 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1541 if (unlikely(this_tsc_khz == 0)) {
1542 local_irq_restore(flags);
1543 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1544 return 1;
1545 }
d828199e
MT		 1546 if (!use_master_clock) {
1547 host_tsc = native_read_tsc();
1548 kernel_ns = get_kernel_ns();
1549 }
1550
1551 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1552
c285545f
ZA		 1553 /*
1554 * We may have to catch up the TSC to match elapsed wall clock
1555 * time for two reasons, even if kvmclock is used.
1556 * 1) CPU could have been running below the maximum TSC rate
1557 * 2) Broken TSC compensation resets the base at each VCPU
1558 * entry to avoid unknown leaps of TSC even when running
1559 * again on the same CPU. This may cause apparent elapsed
1560 * time to disappear, and the guest to stand still or run
1561 * very slowly.
1562 */
1563 if (vcpu->tsc_catchup) {
1564 u64 tsc = compute_guest_tsc(v, kernel_ns);
1565 if (tsc > tsc_timestamp) {
f1e2b260 1566 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1567 tsc_timestamp = tsc;
1568 }
50d0a0f9
GH		 1569 }
1570
18068523
GOC		 1571 local_irq_restore(flags);
1572
0b79459b 1573 if (!vcpu->pv_time_enabled)
c285545f 1574 return 0;
18068523 1575
e48672fa 1576 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1577 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1578 &vcpu->hv_clock.tsc_shift,
1579 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1580 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1581 }
1582
1583 /* With all the info we got, fill in the values */
1d5f066e 1584 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1585 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1586 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1587
18068523
GOC		 1588 /*
1589 * The interface expects us to write an even number signaling that the
1590 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1591 * state, we just increase by 2 at the end.
18068523 1592 */
50d0a0f9 1593 vcpu->hv_clock.version += 2;
18068523 1594
0b79459b
AH		 1595 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1596 &guest_hv_clock, sizeof(guest_hv_clock))))
1597 return 0;
78c0337a
MT		 1598
1599 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1600 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1601
1602 if (vcpu->pvclock_set_guest_stopped_request) {
1603 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1604 vcpu->pvclock_set_guest_stopped_request = false;
1605 }
1606
d828199e
MT		 1607 /* If the host uses TSC clocksource, then it is stable */
1608 if (use_master_clock)
1609 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1610
78c0337a
MT		 1611 vcpu->hv_clock.flags = pvclock_flags;
1612
0b79459b
AH		 1613 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1614 &vcpu->hv_clock,
1615 sizeof(vcpu->hv_clock));
8cfdc000 1616 return 0;
c8076604
GH		 1617}
1618
0061d53d
MT		 1619/*
1620 * kvmclock updates which are isolated to a given vcpu, such as
1621 * vcpu->cpu migration, should not allow system_timestamp from
1622 * the rest of the vcpus to remain static. Otherwise ntp frequency
1623 * correction applies to one vcpu's system_timestamp but not
1624 * the others.
1625 *
1626 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1627 * We need to rate-limit these requests though, as they can
1628 * considerably slow guests that have a large number of vcpus.
1629 * The time for a remote vcpu to update its kvmclock is bound
1630 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1631 */
1632
7e44e449
AJ		 1633#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1634
1635static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1636{
1637 int i;
7e44e449
AJ		 1638 struct delayed_work *dwork = to_delayed_work(work);
1639 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1640 kvmclock_update_work);
1641 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1642 struct kvm_vcpu *vcpu;
1643
1644 kvm_for_each_vcpu(i, vcpu, kvm) {
1645 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1646 kvm_vcpu_kick(vcpu);
1647 }
1648}
1649
7e44e449
AJ		 1650static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1651{
1652 struct kvm *kvm = v->kvm;
1653
1654 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1655 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1656 KVMCLOCK_UPDATE_DELAY);
1657}
1658
332967a3
AJ		 1659#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1660
1661static void kvmclock_sync_fn(struct work_struct *work)
1662{
1663 struct delayed_work *dwork = to_delayed_work(work);
1664 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1665 kvmclock_sync_work);
1666 struct kvm *kvm = container_of(ka, struct kvm, arch);
1667
1668 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1669 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1670 KVMCLOCK_SYNC_PERIOD);
1671}
1672
9ba075a6
AK		 1673static bool msr_mtrr_valid(unsigned msr)
1674{
1675 switch (msr) {
1676 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1677 case MSR_MTRRfix64K_00000:
1678 case MSR_MTRRfix16K_80000:
1679 case MSR_MTRRfix16K_A0000:
1680 case MSR_MTRRfix4K_C0000:
1681 case MSR_MTRRfix4K_C8000:
1682 case MSR_MTRRfix4K_D0000:
1683 case MSR_MTRRfix4K_D8000:
1684 case MSR_MTRRfix4K_E0000:
1685 case MSR_MTRRfix4K_E8000:
1686 case MSR_MTRRfix4K_F0000:
1687 case MSR_MTRRfix4K_F8000:
1688 case MSR_MTRRdefType:
1689 case MSR_IA32_CR_PAT:
1690 return true;
1691 case 0x2f8:
1692 return true;
1693 }
1694 return false;
1695}
1696
d6289b93
MT		 1697static bool valid_pat_type(unsigned t)
1698{
1699 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1700}
1701
1702static bool valid_mtrr_type(unsigned t)
1703{
1704 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1705}
1706
1707static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1708{
1709 int i;
1710
1711 if (!msr_mtrr_valid(msr))
1712 return false;
1713
1714 if (msr == MSR_IA32_CR_PAT) {
1715 for (i = 0; i < 8; i++)
1716 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1717 return false;
1718 return true;
1719 } else if (msr == MSR_MTRRdefType) {
1720 if (data & ~0xcff)
1721 return false;
1722 return valid_mtrr_type(data & 0xff);
1723 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1724 for (i = 0; i < 8 ; i++)
1725 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1726 return false;
1727 return true;
1728 }
1729
1730 /* variable MTRRs */
1731 return valid_mtrr_type(data & 0xff);
1732}
1733
9ba075a6
AK		 1734static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1735{
0bed3b56
SY		 1736 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1737
d6289b93 1738 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1739 return 1;
1740
0bed3b56
SY		 1741 if (msr == MSR_MTRRdefType) {
1742 vcpu->arch.mtrr_state.def_type = data;
1743 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1744 } else if (msr == MSR_MTRRfix64K_00000)
1745 p[0] = data;
1746 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1747 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1748 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1749 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1750 else if (msr == MSR_IA32_CR_PAT)
1751 vcpu->arch.pat = data;
1752 else { /* Variable MTRRs */
1753 int idx, is_mtrr_mask;
1754 u64 *pt;
1755
1756 idx = (msr - 0x200) / 2;
1757 is_mtrr_mask = msr - 0x200 - 2 * idx;
1758 if (!is_mtrr_mask)
1759 pt =
1760 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1761 else
1762 pt =
1763 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1764 *pt = data;
1765 }
1766
1767 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1768 return 0;
1769}
15c4a640 1770
890ca9ae 1771static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1772{
890ca9ae
HY		 1773 u64 mcg_cap = vcpu->arch.mcg_cap;
1774 unsigned bank_num = mcg_cap & 0xff;
1775
15c4a640 1776 switch (msr) {
15c4a640 1777 case MSR_IA32_MCG_STATUS:
890ca9ae 1778 vcpu->arch.mcg_status = data;
15c4a640 1779 break;
c7ac679c 1780 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1781 if (!(mcg_cap & MCG_CTL_P))
1782 return 1;
1783 if (data != 0 && data != ~(u64)0)
1784 return -1;
1785 vcpu->arch.mcg_ctl = data;
1786 break;
1787 default:
1788 if (msr >= MSR_IA32_MC0_CTL &&
1789 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1790 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1791 /* only 0 or all 1s can be written to IA32_MCi_CTL
1792 * some Linux kernels though clear bit 10 in bank 4 to
1793 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1794 * this to avoid an uncatched #GP in the guest
1795 */
890ca9ae 1796 if ((offset & 0x3) == 0 &&
114be429 1797 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1798 return -1;
1799 vcpu->arch.mce_banks[offset] = data;
1800 break;
1801 }
1802 return 1;
1803 }
1804 return 0;
1805}
1806
ffde22ac
ES		 1807static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1808{
1809 struct kvm *kvm = vcpu->kvm;
1810 int lm = is_long_mode(vcpu);
1811 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1812 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1813 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1814 : kvm->arch.xen_hvm_config.blob_size_32;
1815 u32 page_num = data & ~PAGE_MASK;
1816 u64 page_addr = data & PAGE_MASK;
1817 u8 *page;
1818 int r;
1819
1820 r = -E2BIG;
1821 if (page_num >= blob_size)
1822 goto out;
1823 r = -ENOMEM;
ff5c2c03
SL		 1824 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1825 if (IS_ERR(page)) {
1826 r = PTR_ERR(page);
ffde22ac 1827 goto out;
ff5c2c03 1828 }
ffde22ac
ES		 1829 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1830 goto out_free;
1831 r = 0;
1832out_free:
1833 kfree(page);
1834out:
1835 return r;
1836}
1837
55cd8e5a
GN		 1838static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1839{
1840 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1841}
1842
1843static bool kvm_hv_msr_partition_wide(u32 msr)
1844{
1845 bool r = false;
1846 switch (msr) {
1847 case HV_X64_MSR_GUEST_OS_ID:
1848 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1849 case HV_X64_MSR_REFERENCE_TSC:
1850 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1851 r = true;
1852 break;
1853 }
1854
1855 return r;
1856}
1857
1858static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1859{
1860 struct kvm *kvm = vcpu->kvm;
1861
1862 switch (msr) {
1863 case HV_X64_MSR_GUEST_OS_ID:
1864 kvm->arch.hv_guest_os_id = data;
1865 /* setting guest os id to zero disables hypercall page */
1866 if (!kvm->arch.hv_guest_os_id)
1867 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1868 break;
1869 case HV_X64_MSR_HYPERCALL: {
1870 u64 gfn;
1871 unsigned long addr;
1872 u8 instructions[4];
1873
1874 /* if guest os id is not set hypercall should remain disabled */
1875 if (!kvm->arch.hv_guest_os_id)
1876 break;
1877 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1878 kvm->arch.hv_hypercall = data;
1879 break;
1880 }
1881 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1882 addr = gfn_to_hva(kvm, gfn);
1883 if (kvm_is_error_hva(addr))
1884 return 1;
1885 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1886 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1887 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1888 return 1;
1889 kvm->arch.hv_hypercall = data;
b94b64c9 1890 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1891 break;
1892 }
e984097b
VR		 1893 case HV_X64_MSR_REFERENCE_TSC: {
1894 u64 gfn;
1895 HV_REFERENCE_TSC_PAGE tsc_ref;
1896 memset(&tsc_ref, 0, sizeof(tsc_ref));
1897 kvm->arch.hv_tsc_page = data;
1898 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1899 break;
1900 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1901 if (kvm_write_guest(kvm, data,
1902 &tsc_ref, sizeof(tsc_ref)))
1903 return 1;
1904 mark_page_dirty(kvm, gfn);
1905 break;
1906 }
55cd8e5a 1907 default:
a737f256
CD		 1908 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1909 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1910 return 1;
1911 }
1912 return 0;
1913}
1914
1915static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1916{
10388a07
GN		 1917 switch (msr) {
1918 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1919 u64 gfn;
10388a07 1920 unsigned long addr;
55cd8e5a 1921
10388a07
GN		 1922 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1923 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1924 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1925 return 1;
10388a07
GN		 1926 break;
1927 }
b3af1e88
VR		 1928 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1929 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1930 if (kvm_is_error_hva(addr))
1931 return 1;
8b0cedff 1932 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1933 return 1;
1934 vcpu->arch.hv_vapic = data;
b3af1e88 1935 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1936 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1937 return 1;
10388a07
GN		 1938 break;
1939 }
1940 case HV_X64_MSR_EOI:
1941 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1942 case HV_X64_MSR_ICR:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1944 case HV_X64_MSR_TPR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1946 default:
a737f256
CD		 1947 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948 "data 0x%llx\n", msr, data);
10388a07
GN		 1949 return 1;
1950 }
1951
1952 return 0;
55cd8e5a
GN		 1953}
1954
344d9588
GN		 1955static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1956{
1957 gpa_t gpa = data & ~0x3f;
1958
4a969980 1959 /* Bits 2:5 are reserved, Should be zero */
6adba527 1960 if (data & 0x3c)
344d9588
GN		 1961 return 1;
1962
1963 vcpu->arch.apf.msr_val = data;
1964
1965 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1966 kvm_clear_async_pf_completion_queue(vcpu);
1967 kvm_async_pf_hash_reset(vcpu);
1968 return 0;
1969 }
1970
8f964525
AH		 1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1972 sizeof(u32)))
344d9588
GN		 1973 return 1;
1974
6adba527 1975 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1976 kvm_async_pf_wakeup_all(vcpu);
1977 return 0;
1978}
1979
12f9a48f
GC		 1980static void kvmclock_reset(struct kvm_vcpu *vcpu)
1981{
0b79459b 1982 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1983}
1984
c9aaa895
GC		 1985static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1986{
1987 u64 delta;
1988
1989 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1990 return;
1991
1992 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1993 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1994 vcpu->arch.st.accum_steal = delta;
1995}
1996
1997static void record_steal_time(struct kvm_vcpu *vcpu)
1998{
1999 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2000 return;
2001
2002 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2004 return;
2005
2006 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2007 vcpu->arch.st.steal.version += 2;
2008 vcpu->arch.st.accum_steal = 0;
2009
2010 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2012}
2013
8fe8ab46 2014int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2015{
5753785f 2016 bool pr = false;
8fe8ab46
WA		 2017 u32 msr = msr_info->index;
2018 u64 data = msr_info->data;
5753785f 2019
15c4a640 2020 switch (msr) {
2e32b719
BP		 2021 case MSR_AMD64_NB_CFG:
2022 case MSR_IA32_UCODE_REV:
2023 case MSR_IA32_UCODE_WRITE:
2024 case MSR_VM_HSAVE_PA:
2025 case MSR_AMD64_PATCH_LOADER:
2026 case MSR_AMD64_BU_CFG2:
2027 break;
2028
15c4a640 2029 case MSR_EFER:
b69e8cae 2030 return set_efer(vcpu, data);
8f1589d9
AP		 2031 case MSR_K7_HWCR:
2032 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2033 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2034 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2035 if (data != 0) {
a737f256
CD		 2036 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2037 data);
8f1589d9
AP		 2038 return 1;
2039 }
15c4a640 2040 break;
f7c6d140
AP		 2041 case MSR_FAM10H_MMIO_CONF_BASE:
2042 if (data != 0) {
a737f256
CD		 2043 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2044 "0x%llx\n", data);
f7c6d140
AP		 2045 return 1;
2046 }
15c4a640 2047 break;
b5e2fec0
AG		 2048 case MSR_IA32_DEBUGCTLMSR:
2049 if (!data) {
2050 /* We support the non-activated case already */
2051 break;
2052 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2053 /* Values other than LBR and BTF are vendor-specific,
2054 thus reserved and should throw a #GP */
2055 return 1;
2056 }
a737f256
CD		 2057 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2058 __func__, data);
b5e2fec0 2059 break;
9ba075a6
AK		 2060 case 0x200 ... 0x2ff:
2061 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2062 case MSR_IA32_APICBASE:
58cb628d 2063 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2064 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2065 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2066 case MSR_IA32_TSCDEADLINE:
2067 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2068 break;
ba904635
WA		 2069 case MSR_IA32_TSC_ADJUST:
2070 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2071 if (!msr_info->host_initiated) {
2072 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2073 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2074 }
2075 vcpu->arch.ia32_tsc_adjust_msr = data;
2076 }
2077 break;
15c4a640 2078 case MSR_IA32_MISC_ENABLE:
ad312c7c 2079 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2080 break;
11c6bffa 2081 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2082 case MSR_KVM_WALL_CLOCK:
2083 vcpu->kvm->arch.wall_clock = data;
2084 kvm_write_wall_clock(vcpu->kvm, data);
2085 break;
11c6bffa 2086 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2087 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2088 u64 gpa_offset;
12f9a48f 2089 kvmclock_reset(vcpu);
18068523
GOC		 2090
2091 vcpu->arch.time = data;
0061d53d 2092 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2093
2094 /* we verify if the enable bit is set... */
2095 if (!(data & 1))
2096 break;
2097
0b79459b 2098 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2099
0b79459b 2100 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2101 &vcpu->arch.pv_time, data & ~1ULL,
2102 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2103 vcpu->arch.pv_time_enabled = false;
2104 else
2105 vcpu->arch.pv_time_enabled = true;
32cad84f 2106
18068523
GOC		 2107 break;
2108 }
344d9588
GN		 2109 case MSR_KVM_ASYNC_PF_EN:
2110 if (kvm_pv_enable_async_pf(vcpu, data))
2111 return 1;
2112 break;
c9aaa895
GC		 2113 case MSR_KVM_STEAL_TIME:
2114
2115 if (unlikely(!sched_info_on()))
2116 return 1;
2117
2118 if (data & KVM_STEAL_RESERVED_MASK)
2119 return 1;
2120
2121 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2122 data & KVM_STEAL_VALID_BITS,
2123 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2124 return 1;
2125
2126 vcpu->arch.st.msr_val = data;
2127
2128 if (!(data & KVM_MSR_ENABLED))
2129 break;
2130
2131 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2132
2133 preempt_disable();
2134 accumulate_steal_time(vcpu);
2135 preempt_enable();
2136
2137 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2138
2139 break;
ae7a2a3f
MT		 2140 case MSR_KVM_PV_EOI_EN:
2141 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2142 return 1;
2143 break;
c9aaa895 2144
890ca9ae
HY		 2145 case MSR_IA32_MCG_CTL:
2146 case MSR_IA32_MCG_STATUS:
2147 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2148 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2149
2150 /* Performance counters are not protected by a CPUID bit,
2151 * so we should check all of them in the generic path for the sake of
2152 * cross vendor migration.
2153 * Writing a zero into the event select MSRs disables them,
2154 * which we perfectly emulate ;-). Any other value should be at least
2155 * reported, some guests depend on them.
2156 */
71db6023
AP		 2157 case MSR_K7_EVNTSEL0:
2158 case MSR_K7_EVNTSEL1:
2159 case MSR_K7_EVNTSEL2:
2160 case MSR_K7_EVNTSEL3:
2161 if (data != 0)
a737f256
CD		 2162 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2163 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2164 break;
2165 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2166 * so we ignore writes to make it happy.
2167 */
71db6023
AP		 2168 case MSR_K7_PERFCTR0:
2169 case MSR_K7_PERFCTR1:
2170 case MSR_K7_PERFCTR2:
2171 case MSR_K7_PERFCTR3:
a737f256
CD		 2172 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2173 "0x%x data 0x%llx\n", msr, data);
71db6023 2174 break;
5753785f
GN		 2175 case MSR_P6_PERFCTR0:
2176 case MSR_P6_PERFCTR1:
2177 pr = true;
2178 case MSR_P6_EVNTSEL0:
2179 case MSR_P6_EVNTSEL1:
2180 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2181 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2182
2183 if (pr || data != 0)
a737f256
CD		 2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2185 "0x%x data 0x%llx\n", msr, data);
5753785f 2186 break;
84e0cefa
JS		 2187 case MSR_K7_CLK_CTL:
2188 /*
2189 * Ignore all writes to this no longer documented MSR.
2190 * Writes are only relevant for old K7 processors,
2191 * all pre-dating SVM, but a recommended workaround from
4a969980 2192 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2193 * affected processor models on the command line, hence
2194 * the need to ignore the workaround.
2195 */
2196 break;
55cd8e5a
GN		 2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2198 if (kvm_hv_msr_partition_wide(msr)) {
2199 int r;
2200 mutex_lock(&vcpu->kvm->lock);
2201 r = set_msr_hyperv_pw(vcpu, msr, data);
2202 mutex_unlock(&vcpu->kvm->lock);
2203 return r;
2204 } else
2205 return set_msr_hyperv(vcpu, msr, data);
2206 break;
91c9c3ed 2207 case MSR_IA32_BBL_CR_CTL3:
2208 /* Drop writes to this legacy MSR -- see rdmsr
2209 * counterpart for further detail.
2210 */
a737f256 2211 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2212 break;
2b036c6b
BO		 2213 case MSR_AMD64_OSVW_ID_LENGTH:
2214 if (!guest_cpuid_has_osvw(vcpu))
2215 return 1;
2216 vcpu->arch.osvw.length = data;
2217 break;
2218 case MSR_AMD64_OSVW_STATUS:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.status = data;
2222 break;
15c4a640 2223 default:
ffde22ac
ES		 2224 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2225 return xen_hvm_config(vcpu, data);
f5132b01 2226 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2227 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2228 if (!ignore_msrs) {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 return 1;
2232 } else {
a737f256
CD		 2233 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2234 msr, data);
ed85c068
AP		 2235 break;
2236 }
15c4a640
CO		 2237 }
2238 return 0;
2239}
2240EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2241
2242
2243/*
2244 * Reads an msr value (of 'msr_index') into 'pdata'.
2245 * Returns 0 on success, non-0 otherwise.
2246 * Assumes vcpu_load() was already called.
2247 */
2248int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2249{
2250 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2251}
2252
9ba075a6
AK		 2253static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254{
0bed3b56
SY		 2255 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2256
9ba075a6
AK		 2257 if (!msr_mtrr_valid(msr))
2258 return 1;
2259
0bed3b56
SY		 2260 if (msr == MSR_MTRRdefType)
2261 *pdata = vcpu->arch.mtrr_state.def_type +
2262 (vcpu->arch.mtrr_state.enabled << 10);
2263 else if (msr == MSR_MTRRfix64K_00000)
2264 *pdata = p[0];
2265 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2266 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2267 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2268 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2269 else if (msr == MSR_IA32_CR_PAT)
2270 *pdata = vcpu->arch.pat;
2271 else { /* Variable MTRRs */
2272 int idx, is_mtrr_mask;
2273 u64 *pt;
2274
2275 idx = (msr - 0x200) / 2;
2276 is_mtrr_mask = msr - 0x200 - 2 * idx;
2277 if (!is_mtrr_mask)
2278 pt =
2279 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2280 else
2281 pt =
2282 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2283 *pdata = *pt;
2284 }
2285
9ba075a6
AK		 2286 return 0;
2287}
2288
890ca9ae 2289static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2290{
2291 u64 data;
890ca9ae
HY		 2292 u64 mcg_cap = vcpu->arch.mcg_cap;
2293 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2294
2295 switch (msr) {
15c4a640
CO		 2296 case MSR_IA32_P5_MC_ADDR:
2297 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2298 data = 0;
2299 break;
15c4a640 2300 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2301 data = vcpu->arch.mcg_cap;
2302 break;
c7ac679c 2303 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2304 if (!(mcg_cap & MCG_CTL_P))
2305 return 1;
2306 data = vcpu->arch.mcg_ctl;
2307 break;
2308 case MSR_IA32_MCG_STATUS:
2309 data = vcpu->arch.mcg_status;
2310 break;
2311 default:
2312 if (msr >= MSR_IA32_MC0_CTL &&
2313 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2314 u32 offset = msr - MSR_IA32_MC0_CTL;
2315 data = vcpu->arch.mce_banks[offset];
2316 break;
2317 }
2318 return 1;
2319 }
2320 *pdata = data;
2321 return 0;
2322}
2323
55cd8e5a
GN		 2324static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2325{
2326 u64 data = 0;
2327 struct kvm *kvm = vcpu->kvm;
2328
2329 switch (msr) {
2330 case HV_X64_MSR_GUEST_OS_ID:
2331 data = kvm->arch.hv_guest_os_id;
2332 break;
2333 case HV_X64_MSR_HYPERCALL:
2334 data = kvm->arch.hv_hypercall;
2335 break;
e984097b
VR		 2336 case HV_X64_MSR_TIME_REF_COUNT: {
2337 data =
2338 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2339 break;
2340 }
2341 case HV_X64_MSR_REFERENCE_TSC:
2342 data = kvm->arch.hv_tsc_page;
2343 break;
55cd8e5a 2344 default:
a737f256 2345 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2346 return 1;
2347 }
2348
2349 *pdata = data;
2350 return 0;
2351}
2352
2353static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2354{
2355 u64 data = 0;
2356
2357 switch (msr) {
2358 case HV_X64_MSR_VP_INDEX: {
2359 int r;
2360 struct kvm_vcpu *v;
684851a1
TY		 2361 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2362 if (v == vcpu) {
55cd8e5a 2363 data = r;
684851a1
TY		 2364 break;
2365 }
2366 }
55cd8e5a
GN		 2367 break;
2368 }
10388a07
GN		 2369 case HV_X64_MSR_EOI:
2370 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2371 case HV_X64_MSR_ICR:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2373 case HV_X64_MSR_TPR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2375 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2376 data = vcpu->arch.hv_vapic;
2377 break;
55cd8e5a 2378 default:
a737f256 2379 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2380 return 1;
2381 }
2382 *pdata = data;
2383 return 0;
2384}
2385
890ca9ae
HY		 2386int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2387{
2388 u64 data;
2389
2390 switch (msr) {
890ca9ae 2391 case MSR_IA32_PLATFORM_ID:
15c4a640 2392 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2393 case MSR_IA32_DEBUGCTLMSR:
2394 case MSR_IA32_LASTBRANCHFROMIP:
2395 case MSR_IA32_LASTBRANCHTOIP:
2396 case MSR_IA32_LASTINTFROMIP:
2397 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2398 case MSR_K8_SYSCFG:
2399 case MSR_K7_HWCR:
61a6bd67 2400 case MSR_VM_HSAVE_PA:
9e699624 2401 case MSR_K7_EVNTSEL0:
1f3ee616 2402 case MSR_K7_PERFCTR0:
1fdbd48c 2403 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2404 case MSR_AMD64_NB_CFG:
f7c6d140 2405 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2406 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2407 data = 0;
2408 break;
5753785f
GN		 2409 case MSR_P6_PERFCTR0:
2410 case MSR_P6_PERFCTR1:
2411 case MSR_P6_EVNTSEL0:
2412 case MSR_P6_EVNTSEL1:
2413 if (kvm_pmu_msr(vcpu, msr))
2414 return kvm_pmu_get_msr(vcpu, msr, pdata);
2415 data = 0;
2416 break;
742bc670
MT		 2417 case MSR_IA32_UCODE_REV:
2418 data = 0x100000000ULL;
2419 break;
9ba075a6
AK		 2420 case MSR_MTRRcap:
2421 data = 0x500 | KVM_NR_VAR_MTRR;
2422 break;
2423 case 0x200 ... 0x2ff:
2424 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2425 case 0xcd: /* fsb frequency */
2426 data = 3;
2427 break;
7b914098
JS		 2428 /*
2429 * MSR_EBC_FREQUENCY_ID
2430 * Conservative value valid for even the basic CPU models.
2431 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2432 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2433 * and 266MHz for model 3, or 4. Set Core Clock
2434 * Frequency to System Bus Frequency Ratio to 1 (bits
2435 * 31:24) even though these are only valid for CPU
2436 * models > 2, however guests may end up dividing or
2437 * multiplying by zero otherwise.
2438 */
2439 case MSR_EBC_FREQUENCY_ID:
2440 data = 1 << 24;
2441 break;
15c4a640
CO		 2442 case MSR_IA32_APICBASE:
2443 data = kvm_get_apic_base(vcpu);
2444 break;
0105d1a5
GN		 2445 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2446 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2447 break;
a3e06bbe
LJ		 2448 case MSR_IA32_TSCDEADLINE:
2449 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2450 break;
ba904635
WA		 2451 case MSR_IA32_TSC_ADJUST:
2452 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2453 break;
15c4a640 2454 case MSR_IA32_MISC_ENABLE:
ad312c7c 2455 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2456 break;
847f0ad8
AG		 2457 case MSR_IA32_PERF_STATUS:
2458 /* TSC increment by tick */
2459 data = 1000ULL;
2460 /* CPU multiplier */
2461 data |= (((uint64_t)4ULL) << 40);
2462 break;
15c4a640 2463 case MSR_EFER:
f6801dff 2464 data = vcpu->arch.efer;
15c4a640 2465 break;
18068523 2466 case MSR_KVM_WALL_CLOCK:
11c6bffa 2467 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2468 data = vcpu->kvm->arch.wall_clock;
2469 break;
2470 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2471 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2472 data = vcpu->arch.time;
2473 break;
344d9588
GN		 2474 case MSR_KVM_ASYNC_PF_EN:
2475 data = vcpu->arch.apf.msr_val;
2476 break;
c9aaa895
GC		 2477 case MSR_KVM_STEAL_TIME:
2478 data = vcpu->arch.st.msr_val;
2479 break;
1d92128f
MT		 2480 case MSR_KVM_PV_EOI_EN:
2481 data = vcpu->arch.pv_eoi.msr_val;
2482 break;
890ca9ae
HY		 2483 case MSR_IA32_P5_MC_ADDR:
2484 case MSR_IA32_P5_MC_TYPE:
2485 case MSR_IA32_MCG_CAP:
2486 case MSR_IA32_MCG_CTL:
2487 case MSR_IA32_MCG_STATUS:
2488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2489 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2490 case MSR_K7_CLK_CTL:
2491 /*
2492 * Provide expected ramp-up count for K7. All other
2493 * are set to zero, indicating minimum divisors for
2494 * every field.
2495 *
2496 * This prevents guest kernels on AMD host with CPU
2497 * type 6, model 8 and higher from exploding due to
2498 * the rdmsr failing.
2499 */
2500 data = 0x20000000;
2501 break;
55cd8e5a
GN		 2502 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2503 if (kvm_hv_msr_partition_wide(msr)) {
2504 int r;
2505 mutex_lock(&vcpu->kvm->lock);
2506 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2507 mutex_unlock(&vcpu->kvm->lock);
2508 return r;
2509 } else
2510 return get_msr_hyperv(vcpu, msr, pdata);
2511 break;
91c9c3ed 2512 case MSR_IA32_BBL_CR_CTL3:
2513 /* This legacy MSR exists but isn't fully documented in current
2514 * silicon. It is however accessed by winxp in very narrow
2515 * scenarios where it sets bit #19, itself documented as
2516 * a "reserved" bit. Best effort attempt to source coherent
2517 * read data here should the balance of the register be
2518 * interpreted by the guest:
2519 *
2520 * L2 cache control register 3: 64GB range, 256KB size,
2521 * enabled, latency 0x1, configured
2522 */
2523 data = 0xbe702111;
2524 break;
2b036c6b
BO		 2525 case MSR_AMD64_OSVW_ID_LENGTH:
2526 if (!guest_cpuid_has_osvw(vcpu))
2527 return 1;
2528 data = vcpu->arch.osvw.length;
2529 break;
2530 case MSR_AMD64_OSVW_STATUS:
2531 if (!guest_cpuid_has_osvw(vcpu))
2532 return 1;
2533 data = vcpu->arch.osvw.status;
2534 break;
15c4a640 2535 default:
f5132b01
GN		 2536 if (kvm_pmu_msr(vcpu, msr))
2537 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2538 if (!ignore_msrs) {
a737f256 2539 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2540 return 1;
2541 } else {
a737f256 2542 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2543 data = 0;
2544 }
2545 break;
15c4a640
CO		 2546 }
2547 *pdata = data;
2548 return 0;
2549}
2550EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2551
313a3dc7
CO		 2552/*
2553 * Read or write a bunch of msrs. All parameters are kernel addresses.
2554 *
2555 * @return number of msrs set successfully.
2556 */
2557static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2558 struct kvm_msr_entry *entries,
2559 int (*do_msr)(struct kvm_vcpu *vcpu,
2560 unsigned index, u64 *data))
2561{
f656ce01 2562 int i, idx;
313a3dc7 2563
f656ce01 2564 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2565 for (i = 0; i < msrs->nmsrs; ++i)
2566 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2567 break;
f656ce01 2568 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2569
313a3dc7
CO		 2570 return i;
2571}
2572
2573/*
2574 * Read or write a bunch of msrs. Parameters are user addresses.
2575 *
2576 * @return number of msrs set successfully.
2577 */
2578static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data),
2581 int writeback)
2582{
2583 struct kvm_msrs msrs;
2584 struct kvm_msr_entry *entries;
2585 int r, n;
2586 unsigned size;
2587
2588 r = -EFAULT;
2589 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2590 goto out;
2591
2592 r = -E2BIG;
2593 if (msrs.nmsrs >= MAX_IO_MSRS)
2594 goto out;
2595
313a3dc7 2596 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2597 entries = memdup_user(user_msrs->entries, size);
2598 if (IS_ERR(entries)) {
2599 r = PTR_ERR(entries);
313a3dc7 2600 goto out;
ff5c2c03 2601 }
313a3dc7
CO		 2602
2603 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2604 if (r < 0)
2605 goto out_free;
2606
2607 r = -EFAULT;
2608 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2609 goto out_free;
2610
2611 r = n;
2612
2613out_free:
7a73c028 2614 kfree(entries);
313a3dc7
CO		 2615out:
2616 return r;
2617}
2618
018d00d2
ZX		 2619int kvm_dev_ioctl_check_extension(long ext)
2620{
2621 int r;
2622
2623 switch (ext) {
2624 case KVM_CAP_IRQCHIP:
2625 case KVM_CAP_HLT:
2626 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2627 case KVM_CAP_SET_TSS_ADDR:
07716717 2628 case KVM_CAP_EXT_CPUID:
9c15bb1d 2629 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2630 case KVM_CAP_CLOCKSOURCE:
7837699f 2631 case KVM_CAP_PIT:
a28e4f5a 2632 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2633 case KVM_CAP_MP_STATE:
ed848624 2634 case KVM_CAP_SYNC_MMU:
a355c85c 2635 case KVM_CAP_USER_NMI:
52d939a0 2636 case KVM_CAP_REINJECT_CONTROL:
4925663a 2637 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2638 case KVM_CAP_IRQFD:
d34e6b17 2639 case KVM_CAP_IOEVENTFD:
f848a5a8 2640 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2641 case KVM_CAP_PIT2:
e9f42757 2642 case KVM_CAP_PIT_STATE2:
b927a3ce 2643 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2644 case KVM_CAP_XEN_HVM:
afbcf7ab 2645 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2646 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2647 case KVM_CAP_HYPERV:
10388a07 2648 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2649 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2650 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2651 case KVM_CAP_DEBUGREGS:
d2be1651 2652 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2653 case KVM_CAP_XSAVE:
344d9588 2654 case KVM_CAP_ASYNC_PF:
92a1f12d 2655 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2656 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2657 case KVM_CAP_READONLY_MEM:
5f66b620 2658 case KVM_CAP_HYPERV_TIME:
100943c5 2659 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2660#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2661 case KVM_CAP_ASSIGN_DEV_IRQ:
2662 case KVM_CAP_PCI_2_3:
2663#endif
018d00d2
ZX		 2664 r = 1;
2665 break;
542472b5
LV		 2666 case KVM_CAP_COALESCED_MMIO:
2667 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2668 break;
774ead3a
AK		 2669 case KVM_CAP_VAPIC:
2670 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2671 break;
f725230a 2672 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2673 r = KVM_SOFT_MAX_VCPUS;
2674 break;
2675 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2676 r = KVM_MAX_VCPUS;
2677 break;
a988b910 2678 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2679 r = KVM_USER_MEM_SLOTS;
a988b910 2680 break;
a68a6a72
MT		 2681 case KVM_CAP_PV_MMU: /* obsolete */
2682 r = 0;
2f333bcb 2683 break;
4cee4b72 2684#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2685 case KVM_CAP_IOMMU:
a1b60c1c 2686 r = iommu_present(&pci_bus_type);
62c476c7 2687 break;
4cee4b72 2688#endif
890ca9ae
HY		 2689 case KVM_CAP_MCE:
2690 r = KVM_MAX_MCE_BANKS;
2691 break;
2d5b5a66
SY		 2692 case KVM_CAP_XCRS:
2693 r = cpu_has_xsave;
2694 break;
92a1f12d
JR		 2695 case KVM_CAP_TSC_CONTROL:
2696 r = kvm_has_tsc_control;
2697 break;
4d25a066
JK		 2698 case KVM_CAP_TSC_DEADLINE_TIMER:
2699 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2700 break;
018d00d2
ZX		 2701 default:
2702 r = 0;
2703 break;
2704 }
2705 return r;
2706
2707}
2708
043405e1
CO		 2709long kvm_arch_dev_ioctl(struct file *filp,
2710 unsigned int ioctl, unsigned long arg)
2711{
2712 void __user *argp = (void __user *)arg;
2713 long r;
2714
2715 switch (ioctl) {
2716 case KVM_GET_MSR_INDEX_LIST: {
2717 struct kvm_msr_list __user *user_msr_list = argp;
2718 struct kvm_msr_list msr_list;
2719 unsigned n;
2720
2721 r = -EFAULT;
2722 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2723 goto out;
2724 n = msr_list.nmsrs;
2725 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2726 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2727 goto out;
2728 r = -E2BIG;
e125e7b6 2729 if (n < msr_list.nmsrs)
043405e1
CO		 2730 goto out;
2731 r = -EFAULT;
2732 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2733 num_msrs_to_save * sizeof(u32)))
2734 goto out;
e125e7b6 2735 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2736 &emulated_msrs,
2737 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2738 goto out;
2739 r = 0;
2740 break;
2741 }
9c15bb1d
BP		 2742 case KVM_GET_SUPPORTED_CPUID:
2743 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2744 struct kvm_cpuid2 __user *cpuid_arg = argp;
2745 struct kvm_cpuid2 cpuid;
2746
2747 r = -EFAULT;
2748 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2749 goto out;
9c15bb1d
BP		 2750
2751 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2752 ioctl);
674eea0f
AK		 2753 if (r)
2754 goto out;
2755
2756 r = -EFAULT;
2757 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2758 goto out;
2759 r = 0;
2760 break;
2761 }
890ca9ae
HY		 2762 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2763 u64 mce_cap;
2764
2765 mce_cap = KVM_MCE_CAP_SUPPORTED;
2766 r = -EFAULT;
2767 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2768 goto out;
2769 r = 0;
2770 break;
2771 }
043405e1
CO		 2772 default:
2773 r = -EINVAL;
2774 }
2775out:
2776 return r;
2777}
2778
f5f48ee1
SY		 2779static void wbinvd_ipi(void *garbage)
2780{
2781 wbinvd();
2782}
2783
2784static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2785{
e0f0bbc5 2786 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2787}
2788
313a3dc7
CO		 2789void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2790{
f5f48ee1
SY		 2791 /* Address WBINVD may be executed by guest */
2792 if (need_emulate_wbinvd(vcpu)) {
2793 if (kvm_x86_ops->has_wbinvd_exit())
2794 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2795 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2796 smp_call_function_single(vcpu->cpu,
2797 wbinvd_ipi, NULL, 1);
2798 }
2799
313a3dc7 2800 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2801
0dd6a6ed
ZA		 2802 /* Apply any externally detected TSC adjustments (due to suspend) */
2803 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2804 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2805 vcpu->arch.tsc_offset_adjustment = 0;
2806 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2807 }
8f6055cb 2808
48434c20 2809 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2810 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2811 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2812 if (tsc_delta < 0)
2813 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2814 if (check_tsc_unstable()) {
b183aa58
ZA		 2815 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2816 vcpu->arch.last_guest_tsc);
2817 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2818 vcpu->arch.tsc_catchup = 1;
c285545f 2819 }
d98d07ca
MT		 2820 /*
2821 * On a host with synchronized TSC, there is no need to update
2822 * kvmclock on vcpu->cpu migration
2823 */
2824 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2825 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2826 if (vcpu->cpu != cpu)
2827 kvm_migrate_timers(vcpu);
e48672fa 2828 vcpu->cpu = cpu;
6b7d7e76 2829 }
c9aaa895
GC		 2830
2831 accumulate_steal_time(vcpu);
2832 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2833}
2834
2835void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2836{
02daab21 2837 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2838 kvm_put_guest_fpu(vcpu);
6f526ec5 2839 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2840}
2841
313a3dc7
CO		 2842static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2843 struct kvm_lapic_state *s)
2844{
5a71785d 2845 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2846 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2847
2848 return 0;
2849}
2850
2851static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2852 struct kvm_lapic_state *s)
2853{
64eb0620 2854 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2855 update_cr8_intercept(vcpu);
313a3dc7
CO		 2856
2857 return 0;
2858}
2859
f77bc6a4
ZX		 2860static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2861 struct kvm_interrupt *irq)
2862{
02cdb50f 2863 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2864 return -EINVAL;
2865 if (irqchip_in_kernel(vcpu->kvm))
2866 return -ENXIO;
f77bc6a4 2867
66fd3f7f 2868 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2870
f77bc6a4
ZX		 2871 return 0;
2872}
2873
c4abb7c9
JK		 2874static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2875{
c4abb7c9 2876 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2877
2878 return 0;
2879}
2880
b209749f
AK		 2881static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2882 struct kvm_tpr_access_ctl *tac)
2883{
2884 if (tac->flags)
2885 return -EINVAL;
2886 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2887 return 0;
2888}
2889
890ca9ae
HY		 2890static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2891 u64 mcg_cap)
2892{
2893 int r;
2894 unsigned bank_num = mcg_cap & 0xff, bank;
2895
2896 r = -EINVAL;
a9e38c3e 2897 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2898 goto out;
2899 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2900 goto out;
2901 r = 0;
2902 vcpu->arch.mcg_cap = mcg_cap;
2903 /* Init IA32_MCG_CTL to all 1s */
2904 if (mcg_cap & MCG_CTL_P)
2905 vcpu->arch.mcg_ctl = ~(u64)0;
2906 /* Init IA32_MCi_CTL to all 1s */
2907 for (bank = 0; bank < bank_num; bank++)
2908 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2909out:
2910 return r;
2911}
2912
2913static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2914 struct kvm_x86_mce *mce)
2915{
2916 u64 mcg_cap = vcpu->arch.mcg_cap;
2917 unsigned bank_num = mcg_cap & 0xff;
2918 u64 *banks = vcpu->arch.mce_banks;
2919
2920 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2921 return -EINVAL;
2922 /*
2923 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2924 * reporting is disabled
2925 */
2926 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2927 vcpu->arch.mcg_ctl != ~(u64)0)
2928 return 0;
2929 banks += 4 * mce->bank;
2930 /*
2931 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2932 * reporting is disabled for the bank
2933 */
2934 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2935 return 0;
2936 if (mce->status & MCI_STATUS_UC) {
2937 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2938 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2939 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2940 return 0;
2941 }
2942 if (banks[1] & MCI_STATUS_VAL)
2943 mce->status |= MCI_STATUS_OVER;
2944 banks[2] = mce->addr;
2945 banks[3] = mce->misc;
2946 vcpu->arch.mcg_status = mce->mcg_status;
2947 banks[1] = mce->status;
2948 kvm_queue_exception(vcpu, MC_VECTOR);
2949 } else if (!(banks[1] & MCI_STATUS_VAL)
2950 || !(banks[1] & MCI_STATUS_UC)) {
2951 if (banks[1] & MCI_STATUS_VAL)
2952 mce->status |= MCI_STATUS_OVER;
2953 banks[2] = mce->addr;
2954 banks[3] = mce->misc;
2955 banks[1] = mce->status;
2956 } else
2957 banks[1] |= MCI_STATUS_OVER;
2958 return 0;
2959}
2960
3cfc3092
JK		 2961static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2962 struct kvm_vcpu_events *events)
2963{
7460fb4a 2964 process_nmi(vcpu);
03b82a30
JK		 2965 events->exception.injected =
2966 vcpu->arch.exception.pending &&
2967 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2968 events->exception.nr = vcpu->arch.exception.nr;
2969 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2970 events->exception.pad = 0;
3cfc3092
JK		 2971 events->exception.error_code = vcpu->arch.exception.error_code;
2972
03b82a30
JK		 2973 events->interrupt.injected =
2974 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2975 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2976 events->interrupt.soft = 0;
48005f64
JK		 2977 events->interrupt.shadow =
2978 kvm_x86_ops->get_interrupt_shadow(vcpu,
2979 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2980
2981 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2982 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2983 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2984 events->nmi.pad = 0;
3cfc3092 2985
66450a21 2986 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2987
dab4b911 2988 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2989 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2990 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2991}
2992
2993static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2994 struct kvm_vcpu_events *events)
2995{
dab4b911 2996 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2997 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2998 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2999 return -EINVAL;
3000
7460fb4a 3001 process_nmi(vcpu);
3cfc3092
JK		 3002 vcpu->arch.exception.pending = events->exception.injected;
3003 vcpu->arch.exception.nr = events->exception.nr;
3004 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3005 vcpu->arch.exception.error_code = events->exception.error_code;
3006
3007 vcpu->arch.interrupt.pending = events->interrupt.injected;
3008 vcpu->arch.interrupt.nr = events->interrupt.nr;
3009 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3010 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3011 kvm_x86_ops->set_interrupt_shadow(vcpu,
3012 events->interrupt.shadow);
3cfc3092
JK		 3013
3014 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3015 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3016 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3017 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3018
66450a21
JK		 3019 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3020 kvm_vcpu_has_lapic(vcpu))
3021 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3022
3842d135
AK		 3023 kvm_make_request(KVM_REQ_EVENT, vcpu);
3024
3cfc3092
JK		 3025 return 0;
3026}
3027
a1efbe77
JK		 3028static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3029 struct kvm_debugregs *dbgregs)
3030{
73aaf249
JK		 3031 unsigned long val;
3032
a1efbe77 3033 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3034 _kvm_get_dr(vcpu, 6, &val);
3035 dbgregs->dr6 = val;
a1efbe77
JK		 3036 dbgregs->dr7 = vcpu->arch.dr7;
3037 dbgregs->flags = 0;
97e69aa6 3038 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3039}
3040
3041static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3042 struct kvm_debugregs *dbgregs)
3043{
3044 if (dbgregs->flags)
3045 return -EINVAL;
3046
a1efbe77
JK		 3047 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3048 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3049 kvm_update_dr6(vcpu);
a1efbe77 3050 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3051 kvm_update_dr7(vcpu);
a1efbe77 3052
a1efbe77
JK		 3053 return 0;
3054}
3055
2d5b5a66
SY		 3056static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3057 struct kvm_xsave *guest_xsave)
3058{
4344ee98 3059 if (cpu_has_xsave) {
2d5b5a66
SY		 3060 memcpy(guest_xsave->region,
3061 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3062 vcpu->arch.guest_xstate_size);
3063 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3064 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3065 } else {
2d5b5a66
SY		 3066 memcpy(guest_xsave->region,
3067 &vcpu->arch.guest_fpu.state->fxsave,
3068 sizeof(struct i387_fxsave_struct));
3069 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3070 XSTATE_FPSSE;
3071 }
3072}
3073
3074static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3075 struct kvm_xsave *guest_xsave)
3076{
3077 u64 xstate_bv =
3078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3079
d7876f1b
PB		 3080 if (cpu_has_xsave) {
3081 /*
3082 * Here we allow setting states that are not present in
3083 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3084 * with old userspace.
3085 */
4ff41732 3086 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3087 return -EINVAL;
2d5b5a66 3088 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3089 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3090 } else {
2d5b5a66
SY		 3091 if (xstate_bv & ~XSTATE_FPSSE)
3092 return -EINVAL;
3093 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3094 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3095 }
3096 return 0;
3097}
3098
3099static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3100 struct kvm_xcrs *guest_xcrs)
3101{
3102 if (!cpu_has_xsave) {
3103 guest_xcrs->nr_xcrs = 0;
3104 return;
3105 }
3106
3107 guest_xcrs->nr_xcrs = 1;
3108 guest_xcrs->flags = 0;
3109 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3110 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3111}
3112
3113static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3114 struct kvm_xcrs *guest_xcrs)
3115{
3116 int i, r = 0;
3117
3118 if (!cpu_has_xsave)
3119 return -EINVAL;
3120
3121 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3122 return -EINVAL;
3123
3124 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3125 /* Only support XCR0 currently */
c67a04cb 3126 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3127 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3128 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3129 break;
3130 }
3131 if (r)
3132 r = -EINVAL;
3133 return r;
3134}
3135
1c0b28c2
EM		 3136/*
3137 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3138 * stopped by the hypervisor. This function will be called from the host only.
3139 * EINVAL is returned when the host attempts to set the flag for a guest that
3140 * does not support pv clocks.
3141 */
3142static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3143{
0b79459b 3144 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3145 return -EINVAL;
51d59c6b 3146 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3148 return 0;
3149}
3150
313a3dc7
CO		 3151long kvm_arch_vcpu_ioctl(struct file *filp,
3152 unsigned int ioctl, unsigned long arg)
3153{
3154 struct kvm_vcpu *vcpu = filp->private_data;
3155 void __user *argp = (void __user *)arg;
3156 int r;
d1ac91d8
AK		 3157 union {
3158 struct kvm_lapic_state *lapic;
3159 struct kvm_xsave *xsave;
3160 struct kvm_xcrs *xcrs;
3161 void *buffer;
3162 } u;
3163
3164 u.buffer = NULL;
313a3dc7
CO		 3165 switch (ioctl) {
3166 case KVM_GET_LAPIC: {
2204ae3c
MT		 3167 r = -EINVAL;
3168 if (!vcpu->arch.apic)
3169 goto out;
d1ac91d8 3170 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3171
b772ff36 3172 r = -ENOMEM;
d1ac91d8 3173 if (!u.lapic)
b772ff36 3174 goto out;
d1ac91d8 3175 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3176 if (r)
3177 goto out;
3178 r = -EFAULT;
d1ac91d8 3179 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3180 goto out;
3181 r = 0;
3182 break;
3183 }
3184 case KVM_SET_LAPIC: {
2204ae3c
MT		 3185 r = -EINVAL;
3186 if (!vcpu->arch.apic)
3187 goto out;
ff5c2c03 3188 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3189 if (IS_ERR(u.lapic))
3190 return PTR_ERR(u.lapic);
ff5c2c03 3191
d1ac91d8 3192 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3193 break;
3194 }
f77bc6a4
ZX		 3195 case KVM_INTERRUPT: {
3196 struct kvm_interrupt irq;
3197
3198 r = -EFAULT;
3199 if (copy_from_user(&irq, argp, sizeof irq))
3200 goto out;
3201 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3202 break;
3203 }
c4abb7c9
JK		 3204 case KVM_NMI: {
3205 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3206 break;
3207 }
313a3dc7
CO		 3208 case KVM_SET_CPUID: {
3209 struct kvm_cpuid __user *cpuid_arg = argp;
3210 struct kvm_cpuid cpuid;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3214 goto out;
3215 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3216 break;
3217 }
07716717
DK		 3218 case KVM_SET_CPUID2: {
3219 struct kvm_cpuid2 __user *cpuid_arg = argp;
3220 struct kvm_cpuid2 cpuid;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3224 goto out;
3225 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3226 cpuid_arg->entries);
07716717
DK		 3227 break;
3228 }
3229 case KVM_GET_CPUID2: {
3230 struct kvm_cpuid2 __user *cpuid_arg = argp;
3231 struct kvm_cpuid2 cpuid;
3232
3233 r = -EFAULT;
3234 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3235 goto out;
3236 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3237 cpuid_arg->entries);
07716717
DK		 3238 if (r)
3239 goto out;
3240 r = -EFAULT;
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3242 goto out;
3243 r = 0;
3244 break;
3245 }
313a3dc7
CO		 3246 case KVM_GET_MSRS:
3247 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3248 break;
3249 case KVM_SET_MSRS:
3250 r = msr_io(vcpu, argp, do_set_msr, 0);
3251 break;
b209749f
AK		 3252 case KVM_TPR_ACCESS_REPORTING: {
3253 struct kvm_tpr_access_ctl tac;
3254
3255 r = -EFAULT;
3256 if (copy_from_user(&tac, argp, sizeof tac))
3257 goto out;
3258 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3259 if (r)
3260 goto out;
3261 r = -EFAULT;
3262 if (copy_to_user(argp, &tac, sizeof tac))
3263 goto out;
3264 r = 0;
3265 break;
3266 };
b93463aa
AK		 3267 case KVM_SET_VAPIC_ADDR: {
3268 struct kvm_vapic_addr va;
3269
3270 r = -EINVAL;
3271 if (!irqchip_in_kernel(vcpu->kvm))
3272 goto out;
3273 r = -EFAULT;
3274 if (copy_from_user(&va, argp, sizeof va))
3275 goto out;
fda4e2e8 3276 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3277 break;
3278 }
890ca9ae
HY		 3279 case KVM_X86_SETUP_MCE: {
3280 u64 mcg_cap;
3281
3282 r = -EFAULT;
3283 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3284 goto out;
3285 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3286 break;
3287 }
3288 case KVM_X86_SET_MCE: {
3289 struct kvm_x86_mce mce;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&mce, argp, sizeof mce))
3293 goto out;
3294 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3295 break;
3296 }
3cfc3092
JK		 3297 case KVM_GET_VCPU_EVENTS: {
3298 struct kvm_vcpu_events events;
3299
3300 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3301
3302 r = -EFAULT;
3303 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3304 break;
3305 r = 0;
3306 break;
3307 }
3308 case KVM_SET_VCPU_EVENTS: {
3309 struct kvm_vcpu_events events;
3310
3311 r = -EFAULT;
3312 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3313 break;
3314
3315 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3316 break;
3317 }
a1efbe77
JK		 3318 case KVM_GET_DEBUGREGS: {
3319 struct kvm_debugregs dbgregs;
3320
3321 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3322
3323 r = -EFAULT;
3324 if (copy_to_user(argp, &dbgregs,
3325 sizeof(struct kvm_debugregs)))
3326 break;
3327 r = 0;
3328 break;
3329 }
3330 case KVM_SET_DEBUGREGS: {
3331 struct kvm_debugregs dbgregs;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&dbgregs, argp,
3335 sizeof(struct kvm_debugregs)))
3336 break;
3337
3338 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3339 break;
3340 }
2d5b5a66 3341 case KVM_GET_XSAVE: {
d1ac91d8 3342 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3343 r = -ENOMEM;
d1ac91d8 3344 if (!u.xsave)
2d5b5a66
SY		 3345 break;
3346
d1ac91d8 3347 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3348
3349 r = -EFAULT;
d1ac91d8 3350 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3351 break;
3352 r = 0;
3353 break;
3354 }
3355 case KVM_SET_XSAVE: {
ff5c2c03 3356 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3357 if (IS_ERR(u.xsave))
3358 return PTR_ERR(u.xsave);
2d5b5a66 3359
d1ac91d8 3360 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3361 break;
3362 }
3363 case KVM_GET_XCRS: {
d1ac91d8 3364 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3365 r = -ENOMEM;
d1ac91d8 3366 if (!u.xcrs)
2d5b5a66
SY		 3367 break;
3368
d1ac91d8 3369 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3370
3371 r = -EFAULT;
d1ac91d8 3372 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3373 sizeof(struct kvm_xcrs)))
3374 break;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_XCRS: {
ff5c2c03 3379 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3380 if (IS_ERR(u.xcrs))
3381 return PTR_ERR(u.xcrs);
2d5b5a66 3382
d1ac91d8 3383 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3384 break;
3385 }
92a1f12d
JR		 3386 case KVM_SET_TSC_KHZ: {
3387 u32 user_tsc_khz;
3388
3389 r = -EINVAL;
92a1f12d
JR		 3390 user_tsc_khz = (u32)arg;
3391
3392 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3393 goto out;
3394
cc578287
ZA		 3395 if (user_tsc_khz == 0)
3396 user_tsc_khz = tsc_khz;
3397
3398 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3399
3400 r = 0;
3401 goto out;
3402 }
3403 case KVM_GET_TSC_KHZ: {
cc578287 3404 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3405 goto out;
3406 }
1c0b28c2
EM		 3407 case KVM_KVMCLOCK_CTRL: {
3408 r = kvm_set_guest_paused(vcpu);
3409 goto out;
3410 }
313a3dc7
CO		 3411 default:
3412 r = -EINVAL;
3413 }
3414out:
d1ac91d8 3415 kfree(u.buffer);
313a3dc7
CO		 3416 return r;
3417}
3418
5b1c1493
CO		 3419int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3420{
3421 return VM_FAULT_SIGBUS;
3422}
3423
1fe779f8
CO		 3424static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3425{
3426 int ret;
3427
3428 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3429 return -EINVAL;
1fe779f8
CO		 3430 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3431 return ret;
3432}
3433
b927a3ce
SY		 3434static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3435 u64 ident_addr)
3436{
3437 kvm->arch.ept_identity_map_addr = ident_addr;
3438 return 0;
3439}
3440
1fe779f8
CO		 3441static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3442 u32 kvm_nr_mmu_pages)
3443{
3444 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3445 return -EINVAL;
3446
79fac95e 3447 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3448
3449 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3450 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3451
79fac95e 3452 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3453 return 0;
3454}
3455
3456static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3457{
39de71ec 3458 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3459}
3460
1fe779f8
CO		 3461static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3462{
3463 int r;
3464
3465 r = 0;
3466 switch (chip->chip_id) {
3467 case KVM_IRQCHIP_PIC_MASTER:
3468 memcpy(&chip->chip.pic,
3469 &pic_irqchip(kvm)->pics[0],
3470 sizeof(struct kvm_pic_state));
3471 break;
3472 case KVM_IRQCHIP_PIC_SLAVE:
3473 memcpy(&chip->chip.pic,
3474 &pic_irqchip(kvm)->pics[1],
3475 sizeof(struct kvm_pic_state));
3476 break;
3477 case KVM_IRQCHIP_IOAPIC:
eba0226b 3478 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3479 break;
3480 default:
3481 r = -EINVAL;
3482 break;
3483 }
3484 return r;
3485}
3486
3487static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3488{
3489 int r;
3490
3491 r = 0;
3492 switch (chip->chip_id) {
3493 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3494 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3495 memcpy(&pic_irqchip(kvm)->pics[0],
3496 &chip->chip.pic,
3497 sizeof(struct kvm_pic_state));
f4f51050 3498 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3499 break;
3500 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3501 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 memcpy(&pic_irqchip(kvm)->pics[1],
3503 &chip->chip.pic,
3504 sizeof(struct kvm_pic_state));
f4f51050 3505 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3506 break;
3507 case KVM_IRQCHIP_IOAPIC:
eba0226b 3508 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3509 break;
3510 default:
3511 r = -EINVAL;
3512 break;
3513 }
3514 kvm_pic_update_irq(pic_irqchip(kvm));
3515 return r;
3516}
3517
e0f63cb9
SY		 3518static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3519{
3520 int r = 0;
3521
894a9c55 3522 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3523 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3524 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3525 return r;
3526}
3527
3528static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3529{
3530 int r = 0;
3531
894a9c55 3532 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3533 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3534 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3536 return r;
3537}
3538
3539static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3540{
3541 int r = 0;
3542
3543 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3544 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3545 sizeof(ps->channels));
3546 ps->flags = kvm->arch.vpit->pit_state.flags;
3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3548 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3549 return r;
3550}
3551
3552static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3553{
3554 int r = 0, start = 0;
3555 u32 prev_legacy, cur_legacy;
3556 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3557 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3558 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 if (!prev_legacy && cur_legacy)
3560 start = 1;
3561 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3562 sizeof(kvm->arch.vpit->pit_state.channels));
3563 kvm->arch.vpit->pit_state.flags = ps->flags;
3564 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3566 return r;
3567}
3568
52d939a0
MT		 3569static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3570 struct kvm_reinject_control *control)
3571{
3572 if (!kvm->arch.vpit)
3573 return -ENXIO;
894a9c55 3574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3575 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3577 return 0;
3578}
3579
95d4c16c 3580/**
60c34612
TY		 3581 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3582 * @kvm: kvm instance
3583 * @log: slot id and address to which we copy the log
95d4c16c 3584 *
60c34612
TY		 3585 * We need to keep it in mind that VCPU threads can write to the bitmap
3586 * concurrently. So, to avoid losing data, we keep the following order for
3587 * each bit:
95d4c16c 3588 *
60c34612
TY		 3589 * 1. Take a snapshot of the bit and clear it if needed.
3590 * 2. Write protect the corresponding page.
3591 * 3. Flush TLB's if needed.
3592 * 4. Copy the snapshot to the userspace.
95d4c16c 3593 *
60c34612
TY		 3594 * Between 2 and 3, the guest may write to the page using the remaining TLB
3595 * entry. This is not a problem because the page will be reported dirty at
3596 * step 4 using the snapshot taken before and step 3 ensures that successive
3597 * writes will be logged for the next call.
5bb064dc 3598 */
60c34612 3599int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3600{
7850ac54 3601 int r;
5bb064dc 3602 struct kvm_memory_slot *memslot;
60c34612
TY		 3603 unsigned long n, i;
3604 unsigned long *dirty_bitmap;
3605 unsigned long *dirty_bitmap_buffer;
3606 bool is_dirty = false;
5bb064dc 3607
79fac95e 3608 mutex_lock(&kvm->slots_lock);
5bb064dc 3609
b050b015 3610 r = -EINVAL;
bbacc0c1 3611 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3612 goto out;
3613
28a37544 3614 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3615
3616 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3617 r = -ENOENT;
60c34612 3618 if (!dirty_bitmap)
b050b015
MT		 3619 goto out;
3620
87bf6e7d 3621 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3622
60c34612
TY		 3623 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3624 memset(dirty_bitmap_buffer, 0, n);
b050b015 3625
60c34612 3626 spin_lock(&kvm->mmu_lock);
b050b015 3627
60c34612
TY		 3628 for (i = 0; i < n / sizeof(long); i++) {
3629 unsigned long mask;
3630 gfn_t offset;
cdfca7b3 3631
60c34612
TY		 3632 if (!dirty_bitmap[i])
3633 continue;
b050b015 3634
60c34612 3635 is_dirty = true;
914ebccd 3636
60c34612
TY		 3637 mask = xchg(&dirty_bitmap[i], 0);
3638 dirty_bitmap_buffer[i] = mask;
edde99ce 3639
60c34612
TY		 3640 offset = i * BITS_PER_LONG;
3641 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3642 }
60c34612
TY		 3643
3644 spin_unlock(&kvm->mmu_lock);
3645
198c74f4
XG		 3646 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3647 lockdep_assert_held(&kvm->slots_lock);
3648
3649 /*
3650 * All the TLBs can be flushed out of mmu lock, see the comments in
3651 * kvm_mmu_slot_remove_write_access().
3652 */
3653 if (is_dirty)
3654 kvm_flush_remote_tlbs(kvm);
3655
60c34612
TY		 3656 r = -EFAULT;
3657 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3658 goto out;
b050b015 3659
5bb064dc
ZX		 3660 r = 0;
3661out:
79fac95e 3662 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3663 return r;
3664}
3665
aa2fbe6d
YZ		 3666int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3667 bool line_status)
23d43cf9
CD		 3668{
3669 if (!irqchip_in_kernel(kvm))
3670 return -ENXIO;
3671
3672 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3673 irq_event->irq, irq_event->level,
3674 line_status);
23d43cf9
CD		 3675 return 0;
3676}
3677
1fe779f8
CO		 3678long kvm_arch_vm_ioctl(struct file *filp,
3679 unsigned int ioctl, unsigned long arg)
3680{
3681 struct kvm *kvm = filp->private_data;
3682 void __user *argp = (void __user *)arg;
367e1319 3683 int r = -ENOTTY;
f0d66275
DH		 3684 /*
3685 * This union makes it completely explicit to gcc-3.x
3686 * that these two variables' stack usage should be
3687 * combined, not added together.
3688 */
3689 union {
3690 struct kvm_pit_state ps;
e9f42757 3691 struct kvm_pit_state2 ps2;
c5ff41ce 3692 struct kvm_pit_config pit_config;
f0d66275 3693 } u;
1fe779f8
CO		 3694
3695 switch (ioctl) {
3696 case KVM_SET_TSS_ADDR:
3697 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3698 break;
b927a3ce
SY		 3699 case KVM_SET_IDENTITY_MAP_ADDR: {
3700 u64 ident_addr;
3701
3702 r = -EFAULT;
3703 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3704 goto out;
3705 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3706 break;
3707 }
1fe779f8
CO		 3708 case KVM_SET_NR_MMU_PAGES:
3709 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3710 break;
3711 case KVM_GET_NR_MMU_PAGES:
3712 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3713 break;
3ddea128
MT		 3714 case KVM_CREATE_IRQCHIP: {
3715 struct kvm_pic *vpic;
3716
3717 mutex_lock(&kvm->lock);
3718 r = -EEXIST;
3719 if (kvm->arch.vpic)
3720 goto create_irqchip_unlock;
3e515705
AK		 3721 r = -EINVAL;
3722 if (atomic_read(&kvm->online_vcpus))
3723 goto create_irqchip_unlock;
1fe779f8 3724 r = -ENOMEM;
3ddea128
MT		 3725 vpic = kvm_create_pic(kvm);
3726 if (vpic) {
1fe779f8
CO		 3727 r = kvm_ioapic_init(kvm);
3728 if (r) {
175504cd 3729 mutex_lock(&kvm->slots_lock);
72bb2fcd 3730 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3731 &vpic->dev_master);
3732 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3733 &vpic->dev_slave);
3734 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3735 &vpic->dev_eclr);
175504cd 3736 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3737 kfree(vpic);
3738 goto create_irqchip_unlock;
1fe779f8
CO		 3739 }
3740 } else
3ddea128
MT		 3741 goto create_irqchip_unlock;
3742 smp_wmb();
3743 kvm->arch.vpic = vpic;
3744 smp_wmb();
399ec807
AK		 3745 r = kvm_setup_default_irq_routing(kvm);
3746 if (r) {
175504cd 3747 mutex_lock(&kvm->slots_lock);
3ddea128 3748 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3749 kvm_ioapic_destroy(kvm);
3750 kvm_destroy_pic(kvm);
3ddea128 3751 mutex_unlock(&kvm->irq_lock);
175504cd 3752 mutex_unlock(&kvm->slots_lock);
399ec807 3753 }
3ddea128
MT		 3754 create_irqchip_unlock:
3755 mutex_unlock(&kvm->lock);
1fe779f8 3756 break;
3ddea128 3757 }
7837699f 3758 case KVM_CREATE_PIT:
c5ff41ce
JK		 3759 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3760 goto create_pit;
3761 case KVM_CREATE_PIT2:
3762 r = -EFAULT;
3763 if (copy_from_user(&u.pit_config, argp,
3764 sizeof(struct kvm_pit_config)))
3765 goto out;
3766 create_pit:
79fac95e 3767 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3768 r = -EEXIST;
3769 if (kvm->arch.vpit)
3770 goto create_pit_unlock;
7837699f 3771 r = -ENOMEM;
c5ff41ce 3772 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3773 if (kvm->arch.vpit)
3774 r = 0;
269e05e4 3775 create_pit_unlock:
79fac95e 3776 mutex_unlock(&kvm->slots_lock);
7837699f 3777 break;
1fe779f8
CO		 3778 case KVM_GET_IRQCHIP: {
3779 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3780 struct kvm_irqchip *chip;
1fe779f8 3781
ff5c2c03
SL		 3782 chip = memdup_user(argp, sizeof(*chip));
3783 if (IS_ERR(chip)) {
3784 r = PTR_ERR(chip);
1fe779f8 3785 goto out;
ff5c2c03
SL		 3786 }
3787
1fe779f8
CO		 3788 r = -ENXIO;
3789 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3790 goto get_irqchip_out;
3791 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3792 if (r)
f0d66275 3793 goto get_irqchip_out;
1fe779f8 3794 r = -EFAULT;
f0d66275
DH		 3795 if (copy_to_user(argp, chip, sizeof *chip))
3796 goto get_irqchip_out;
1fe779f8 3797 r = 0;
f0d66275
DH		 3798 get_irqchip_out:
3799 kfree(chip);
1fe779f8
CO		 3800 break;
3801 }
3802 case KVM_SET_IRQCHIP: {
3803 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3804 struct kvm_irqchip *chip;
1fe779f8 3805
ff5c2c03
SL		 3806 chip = memdup_user(argp, sizeof(*chip));
3807 if (IS_ERR(chip)) {
3808 r = PTR_ERR(chip);
1fe779f8 3809 goto out;
ff5c2c03
SL		 3810 }
3811
1fe779f8
CO		 3812 r = -ENXIO;
3813 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3814 goto set_irqchip_out;
3815 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3816 if (r)
f0d66275 3817 goto set_irqchip_out;
1fe779f8 3818 r = 0;
f0d66275
DH		 3819 set_irqchip_out:
3820 kfree(chip);
1fe779f8
CO		 3821 break;
3822 }
e0f63cb9 3823 case KVM_GET_PIT: {
e0f63cb9 3824 r = -EFAULT;
f0d66275 3825 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3826 goto out;
3827 r = -ENXIO;
3828 if (!kvm->arch.vpit)
3829 goto out;
f0d66275 3830 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3831 if (r)
3832 goto out;
3833 r = -EFAULT;
f0d66275 3834 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3835 goto out;
3836 r = 0;
3837 break;
3838 }
3839 case KVM_SET_PIT: {
e0f63cb9 3840 r = -EFAULT;
f0d66275 3841 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3842 goto out;
3843 r = -ENXIO;
3844 if (!kvm->arch.vpit)
3845 goto out;
f0d66275 3846 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3847 break;
3848 }
e9f42757
BK		 3849 case KVM_GET_PIT2: {
3850 r = -ENXIO;
3851 if (!kvm->arch.vpit)
3852 goto out;
3853 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3854 if (r)
3855 goto out;
3856 r = -EFAULT;
3857 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3858 goto out;
3859 r = 0;
3860 break;
3861 }
3862 case KVM_SET_PIT2: {
3863 r = -EFAULT;
3864 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3865 goto out;
3866 r = -ENXIO;
3867 if (!kvm->arch.vpit)
3868 goto out;
3869 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3870 break;
3871 }
52d939a0
MT		 3872 case KVM_REINJECT_CONTROL: {
3873 struct kvm_reinject_control control;
3874 r = -EFAULT;
3875 if (copy_from_user(&control, argp, sizeof(control)))
3876 goto out;
3877 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3878 break;
3879 }
ffde22ac
ES		 3880 case KVM_XEN_HVM_CONFIG: {
3881 r = -EFAULT;
3882 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3883 sizeof(struct kvm_xen_hvm_config)))
3884 goto out;
3885 r = -EINVAL;
3886 if (kvm->arch.xen_hvm_config.flags)
3887 goto out;
3888 r = 0;
3889 break;
3890 }
afbcf7ab 3891 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3892 struct kvm_clock_data user_ns;
3893 u64 now_ns;
3894 s64 delta;
3895
3896 r = -EFAULT;
3897 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3898 goto out;
3899
3900 r = -EINVAL;
3901 if (user_ns.flags)
3902 goto out;
3903
3904 r = 0;
395c6b0a 3905 local_irq_disable();
759379dd 3906 now_ns = get_kernel_ns();
afbcf7ab 3907 delta = user_ns.clock - now_ns;
395c6b0a 3908 local_irq_enable();
afbcf7ab 3909 kvm->arch.kvmclock_offset = delta;
2e762ff7 3910 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3911 break;
3912 }
3913 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3914 struct kvm_clock_data user_ns;
3915 u64 now_ns;
3916
395c6b0a 3917 local_irq_disable();
759379dd 3918 now_ns = get_kernel_ns();
afbcf7ab 3919 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3920 local_irq_enable();
afbcf7ab 3921 user_ns.flags = 0;
97e69aa6 3922 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3923
3924 r = -EFAULT;
3925 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3926 goto out;
3927 r = 0;
3928 break;
3929 }
3930
1fe779f8
CO		 3931 default:
3932 ;
3933 }
3934out:
3935 return r;
3936}
3937
a16b043c 3938static void kvm_init_msr_list(void)
043405e1
CO		 3939{
3940 u32 dummy[2];
3941 unsigned i, j;
3942
e3267cbb
GC		 3943 /* skip the first msrs in the list. KVM-specific */
3944 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3945 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3946 continue;
93c4adc7
PB		 3947
3948 /*
3949 * Even MSRs that are valid in the host may not be exposed
3950 * to the guests in some cases. We could work around this
3951 * in VMX with the generic MSR save/load machinery, but it
3952 * is not really worthwhile since it will really only
3953 * happen with nested virtualization.
3954 */
3955 switch (msrs_to_save[i]) {
3956 case MSR_IA32_BNDCFGS:
3957 if (!kvm_x86_ops->mpx_supported())
3958 continue;
3959 break;
3960 default:
3961 break;
3962 }
3963
043405e1
CO		 3964 if (j < i)
3965 msrs_to_save[j] = msrs_to_save[i];
3966 j++;
3967 }
3968 num_msrs_to_save = j;
3969}
3970
bda9020e
MT		 3971static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3972 const void *v)
bbd9b64e 3973{
70252a10
AK		 3974 int handled = 0;
3975 int n;
3976
3977 do {
3978 n = min(len, 8);
3979 if (!(vcpu->arch.apic &&
3980 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3981 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3982 break;
3983 handled += n;
3984 addr += n;
3985 len -= n;
3986 v += n;
3987 } while (len);
bbd9b64e 3988
70252a10 3989 return handled;
bbd9b64e
CO		 3990}
3991
bda9020e 3992static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3993{
70252a10
AK		 3994 int handled = 0;
3995 int n;
3996
3997 do {
3998 n = min(len, 8);
3999 if (!(vcpu->arch.apic &&
4000 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4001 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4002 break;
4003 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4004 handled += n;
4005 addr += n;
4006 len -= n;
4007 v += n;
4008 } while (len);
bbd9b64e 4009
70252a10 4010 return handled;
bbd9b64e
CO		 4011}
4012
2dafc6c2
GN		 4013static void kvm_set_segment(struct kvm_vcpu *vcpu,
4014 struct kvm_segment *var, int seg)
4015{
4016 kvm_x86_ops->set_segment(vcpu, var, seg);
4017}
4018
4019void kvm_get_segment(struct kvm_vcpu *vcpu,
4020 struct kvm_segment *var, int seg)
4021{
4022 kvm_x86_ops->get_segment(vcpu, var, seg);
4023}
4024
e459e322 4025gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4026{
4027 gpa_t t_gpa;
ab9ae313 4028 struct x86_exception exception;
02f59dc9
JR		 4029
4030 BUG_ON(!mmu_is_nested(vcpu));
4031
4032 /* NPT walks are always user-walks */
4033 access |= PFERR_USER_MASK;
ab9ae313 4034 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4035
4036 return t_gpa;
4037}
4038
ab9ae313
AK		 4039gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4040 struct x86_exception *exception)
1871c602
GN		 4041{
4042 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4044}
4045
ab9ae313
AK		 4046 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4047 struct x86_exception *exception)
1871c602
GN		 4048{
4049 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4050 access |= PFERR_FETCH_MASK;
ab9ae313 4051 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4052}
4053
ab9ae313
AK		 4054gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4055 struct x86_exception *exception)
1871c602
GN		 4056{
4057 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4058 access |= PFERR_WRITE_MASK;
ab9ae313 4059 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4060}
4061
4062/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4063gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4064 struct x86_exception *exception)
1871c602 4065{
ab9ae313 4066 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4067}
4068
4069static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4070 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4071 struct x86_exception *exception)
bbd9b64e
CO		 4072{
4073 void *data = val;
10589a46 4074 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4075
4076 while (bytes) {
14dfe855 4077 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4078 exception);
bbd9b64e 4079 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4080 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4081 int ret;
4082
bcc55cba 4083 if (gpa == UNMAPPED_GVA)
ab9ae313 4084 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4085 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4086 if (ret < 0) {
c3cd7ffa 4087 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4088 goto out;
4089 }
bbd9b64e 4090
77c2002e
IE		 4091 bytes -= toread;
4092 data += toread;
4093 addr += toread;
bbd9b64e 4094 }
10589a46 4095out:
10589a46 4096 return r;
bbd9b64e 4097}
77c2002e 4098
1871c602 4099/* used for instruction fetching */
0f65dd70
AK		 4100static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4101 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4102 struct x86_exception *exception)
1871c602 4103{
0f65dd70 4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4106
1871c602 4107 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4108 access | PFERR_FETCH_MASK,
4109 exception);
1871c602
GN		 4110}
4111
064aea77 4112int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4113 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4114 struct x86_exception *exception)
1871c602 4115{
0f65dd70 4116 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4118
1871c602 4119 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4120 exception);
1871c602 4121}
064aea77 4122EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4123
0f65dd70
AK		 4124static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4125 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4126 struct x86_exception *exception)
1871c602 4127{
0f65dd70 4128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4129 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4130}
4131
6a4d7550 4132int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4133 gva_t addr, void *val,
2dafc6c2 4134 unsigned int bytes,
bcc55cba 4135 struct x86_exception *exception)
77c2002e 4136{
0f65dd70 4137 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4138 void *data = val;
4139 int r = X86EMUL_CONTINUE;
4140
4141 while (bytes) {
14dfe855
JR		 4142 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4143 PFERR_WRITE_MASK,
ab9ae313 4144 exception);
77c2002e
IE		 4145 unsigned offset = addr & (PAGE_SIZE-1);
4146 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4147 int ret;
4148
bcc55cba 4149 if (gpa == UNMAPPED_GVA)
ab9ae313 4150 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4151 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4152 if (ret < 0) {
c3cd7ffa 4153 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4154 goto out;
4155 }
4156
4157 bytes -= towrite;
4158 data += towrite;
4159 addr += towrite;
4160 }
4161out:
4162 return r;
4163}
6a4d7550 4164EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4165
af7cc7d1
XG		 4166static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4167 gpa_t *gpa, struct x86_exception *exception,
4168 bool write)
4169{
97d64b78
AK		 4170 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4171 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4172
97d64b78 4173 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4174 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4175 vcpu->arch.access, access)) {
bebb106a
XG		 4176 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4177 (gva & (PAGE_SIZE - 1));
4f022648 4178 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4179 return 1;
4180 }
4181
af7cc7d1
XG		 4182 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4183
4184 if (*gpa == UNMAPPED_GVA)
4185 return -1;
4186
4187 /* For APIC access vmexit */
4188 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4189 return 1;
4190
4f022648
XG		 4191 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4192 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4193 return 1;
4f022648 4194 }
bebb106a 4195
af7cc7d1
XG		 4196 return 0;
4197}
4198
3200f405 4199int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4200 const void *val, int bytes)
bbd9b64e
CO		 4201{
4202 int ret;
4203
4204 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4205 if (ret < 0)
bbd9b64e 4206 return 0;
f57f2ef5 4207 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4208 return 1;
4209}
4210
77d197b2
XG		 4211struct read_write_emulator_ops {
4212 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4213 int bytes);
4214 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215 void *val, int bytes);
4216 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217 int bytes, void *val);
4218 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 void *val, int bytes);
4220 bool write;
4221};
4222
4223static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4224{
4225 if (vcpu->mmio_read_completed) {
77d197b2 4226 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4227 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4228 vcpu->mmio_read_completed = 0;
4229 return 1;
4230 }
4231
4232 return 0;
4233}
4234
4235static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4236 void *val, int bytes)
4237{
4238 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4239}
4240
4241static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4242 void *val, int bytes)
4243{
4244 return emulator_write_phys(vcpu, gpa, val, bytes);
4245}
4246
4247static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4248{
4249 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4250 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4251}
4252
4253static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4254 void *val, int bytes)
4255{
4256 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4257 return X86EMUL_IO_NEEDED;
4258}
4259
4260static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4261 void *val, int bytes)
4262{
f78146b0
AK		 4263 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4264
87da7e66 4265 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4266 return X86EMUL_CONTINUE;
4267}
4268
0fbe9b0b 4269static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4270 .read_write_prepare = read_prepare,
4271 .read_write_emulate = read_emulate,
4272 .read_write_mmio = vcpu_mmio_read,
4273 .read_write_exit_mmio = read_exit_mmio,
4274};
4275
0fbe9b0b 4276static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4277 .read_write_emulate = write_emulate,
4278 .read_write_mmio = write_mmio,
4279 .read_write_exit_mmio = write_exit_mmio,
4280 .write = true,
4281};
4282
22388a3c
XG		 4283static int emulator_read_write_onepage(unsigned long addr, void *val,
4284 unsigned int bytes,
4285 struct x86_exception *exception,
4286 struct kvm_vcpu *vcpu,
0fbe9b0b 4287 const struct read_write_emulator_ops *ops)
bbd9b64e 4288{
af7cc7d1
XG		 4289 gpa_t gpa;
4290 int handled, ret;
22388a3c 4291 bool write = ops->write;
f78146b0 4292 struct kvm_mmio_fragment *frag;
10589a46 4293
22388a3c 4294 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4295
af7cc7d1 4296 if (ret < 0)
bbd9b64e 4297 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4298
4299 /* For APIC access vmexit */
af7cc7d1 4300 if (ret)
bbd9b64e
CO		 4301 goto mmio;
4302
22388a3c 4303 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4304 return X86EMUL_CONTINUE;
4305
4306mmio:
4307 /*
4308 * Is this MMIO handled locally?
4309 */
22388a3c 4310 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4311 if (handled == bytes)
bbd9b64e 4312 return X86EMUL_CONTINUE;
bbd9b64e 4313
70252a10
AK		 4314 gpa += handled;
4315 bytes -= handled;
4316 val += handled;
4317
87da7e66
XG		 4318 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4319 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4320 frag->gpa = gpa;
4321 frag->data = val;
4322 frag->len = bytes;
f78146b0 4323 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4324}
4325
22388a3c
XG		 4326int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4327 void *val, unsigned int bytes,
4328 struct x86_exception *exception,
0fbe9b0b 4329 const struct read_write_emulator_ops *ops)
bbd9b64e 4330{
0f65dd70 4331 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4332 gpa_t gpa;
4333 int rc;
4334
4335 if (ops->read_write_prepare &&
4336 ops->read_write_prepare(vcpu, val, bytes))
4337 return X86EMUL_CONTINUE;
4338
4339 vcpu->mmio_nr_fragments = 0;
0f65dd70 4340
bbd9b64e
CO		 4341 /* Crossing a page boundary? */
4342 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4343 int now;
bbd9b64e
CO		 4344
4345 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4346 rc = emulator_read_write_onepage(addr, val, now, exception,
4347 vcpu, ops);
4348
bbd9b64e
CO		 4349 if (rc != X86EMUL_CONTINUE)
4350 return rc;
4351 addr += now;
4352 val += now;
4353 bytes -= now;
4354 }
22388a3c 4355
f78146b0
AK		 4356 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4357 vcpu, ops);
4358 if (rc != X86EMUL_CONTINUE)
4359 return rc;
4360
4361 if (!vcpu->mmio_nr_fragments)
4362 return rc;
4363
4364 gpa = vcpu->mmio_fragments[0].gpa;
4365
4366 vcpu->mmio_needed = 1;
4367 vcpu->mmio_cur_fragment = 0;
4368
87da7e66 4369 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4370 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4371 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4372 vcpu->run->mmio.phys_addr = gpa;
4373
4374 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4375}
4376
4377static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4378 unsigned long addr,
4379 void *val,
4380 unsigned int bytes,
4381 struct x86_exception *exception)
4382{
4383 return emulator_read_write(ctxt, addr, val, bytes,
4384 exception, &read_emultor);
4385}
4386
4387int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4388 unsigned long addr,
4389 const void *val,
4390 unsigned int bytes,
4391 struct x86_exception *exception)
4392{
4393 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4394 exception, &write_emultor);
bbd9b64e 4395}
bbd9b64e 4396
daea3e73
AK		 4397#define CMPXCHG_TYPE(t, ptr, old, new) \
4398 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4399
4400#ifdef CONFIG_X86_64
4401# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4402#else
4403# define CMPXCHG64(ptr, old, new) \
9749a6c0 4404 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4405#endif
4406
0f65dd70
AK		 4407static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4408 unsigned long addr,
bbd9b64e
CO		 4409 const void *old,
4410 const void *new,
4411 unsigned int bytes,
0f65dd70 4412 struct x86_exception *exception)
bbd9b64e 4413{
0f65dd70 4414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4415 gpa_t gpa;
4416 struct page *page;
4417 char *kaddr;
4418 bool exchanged;
2bacc55c 4419
daea3e73
AK		 4420 /* guests cmpxchg8b have to be emulated atomically */
4421 if (bytes > 8 || (bytes & (bytes - 1)))
4422 goto emul_write;
10589a46 4423
daea3e73 4424 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4425
daea3e73
AK		 4426 if (gpa == UNMAPPED_GVA ||
4427 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4428 goto emul_write;
2bacc55c 4429
daea3e73
AK		 4430 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4431 goto emul_write;
72dc67a6 4432
daea3e73 4433 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4434 if (is_error_page(page))
c19b8bd6 4435 goto emul_write;
72dc67a6 4436
8fd75e12 4437 kaddr = kmap_atomic(page);
daea3e73
AK		 4438 kaddr += offset_in_page(gpa);
4439 switch (bytes) {
4440 case 1:
4441 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4442 break;
4443 case 2:
4444 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4445 break;
4446 case 4:
4447 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4448 break;
4449 case 8:
4450 exchanged = CMPXCHG64(kaddr, old, new);
4451 break;
4452 default:
4453 BUG();
2bacc55c 4454 }
8fd75e12 4455 kunmap_atomic(kaddr);
daea3e73
AK		 4456 kvm_release_page_dirty(page);
4457
4458 if (!exchanged)
4459 return X86EMUL_CMPXCHG_FAILED;
4460
d3714010 4461 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4462 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4463
4464 return X86EMUL_CONTINUE;
4a5f48f6 4465
3200f405 4466emul_write:
daea3e73 4467 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4468
0f65dd70 4469 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4470}
4471
cf8f70bf
GN		 4472static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4473{
4474 /* TODO: String I/O for in kernel device */
4475 int r;
4476
4477 if (vcpu->arch.pio.in)
4478 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4479 vcpu->arch.pio.size, pd);
4480 else
4481 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4482 vcpu->arch.pio.port, vcpu->arch.pio.size,
4483 pd);
4484 return r;
4485}
4486
6f6fbe98
XG		 4487static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4488 unsigned short port, void *val,
4489 unsigned int count, bool in)
cf8f70bf 4490{
cf8f70bf 4491 vcpu->arch.pio.port = port;
6f6fbe98 4492 vcpu->arch.pio.in = in;
7972995b 4493 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4494 vcpu->arch.pio.size = size;
4495
4496 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4497 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4498 return 1;
4499 }
4500
4501 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4502 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4503 vcpu->run->io.size = size;
4504 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4505 vcpu->run->io.count = count;
4506 vcpu->run->io.port = port;
4507
4508 return 0;
4509}
4510
6f6fbe98
XG		 4511static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4512 int size, unsigned short port, void *val,
4513 unsigned int count)
cf8f70bf 4514{
ca1d4a9e 4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4516 int ret;
ca1d4a9e 4517
6f6fbe98
XG		 4518 if (vcpu->arch.pio.count)
4519 goto data_avail;
cf8f70bf 4520
6f6fbe98
XG		 4521 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4522 if (ret) {
4523data_avail:
4524 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4525 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4526 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4527 return 1;
4528 }
4529
cf8f70bf
GN		 4530 return 0;
4531}
4532
6f6fbe98
XG		 4533static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4534 int size, unsigned short port,
4535 const void *val, unsigned int count)
4536{
4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4538
4539 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4540 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4541 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4542}
4543
bbd9b64e
CO		 4544static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4545{
4546 return kvm_x86_ops->get_segment_base(vcpu, seg);
4547}
4548
3cb16fe7 4549static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4550{
3cb16fe7 4551 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4552}
4553
f5f48ee1
SY		 4554int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4555{
4556 if (!need_emulate_wbinvd(vcpu))
4557 return X86EMUL_CONTINUE;
4558
4559 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4560 int cpu = get_cpu();
4561
4562 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4563 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4564 wbinvd_ipi, NULL, 1);
2eec7343 4565 put_cpu();
f5f48ee1 4566 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4567 } else
4568 wbinvd();
f5f48ee1
SY		 4569 return X86EMUL_CONTINUE;
4570}
4571EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4572
bcaf5cc5
AK		 4573static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4574{
4575 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4576}
4577
717746e3 4578int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4579{
717746e3 4580 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4581}
4582
717746e3 4583int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4584{
338dbc97 4585
717746e3 4586 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4587}
4588
52a46617 4589static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4590{
52a46617 4591 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4592}
4593
717746e3 4594static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4595{
717746e3 4596 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4597 unsigned long value;
4598
4599 switch (cr) {
4600 case 0:
4601 value = kvm_read_cr0(vcpu);
4602 break;
4603 case 2:
4604 value = vcpu->arch.cr2;
4605 break;
4606 case 3:
9f8fe504 4607 value = kvm_read_cr3(vcpu);
52a46617
GN		 4608 break;
4609 case 4:
4610 value = kvm_read_cr4(vcpu);
4611 break;
4612 case 8:
4613 value = kvm_get_cr8(vcpu);
4614 break;
4615 default:
a737f256 4616 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4617 return 0;
4618 }
4619
4620 return value;
4621}
4622
717746e3 4623static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4624{
717746e3 4625 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4626 int res = 0;
4627
52a46617
GN		 4628 switch (cr) {
4629 case 0:
49a9b07e 4630 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4631 break;
4632 case 2:
4633 vcpu->arch.cr2 = val;
4634 break;
4635 case 3:
2390218b 4636 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4637 break;
4638 case 4:
a83b29c6 4639 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4640 break;
4641 case 8:
eea1cff9 4642 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4643 break;
4644 default:
a737f256 4645 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4646 res = -1;
52a46617 4647 }
0f12244f
GN		 4648
4649 return res;
52a46617
GN		 4650}
4651
717746e3 4652static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4653{
717746e3 4654 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4655}
4656
4bff1e86 4657static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4658{
4bff1e86 4659 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4660}
4661
4bff1e86 4662static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4663{
4bff1e86 4664 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4665}
4666
1ac9d0cf
AK		 4667static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4668{
4669 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4670}
4671
4672static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4673{
4674 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4675}
4676
4bff1e86
AK		 4677static unsigned long emulator_get_cached_segment_base(
4678 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4679{
4bff1e86 4680 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4681}
4682
1aa36616
AK		 4683static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4684 struct desc_struct *desc, u32 *base3,
4685 int seg)
2dafc6c2
GN		 4686{
4687 struct kvm_segment var;
4688
4bff1e86 4689 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4690 *selector = var.selector;
2dafc6c2 4691
378a8b09
GN		 4692 if (var.unusable) {
4693 memset(desc, 0, sizeof(*desc));
2dafc6c2 4694 return false;
378a8b09 4695 }
2dafc6c2
GN		 4696
4697 if (var.g)
4698 var.limit >>= 12;
4699 set_desc_limit(desc, var.limit);
4700 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4701#ifdef CONFIG_X86_64
4702 if (base3)
4703 *base3 = var.base >> 32;
4704#endif
2dafc6c2
GN		 4705 desc->type = var.type;
4706 desc->s = var.s;
4707 desc->dpl = var.dpl;
4708 desc->p = var.present;
4709 desc->avl = var.avl;
4710 desc->l = var.l;
4711 desc->d = var.db;
4712 desc->g = var.g;
4713
4714 return true;
4715}
4716
1aa36616
AK		 4717static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4718 struct desc_struct *desc, u32 base3,
4719 int seg)
2dafc6c2 4720{
4bff1e86 4721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4722 struct kvm_segment var;
4723
1aa36616 4724 var.selector = selector;
2dafc6c2 4725 var.base = get_desc_base(desc);
5601d05b
GN		 4726#ifdef CONFIG_X86_64
4727 var.base |= ((u64)base3) << 32;
4728#endif
2dafc6c2
GN		 4729 var.limit = get_desc_limit(desc);
4730 if (desc->g)
4731 var.limit = (var.limit << 12) | 0xfff;
4732 var.type = desc->type;
2dafc6c2
GN		 4733 var.dpl = desc->dpl;
4734 var.db = desc->d;
4735 var.s = desc->s;
4736 var.l = desc->l;
4737 var.g = desc->g;
4738 var.avl = desc->avl;
4739 var.present = desc->p;
4740 var.unusable = !var.present;
4741 var.padding = 0;
4742
4743 kvm_set_segment(vcpu, &var, seg);
4744 return;
4745}
4746
717746e3
AK		 4747static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4748 u32 msr_index, u64 *pdata)
4749{
4750 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4751}
4752
4753static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4754 u32 msr_index, u64 data)
4755{
8fe8ab46
WA		 4756 struct msr_data msr;
4757
4758 msr.data = data;
4759 msr.index = msr_index;
4760 msr.host_initiated = false;
4761 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4762}
4763
67f4d428
NA		 4764static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4765 u32 pmc)
4766{
4767 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4768}
4769
222d21aa
AK		 4770static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4771 u32 pmc, u64 *pdata)
4772{
4773 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4774}
4775
6c3287f7
AK		 4776static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4777{
4778 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4779}
4780
5037f6f3
AK		 4781static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4782{
4783 preempt_disable();
5197b808 4784 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4785 /*
4786 * CR0.TS may reference the host fpu state, not the guest fpu state,
4787 * so it may be clear at this point.
4788 */
4789 clts();
4790}
4791
4792static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4793{
4794 preempt_enable();
4795}
4796
2953538e 4797static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4798 struct x86_instruction_info *info,
c4f035c6
AK		 4799 enum x86_intercept_stage stage)
4800{
2953538e 4801 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4802}
4803
0017f93a 4804static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4805 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4806{
0017f93a 4807 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4808}
4809
dd856efa
AK		 4810static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4811{
4812 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4813}
4814
4815static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4816{
4817 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4818}
4819
0225fb50 4820static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4821 .read_gpr = emulator_read_gpr,
4822 .write_gpr = emulator_write_gpr,
1871c602 4823 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4824 .write_std = kvm_write_guest_virt_system,
1871c602 4825 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4826 .read_emulated = emulator_read_emulated,
4827 .write_emulated = emulator_write_emulated,
4828 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4829 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4830 .pio_in_emulated = emulator_pio_in_emulated,
4831 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4832 .get_segment = emulator_get_segment,
4833 .set_segment = emulator_set_segment,
5951c442 4834 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4835 .get_gdt = emulator_get_gdt,
160ce1f1 4836 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4837 .set_gdt = emulator_set_gdt,
4838 .set_idt = emulator_set_idt,
52a46617
GN		 4839 .get_cr = emulator_get_cr,
4840 .set_cr = emulator_set_cr,
9c537244 4841 .cpl = emulator_get_cpl,
35aa5375
GN		 4842 .get_dr = emulator_get_dr,
4843 .set_dr = emulator_set_dr,
717746e3
AK		 4844 .set_msr = emulator_set_msr,
4845 .get_msr = emulator_get_msr,
67f4d428 4846 .check_pmc = emulator_check_pmc,
222d21aa 4847 .read_pmc = emulator_read_pmc,
6c3287f7 4848 .halt = emulator_halt,
bcaf5cc5 4849 .wbinvd = emulator_wbinvd,
d6aa1000 4850 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4851 .get_fpu = emulator_get_fpu,
4852 .put_fpu = emulator_put_fpu,
c4f035c6 4853 .intercept = emulator_intercept,
bdb42f5a 4854 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4855};
4856
95cb2295
GN		 4857static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4858{
4859 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4860 /*
4861 * an sti; sti; sequence only disable interrupts for the first
4862 * instruction. So, if the last instruction, be it emulated or
4863 * not, left the system with the INT_STI flag enabled, it
4864 * means that the last instruction is an sti. We should not
4865 * leave the flag on in this case. The same goes for mov ss
4866 */
4867 if (!(int_shadow & mask))
4868 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4869}
4870
54b8486f
GN		 4871static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4872{
4873 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4874 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4875 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4876 else if (ctxt->exception.error_code_valid)
4877 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4878 ctxt->exception.error_code);
54b8486f 4879 else
da9cb575 4880 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4881}
4882
dd856efa 4883static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4884{
1ce19dc1
BP		 4885 memset(&ctxt->opcode_len, 0,
4886 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4887
9dac77fa
AK		 4888 ctxt->fetch.start = 0;
4889 ctxt->fetch.end = 0;
4890 ctxt->io_read.pos = 0;
4891 ctxt->io_read.end = 0;
4892 ctxt->mem_read.pos = 0;
4893 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4894}
4895
8ec4722d
MG		 4896static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4897{
adf52235 4898 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4899 int cs_db, cs_l;
4900
8ec4722d
MG		 4901 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4902
adf52235
TY		 4903 ctxt->eflags = kvm_get_rflags(vcpu);
4904 ctxt->eip = kvm_rip_read(vcpu);
4905 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4906 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4907 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4908 cs_db ? X86EMUL_MODE_PROT32 :
4909 X86EMUL_MODE_PROT16;
4910 ctxt->guest_mode = is_guest_mode(vcpu);
4911
dd856efa 4912 init_decode_cache(ctxt);
7ae441ea 4913 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4914}
4915
71f9833b 4916int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4917{
9d74191a 4918 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4919 int ret;
4920
4921 init_emulate_ctxt(vcpu);
4922
9dac77fa
AK		 4923 ctxt->op_bytes = 2;
4924 ctxt->ad_bytes = 2;
4925 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4926 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4927
4928 if (ret != X86EMUL_CONTINUE)
4929 return EMULATE_FAIL;
4930
9dac77fa 4931 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4932 kvm_rip_write(vcpu, ctxt->eip);
4933 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4934
4935 if (irq == NMI_VECTOR)
7460fb4a 4936 vcpu->arch.nmi_pending = 0;
63995653
MG		 4937 else
4938 vcpu->arch.interrupt.pending = false;
4939
4940 return EMULATE_DONE;
4941}
4942EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4943
6d77dbfc
GN		 4944static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4945{
fc3a9157
JR		 4946 int r = EMULATE_DONE;
4947
6d77dbfc
GN		 4948 ++vcpu->stat.insn_emulation_fail;
4949 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4950 if (!is_guest_mode(vcpu)) {
4951 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4952 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4953 vcpu->run->internal.ndata = 0;
4954 r = EMULATE_FAIL;
4955 }
6d77dbfc 4956 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4957
4958 return r;
6d77dbfc
GN		 4959}
4960
93c05d3e 4961static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4962 bool write_fault_to_shadow_pgtable,
4963 int emulation_type)
a6f177ef 4964{
95b3cf69 4965 gpa_t gpa = cr2;
8e3d9d06 4966 pfn_t pfn;
a6f177ef 4967
991eebf9
GN		 4968 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4969 return false;
4970
95b3cf69
XG		 4971 if (!vcpu->arch.mmu.direct_map) {
4972 /*
4973 * Write permission should be allowed since only
4974 * write access need to be emulated.
4975 */
4976 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4977
95b3cf69
XG		 4978 /*
4979 * If the mapping is invalid in guest, let cpu retry
4980 * it to generate fault.
4981 */
4982 if (gpa == UNMAPPED_GVA)
4983 return true;
4984 }
a6f177ef 4985
8e3d9d06
XG		 4986 /*
4987 * Do not retry the unhandleable instruction if it faults on the
4988 * readonly host memory, otherwise it will goto a infinite loop:
4989 * retry instruction -> write #PF -> emulation fail -> retry
4990 * instruction -> ...
4991 */
4992 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4993
4994 /*
4995 * If the instruction failed on the error pfn, it can not be fixed,
4996 * report the error to userspace.
4997 */
4998 if (is_error_noslot_pfn(pfn))
4999 return false;
5000
5001 kvm_release_pfn_clean(pfn);
5002
5003 /* The instructions are well-emulated on direct mmu. */
5004 if (vcpu->arch.mmu.direct_map) {
5005 unsigned int indirect_shadow_pages;
5006
5007 spin_lock(&vcpu->kvm->mmu_lock);
5008 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5009 spin_unlock(&vcpu->kvm->mmu_lock);
5010
5011 if (indirect_shadow_pages)
5012 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5013
a6f177ef 5014 return true;
8e3d9d06 5015 }
a6f177ef 5016
95b3cf69
XG		 5017 /*
5018 * if emulation was due to access to shadowed page table
5019 * and it failed try to unshadow page and re-enter the
5020 * guest to let CPU execute the instruction.
5021 */
5022 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5023
5024 /*
5025 * If the access faults on its page table, it can not
5026 * be fixed by unprotecting shadow page and it should
5027 * be reported to userspace.
5028 */
5029 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5030}
5031
1cb3f3ae
XG		 5032static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5033 unsigned long cr2, int emulation_type)
5034{
5035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5036 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5037
5038 last_retry_eip = vcpu->arch.last_retry_eip;
5039 last_retry_addr = vcpu->arch.last_retry_addr;
5040
5041 /*
5042 * If the emulation is caused by #PF and it is non-page_table
5043 * writing instruction, it means the VM-EXIT is caused by shadow
5044 * page protected, we can zap the shadow page and retry this
5045 * instruction directly.
5046 *
5047 * Note: if the guest uses a non-page-table modifying instruction
5048 * on the PDE that points to the instruction, then we will unmap
5049 * the instruction and go to an infinite loop. So, we cache the
5050 * last retried eip and the last fault address, if we meet the eip
5051 * and the address again, we can break out of the potential infinite
5052 * loop.
5053 */
5054 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5055
5056 if (!(emulation_type & EMULTYPE_RETRY))
5057 return false;
5058
5059 if (x86_page_table_writing_insn(ctxt))
5060 return false;
5061
5062 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5063 return false;
5064
5065 vcpu->arch.last_retry_eip = ctxt->eip;
5066 vcpu->arch.last_retry_addr = cr2;
5067
5068 if (!vcpu->arch.mmu.direct_map)
5069 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5070
22368028 5071 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5072
5073 return true;
5074}
5075
716d51ab
GN		 5076static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5077static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5078
4a1e10d5
PB		 5079static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5080 unsigned long *db)
5081{
5082 u32 dr6 = 0;
5083 int i;
5084 u32 enable, rwlen;
5085
5086 enable = dr7;
5087 rwlen = dr7 >> 16;
5088 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5089 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5090 dr6 |= (1 << i);
5091 return dr6;
5092}
5093
663f4c61
PB		 5094static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5095{
5096 struct kvm_run *kvm_run = vcpu->run;
5097
5098 /*
5099 * Use the "raw" value to see if TF was passed to the processor.
5100 * Note that the new value of the flags has not been saved yet.
5101 *
5102 * This is correct even for TF set by the guest, because "the
5103 * processor will not generate this exception after the instruction
5104 * that sets the TF flag".
5105 */
5106 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5107
5108 if (unlikely(rflags & X86_EFLAGS_TF)) {
5109 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5110 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5111 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5112 kvm_run->debug.arch.exception = DB_VECTOR;
5113 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5114 *r = EMULATE_USER_EXIT;
5115 } else {
5116 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5117 /*
5118 * "Certain debug exceptions may clear bit 0-3. The
5119 * remaining contents of the DR6 register are never
5120 * cleared by the processor".
5121 */
5122 vcpu->arch.dr6 &= ~15;
5123 vcpu->arch.dr6 |= DR6_BS;
5124 kvm_queue_exception(vcpu, DB_VECTOR);
5125 }
5126 }
5127}
5128
4a1e10d5
PB		 5129static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5130{
5131 struct kvm_run *kvm_run = vcpu->run;
5132 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5133 u32 dr6 = 0;
5134
5135 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5136 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5137 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5138 vcpu->arch.guest_debug_dr7,
5139 vcpu->arch.eff_db);
5140
5141 if (dr6 != 0) {
5142 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5143 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5144 get_segment_base(vcpu, VCPU_SREG_CS);
5145
5146 kvm_run->debug.arch.exception = DB_VECTOR;
5147 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5148 *r = EMULATE_USER_EXIT;
5149 return true;
5150 }
5151 }
5152
5153 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5154 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5155 vcpu->arch.dr7,
5156 vcpu->arch.db);
5157
5158 if (dr6 != 0) {
5159 vcpu->arch.dr6 &= ~15;
5160 vcpu->arch.dr6 |= dr6;
5161 kvm_queue_exception(vcpu, DB_VECTOR);
5162 *r = EMULATE_DONE;
5163 return true;
5164 }
5165 }
5166
5167 return false;
5168}
5169
51d8b661
AP		 5170int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5171 unsigned long cr2,
dc25e89e
AP		 5172 int emulation_type,
5173 void *insn,
5174 int insn_len)
bbd9b64e 5175{
95cb2295 5176 int r;
9d74191a 5177 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5178 bool writeback = true;
93c05d3e 5179 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5180
93c05d3e
XG		 5181 /*
5182 * Clear write_fault_to_shadow_pgtable here to ensure it is
5183 * never reused.
5184 */
5185 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5186 kvm_clear_exception_queue(vcpu);
8d7d8102 5187
571008da 5188 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5189 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5190
5191 /*
5192 * We will reenter on the same instruction since
5193 * we do not set complete_userspace_io. This does not
5194 * handle watchpoints yet, those would be handled in
5195 * the emulate_ops.
5196 */
5197 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5198 return r;
5199
9d74191a
TY		 5200 ctxt->interruptibility = 0;
5201 ctxt->have_exception = false;
5202 ctxt->perm_ok = false;
bbd9b64e 5203
b51e974f 5204 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5205
9d74191a 5206 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5207
e46479f8 5208 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5209 ++vcpu->stat.insn_emulation;
1d2887e2 5210 if (r != EMULATION_OK) {
4005996e
AK		 5211 if (emulation_type & EMULTYPE_TRAP_UD)
5212 return EMULATE_FAIL;
991eebf9
GN		 5213 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5214 emulation_type))
bbd9b64e 5215 return EMULATE_DONE;
6d77dbfc
GN		 5216 if (emulation_type & EMULTYPE_SKIP)
5217 return EMULATE_FAIL;
5218 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5219 }
5220 }
5221
ba8afb6b 5222 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5223 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5224 return EMULATE_DONE;
5225 }
5226
1cb3f3ae
XG		 5227 if (retry_instruction(ctxt, cr2, emulation_type))
5228 return EMULATE_DONE;
5229
7ae441ea 5230 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5231 changes registers values during IO operation */
7ae441ea
GN		 5232 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5233 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5234 emulator_invalidate_register_cache(ctxt);
7ae441ea 5235 }
4d2179e1 5236
5cd21917 5237restart:
9d74191a 5238 r = x86_emulate_insn(ctxt);
bbd9b64e 5239
775fde86
JR		 5240 if (r == EMULATION_INTERCEPTED)
5241 return EMULATE_DONE;
5242
d2ddd1c4 5243 if (r == EMULATION_FAILED) {
991eebf9
GN		 5244 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5245 emulation_type))
c3cd7ffa
GN		 5246 return EMULATE_DONE;
5247
6d77dbfc 5248 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5249 }
5250
9d74191a 5251 if (ctxt->have_exception) {
54b8486f 5252 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5253 r = EMULATE_DONE;
5254 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5255 if (!vcpu->arch.pio.in) {
5256 /* FIXME: return into emulator if single-stepping. */
3457e419 5257 vcpu->arch.pio.count = 0;
0912c977 5258 } else {
7ae441ea 5259 writeback = false;
716d51ab
GN		 5260 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5261 }
ac0a48c3 5262 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5263 } else if (vcpu->mmio_needed) {
5264 if (!vcpu->mmio_is_write)
5265 writeback = false;
ac0a48c3 5266 r = EMULATE_USER_EXIT;
716d51ab 5267 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5268 } else if (r == EMULATION_RESTART)
5cd21917 5269 goto restart;
d2ddd1c4
GN		 5270 else
5271 r = EMULATE_DONE;
f850e2e6 5272
7ae441ea 5273 if (writeback) {
9d74191a 5274 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5275 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5277 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5278 if (r == EMULATE_DONE)
5279 kvm_vcpu_check_singlestep(vcpu, &r);
5280 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5281 } else
5282 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5283
5284 return r;
de7d789a 5285}
51d8b661 5286EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5287
cf8f70bf 5288int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5289{
cf8f70bf 5290 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5291 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5292 size, port, &val, 1);
cf8f70bf 5293 /* do not return to emulator after return from userspace */
7972995b 5294 vcpu->arch.pio.count = 0;
de7d789a
CO		 5295 return ret;
5296}
cf8f70bf 5297EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5298
8cfdc000
ZA		 5299static void tsc_bad(void *info)
5300{
0a3aee0d 5301 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5302}
5303
5304static void tsc_khz_changed(void *data)
c8076604 5305{
8cfdc000
ZA		 5306 struct cpufreq_freqs *freq = data;
5307 unsigned long khz = 0;
5308
5309 if (data)
5310 khz = freq->new;
5311 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5312 khz = cpufreq_quick_get(raw_smp_processor_id());
5313 if (!khz)
5314 khz = tsc_khz;
0a3aee0d 5315 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5316}
5317
c8076604
GH		 5318static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5319 void *data)
5320{
5321 struct cpufreq_freqs *freq = data;
5322 struct kvm *kvm;
5323 struct kvm_vcpu *vcpu;
5324 int i, send_ipi = 0;
5325
8cfdc000
ZA		 5326 /*
5327 * We allow guests to temporarily run on slowing clocks,
5328 * provided we notify them after, or to run on accelerating
5329 * clocks, provided we notify them before. Thus time never
5330 * goes backwards.
5331 *
5332 * However, we have a problem. We can't atomically update
5333 * the frequency of a given CPU from this function; it is
5334 * merely a notifier, which can be called from any CPU.
5335 * Changing the TSC frequency at arbitrary points in time
5336 * requires a recomputation of local variables related to
5337 * the TSC for each VCPU. We must flag these local variables
5338 * to be updated and be sure the update takes place with the
5339 * new frequency before any guests proceed.
5340 *
5341 * Unfortunately, the combination of hotplug CPU and frequency
5342 * change creates an intractable locking scenario; the order
5343 * of when these callouts happen is undefined with respect to
5344 * CPU hotplug, and they can race with each other. As such,
5345 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5346 * undefined; you can actually have a CPU frequency change take
5347 * place in between the computation of X and the setting of the
5348 * variable. To protect against this problem, all updates of
5349 * the per_cpu tsc_khz variable are done in an interrupt
5350 * protected IPI, and all callers wishing to update the value
5351 * must wait for a synchronous IPI to complete (which is trivial
5352 * if the caller is on the CPU already). This establishes the
5353 * necessary total order on variable updates.
5354 *
5355 * Note that because a guest time update may take place
5356 * anytime after the setting of the VCPU's request bit, the
5357 * correct TSC value must be set before the request. However,
5358 * to ensure the update actually makes it to any guest which
5359 * starts running in hardware virtualization between the set
5360 * and the acquisition of the spinlock, we must also ping the
5361 * CPU after setting the request bit.
5362 *
5363 */
5364
c8076604
GH		 5365 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5366 return 0;
5367 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5368 return 0;
8cfdc000
ZA		 5369
5370 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5371
2f303b74 5372 spin_lock(&kvm_lock);
c8076604 5373 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5374 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5375 if (vcpu->cpu != freq->cpu)
5376 continue;
c285545f 5377 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5378 if (vcpu->cpu != smp_processor_id())
8cfdc000 5379 send_ipi = 1;
c8076604
GH		 5380 }
5381 }
2f303b74 5382 spin_unlock(&kvm_lock);
c8076604
GH		 5383
5384 if (freq->old < freq->new && send_ipi) {
5385 /*
5386 * We upscale the frequency. Must make the guest
5387 * doesn't see old kvmclock values while running with
5388 * the new frequency, otherwise we risk the guest sees
5389 * time go backwards.
5390 *
5391 * In case we update the frequency for another cpu
5392 * (which might be in guest context) send an interrupt
5393 * to kick the cpu out of guest context. Next time
5394 * guest context is entered kvmclock will be updated,
5395 * so the guest will not see stale values.
5396 */
8cfdc000 5397 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5398 }
5399 return 0;
5400}
5401
5402static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5403 .notifier_call = kvmclock_cpufreq_notifier
5404};
5405
5406static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5407 unsigned long action, void *hcpu)
5408{
5409 unsigned int cpu = (unsigned long)hcpu;
5410
5411 switch (action) {
5412 case CPU_ONLINE:
5413 case CPU_DOWN_FAILED:
5414 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5415 break;
5416 case CPU_DOWN_PREPARE:
5417 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5418 break;
5419 }
5420 return NOTIFY_OK;
5421}
5422
5423static struct notifier_block kvmclock_cpu_notifier_block = {
5424 .notifier_call = kvmclock_cpu_notifier,
5425 .priority = -INT_MAX
c8076604
GH		 5426};
5427
b820cc0c
ZA		 5428static void kvm_timer_init(void)
5429{
5430 int cpu;
5431
c285545f 5432 max_tsc_khz = tsc_khz;
460dd42e
SB		 5433
5434 cpu_notifier_register_begin();
b820cc0c 5435 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5436#ifdef CONFIG_CPU_FREQ
5437 struct cpufreq_policy policy;
5438 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5439 cpu = get_cpu();
5440 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5441 if (policy.cpuinfo.max_freq)
5442 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5443 put_cpu();
c285545f 5444#endif
b820cc0c
ZA		 5445 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5446 CPUFREQ_TRANSITION_NOTIFIER);
5447 }
c285545f 5448 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5449 for_each_online_cpu(cpu)
5450 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5451
5452 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5453 cpu_notifier_register_done();
5454
b820cc0c
ZA		 5455}
5456
ff9d07a0
ZY		 5457static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5458
f5132b01 5459int kvm_is_in_guest(void)
ff9d07a0 5460{
086c9855 5461 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5462}
5463
5464static int kvm_is_user_mode(void)
5465{
5466 int user_mode = 3;
dcf46b94 5467
086c9855
AS		 5468 if (__this_cpu_read(current_vcpu))
5469 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5470
ff9d07a0
ZY		 5471 return user_mode != 0;
5472}
5473
5474static unsigned long kvm_get_guest_ip(void)
5475{
5476 unsigned long ip = 0;
dcf46b94 5477
086c9855
AS		 5478 if (__this_cpu_read(current_vcpu))
5479 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5480
ff9d07a0
ZY		 5481 return ip;
5482}
5483
5484static struct perf_guest_info_callbacks kvm_guest_cbs = {
5485 .is_in_guest = kvm_is_in_guest,
5486 .is_user_mode = kvm_is_user_mode,
5487 .get_guest_ip = kvm_get_guest_ip,
5488};
5489
5490void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5491{
086c9855 5492 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5493}
5494EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5495
5496void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5497{
086c9855 5498 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5499}
5500EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5501
ce88decf
XG		 5502static void kvm_set_mmio_spte_mask(void)
5503{
5504 u64 mask;
5505 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5506
5507 /*
5508 * Set the reserved bits and the present bit of an paging-structure
5509 * entry to generate page fault with PFER.RSV = 1.
5510 */
885032b9
XG		 5511 /* Mask the reserved physical address bits. */
5512 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5513
5514 /* Bit 62 is always reserved for 32bit host. */
5515 mask |= 0x3ull << 62;
5516
5517 /* Set the present bit. */
ce88decf
XG		 5518 mask |= 1ull;
5519
5520#ifdef CONFIG_X86_64
5521 /*
5522 * If reserved bit is not supported, clear the present bit to disable
5523 * mmio page fault.
5524 */
5525 if (maxphyaddr == 52)
5526 mask &= ~1ull;
5527#endif
5528
5529 kvm_mmu_set_mmio_spte_mask(mask);
5530}
5531
16e8d74d
MT		 5532#ifdef CONFIG_X86_64
5533static void pvclock_gtod_update_fn(struct work_struct *work)
5534{
d828199e
MT		 5535 struct kvm *kvm;
5536
5537 struct kvm_vcpu *vcpu;
5538 int i;
5539
2f303b74 5540 spin_lock(&kvm_lock);
d828199e
MT		 5541 list_for_each_entry(kvm, &vm_list, vm_list)
5542 kvm_for_each_vcpu(i, vcpu, kvm)
5543 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5544 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5545 spin_unlock(&kvm_lock);
16e8d74d
MT		 5546}
5547
5548static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5549
5550/*
5551 * Notification about pvclock gtod data update.
5552 */
5553static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5554 void *priv)
5555{
5556 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5557 struct timekeeper *tk = priv;
5558
5559 update_pvclock_gtod(tk);
5560
5561 /* disable master clock if host does not trust, or does not
5562 * use, TSC clocksource
5563 */
5564 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5565 atomic_read(&kvm_guest_has_master_clock) != 0)
5566 queue_work(system_long_wq, &pvclock_gtod_work);
5567
5568 return 0;
5569}
5570
5571static struct notifier_block pvclock_gtod_notifier = {
5572 .notifier_call = pvclock_gtod_notify,
5573};
5574#endif
5575
f8c16bba 5576int kvm_arch_init(void *opaque)
043405e1 5577{
b820cc0c 5578 int r;
6b61edf7 5579 struct kvm_x86_ops *ops = opaque;
f8c16bba 5580
f8c16bba
ZX		 5581 if (kvm_x86_ops) {
5582 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5583 r = -EEXIST;
5584 goto out;
f8c16bba
ZX		 5585 }
5586
5587 if (!ops->cpu_has_kvm_support()) {
5588 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5589 r = -EOPNOTSUPP;
5590 goto out;
f8c16bba
ZX		 5591 }
5592 if (ops->disabled_by_bios()) {
5593 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5594 r = -EOPNOTSUPP;
5595 goto out;
f8c16bba
ZX		 5596 }
5597
013f6a5d
MT		 5598 r = -ENOMEM;
5599 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5600 if (!shared_msrs) {
5601 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5602 goto out;
5603 }
5604
97db56ce
AK		 5605 r = kvm_mmu_module_init();
5606 if (r)
013f6a5d 5607 goto out_free_percpu;
97db56ce 5608
ce88decf 5609 kvm_set_mmio_spte_mask();
97db56ce 5610
f8c16bba 5611 kvm_x86_ops = ops;
920c8377
PB		 5612 kvm_init_msr_list();
5613
7b52345e 5614 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5615 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5616
b820cc0c 5617 kvm_timer_init();
c8076604 5618
ff9d07a0
ZY		 5619 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5620
2acf923e
DC		 5621 if (cpu_has_xsave)
5622 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5623
c5cc421b 5624 kvm_lapic_init();
16e8d74d
MT		 5625#ifdef CONFIG_X86_64
5626 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5627#endif
5628
f8c16bba 5629 return 0;
56c6d28a 5630
013f6a5d
MT		 5631out_free_percpu:
5632 free_percpu(shared_msrs);
56c6d28a 5633out:
56c6d28a 5634 return r;
043405e1 5635}
8776e519 5636
f8c16bba
ZX		 5637void kvm_arch_exit(void)
5638{
ff9d07a0
ZY		 5639 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5640
888d256e
JK		 5641 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5642 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5643 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5644 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5645#ifdef CONFIG_X86_64
5646 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5647#endif
f8c16bba 5648 kvm_x86_ops = NULL;
56c6d28a 5649 kvm_mmu_module_exit();
013f6a5d 5650 free_percpu(shared_msrs);
56c6d28a 5651}
f8c16bba 5652
8776e519
HB		 5653int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5654{
5655 ++vcpu->stat.halt_exits;
5656 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5657 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5658 return 1;
5659 } else {
5660 vcpu->run->exit_reason = KVM_EXIT_HLT;
5661 return 0;
5662 }
5663}
5664EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5665
55cd8e5a
GN		 5666int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5667{
5668 u64 param, ingpa, outgpa, ret;
5669 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5670 bool fast, longmode;
55cd8e5a
GN		 5671
5672 /*
5673 * hypercall generates UD from non zero cpl and real mode
5674 * per HYPER-V spec
5675 */
3eeb3288 5676 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5677 kvm_queue_exception(vcpu, UD_VECTOR);
5678 return 0;
5679 }
5680
a449c7aa 5681 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5682
5683 if (!longmode) {
ccd46936
GN		 5684 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5685 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5686 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5687 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5688 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5689 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5690 }
5691#ifdef CONFIG_X86_64
5692 else {
5693 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5694 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5695 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5696 }
5697#endif
5698
5699 code = param & 0xffff;
5700 fast = (param >> 16) & 0x1;
5701 rep_cnt = (param >> 32) & 0xfff;
5702 rep_idx = (param >> 48) & 0xfff;
5703
5704 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5705
c25bc163
GN		 5706 switch (code) {
5707 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5708 kvm_vcpu_on_spin(vcpu);
5709 break;
5710 default:
5711 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5712 break;
5713 }
55cd8e5a
GN		 5714
5715 ret = res | (((u64)rep_done & 0xfff) << 32);
5716 if (longmode) {
5717 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5718 } else {
5719 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5720 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5721 }
5722
5723 return 1;
5724}
5725
6aef266c
SV		 5726/*
5727 * kvm_pv_kick_cpu_op: Kick a vcpu.
5728 *
5729 * @apicid - apicid of vcpu to be kicked.
5730 */
5731static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5732{
24d2166b 5733 struct kvm_lapic_irq lapic_irq;
6aef266c 5734
24d2166b
R		 5735 lapic_irq.shorthand = 0;
5736 lapic_irq.dest_mode = 0;
5737 lapic_irq.dest_id = apicid;
6aef266c 5738
24d2166b
R		 5739 lapic_irq.delivery_mode = APIC_DM_REMRD;
5740 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5741}
5742
8776e519
HB		 5743int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5744{
5745 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5746 int op_64_bit, r = 1;
8776e519 5747
55cd8e5a
GN		 5748 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5749 return kvm_hv_hypercall(vcpu);
5750
5fdbf976
MT		 5751 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5752 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5753 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5756
229456fc 5757 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5758
a449c7aa
NA		 5759 op_64_bit = is_64_bit_mode(vcpu);
5760 if (!op_64_bit) {
8776e519
HB		 5761 nr &= 0xFFFFFFFF;
5762 a0 &= 0xFFFFFFFF;
5763 a1 &= 0xFFFFFFFF;
5764 a2 &= 0xFFFFFFFF;
5765 a3 &= 0xFFFFFFFF;
5766 }
5767
07708c4a
JK		 5768 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5769 ret = -KVM_EPERM;
5770 goto out;
5771 }
5772
8776e519 5773 switch (nr) {
b93463aa
AK		 5774 case KVM_HC_VAPIC_POLL_IRQ:
5775 ret = 0;
5776 break;
6aef266c
SV		 5777 case KVM_HC_KICK_CPU:
5778 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5779 ret = 0;
5780 break;
8776e519
HB		 5781 default:
5782 ret = -KVM_ENOSYS;
5783 break;
5784 }
07708c4a 5785out:
a449c7aa
NA		 5786 if (!op_64_bit)
5787 ret = (u32)ret;
5fdbf976 5788 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5789 ++vcpu->stat.hypercalls;
2f333bcb 5790 return r;
8776e519
HB		 5791}
5792EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5793
b6785def 5794static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5795{
d6aa1000 5796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5797 char instruction[3];
5fdbf976 5798 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5799
8776e519 5800 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5801
9d74191a 5802 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5803}
5804
b6c7a5dc
HB		 5805/*
5806 * Check if userspace requested an interrupt window, and that the
5807 * interrupt window is open.
5808 *
5809 * No need to exit to userspace if we already have an interrupt queued.
5810 */
851ba692 5811static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5812{
8061823a 5813 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5814 vcpu->run->request_interrupt_window &&
5df56646 5815 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5816}
5817
851ba692 5818static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5819{
851ba692
AK		 5820 struct kvm_run *kvm_run = vcpu->run;
5821
91586a3b 5822 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5823 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5824 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5825 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5826 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5827 else
b6c7a5dc 5828 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5829 kvm_arch_interrupt_allowed(vcpu) &&
5830 !kvm_cpu_has_interrupt(vcpu) &&
5831 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5832}
5833
95ba8273
GN		 5834static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5835{
5836 int max_irr, tpr;
5837
5838 if (!kvm_x86_ops->update_cr8_intercept)
5839 return;
5840
88c808fd
AK		 5841 if (!vcpu->arch.apic)
5842 return;
5843
8db3baa2
GN		 5844 if (!vcpu->arch.apic->vapic_addr)
5845 max_irr = kvm_lapic_find_highest_irr(vcpu);
5846 else
5847 max_irr = -1;
95ba8273
GN		 5848
5849 if (max_irr != -1)
5850 max_irr >>= 4;
5851
5852 tpr = kvm_lapic_get_cr8(vcpu);
5853
5854 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5855}
5856
b6b8a145 5857static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5858{
b6b8a145
JK		 5859 int r;
5860
95ba8273 5861 /* try to reinject previous events if any */
b59bb7bd 5862 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5863 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5864 vcpu->arch.exception.has_error_code,
5865 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5866 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5867 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5868 vcpu->arch.exception.error_code,
5869 vcpu->arch.exception.reinject);
b6b8a145 5870 return 0;
b59bb7bd
GN		 5871 }
5872
95ba8273
GN		 5873 if (vcpu->arch.nmi_injected) {
5874 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5875 return 0;
95ba8273
GN		 5876 }
5877
5878 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5879 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5880 return 0;
5881 }
5882
5883 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5884 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5885 if (r != 0)
5886 return r;
95ba8273
GN		 5887 }
5888
5889 /* try to inject new event if pending */
5890 if (vcpu->arch.nmi_pending) {
5891 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5892 --vcpu->arch.nmi_pending;
95ba8273
GN		 5893 vcpu->arch.nmi_injected = true;
5894 kvm_x86_ops->set_nmi(vcpu);
5895 }
c7c9c56c 5896 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5897 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5898 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5899 false);
5900 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5901 }
5902 }
b6b8a145 5903 return 0;
95ba8273
GN		 5904}
5905
7460fb4a
AK		 5906static void process_nmi(struct kvm_vcpu *vcpu)
5907{
5908 unsigned limit = 2;
5909
5910 /*
5911 * x86 is limited to one NMI running, and one NMI pending after it.
5912 * If an NMI is already in progress, limit further NMIs to just one.
5913 * Otherwise, allow two (and we'll inject the first one immediately).
5914 */
5915 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5916 limit = 1;
5917
5918 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5919 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5920 kvm_make_request(KVM_REQ_EVENT, vcpu);
5921}
5922
3d81bc7e 5923static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5924{
5925 u64 eoi_exit_bitmap[4];
cf9e65b7 5926 u32 tmr[8];
c7c9c56c 5927
3d81bc7e
YZ		 5928 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5929 return;
c7c9c56c
YZ		 5930
5931 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5932 memset(tmr, 0, 32);
c7c9c56c 5933
cf9e65b7 5934 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5935 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5936 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5937}
5938
9357d939
TY		 5939/*
5940 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5941 * exiting to the userspace. Otherwise, the value will be returned to the
5942 * userspace.
5943 */
851ba692 5944static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5945{
5946 int r;
6a8b1d13 5947 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5948 vcpu->run->request_interrupt_window;
730dca42 5949 bool req_immediate_exit = false;
b6c7a5dc 5950
3e007509 5951 if (vcpu->requests) {
a8eeb04a 5952 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5953 kvm_mmu_unload(vcpu);
a8eeb04a 5954 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5955 __kvm_migrate_timers(vcpu);
d828199e
MT		 5956 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5957 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5958 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5959 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5960 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5961 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5962 if (unlikely(r))
5963 goto out;
5964 }
a8eeb04a 5965 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5966 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5967 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5968 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5969 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5970 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5971 r = 0;
5972 goto out;
5973 }
a8eeb04a 5974 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5975 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5976 r = 0;
5977 goto out;
5978 }
a8eeb04a 5979 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5980 vcpu->fpu_active = 0;
5981 kvm_x86_ops->fpu_deactivate(vcpu);
5982 }
af585b92
GN		 5983 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5984 /* Page is swapped out. Do synthetic halt */
5985 vcpu->arch.apf.halted = true;
5986 r = 1;
5987 goto out;
5988 }
c9aaa895
GC		 5989 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5990 record_steal_time(vcpu);
7460fb4a
AK		 5991 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5992 process_nmi(vcpu);
f5132b01
GN		 5993 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5994 kvm_handle_pmu_event(vcpu);
5995 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5996 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5997 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5998 vcpu_scan_ioapic(vcpu);
2f52d58c 5999 }
b93463aa 6000
b463a6f7 6001 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6002 kvm_apic_accept_events(vcpu);
6003 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6004 r = 1;
6005 goto out;
6006 }
6007
b6b8a145
JK		 6008 if (inject_pending_event(vcpu, req_int_win) != 0)
6009 req_immediate_exit = true;
b463a6f7 6010 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6011 else if (vcpu->arch.nmi_pending)
c9a7953f 6012 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6013 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6014 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6015
6016 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6017 /*
6018 * Update architecture specific hints for APIC
6019 * virtual interrupt delivery.
6020 */
6021 if (kvm_x86_ops->hwapic_irr_update)
6022 kvm_x86_ops->hwapic_irr_update(vcpu,
6023 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6024 update_cr8_intercept(vcpu);
6025 kvm_lapic_sync_to_vapic(vcpu);
6026 }
6027 }
6028
d8368af8
AK		 6029 r = kvm_mmu_reload(vcpu);
6030 if (unlikely(r)) {
d905c069 6031 goto cancel_injection;
d8368af8
AK		 6032 }
6033
b6c7a5dc
HB		 6034 preempt_disable();
6035
6036 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6037 if (vcpu->fpu_active)
6038 kvm_load_guest_fpu(vcpu);
2acf923e 6039 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6040
6b7e2d09
XG		 6041 vcpu->mode = IN_GUEST_MODE;
6042
01b71917
MT		 6043 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6044
6b7e2d09
XG		 6045 /* We should set ->mode before check ->requests,
6046 * see the comment in make_all_cpus_request.
6047 */
01b71917 6048 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6049
d94e1dc9 6050 local_irq_disable();
32f88400 6051
6b7e2d09 6052 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6053 || need_resched() || signal_pending(current)) {
6b7e2d09 6054 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6055 smp_wmb();
6c142801
AK		 6056 local_irq_enable();
6057 preempt_enable();
01b71917 6058 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6059 r = 1;
d905c069 6060 goto cancel_injection;
6c142801
AK		 6061 }
6062
d6185f20
NHE		 6063 if (req_immediate_exit)
6064 smp_send_reschedule(vcpu->cpu);
6065
b6c7a5dc
HB		 6066 kvm_guest_enter();
6067
42dbaa5a 6068 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6069 set_debugreg(0, 7);
6070 set_debugreg(vcpu->arch.eff_db[0], 0);
6071 set_debugreg(vcpu->arch.eff_db[1], 1);
6072 set_debugreg(vcpu->arch.eff_db[2], 2);
6073 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6074 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6075 }
b6c7a5dc 6076
229456fc 6077 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6078 kvm_x86_ops->run(vcpu);
b6c7a5dc 6079
c77fb5fe
PB		 6080 /*
6081 * Do this here before restoring debug registers on the host. And
6082 * since we do this before handling the vmexit, a DR access vmexit
6083 * can (a) read the correct value of the debug registers, (b) set
6084 * KVM_DEBUGREG_WONT_EXIT again.
6085 */
6086 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6087 int i;
6088
6089 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6090 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6091 for (i = 0; i < KVM_NR_DB_REGS; i++)
6092 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6093 }
6094
24f1e32c
FW		 6095 /*
6096 * If the guest has used debug registers, at least dr7
6097 * will be disabled while returning to the host.
6098 * If we don't have active breakpoints in the host, we don't
6099 * care about the messed up debug address registers. But if
6100 * we have some of them active, restore the old state.
6101 */
59d8eb53 6102 if (hw_breakpoint_active())
24f1e32c 6103 hw_breakpoint_restore();
42dbaa5a 6104
886b470c
MT		 6105 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6106 native_read_tsc());
1d5f066e 6107
6b7e2d09 6108 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6109 smp_wmb();
a547c6db
YZ		 6110
6111 /* Interrupt is enabled by handle_external_intr() */
6112 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6113
6114 ++vcpu->stat.exits;
6115
6116 /*
6117 * We must have an instruction between local_irq_enable() and
6118 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6119 * the interrupt shadow. The stat.exits increment will do nicely.
6120 * But we need to prevent reordering, hence this barrier():
6121 */
6122 barrier();
6123
6124 kvm_guest_exit();
6125
6126 preempt_enable();
6127
f656ce01 6128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6129
b6c7a5dc
HB		 6130 /*
6131 * Profile KVM exit RIPs:
6132 */
6133 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6134 unsigned long rip = kvm_rip_read(vcpu);
6135 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6136 }
6137
cc578287
ZA		 6138 if (unlikely(vcpu->arch.tsc_always_catchup))
6139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6140
5cfb1d5a
MT		 6141 if (vcpu->arch.apic_attention)
6142 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6143
851ba692 6144 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6145 return r;
6146
6147cancel_injection:
6148 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6149 if (unlikely(vcpu->arch.apic_attention))
6150 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6151out:
6152 return r;
6153}
b6c7a5dc 6154
09cec754 6155
851ba692 6156static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6157{
6158 int r;
f656ce01 6159 struct kvm *kvm = vcpu->kvm;
d7690175 6160
f656ce01 6161 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6162
6163 r = 1;
6164 while (r > 0) {
af585b92
GN		 6165 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6166 !vcpu->arch.apf.halted)
851ba692 6167 r = vcpu_enter_guest(vcpu);
d7690175 6168 else {
f656ce01 6169 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6170 kvm_vcpu_block(vcpu);
f656ce01 6171 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6172 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6173 kvm_apic_accept_events(vcpu);
09cec754
GN		 6174 switch(vcpu->arch.mp_state) {
6175 case KVM_MP_STATE_HALTED:
6aef266c 6176 vcpu->arch.pv.pv_unhalted = false;
d7690175 6177 vcpu->arch.mp_state =
09cec754
GN		 6178 KVM_MP_STATE_RUNNABLE;
6179 case KVM_MP_STATE_RUNNABLE:
af585b92 6180 vcpu->arch.apf.halted = false;
09cec754 6181 break;
66450a21
JK		 6182 case KVM_MP_STATE_INIT_RECEIVED:
6183 break;
09cec754
GN		 6184 default:
6185 r = -EINTR;
6186 break;
6187 }
6188 }
d7690175
MT		 6189 }
6190
09cec754
GN		 6191 if (r <= 0)
6192 break;
6193
6194 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6195 if (kvm_cpu_has_pending_timer(vcpu))
6196 kvm_inject_pending_timer_irqs(vcpu);
6197
851ba692 6198 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6199 r = -EINTR;
851ba692 6200 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6201 ++vcpu->stat.request_irq_exits;
6202 }
af585b92
GN		 6203
6204 kvm_check_async_pf_completion(vcpu);
6205
09cec754
GN		 6206 if (signal_pending(current)) {
6207 r = -EINTR;
851ba692 6208 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6209 ++vcpu->stat.signal_exits;
6210 }
6211 if (need_resched()) {
f656ce01 6212 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6213 cond_resched();
f656ce01 6214 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6215 }
b6c7a5dc
HB		 6216 }
6217
f656ce01 6218 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6219
6220 return r;
6221}
6222
716d51ab
GN		 6223static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6224{
6225 int r;
6226 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6227 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6228 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6229 if (r != EMULATE_DONE)
6230 return 0;
6231 return 1;
6232}
6233
6234static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6235{
6236 BUG_ON(!vcpu->arch.pio.count);
6237
6238 return complete_emulated_io(vcpu);
6239}
6240
f78146b0
AK		 6241/*
6242 * Implements the following, as a state machine:
6243 *
6244 * read:
6245 * for each fragment
87da7e66
XG		 6246 * for each mmio piece in the fragment
6247 * write gpa, len
6248 * exit
6249 * copy data
f78146b0
AK		 6250 * execute insn
6251 *
6252 * write:
6253 * for each fragment
87da7e66
XG		 6254 * for each mmio piece in the fragment
6255 * write gpa, len
6256 * copy data
6257 * exit
f78146b0 6258 */
716d51ab 6259static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6260{
6261 struct kvm_run *run = vcpu->run;
f78146b0 6262 struct kvm_mmio_fragment *frag;
87da7e66 6263 unsigned len;
5287f194 6264
716d51ab 6265 BUG_ON(!vcpu->mmio_needed);
5287f194 6266
716d51ab 6267 /* Complete previous fragment */
87da7e66
XG		 6268 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6269 len = min(8u, frag->len);
716d51ab 6270 if (!vcpu->mmio_is_write)
87da7e66
XG		 6271 memcpy(frag->data, run->mmio.data, len);
6272
6273 if (frag->len <= 8) {
6274 /* Switch to the next fragment. */
6275 frag++;
6276 vcpu->mmio_cur_fragment++;
6277 } else {
6278 /* Go forward to the next mmio piece. */
6279 frag->data += len;
6280 frag->gpa += len;
6281 frag->len -= len;
6282 }
6283
a08d3b3b 6284 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6285 vcpu->mmio_needed = 0;
0912c977
PB		 6286
6287 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6288 if (vcpu->mmio_is_write)
716d51ab
GN		 6289 return 1;
6290 vcpu->mmio_read_completed = 1;
6291 return complete_emulated_io(vcpu);
6292 }
87da7e66 6293
716d51ab
GN		 6294 run->exit_reason = KVM_EXIT_MMIO;
6295 run->mmio.phys_addr = frag->gpa;
6296 if (vcpu->mmio_is_write)
87da7e66
XG		 6297 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6298 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6299 run->mmio.is_write = vcpu->mmio_is_write;
6300 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6301 return 0;
5287f194
AK		 6302}
6303
716d51ab 6304
b6c7a5dc
HB		 6305int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6306{
6307 int r;
6308 sigset_t sigsaved;
6309
e5c30142
AK		 6310 if (!tsk_used_math(current) && init_fpu(current))
6311 return -ENOMEM;
6312
ac9f6dc0
AK		 6313 if (vcpu->sigset_active)
6314 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6315
a4535290 6316 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6317 kvm_vcpu_block(vcpu);
66450a21 6318 kvm_apic_accept_events(vcpu);
d7690175 6319 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6320 r = -EAGAIN;
6321 goto out;
b6c7a5dc
HB		 6322 }
6323
b6c7a5dc 6324 /* re-sync apic's tpr */
eea1cff9
AP		 6325 if (!irqchip_in_kernel(vcpu->kvm)) {
6326 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6327 r = -EINVAL;
6328 goto out;
6329 }
6330 }
b6c7a5dc 6331
716d51ab
GN		 6332 if (unlikely(vcpu->arch.complete_userspace_io)) {
6333 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6334 vcpu->arch.complete_userspace_io = NULL;
6335 r = cui(vcpu);
6336 if (r <= 0)
6337 goto out;
6338 } else
6339 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6340
851ba692 6341 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6342
6343out:
f1d86e46 6344 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6345 if (vcpu->sigset_active)
6346 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6347
b6c7a5dc
HB		 6348 return r;
6349}
6350
6351int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6352{
7ae441ea
GN		 6353 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6354 /*
6355 * We are here if userspace calls get_regs() in the middle of
6356 * instruction emulation. Registers state needs to be copied
4a969980 6357 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6358 * that usually, but some bad designed PV devices (vmware
6359 * backdoor interface) need this to work
6360 */
dd856efa 6361 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6362 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6363 }
5fdbf976
MT		 6364 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6365 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6366 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6367 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6368 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6369 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6370 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6371 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6372#ifdef CONFIG_X86_64
5fdbf976
MT		 6373 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6374 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6375 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6376 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6377 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6378 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6379 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6380 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6381#endif
6382
5fdbf976 6383 regs->rip = kvm_rip_read(vcpu);
91586a3b 6384 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6385
b6c7a5dc
HB		 6386 return 0;
6387}
6388
6389int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6390{
7ae441ea
GN		 6391 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6392 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6393
5fdbf976
MT		 6394 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6395 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6396 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6397 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6398 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6399 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6400 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6401 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6402#ifdef CONFIG_X86_64
5fdbf976
MT		 6403 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6404 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6405 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6406 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6407 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6408 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6409 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6410 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6411#endif
6412
5fdbf976 6413 kvm_rip_write(vcpu, regs->rip);
91586a3b 6414 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6415
b4f14abd
JK		 6416 vcpu->arch.exception.pending = false;
6417
3842d135
AK		 6418 kvm_make_request(KVM_REQ_EVENT, vcpu);
6419
b6c7a5dc
HB		 6420 return 0;
6421}
6422
b6c7a5dc
HB		 6423void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6424{
6425 struct kvm_segment cs;
6426
3e6e0aab 6427 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6428 *db = cs.db;
6429 *l = cs.l;
6430}
6431EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6432
6433int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6434 struct kvm_sregs *sregs)
6435{
89a27f4d 6436 struct desc_ptr dt;
b6c7a5dc 6437
3e6e0aab
GT		 6438 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6439 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6440 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6441 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6442 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6443 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6444
3e6e0aab
GT		 6445 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6446 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6447
6448 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6449 sregs->idt.limit = dt.size;
6450 sregs->idt.base = dt.address;
b6c7a5dc 6451 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6452 sregs->gdt.limit = dt.size;
6453 sregs->gdt.base = dt.address;
b6c7a5dc 6454
4d4ec087 6455 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6456 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6457 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6458 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6459 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6460 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6461 sregs->apic_base = kvm_get_apic_base(vcpu);
6462
923c61bb 6463 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6464
36752c9b 6465 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6466 set_bit(vcpu->arch.interrupt.nr,
6467 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6468
b6c7a5dc
HB		 6469 return 0;
6470}
6471
62d9f0db
MT		 6472int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6473 struct kvm_mp_state *mp_state)
6474{
66450a21 6475 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6476 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6477 vcpu->arch.pv.pv_unhalted)
6478 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6479 else
6480 mp_state->mp_state = vcpu->arch.mp_state;
6481
62d9f0db
MT		 6482 return 0;
6483}
6484
6485int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6486 struct kvm_mp_state *mp_state)
6487{
66450a21
JK		 6488 if (!kvm_vcpu_has_lapic(vcpu) &&
6489 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6490 return -EINVAL;
6491
6492 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6493 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6494 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6495 } else
6496 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6497 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6498 return 0;
6499}
6500
7f3d35fd
KW		 6501int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6502 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6503{
9d74191a 6504 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6505 int ret;
e01c2426 6506
8ec4722d 6507 init_emulate_ctxt(vcpu);
c697518a 6508
7f3d35fd 6509 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6510 has_error_code, error_code);
c697518a 6511
c697518a 6512 if (ret)
19d04437 6513 return EMULATE_FAIL;
37817f29 6514
9d74191a
TY		 6515 kvm_rip_write(vcpu, ctxt->eip);
6516 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6517 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6518 return EMULATE_DONE;
37817f29
IE		 6519}
6520EXPORT_SYMBOL_GPL(kvm_task_switch);
6521
b6c7a5dc
HB		 6522int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6523 struct kvm_sregs *sregs)
6524{
58cb628d 6525 struct msr_data apic_base_msr;
b6c7a5dc 6526 int mmu_reset_needed = 0;
63f42e02 6527 int pending_vec, max_bits, idx;
89a27f4d 6528 struct desc_ptr dt;
b6c7a5dc 6529
6d1068b3
PM		 6530 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6531 return -EINVAL;
6532
89a27f4d
GN		 6533 dt.size = sregs->idt.limit;
6534 dt.address = sregs->idt.base;
b6c7a5dc 6535 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6536 dt.size = sregs->gdt.limit;
6537 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6538 kvm_x86_ops->set_gdt(vcpu, &dt);
6539
ad312c7c 6540 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6541 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6542 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6543 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6544
2d3ad1f4 6545 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6546
f6801dff 6547 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6548 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6549 apic_base_msr.data = sregs->apic_base;
6550 apic_base_msr.host_initiated = true;
6551 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6552
4d4ec087 6553 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6554 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6555 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6556
fc78f519 6557 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6558 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6559 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6560 kvm_update_cpuid(vcpu);
63f42e02
XG		 6561
6562 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6563 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6564 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6565 mmu_reset_needed = 1;
6566 }
63f42e02 6567 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6568
6569 if (mmu_reset_needed)
6570 kvm_mmu_reset_context(vcpu);
6571
a50abc3b 6572 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6573 pending_vec = find_first_bit(
6574 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6575 if (pending_vec < max_bits) {
66fd3f7f 6576 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6577 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6578 }
6579
3e6e0aab
GT		 6580 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6581 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6582 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6583 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6584 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6585 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6586
3e6e0aab
GT		 6587 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6588 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6589
5f0269f5
ME		 6590 update_cr8_intercept(vcpu);
6591
9c3e4aab 6592 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6593 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6594 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6595 !is_protmode(vcpu))
9c3e4aab
MT		 6596 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6597
3842d135
AK		 6598 kvm_make_request(KVM_REQ_EVENT, vcpu);
6599
b6c7a5dc
HB		 6600 return 0;
6601}
6602
d0bfb940
JK		 6603int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6604 struct kvm_guest_debug *dbg)
b6c7a5dc 6605{
355be0b9 6606 unsigned long rflags;
ae675ef0 6607 int i, r;
b6c7a5dc 6608
4f926bf2
JK		 6609 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6610 r = -EBUSY;
6611 if (vcpu->arch.exception.pending)
2122ff5e 6612 goto out;
4f926bf2
JK		 6613 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6614 kvm_queue_exception(vcpu, DB_VECTOR);
6615 else
6616 kvm_queue_exception(vcpu, BP_VECTOR);
6617 }
6618
91586a3b
JK		 6619 /*
6620 * Read rflags as long as potentially injected trace flags are still
6621 * filtered out.
6622 */
6623 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6624
6625 vcpu->guest_debug = dbg->control;
6626 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6627 vcpu->guest_debug = 0;
6628
6629 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6630 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6631 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6632 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6633 } else {
6634 for (i = 0; i < KVM_NR_DB_REGS; i++)
6635 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6636 }
c8639010 6637 kvm_update_dr7(vcpu);
ae675ef0 6638
f92653ee
JK		 6639 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6640 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6641 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6642
91586a3b
JK		 6643 /*
6644 * Trigger an rflags update that will inject or remove the trace
6645 * flags.
6646 */
6647 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6648
c8639010 6649 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6650
4f926bf2 6651 r = 0;
d0bfb940 6652
2122ff5e 6653out:
b6c7a5dc
HB		 6654
6655 return r;
6656}
6657
8b006791
ZX		 6658/*
6659 * Translate a guest virtual address to a guest physical address.
6660 */
6661int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6662 struct kvm_translation *tr)
6663{
6664 unsigned long vaddr = tr->linear_address;
6665 gpa_t gpa;
f656ce01 6666 int idx;
8b006791 6667
f656ce01 6668 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6669 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6670 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6671 tr->physical_address = gpa;
6672 tr->valid = gpa != UNMAPPED_GVA;
6673 tr->writeable = 1;
6674 tr->usermode = 0;
8b006791
ZX		 6675
6676 return 0;
6677}
6678
d0752060
HB		 6679int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6680{
98918833
SY		 6681 struct i387_fxsave_struct *fxsave =
6682 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6683
d0752060
HB		 6684 memcpy(fpu->fpr, fxsave->st_space, 128);
6685 fpu->fcw = fxsave->cwd;
6686 fpu->fsw = fxsave->swd;
6687 fpu->ftwx = fxsave->twd;
6688 fpu->last_opcode = fxsave->fop;
6689 fpu->last_ip = fxsave->rip;
6690 fpu->last_dp = fxsave->rdp;
6691 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6692
d0752060
HB		 6693 return 0;
6694}
6695
6696int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6697{
98918833
SY		 6698 struct i387_fxsave_struct *fxsave =
6699 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6700
d0752060
HB		 6701 memcpy(fxsave->st_space, fpu->fpr, 128);
6702 fxsave->cwd = fpu->fcw;
6703 fxsave->swd = fpu->fsw;
6704 fxsave->twd = fpu->ftwx;
6705 fxsave->fop = fpu->last_opcode;
6706 fxsave->rip = fpu->last_ip;
6707 fxsave->rdp = fpu->last_dp;
6708 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6709
d0752060
HB		 6710 return 0;
6711}
6712
10ab25cd 6713int fx_init(struct kvm_vcpu *vcpu)
d0752060 6714{
10ab25cd
JK		 6715 int err;
6716
6717 err = fpu_alloc(&vcpu->arch.guest_fpu);
6718 if (err)
6719 return err;
6720
98918833 6721 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6722
2acf923e
DC		 6723 /*
6724 * Ensure guest xcr0 is valid for loading
6725 */
6726 vcpu->arch.xcr0 = XSTATE_FP;
6727
ad312c7c 6728 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6729
6730 return 0;
d0752060
HB		 6731}
6732EXPORT_SYMBOL_GPL(fx_init);
6733
98918833
SY		 6734static void fx_free(struct kvm_vcpu *vcpu)
6735{
6736 fpu_free(&vcpu->arch.guest_fpu);
6737}
6738
d0752060
HB		 6739void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6740{
2608d7a1 6741 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6742 return;
6743
2acf923e
DC		 6744 /*
6745 * Restore all possible states in the guest,
6746 * and assume host would use all available bits.
6747 * Guest xcr0 would be loaded later.
6748 */
6749 kvm_put_guest_xcr0(vcpu);
d0752060 6750 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6751 __kernel_fpu_begin();
98918833 6752 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6753 trace_kvm_fpu(1);
d0752060 6754}
d0752060
HB		 6755
6756void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6757{
2acf923e
DC		 6758 kvm_put_guest_xcr0(vcpu);
6759
d0752060
HB		 6760 if (!vcpu->guest_fpu_loaded)
6761 return;
6762
6763 vcpu->guest_fpu_loaded = 0;
98918833 6764 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6765 __kernel_fpu_end();
f096ed85 6766 ++vcpu->stat.fpu_reload;
a8eeb04a 6767 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6768 trace_kvm_fpu(0);
d0752060 6769}
e9b11c17
ZX		 6770
6771void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6772{
12f9a48f 6773 kvmclock_reset(vcpu);
7f1ea208 6774
f5f48ee1 6775 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6776 fx_free(vcpu);
e9b11c17
ZX		 6777 kvm_x86_ops->vcpu_free(vcpu);
6778}
6779
6780struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6781 unsigned int id)
6782{
6755bae8
ZA		 6783 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6784 printk_once(KERN_WARNING
6785 "kvm: SMP vm created on host with unstable TSC; "
6786 "guest TSC will not be reliable\n");
26e5215f
AK		 6787 return kvm_x86_ops->vcpu_create(kvm, id);
6788}
e9b11c17 6789
26e5215f
AK		 6790int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6791{
6792 int r;
e9b11c17 6793
0bed3b56 6794 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6795 r = vcpu_load(vcpu);
6796 if (r)
6797 return r;
57f252f2 6798 kvm_vcpu_reset(vcpu);
8a3c1a33 6799 kvm_mmu_setup(vcpu);
e9b11c17 6800 vcpu_put(vcpu);
e9b11c17 6801
26e5215f 6802 return r;
e9b11c17
ZX		 6803}
6804
42897d86
MT		 6805int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6806{
6807 int r;
8fe8ab46 6808 struct msr_data msr;
332967a3 6809 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6810
6811 r = vcpu_load(vcpu);
6812 if (r)
6813 return r;
8fe8ab46
WA		 6814 msr.data = 0x0;
6815 msr.index = MSR_IA32_TSC;
6816 msr.host_initiated = true;
6817 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6818 vcpu_put(vcpu);
6819
332967a3
AJ		 6820 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6821 KVMCLOCK_SYNC_PERIOD);
6822
42897d86
MT		 6823 return r;
6824}
6825
d40ccc62 6826void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6827{
9fc77441 6828 int r;
344d9588
GN		 6829 vcpu->arch.apf.msr_val = 0;
6830
9fc77441
MT		 6831 r = vcpu_load(vcpu);
6832 BUG_ON(r);
e9b11c17
ZX		 6833 kvm_mmu_unload(vcpu);
6834 vcpu_put(vcpu);
6835
98918833 6836 fx_free(vcpu);
e9b11c17
ZX		 6837 kvm_x86_ops->vcpu_free(vcpu);
6838}
6839
66450a21 6840void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6841{
7460fb4a
AK		 6842 atomic_set(&vcpu->arch.nmi_queued, 0);
6843 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6844 vcpu->arch.nmi_injected = false;
6845
42dbaa5a
JK		 6846 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6847 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6848 kvm_update_dr6(vcpu);
42dbaa5a 6849 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6850 kvm_update_dr7(vcpu);
42dbaa5a 6851
3842d135 6852 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6853 vcpu->arch.apf.msr_val = 0;
c9aaa895 6854 vcpu->arch.st.msr_val = 0;
3842d135 6855
12f9a48f
GC		 6856 kvmclock_reset(vcpu);
6857
af585b92
GN		 6858 kvm_clear_async_pf_completion_queue(vcpu);
6859 kvm_async_pf_hash_reset(vcpu);
6860 vcpu->arch.apf.halted = false;
3842d135 6861
f5132b01
GN		 6862 kvm_pmu_reset(vcpu);
6863
66f7b72e
JS		 6864 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6865 vcpu->arch.regs_avail = ~0;
6866 vcpu->arch.regs_dirty = ~0;
6867
57f252f2 6868 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6869}
6870
66450a21
JK		 6871void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6872{
6873 struct kvm_segment cs;
6874
6875 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6876 cs.selector = vector << 8;
6877 cs.base = vector << 12;
6878 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6879 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6880}
6881
10474ae8 6882int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6883{
ca84d1a2
ZA		 6884 struct kvm *kvm;
6885 struct kvm_vcpu *vcpu;
6886 int i;
0dd6a6ed
ZA		 6887 int ret;
6888 u64 local_tsc;
6889 u64 max_tsc = 0;
6890 bool stable, backwards_tsc = false;
18863bdd
AK		 6891
6892 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6893 ret = kvm_x86_ops->hardware_enable(garbage);
6894 if (ret != 0)
6895 return ret;
6896
6897 local_tsc = native_read_tsc();
6898 stable = !check_tsc_unstable();
6899 list_for_each_entry(kvm, &vm_list, vm_list) {
6900 kvm_for_each_vcpu(i, vcpu, kvm) {
6901 if (!stable && vcpu->cpu == smp_processor_id())
6902 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6903 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6904 backwards_tsc = true;
6905 if (vcpu->arch.last_host_tsc > max_tsc)
6906 max_tsc = vcpu->arch.last_host_tsc;
6907 }
6908 }
6909 }
6910
6911 /*
6912 * Sometimes, even reliable TSCs go backwards. This happens on
6913 * platforms that reset TSC during suspend or hibernate actions, but
6914 * maintain synchronization. We must compensate. Fortunately, we can
6915 * detect that condition here, which happens early in CPU bringup,
6916 * before any KVM threads can be running. Unfortunately, we can't
6917 * bring the TSCs fully up to date with real time, as we aren't yet far
6918 * enough into CPU bringup that we know how much real time has actually
6919 * elapsed; our helper function, get_kernel_ns() will be using boot
6920 * variables that haven't been updated yet.
6921 *
6922 * So we simply find the maximum observed TSC above, then record the
6923 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6924 * the adjustment will be applied. Note that we accumulate
6925 * adjustments, in case multiple suspend cycles happen before some VCPU
6926 * gets a chance to run again. In the event that no KVM threads get a
6927 * chance to run, we will miss the entire elapsed period, as we'll have
6928 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6929 * loose cycle time. This isn't too big a deal, since the loss will be
6930 * uniform across all VCPUs (not to mention the scenario is extremely
6931 * unlikely). It is possible that a second hibernate recovery happens
6932 * much faster than a first, causing the observed TSC here to be
6933 * smaller; this would require additional padding adjustment, which is
6934 * why we set last_host_tsc to the local tsc observed here.
6935 *
6936 * N.B. - this code below runs only on platforms with reliable TSC,
6937 * as that is the only way backwards_tsc is set above. Also note
6938 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6939 * have the same delta_cyc adjustment applied if backwards_tsc
6940 * is detected. Note further, this adjustment is only done once,
6941 * as we reset last_host_tsc on all VCPUs to stop this from being
6942 * called multiple times (one for each physical CPU bringup).
6943 *
4a969980 6944 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6945 * will be compensated by the logic in vcpu_load, which sets the TSC to
6946 * catchup mode. This will catchup all VCPUs to real time, but cannot
6947 * guarantee that they stay in perfect synchronization.
6948 */
6949 if (backwards_tsc) {
6950 u64 delta_cyc = max_tsc - local_tsc;
16a96021 6951 backwards_tsc_observed = true;
0dd6a6ed
ZA		 6952 list_for_each_entry(kvm, &vm_list, vm_list) {
6953 kvm_for_each_vcpu(i, vcpu, kvm) {
6954 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6955 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6956 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6957 &vcpu->requests);
0dd6a6ed
ZA		 6958 }
6959
6960 /*
6961 * We have to disable TSC offset matching.. if you were
6962 * booting a VM while issuing an S4 host suspend....
6963 * you may have some problem. Solving this issue is
6964 * left as an exercise to the reader.
6965 */
6966 kvm->arch.last_tsc_nsec = 0;
6967 kvm->arch.last_tsc_write = 0;
6968 }
6969
6970 }
6971 return 0;
e9b11c17
ZX		 6972}
6973
6974void kvm_arch_hardware_disable(void *garbage)
6975{
6976 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6977 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6978}
6979
6980int kvm_arch_hardware_setup(void)
6981{
6982 return kvm_x86_ops->hardware_setup();
6983}
6984
6985void kvm_arch_hardware_unsetup(void)
6986{
6987 kvm_x86_ops->hardware_unsetup();
6988}
6989
6990void kvm_arch_check_processor_compat(void *rtn)
6991{
6992 kvm_x86_ops->check_processor_compatibility(rtn);
6993}
6994
3e515705
AK		 6995bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6996{
6997 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6998}
6999
54e9818f
GN		 7000struct static_key kvm_no_apic_vcpu __read_mostly;
7001
e9b11c17
ZX		 7002int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7003{
7004 struct page *page;
7005 struct kvm *kvm;
7006 int r;
7007
7008 BUG_ON(vcpu->kvm == NULL);
7009 kvm = vcpu->kvm;
7010
6aef266c 7011 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7012 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7013 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7014 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7015 else
a4535290 7016 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7017
7018 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7019 if (!page) {
7020 r = -ENOMEM;
7021 goto fail;
7022 }
ad312c7c 7023 vcpu->arch.pio_data = page_address(page);
e9b11c17 7024
cc578287 7025 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7026
e9b11c17
ZX		 7027 r = kvm_mmu_create(vcpu);
7028 if (r < 0)
7029 goto fail_free_pio_data;
7030
7031 if (irqchip_in_kernel(kvm)) {
7032 r = kvm_create_lapic(vcpu);
7033 if (r < 0)
7034 goto fail_mmu_destroy;
54e9818f
GN		 7035 } else
7036 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7037
890ca9ae
HY		 7038 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7039 GFP_KERNEL);
7040 if (!vcpu->arch.mce_banks) {
7041 r = -ENOMEM;
443c39bc 7042 goto fail_free_lapic;
890ca9ae
HY		 7043 }
7044 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7045
f1797359
WY		 7046 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7047 r = -ENOMEM;
f5f48ee1 7048 goto fail_free_mce_banks;
f1797359 7049 }
f5f48ee1 7050
66f7b72e
JS		 7051 r = fx_init(vcpu);
7052 if (r)
7053 goto fail_free_wbinvd_dirty_mask;
7054
ba904635 7055 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7056 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7057
7058 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7059 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7060
af585b92 7061 kvm_async_pf_hash_reset(vcpu);
f5132b01 7062 kvm_pmu_init(vcpu);
af585b92 7063
e9b11c17 7064 return 0;
66f7b72e
JS		 7065fail_free_wbinvd_dirty_mask:
7066 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7067fail_free_mce_banks:
7068 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7069fail_free_lapic:
7070 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7071fail_mmu_destroy:
7072 kvm_mmu_destroy(vcpu);
7073fail_free_pio_data:
ad312c7c 7074 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7075fail:
7076 return r;
7077}
7078
7079void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7080{
f656ce01
MT		 7081 int idx;
7082
f5132b01 7083 kvm_pmu_destroy(vcpu);
36cb93fd 7084 kfree(vcpu->arch.mce_banks);
e9b11c17 7085 kvm_free_lapic(vcpu);
f656ce01 7086 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7087 kvm_mmu_destroy(vcpu);
f656ce01 7088 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7089 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7090 if (!irqchip_in_kernel(vcpu->kvm))
7091 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7092}
d19a9cd2 7093
e08b9637 7094int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7095{
e08b9637
CO		 7096 if (type)
7097 return -EINVAL;
7098
f05e70ac 7099 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7100 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7101 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7102 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7103
5550af4d
SY		 7104 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7105 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7106 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7107 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7108 &kvm->arch.irq_sources_bitmap);
5550af4d 7109
038f8c11 7110 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7111 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7112 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7113
7114 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7115
7e44e449 7116 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7117 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7118
d89f5eff 7119 return 0;
d19a9cd2
ZX		 7120}
7121
7122static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7123{
9fc77441
MT		 7124 int r;
7125 r = vcpu_load(vcpu);
7126 BUG_ON(r);
d19a9cd2
ZX		 7127 kvm_mmu_unload(vcpu);
7128 vcpu_put(vcpu);
7129}
7130
7131static void kvm_free_vcpus(struct kvm *kvm)
7132{
7133 unsigned int i;
988a2cae 7134 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7135
7136 /*
7137 * Unpin any mmu pages first.
7138 */
af585b92
GN		 7139 kvm_for_each_vcpu(i, vcpu, kvm) {
7140 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7141 kvm_unload_vcpu_mmu(vcpu);
af585b92 7142 }
988a2cae
GN		 7143 kvm_for_each_vcpu(i, vcpu, kvm)
7144 kvm_arch_vcpu_free(vcpu);
7145
7146 mutex_lock(&kvm->lock);
7147 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7148 kvm->vcpus[i] = NULL;
d19a9cd2 7149
988a2cae
GN		 7150 atomic_set(&kvm->online_vcpus, 0);
7151 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7152}
7153
ad8ba2cd
SY		 7154void kvm_arch_sync_events(struct kvm *kvm)
7155{
332967a3 7156 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7157 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7158 kvm_free_all_assigned_devices(kvm);
aea924f6 7159 kvm_free_pit(kvm);
ad8ba2cd
SY		 7160}
7161
d19a9cd2
ZX		 7162void kvm_arch_destroy_vm(struct kvm *kvm)
7163{
27469d29
AH		 7164 if (current->mm == kvm->mm) {
7165 /*
7166 * Free memory regions allocated on behalf of userspace,
7167 * unless the the memory map has changed due to process exit
7168 * or fd copying.
7169 */
7170 struct kvm_userspace_memory_region mem;
7171 memset(&mem, 0, sizeof(mem));
7172 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7173 kvm_set_memory_region(kvm, &mem);
7174
7175 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7176 kvm_set_memory_region(kvm, &mem);
7177
7178 mem.slot = TSS_PRIVATE_MEMSLOT;
7179 kvm_set_memory_region(kvm, &mem);
7180 }
6eb55818 7181 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7182 kfree(kvm->arch.vpic);
7183 kfree(kvm->arch.vioapic);
d19a9cd2 7184 kvm_free_vcpus(kvm);
3d45830c
AK		 7185 if (kvm->arch.apic_access_page)
7186 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7187 if (kvm->arch.ept_identity_pagetable)
7188 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7189 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7190}
0de10343 7191
5587027c 7192void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7193 struct kvm_memory_slot *dont)
7194{
7195 int i;
7196
d89cc617
TY		 7197 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7198 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7199 kvm_kvfree(free->arch.rmap[i]);
7200 free->arch.rmap[i] = NULL;
77d11309 7201 }
d89cc617
TY		 7202 if (i == 0)
7203 continue;
7204
7205 if (!dont || free->arch.lpage_info[i - 1] !=
7206 dont->arch.lpage_info[i - 1]) {
7207 kvm_kvfree(free->arch.lpage_info[i - 1]);
7208 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7209 }
7210 }
7211}
7212
5587027c
AK		 7213int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7214 unsigned long npages)
db3fe4eb
TY		 7215{
7216 int i;
7217
d89cc617 7218 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7219 unsigned long ugfn;
7220 int lpages;
d89cc617 7221 int level = i + 1;
db3fe4eb
TY		 7222
7223 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7224 slot->base_gfn, level) + 1;
7225
d89cc617
TY		 7226 slot->arch.rmap[i] =
7227 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7228 if (!slot->arch.rmap[i])
77d11309 7229 goto out_free;
d89cc617
TY		 7230 if (i == 0)
7231 continue;
77d11309 7232
d89cc617
TY		 7233 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7234 sizeof(*slot->arch.lpage_info[i - 1]));
7235 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7236 goto out_free;
7237
7238 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7239 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7240 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7241 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7242 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7243 /*
7244 * If the gfn and userspace address are not aligned wrt each
7245 * other, or if explicitly asked to, disable large page
7246 * support for this slot
7247 */
7248 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7249 !kvm_largepages_enabled()) {
7250 unsigned long j;
7251
7252 for (j = 0; j < lpages; ++j)
d89cc617 7253 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7254 }
7255 }
7256
7257 return 0;
7258
7259out_free:
d89cc617
TY		 7260 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7261 kvm_kvfree(slot->arch.rmap[i]);
7262 slot->arch.rmap[i] = NULL;
7263 if (i == 0)
7264 continue;
7265
7266 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7267 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7268 }
7269 return -ENOMEM;
7270}
7271
e59dbe09
TY		 7272void kvm_arch_memslots_updated(struct kvm *kvm)
7273{
e6dff7d1
TY		 7274 /*
7275 * memslots->generation has been incremented.
7276 * mmio generation may have reached its maximum value.
7277 */
7278 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7279}
7280
f7784b8e
MT		 7281int kvm_arch_prepare_memory_region(struct kvm *kvm,
7282 struct kvm_memory_slot *memslot,
f7784b8e 7283 struct kvm_userspace_memory_region *mem,
7b6195a9 7284 enum kvm_mr_change change)
0de10343 7285{
7a905b14
TY		 7286 /*
7287 * Only private memory slots need to be mapped here since
7288 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7289 */
7b6195a9 7290 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7291 unsigned long userspace_addr;
604b38ac 7292
7a905b14
TY		 7293 /*
7294 * MAP_SHARED to prevent internal slot pages from being moved
7295 * by fork()/COW.
7296 */
7b6195a9 7297 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7298 PROT_READ | PROT_WRITE,
7299 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7300
7a905b14
TY		 7301 if (IS_ERR((void *)userspace_addr))
7302 return PTR_ERR((void *)userspace_addr);
604b38ac 7303
7a905b14 7304 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7305 }
7306
f7784b8e
MT		 7307 return 0;
7308}
7309
7310void kvm_arch_commit_memory_region(struct kvm *kvm,
7311 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7312 const struct kvm_memory_slot *old,
7313 enum kvm_mr_change change)
f7784b8e
MT		 7314{
7315
8482644a 7316 int nr_mmu_pages = 0;
f7784b8e 7317
8482644a 7318 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7319 int ret;
7320
8482644a
TY		 7321 ret = vm_munmap(old->userspace_addr,
7322 old->npages * PAGE_SIZE);
f7784b8e
MT		 7323 if (ret < 0)
7324 printk(KERN_WARNING
7325 "kvm_vm_ioctl_set_memory_region: "
7326 "failed to munmap memory\n");
7327 }
7328
48c0e4e9
XG		 7329 if (!kvm->arch.n_requested_mmu_pages)
7330 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7331
48c0e4e9 7332 if (nr_mmu_pages)
0de10343 7333 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7334 /*
7335 * Write protect all pages for dirty logging.
c126d94f
XG		 7336 *
7337 * All the sptes including the large sptes which point to this
7338 * slot are set to readonly. We can not create any new large
7339 * spte on this slot until the end of the logging.
7340 *
7341 * See the comments in fast_page_fault().
c972f3b1 7342 */
8482644a 7343 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7344 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7345}
1d737c8a 7346
2df72e9b 7347void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7348{
6ca18b69 7349 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7350}
7351
2df72e9b
MT		 7352void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7353 struct kvm_memory_slot *slot)
7354{
6ca18b69 7355 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7356}
7357
1d737c8a
ZX		 7358int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7359{
b6b8a145
JK		 7360 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7361 kvm_x86_ops->check_nested_events(vcpu, false);
7362
af585b92
GN		 7363 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7364 !vcpu->arch.apf.halted)
7365 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7366 || kvm_apic_has_events(vcpu)
6aef266c 7367 || vcpu->arch.pv.pv_unhalted
7460fb4a 7368 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7369 (kvm_arch_interrupt_allowed(vcpu) &&
7370 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7371}
5736199a 7372
b6d33834 7373int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7374{
b6d33834 7375 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7376}
78646121
GN		 7377
7378int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7379{
7380 return kvm_x86_ops->interrupt_allowed(vcpu);
7381}
229456fc 7382
f92653ee
JK		 7383bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7384{
7385 unsigned long current_rip = kvm_rip_read(vcpu) +
7386 get_segment_base(vcpu, VCPU_SREG_CS);
7387
7388 return current_rip == linear_rip;
7389}
7390EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7391
94fe45da
JK		 7392unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7393{
7394 unsigned long rflags;
7395
7396 rflags = kvm_x86_ops->get_rflags(vcpu);
7397 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7398 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7399 return rflags;
7400}
7401EXPORT_SYMBOL_GPL(kvm_get_rflags);
7402
7403void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7404{
7405 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7406 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7407 rflags |= X86_EFLAGS_TF;
94fe45da 7408 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7409 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7410}
7411EXPORT_SYMBOL_GPL(kvm_set_rflags);
7412
56028d08
GN		 7413void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7414{
7415 int r;
7416
fb67e14f 7417 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7418 work->wakeup_all)
56028d08
GN		 7419 return;
7420
7421 r = kvm_mmu_reload(vcpu);
7422 if (unlikely(r))
7423 return;
7424
fb67e14f
XG		 7425 if (!vcpu->arch.mmu.direct_map &&
7426 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7427 return;
7428
56028d08
GN		 7429 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7430}
7431
af585b92
GN		 7432static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7433{
7434 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7435}
7436
7437static inline u32 kvm_async_pf_next_probe(u32 key)
7438{
7439 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7440}
7441
7442static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7443{
7444 u32 key = kvm_async_pf_hash_fn(gfn);
7445
7446 while (vcpu->arch.apf.gfns[key] != ~0)
7447 key = kvm_async_pf_next_probe(key);
7448
7449 vcpu->arch.apf.gfns[key] = gfn;
7450}
7451
7452static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7453{
7454 int i;
7455 u32 key = kvm_async_pf_hash_fn(gfn);
7456
7457 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7458 (vcpu->arch.apf.gfns[key] != gfn &&
7459 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7460 key = kvm_async_pf_next_probe(key);
7461
7462 return key;
7463}
7464
7465bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7466{
7467 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7468}
7469
7470static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7471{
7472 u32 i, j, k;
7473
7474 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7475 while (true) {
7476 vcpu->arch.apf.gfns[i] = ~0;
7477 do {
7478 j = kvm_async_pf_next_probe(j);
7479 if (vcpu->arch.apf.gfns[j] == ~0)
7480 return;
7481 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7482 /*
7483 * k lies cyclically in ]i,j]
7484 * | i.k.j |
7485 * |....j i.k.| or |.k..j i...|
7486 */
7487 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7488 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7489 i = j;
7490 }
7491}
7492
7c90705b
GN		 7493static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7494{
7495
7496 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7497 sizeof(val));
7498}
7499
af585b92
GN		 7500void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7501 struct kvm_async_pf *work)
7502{
6389ee94
AK		 7503 struct x86_exception fault;
7504
7c90705b 7505 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7506 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7507
7508 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7509 (vcpu->arch.apf.send_user_only &&
7510 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7511 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7512 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7513 fault.vector = PF_VECTOR;
7514 fault.error_code_valid = true;
7515 fault.error_code = 0;
7516 fault.nested_page_fault = false;
7517 fault.address = work->arch.token;
7518 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7519 }
af585b92
GN		 7520}
7521
7522void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7523 struct kvm_async_pf *work)
7524{
6389ee94
AK		 7525 struct x86_exception fault;
7526
7c90705b 7527 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7528 if (work->wakeup_all)
7c90705b
GN		 7529 work->arch.token = ~0; /* broadcast wakeup */
7530 else
7531 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7532
7533 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7534 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7535 fault.vector = PF_VECTOR;
7536 fault.error_code_valid = true;
7537 fault.error_code = 0;
7538 fault.nested_page_fault = false;
7539 fault.address = work->arch.token;
7540 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7541 }
e6d53e3b 7542 vcpu->arch.apf.halted = false;
a4fa1635 7543 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7544}
7545
7546bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7547{
7548 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7549 return true;
7550 else
7551 return !kvm_event_needs_reinjection(vcpu) &&
7552 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7553}
7554
e0f0bbc5
AW		 7555void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7556{
7557 atomic_inc(&kvm->arch.noncoherent_dma_count);
7558}
7559EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7560
7561void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7562{
7563 atomic_dec(&kvm->arch.noncoherent_dma_count);
7564}
7565EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7566
7567bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7568{
7569 return atomic_read(&kvm->arch.noncoherent_dma_count);
7570}
7571EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7572
229456fc
MT		 7573EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7574EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7575EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7576EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7577EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7578EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7579EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7580EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7581EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7582EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7583EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7584EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git