lib/i386-ports.c

   1 /*
   2  *      The PCI Library -- Direct Configuration access via i386 Ports
   3  *
   4  *      Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #define _GNU_SOURCE
  10
  11 #include "internal.h"
  12
  13 #include <unistd.h>
  14
  15 #if defined(PCI_OS_LINUX)
  16 #include "i386-io-linux.h"
  17 #elif defined(PCI_OS_GNU)
  18 #include "i386-io-hurd.h"
  19 #elif defined(PCI_OS_SUNOS)
  20 #include "i386-io-sunos.h"
  21 #elif defined(PCI_OS_WINDOWS)
  22 #include "i386-io-windows.h"
  23 #elif defined(PCI_OS_CYGWIN)
  24 #include "i386-io-cygwin.h"
  25 #else
  26 #error Do not know how to access I/O ports on this OS.
  27 #endif
  28
  29 static int conf12_io_enabled = -1;              /* -1=haven't tried, 0=failed, 1=succeeded */
  30
  31 static int
  32 conf12_setup_io(struct pci_access *a)
  33 {
  34   if (conf12_io_enabled < 0)
  35     conf12_io_enabled = intel_setup_io(a);
  36   return conf12_io_enabled;
  37 }
  38
  39 static void
  40 conf12_init(struct pci_access *a)
  41 {
  42   if (!conf12_setup_io(a))
  43     a->error("No permission to access I/O ports (you probably have to be root).");
  44 }
  45
  46 static void
  47 conf12_cleanup(struct pci_access *a UNUSED)
  48 {
  49   if (conf12_io_enabled > 0)
  50     conf12_io_enabled = intel_cleanup_io(a);
  51 }
  52
  53 /*
  54  * Before we decide to use direct hardware access mechanisms, we try to do some
  55  * trivial checks to ensure it at least _seems_ to be working -- we just test
  56  * whether bus 00 contains a host bridge (this is similar to checking
  57  * techniques used in XFree86, but ours should be more reliable since we
  58  * attempt to make use of direct access hints provided by the PCI BIOS).
  59  *
  60  * This should be close to trivial, but it isn't, because there are buggy
  61  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  62  */
  63
  64 static int
  65 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
  66 {
  67   struct pci_dev d;
  68
  69   a->debug("...sanity check");
  70   d.bus = 0;
  71   d.func = 0;
  72   for(d.dev = 0; d.dev < 32; d.dev++)
  73     {
  74       u16 class, vendor;
  75       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
  76           (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
  77           m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
  78           (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
  79         {
  80           a->debug("...outside the Asylum at 0/%02x/0", d.dev);
  81           return 1;
  82         }
  83     }
  84   a->debug("...insane");
  85   return 0;
  86 }
  87
  88 /*
  89  *      Configuration type 1
  90  */
  91
  92 #define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
  93
  94 static int
  95 conf1_detect(struct pci_access *a)
  96 {
  97   unsigned int tmp;
  98   int res = 0;
  99
 100   if (!conf12_setup_io(a))
 101     {
 102       a->debug("...no I/O permission");
 103       return 0;
 104     }
 105   outb (0x01, 0xCFB);
 106   tmp = inl (0xCF8);
 107   outl (0x80000000, 0xCF8);
 108   if (inl (0xCF8) == 0x80000000)
 109     res = 1;
 110   outl (tmp, 0xCF8);
 111   if (res)
 112     res = intel_sanity_check(a, &pm_intel_conf1);
 113   return res;
 114 }
 115
 116 static int
 117 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 118 {
 119   int addr = 0xcfc + (pos&3);
 120
 121   if (pos >= 256)
 122     return 0;
 123
 124   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 125
 126   switch (len)
 127     {
 128     case 1:
 129       buf[0] = inb(addr);
 130       break;
 131     case 2:
 132       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 133       break;
 134     case 4:
 135       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 136       break;
 137     default:
 138       return pci_generic_block_read(d, pos, buf, len);
 139     }
 140   return 1;
 141 }
 142
 143 static int
 144 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 145 {
 146   int addr = 0xcfc + (pos&3);
 147
 148   if (pos >= 256)
 149     return 0;
 150
 151   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 152
 153   switch (len)
 154     {
 155     case 1:
 156       outb(buf[0], addr);
 157       break;
 158     case 2:
 159       outw(le16_to_cpu(((u16 *) buf)[0]), addr);
 160       break;
 161     case 4:
 162       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
 163       break;
 164     default:
 165       return pci_generic_block_write(d, pos, buf, len);
 166     }
 167   return 1;
 168 }
 169
 170 /*
 171  *      Configuration type 2. Obsolete and brain-damaged, but existing.
 172  */
 173
 174 static int
 175 conf2_detect(struct pci_access *a)
 176 {
 177   if (!conf12_setup_io(a))
 178     {
 179       a->debug("...no I/O permission");
 180       return 0;
 181     }
 182
 183   /* This is ugly and tends to produce false positives. Beware. */
 184
 185   outb(0x00, 0xCFB);
 186   outb(0x00, 0xCF8);
 187   outb(0x00, 0xCFA);
 188   if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
 189     return intel_sanity_check(a, &pm_intel_conf2);
 190   else
 191     return 0;
 192 }
 193
 194 static int
 195 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 196 {
 197   int addr = 0xc000 | (d->dev << 8) | pos;
 198
 199   if (pos >= 256)
 200     return 0;
 201
 202   if (d->dev >= 16)
 203     /* conf2 supports only 16 devices per bus */
 204     return 0;
 205   outb((d->func << 1) | 0xf0, 0xcf8);
 206   outb(d->bus, 0xcfa);
 207   switch (len)
 208     {
 209     case 1:
 210       buf[0] = inb(addr);
 211       break;
 212     case 2:
 213       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 214       break;
 215     case 4:
 216       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 217       break;
 218     default:
 219       outb(0, 0xcf8);
 220       return pci_generic_block_read(d, pos, buf, len);
 221     }
 222   outb(0, 0xcf8);
 223   return 1;
 224 }
 225
 226 static int
 227 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 228 {
 229   int addr = 0xc000 | (d->dev << 8) | pos;
 230
 231   if (pos >= 256)
 232     return 0;
 233
 234   if (d->dev >= 16)
 235     d->access->error("conf2_write: only first 16 devices exist.");
 236   outb((d->func << 1) | 0xf0, 0xcf8);
 237   outb(d->bus, 0xcfa);
 238   switch (len)
 239     {
 240     case 1:
 241       outb(buf[0], addr);
 242       break;
 243     case 2:
 244       outw(le16_to_cpu(* (u16 *) buf), addr);
 245       break;
 246     case 4:
 247       outl(le32_to_cpu(* (u32 *) buf), addr);
 248       break;
 249     default:
 250       outb(0, 0xcf8);
 251       return pci_generic_block_write(d, pos, buf, len);
 252     }
 253   outb(0, 0xcf8);
 254   return 1;
 255 }
 256
 257 struct pci_methods pm_intel_conf1 = {
 258   "intel-conf1",
 259   "Raw I/O port access using Intel conf1 interface",
 260   NULL,                                 /* config */
 261   conf1_detect,
 262   conf12_init,
 263   conf12_cleanup,
 264   pci_generic_scan,
 265   pci_generic_fill_info,
 266   conf1_read,
 267   conf1_write,
 268   NULL,                                 /* init_dev */
 269   NULL                                  /* cleanup_dev */
 270 };
 271
 272 struct pci_methods pm_intel_conf2 = {
 273   "intel-conf2",
 274   "Raw I/O port access using Intel conf2 interface",
 275   NULL,                                 /* config */
 276   conf2_detect,
 277   conf12_init,
 278   conf12_cleanup,
 279   pci_generic_scan,
 280   pci_generic_fill_info,
 281   conf2_read,
 282   conf2_write,
 283   NULL,                                 /* init_dev */
 284   NULL                                  /* cleanup_dev */
 285 };