lib/i386-ports.c

   1 /*
   2  *      The PCI Library -- Direct Configuration access via i386 Ports
   3  *
   4  *      Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #define _GNU_SOURCE
  10
  11 #include "internal.h"
  12
  13 #include <unistd.h>
  14
  15 #if defined(PCI_OS_LINUX)
  16 #include "i386-io-linux.h"
  17 #elif defined(PCI_OS_GNU)
  18 #include "i386-io-hurd.h"
  19 #elif defined(PCI_OS_SUNOS)
  20 #include "i386-io-sunos.h"
  21 #elif defined(PCI_OS_WINDOWS)
  22 #include "i386-io-windows.h"
  23 #else
  24 #error Do not know how to access I/O ports on this OS.
  25 #endif
  26
  27 static void
  28 conf12_init(struct pci_access *a)
  29 {
  30   if (!intel_setup_io())
  31     a->error("You need to be root to have access to I/O ports.");
  32 }
  33
  34 static void
  35 conf12_cleanup(struct pci_access *a UNUSED)
  36 {
  37   intel_cleanup_io();
  38 }
  39
  40 /*
  41  * Before we decide to use direct hardware access mechanisms, we try to do some
  42  * trivial checks to ensure it at least _seems_ to be working -- we just test
  43  * whether bus 00 contains a host bridge (this is similar to checking
  44  * techniques used in XFree86, but ours should be more reliable since we
  45  * attempt to make use of direct access hints provided by the PCI BIOS).
  46  *
  47  * This should be close to trivial, but it isn't, because there are buggy
  48  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  49  */
  50
  51 static int
  52 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
  53 {
  54   struct pci_dev d;
  55
  56   a->debug("...sanity check");
  57   d.bus = 0;
  58   d.func = 0;
  59   for(d.dev = 0; d.dev < 32; d.dev++)
  60     {
  61       u16 class, vendor;
  62       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
  63           (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
  64           m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
  65           (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
  66         {
  67           a->debug("...outside the Asylum at 0/%02x/0", d.dev);
  68           return 1;
  69         }
  70     }
  71   a->debug("...insane");
  72   return 0;
  73 }
  74
  75 /*
  76  *      Configuration type 1
  77  */
  78
  79 #define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
  80
  81 static int
  82 conf1_detect(struct pci_access *a)
  83 {
  84   unsigned int tmp;
  85   int res = 0;
  86
  87   if (!intel_setup_io())
  88     {
  89       a->debug("...no I/O permission");
  90       return 0;
  91     }
  92   outb (0x01, 0xCFB);
  93   tmp = inl (0xCF8);
  94   outl (0x80000000, 0xCF8);
  95   if (inl (0xCF8) == 0x80000000)
  96     res = 1;
  97   outl (tmp, 0xCF8);
  98   if (res)
  99     res = intel_sanity_check(a, &pm_intel_conf1);
 100   return res;
 101 }
 102
 103 static int
 104 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 105 {
 106   int addr = 0xcfc + (pos&3);
 107
 108   if (pos >= 256)
 109     return 0;
 110
 111   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 112
 113   switch (len)
 114     {
 115     case 1:
 116       buf[0] = inb(addr);
 117       break;
 118     case 2:
 119       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 120       break;
 121     case 4:
 122       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 123       break;
 124     default:
 125       return pci_generic_block_read(d, pos, buf, len);
 126     }
 127   return 1;
 128 }
 129
 130 static int
 131 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 132 {
 133   int addr = 0xcfc + (pos&3);
 134
 135   if (pos >= 256)
 136     return 0;
 137
 138   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 139
 140   switch (len)
 141     {
 142     case 1:
 143       outb(buf[0], addr);
 144       break;
 145     case 2:
 146       outw(le16_to_cpu(((u16 *) buf)[0]), addr);
 147       break;
 148     case 4:
 149       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
 150       break;
 151     default:
 152       return pci_generic_block_write(d, pos, buf, len);
 153     }
 154   return 1;
 155 }
 156
 157 /*
 158  *      Configuration type 2. Obsolete and brain-damaged, but existing.
 159  */
 160
 161 static int
 162 conf2_detect(struct pci_access *a)
 163 {
 164   if (!intel_setup_io())
 165     {
 166       a->debug("...no I/O permission");
 167       return 0;
 168     }
 169
 170   /* This is ugly and tends to produce false positives. Beware. */
 171
 172   outb(0x00, 0xCFB);
 173   outb(0x00, 0xCF8);
 174   outb(0x00, 0xCFA);
 175   if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
 176     return intel_sanity_check(a, &pm_intel_conf2);
 177   else
 178     return 0;
 179 }
 180
 181 static int
 182 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 183 {
 184   int addr = 0xc000 | (d->dev << 8) | pos;
 185
 186   if (pos >= 256)
 187     return 0;
 188
 189   if (d->dev >= 16)
 190     /* conf2 supports only 16 devices per bus */
 191     return 0;
 192   outb((d->func << 1) | 0xf0, 0xcf8);
 193   outb(d->bus, 0xcfa);
 194   switch (len)
 195     {
 196     case 1:
 197       buf[0] = inb(addr);
 198       break;
 199     case 2:
 200       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 201       break;
 202     case 4:
 203       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 204       break;
 205     default:
 206       outb(0, 0xcf8);
 207       return pci_generic_block_read(d, pos, buf, len);
 208     }
 209   outb(0, 0xcf8);
 210   return 1;
 211 }
 212
 213 static int
 214 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 215 {
 216   int addr = 0xc000 | (d->dev << 8) | pos;
 217
 218   if (pos >= 256)
 219     return 0;
 220
 221   if (d->dev >= 16)
 222     d->access->error("conf2_write: only first 16 devices exist.");
 223   outb((d->func << 1) | 0xf0, 0xcf8);
 224   outb(d->bus, 0xcfa);
 225   switch (len)
 226     {
 227     case 1:
 228       outb(buf[0], addr);
 229       break;
 230     case 2:
 231       outw(le16_to_cpu(* (u16 *) buf), addr);
 232       break;
 233     case 4:
 234       outl(le32_to_cpu(* (u32 *) buf), addr);
 235       break;
 236     default:
 237       outb(0, 0xcf8);
 238       return pci_generic_block_write(d, pos, buf, len);
 239     }
 240   outb(0, 0xcf8);
 241   return 1;
 242 }
 243
 244 struct pci_methods pm_intel_conf1 = {
 245   "Intel-conf1",
 246   NULL,                                 /* config */
 247   conf1_detect,
 248   conf12_init,
 249   conf12_cleanup,
 250   pci_generic_scan,
 251   pci_generic_fill_info,
 252   conf1_read,
 253   conf1_write,
 254   NULL,                                 /* init_dev */
 255   NULL                                  /* cleanup_dev */
 256 };
 257
 258 struct pci_methods pm_intel_conf2 = {
 259   "Intel-conf2",
 260   NULL,                                 /* config */
 261   conf2_detect,
 262   conf12_init,
 263   conf12_cleanup,
 264   pci_generic_scan,
 265   pci_generic_fill_info,
 266   conf2_read,
 267   conf2_write,
 268   NULL,                                 /* init_dev */
 269   NULL                                  /* cleanup_dev */
 270 };