lib/i386-ports.c

   1 /*
   2  *      The PCI Library -- Direct Configuration access via i386 Ports
   3  *
   4  *      Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <unistd.h>
  10
  11 #include "internal.h"
  12
  13 #if defined(OS_LINUX)
  14 #include "i386-io-linux.h"
  15 #elif defined(OS_GNU)
  16 #include "i386-io-hurd.h"
  17 #elif defined(OS_SUNOS)
  18 #include "i386-io-sunos.h"
  19 #elif defined(OS_WINDOWS)
  20 #include "i386-io-windows.h"
  21 #else
  22 #error Do not know how to access I/O ports on this OS.
  23 #endif
  24
  25 static void
  26 conf12_init(struct pci_access *a)
  27 {
  28   if (!intel_setup_io())
  29     a->error("You need to be root to have access to I/O ports.");
  30 }
  31
  32 static void
  33 conf12_cleanup(struct pci_access *a UNUSED)
  34 {
  35   intel_cleanup_io();
  36 }
  37
  38 /*
  39  * Before we decide to use direct hardware access mechanisms, we try to do some
  40  * trivial checks to ensure it at least _seems_ to be working -- we just test
  41  * whether bus 00 contains a host bridge (this is similar to checking
  42  * techniques used in XFree86, but ours should be more reliable since we
  43  * attempt to make use of direct access hints provided by the PCI BIOS).
  44  *
  45  * This should be close to trivial, but it isn't, because there are buggy
  46  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  47  */
  48
  49 static int
  50 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
  51 {
  52   struct pci_dev d;
  53
  54   a->debug("...sanity check");
  55   d.bus = 0;
  56   d.func = 0;
  57   for(d.dev = 0; d.dev < 32; d.dev++)
  58     {
  59       u16 class, vendor;
  60       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
  61           (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
  62           m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
  63           (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
  64         {
  65           a->debug("...outside the Asylum at 0/%02x/0", d.dev);
  66           return 1;
  67         }
  68     }
  69   a->debug("...insane");
  70   return 0;
  71 }
  72
  73 /*
  74  *      Configuration type 1
  75  */
  76
  77 #define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
  78
  79 static int
  80 conf1_detect(struct pci_access *a)
  81 {
  82   unsigned int tmp;
  83   int res = 0;
  84
  85   if (!intel_setup_io())
  86     {
  87       a->debug("...no I/O permission");
  88       return 0;
  89     }
  90   outb (0x01, 0xCFB);
  91   tmp = inl (0xCF8);
  92   outl (0x80000000, 0xCF8);
  93   if (inl (0xCF8) == 0x80000000)
  94     res = 1;
  95   outl (tmp, 0xCF8);
  96   if (res)
  97     res = intel_sanity_check(a, &pm_intel_conf1);
  98   return res;
  99 }
 100
 101 static int
 102 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 103 {
 104   int addr = 0xcfc + (pos&3);
 105   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 106
 107   switch (len)
 108     {
 109     case 1:
 110       buf[0] = inb(addr);
 111       break;
 112     case 2:
 113       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 114       break;
 115     case 4:
 116       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 117       break;
 118     default:
 119       return pci_generic_block_read(d, pos, buf, len);
 120     }
 121   return 1;
 122 }
 123
 124 static int
 125 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 126 {
 127   int addr = 0xcfc + (pos&3);
 128   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 129
 130   switch (len)
 131     {
 132     case 1:
 133       outb(buf[0], addr);
 134       break;
 135     case 2:
 136       outw(le16_to_cpu(((u16 *) buf)[0]), addr);
 137       break;
 138     case 4:
 139       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
 140       break;
 141     default:
 142       return pci_generic_block_write(d, pos, buf, len);
 143     }
 144   return 1;
 145 }
 146
 147 /*
 148  *      Configuration type 2. Obsolete and brain-damaged, but existing.
 149  */
 150
 151 static int
 152 conf2_detect(struct pci_access *a)
 153 {
 154   if (!intel_setup_io())
 155     {
 156       a->debug("...no I/O permission");
 157       return 0;
 158     }
 159
 160   /* This is ugly and tends to produce false positives. Beware. */
 161
 162   outb(0x00, 0xCFB);
 163   outb(0x00, 0xCF8);
 164   outb(0x00, 0xCFA);
 165   if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
 166     return intel_sanity_check(a, &pm_intel_conf2);
 167   else
 168     return 0;
 169 }
 170
 171 static int
 172 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 173 {
 174   int addr = 0xc000 | (d->dev << 8) | pos;
 175
 176   if (d->dev >= 16)
 177     /* conf2 supports only 16 devices per bus */
 178     return 0;
 179   outb((d->func << 1) | 0xf0, 0xcf8);
 180   outb(d->bus, 0xcfa);
 181   switch (len)
 182     {
 183     case 1:
 184       buf[0] = inb(addr);
 185       break;
 186     case 2:
 187       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 188       break;
 189     case 4:
 190       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 191       break;
 192     default:
 193       outb(0, 0xcf8);
 194       return pci_generic_block_read(d, pos, buf, len);
 195     }
 196   outb(0, 0xcf8);
 197   return 1;
 198 }
 199
 200 static int
 201 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 202 {
 203   int addr = 0xc000 | (d->dev << 8) | pos;
 204
 205   if (d->dev >= 16)
 206     d->access->error("conf2_write: only first 16 devices exist.");
 207   outb((d->func << 1) | 0xf0, 0xcf8);
 208   outb(d->bus, 0xcfa);
 209   switch (len)
 210     {
 211     case 1:
 212       outb(buf[0], addr);
 213       break;
 214     case 2:
 215       outw(le16_to_cpu(* (u16 *) buf), addr);
 216       break;
 217     case 4:
 218       outl(le32_to_cpu(* (u32 *) buf), addr);
 219       break;
 220     default:
 221       outb(0, 0xcf8);
 222       return pci_generic_block_write(d, pos, buf, len);
 223     }
 224   outb(0, 0xcf8);
 225   return 1;
 226 }
 227
 228 struct pci_methods pm_intel_conf1 = {
 229   "Intel-conf1",
 230   NULL,                                 /* config */
 231   conf1_detect,
 232   conf12_init,
 233   conf12_cleanup,
 234   pci_generic_scan,
 235   pci_generic_fill_info,
 236   conf1_read,
 237   conf1_write,
 238   NULL,                                 /* init_dev */
 239   NULL                                  /* cleanup_dev */
 240 };
 241
 242 struct pci_methods pm_intel_conf2 = {
 243   "Intel-conf2",
 244   NULL,                                 /* config */
 245   conf2_detect,
 246   conf12_init,
 247   conf12_cleanup,
 248   pci_generic_scan,
 249   pci_generic_fill_info,
 250   conf2_read,
 251   conf2_write,
 252   NULL,                                 /* init_dev */
 253   NULL                                  /* cleanup_dev */
 254 };