lib/i386-ports.c

   1 /*
   2  *      The PCI Library -- Direct Configuration access via i386 Ports
   3  *
   4  *      Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #define _GNU_SOURCE
  10
  11 #include "internal.h"
  12
  13 #include <unistd.h>
  14
  15 #if defined(PCI_OS_LINUX)
  16 #include "i386-io-linux.h"
  17 #elif defined(PCI_OS_GNU)
  18 #include "i386-io-hurd.h"
  19 #elif defined(PCI_OS_SUNOS)
  20 #include "i386-io-sunos.h"
  21 #elif defined(PCI_OS_WINDOWS)
  22 #include "i386-io-windows.h"
  23 #else
  24 #error Do not know how to access I/O ports on this OS.
  25 #endif
  26
  27 static int conf12_io_enabled = -1;              /* -1=haven't tried, 0=failed, 1=succeeded */
  28
  29 static int
  30 conf12_setup_io(struct pci_access *a)
  31 {
  32   if (conf12_io_enabled < 0)
  33     conf12_io_enabled = intel_setup_io(a);
  34   return conf12_io_enabled;
  35 }
  36
  37 static void
  38 conf12_init(struct pci_access *a)
  39 {
  40   if (!conf12_setup_io(a))
  41     a->error("No permission to access I/O ports (you probably have to be root).");
  42 }
  43
  44 static void
  45 conf12_cleanup(struct pci_access *a UNUSED)
  46 {
  47   if (conf12_io_enabled > 0)
  48     conf12_io_enabled = intel_cleanup_io(a);
  49 }
  50
  51 /*
  52  * Before we decide to use direct hardware access mechanisms, we try to do some
  53  * trivial checks to ensure it at least _seems_ to be working -- we just test
  54  * whether bus 00 contains a host bridge (this is similar to checking
  55  * techniques used in XFree86, but ours should be more reliable since we
  56  * attempt to make use of direct access hints provided by the PCI BIOS).
  57  *
  58  * This should be close to trivial, but it isn't, because there are buggy
  59  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  60  */
  61
  62 static int
  63 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
  64 {
  65   struct pci_dev d;
  66
  67   a->debug("...sanity check");
  68   d.bus = 0;
  69   d.func = 0;
  70   for(d.dev = 0; d.dev < 32; d.dev++)
  71     {
  72       u16 class, vendor;
  73       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
  74           (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
  75           m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
  76           (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
  77         {
  78           a->debug("...outside the Asylum at 0/%02x/0", d.dev);
  79           return 1;
  80         }
  81     }
  82   a->debug("...insane");
  83   return 0;
  84 }
  85
  86 /*
  87  *      Configuration type 1
  88  */
  89
  90 #define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
  91
  92 static int
  93 conf1_detect(struct pci_access *a)
  94 {
  95   unsigned int tmp;
  96   int res = 0;
  97
  98   if (!conf12_setup_io(a))
  99     {
 100       a->debug("...no I/O permission");
 101       return 0;
 102     }
 103   outb (0x01, 0xCFB);
 104   tmp = inl (0xCF8);
 105   outl (0x80000000, 0xCF8);
 106   if (inl (0xCF8) == 0x80000000)
 107     res = 1;
 108   outl (tmp, 0xCF8);
 109   if (res)
 110     res = intel_sanity_check(a, &pm_intel_conf1);
 111   return res;
 112 }
 113
 114 static int
 115 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 116 {
 117   int addr = 0xcfc + (pos&3);
 118
 119   if (pos >= 256)
 120     return 0;
 121
 122   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 123
 124   switch (len)
 125     {
 126     case 1:
 127       buf[0] = inb(addr);
 128       break;
 129     case 2:
 130       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 131       break;
 132     case 4:
 133       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 134       break;
 135     default:
 136       return pci_generic_block_read(d, pos, buf, len);
 137     }
 138   return 1;
 139 }
 140
 141 static int
 142 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 143 {
 144   int addr = 0xcfc + (pos&3);
 145
 146   if (pos >= 256)
 147     return 0;
 148
 149   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 150
 151   switch (len)
 152     {
 153     case 1:
 154       outb(buf[0], addr);
 155       break;
 156     case 2:
 157       outw(le16_to_cpu(((u16 *) buf)[0]), addr);
 158       break;
 159     case 4:
 160       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
 161       break;
 162     default:
 163       return pci_generic_block_write(d, pos, buf, len);
 164     }
 165   return 1;
 166 }
 167
 168 /*
 169  *      Configuration type 2. Obsolete and brain-damaged, but existing.
 170  */
 171
 172 static int
 173 conf2_detect(struct pci_access *a)
 174 {
 175   if (!conf12_setup_io(a))
 176     {
 177       a->debug("...no I/O permission");
 178       return 0;
 179     }
 180
 181   /* This is ugly and tends to produce false positives. Beware. */
 182
 183   outb(0x00, 0xCFB);
 184   outb(0x00, 0xCF8);
 185   outb(0x00, 0xCFA);
 186   if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
 187     return intel_sanity_check(a, &pm_intel_conf2);
 188   else
 189     return 0;
 190 }
 191
 192 static int
 193 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 194 {
 195   int addr = 0xc000 | (d->dev << 8) | pos;
 196
 197   if (pos >= 256)
 198     return 0;
 199
 200   if (d->dev >= 16)
 201     /* conf2 supports only 16 devices per bus */
 202     return 0;
 203   outb((d->func << 1) | 0xf0, 0xcf8);
 204   outb(d->bus, 0xcfa);
 205   switch (len)
 206     {
 207     case 1:
 208       buf[0] = inb(addr);
 209       break;
 210     case 2:
 211       ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
 212       break;
 213     case 4:
 214       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
 215       break;
 216     default:
 217       outb(0, 0xcf8);
 218       return pci_generic_block_read(d, pos, buf, len);
 219     }
 220   outb(0, 0xcf8);
 221   return 1;
 222 }
 223
 224 static int
 225 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 226 {
 227   int addr = 0xc000 | (d->dev << 8) | pos;
 228
 229   if (pos >= 256)
 230     return 0;
 231
 232   if (d->dev >= 16)
 233     d->access->error("conf2_write: only first 16 devices exist.");
 234   outb((d->func << 1) | 0xf0, 0xcf8);
 235   outb(d->bus, 0xcfa);
 236   switch (len)
 237     {
 238     case 1:
 239       outb(buf[0], addr);
 240       break;
 241     case 2:
 242       outw(le16_to_cpu(* (u16 *) buf), addr);
 243       break;
 244     case 4:
 245       outl(le32_to_cpu(* (u32 *) buf), addr);
 246       break;
 247     default:
 248       outb(0, 0xcf8);
 249       return pci_generic_block_write(d, pos, buf, len);
 250     }
 251   outb(0, 0xcf8);
 252   return 1;
 253 }
 254
 255 struct pci_methods pm_intel_conf1 = {
 256   "Intel-conf1",
 257   NULL,                                 /* config */
 258   conf1_detect,
 259   conf12_init,
 260   conf12_cleanup,
 261   pci_generic_scan,
 262   pci_generic_fill_info,
 263   conf1_read,
 264   conf1_write,
 265   NULL,                                 /* init_dev */
 266   NULL                                  /* cleanup_dev */
 267 };
 268
 269 struct pci_methods pm_intel_conf2 = {
 270   "Intel-conf2",
 271   NULL,                                 /* config */
 272   conf2_detect,
 273   conf12_init,
 274   conf12_cleanup,
 275   pci_generic_scan,
 276   pci_generic_fill_info,
 277   conf2_read,
 278   conf2_write,
 279   NULL,                                 /* init_dev */
 280   NULL                                  /* cleanup_dev */
 281 };