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Fully decode PCI Express capability. Most of the PCIE extended capabilities
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26 static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27
28 const char program_name[] = "lspci";
29
30 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
31
32 static char help_msg[] = "\
33 Usage: lspci [<switches>]\n\
34 \n\
35 -v\t\tBe verbose\n\
36 -n\t\tShow numeric ID's\n\
37 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
38 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
39 -x\t\tShow hex-dump of the standard portion of config space\n\
40 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
41 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
42 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
43 -d [<vendor>]:[<device>]\tShow only selected devices\n\
44 -t\t\tShow bus tree\n\
45 -m\t\tProduce machine-readable output\n\
46 -i <file>\tUse specified ID database instead of %s\n\
47 -D\t\tAlways show domain numbers\n\
48 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
49 GENERIC_HELP
50 ;
51
52 /* Communication with libpci */
53
54 static struct pci_access *pacc;
55
56 /*
57 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
58 * This increases our memory footprint, but only slightly since we don't
59 * use alloca() much.
60 */
61 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
62 /* alloca() is defined in stdlib.h */
63 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
64 #include <alloca.h>
65 #else
66 #undef alloca
67 #define alloca xmalloc
68 #endif
69
70 /* Our view of the PCI bus */
71
72 struct device {
73 struct device *next;
74 struct pci_dev *dev;
75 unsigned int config_cached, config_bufsize;
76 byte *config; /* Cached configuration space data */
77 byte *present; /* Maps which configuration bytes are present */
78 };
79
80 static struct device *first_dev;
81 static int seen_errors;
82
83 static int
84 config_fetch(struct device *d, unsigned int pos, unsigned int len)
85 {
86 unsigned int end = pos+len;
87 int result;
88
89 while (pos < d->config_bufsize && len && d->present[pos])
90 pos++, len--;
91 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
92 len--;
93 if (!len)
94 return 1;
95
96 if (end > d->config_bufsize)
97 {
98 int orig_size = d->config_bufsize;
99 while (end > d->config_bufsize)
100 d->config_bufsize *= 2;
101 d->config = xrealloc(d->config, d->config_bufsize);
102 d->present = xrealloc(d->present, d->config_bufsize);
103 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
104 }
105 result = pci_read_block(d->dev, pos, d->config + pos, len);
106 if (result)
107 memset(d->present + pos, 1, len);
108 return result;
109 }
110
111 static struct device *
112 scan_device(struct pci_dev *p)
113 {
114 struct device *d;
115
116 if (p->domain && !show_domains)
117 show_domains = 1;
118 if (!pci_filter_match(&filter, p))
119 return NULL;
120 d = xmalloc(sizeof(struct device));
121 memset(d, 0, sizeof(*d));
122 d->dev = p;
123 d->config_cached = d->config_bufsize = 64;
124 d->config = xmalloc(64);
125 d->present = xmalloc(64);
126 memset(d->present, 1, 64);
127 if (!pci_read_block(p, 0, d->config, 64))
128 {
129 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
130 p->domain, p->bus, p->dev, p->func);
131 seen_errors++;
132 return NULL;
133 }
134 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
135 {
136 /* For cardbus bridges, we need to fetch 64 bytes more to get the
137 * full standard header... */
138 if (config_fetch(d, 64, 64))
139 d->config_cached += 64;
140 }
141 pci_setup_cache(p, d->config, d->config_cached);
142 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
143 return d;
144 }
145
146 static void
147 scan_devices(void)
148 {
149 struct device *d;
150 struct pci_dev *p;
151
152 pci_scan_bus(pacc);
153 for(p=pacc->devices; p; p=p->next)
154 if (d = scan_device(p))
155 {
156 d->next = first_dev;
157 first_dev = d;
158 }
159 }
160
161 /* Config space accesses */
162
163 static void
164 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
165 {
166 while (len)
167 if (!d->present[pos])
168 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
169 else
170 pos++, len--;
171 }
172
173 static inline byte
174 get_conf_byte(struct device *d, unsigned int pos)
175 {
176 check_conf_range(d, pos, 1);
177 return d->config[pos];
178 }
179
180 static word
181 get_conf_word(struct device *d, unsigned int pos)
182 {
183 check_conf_range(d, pos, 2);
184 return d->config[pos] | (d->config[pos+1] << 8);
185 }
186
187 static u32
188 get_conf_long(struct device *d, unsigned int pos)
189 {
190 check_conf_range(d, pos, 4);
191 return d->config[pos] |
192 (d->config[pos+1] << 8) |
193 (d->config[pos+2] << 16) |
194 (d->config[pos+3] << 24);
195 }
196
197 /* Sorting */
198
199 static int
200 compare_them(const void *A, const void *B)
201 {
202 const struct pci_dev *a = (*(const struct device **)A)->dev;
203 const struct pci_dev *b = (*(const struct device **)B)->dev;
204
205 if (a->domain < b->domain)
206 return -1;
207 if (a->domain > b->domain)
208 return 1;
209 if (a->bus < b->bus)
210 return -1;
211 if (a->bus > b->bus)
212 return 1;
213 if (a->dev < b->dev)
214 return -1;
215 if (a->dev > b->dev)
216 return 1;
217 if (a->func < b->func)
218 return -1;
219 if (a->func > b->func)
220 return 1;
221 return 0;
222 }
223
224 static void
225 sort_them(void)
226 {
227 struct device **index, **h, **last_dev;
228 int cnt;
229 struct device *d;
230
231 cnt = 0;
232 for(d=first_dev; d; d=d->next)
233 cnt++;
234 h = index = alloca(sizeof(struct device *) * cnt);
235 for(d=first_dev; d; d=d->next)
236 *h++ = d;
237 qsort(index, cnt, sizeof(struct device *), compare_them);
238 last_dev = &first_dev;
239 h = index;
240 while (cnt--)
241 {
242 *last_dev = *h;
243 last_dev = &(*h)->next;
244 h++;
245 }
246 *last_dev = NULL;
247 }
248
249 /* Normal output */
250
251 #define FLAG(x,y) ((x & y) ? '+' : '-')
252
253 static void
254 show_slot_name(struct device *d)
255 {
256 struct pci_dev *p = d->dev;
257
258 if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
259 printf("%04x:", p->domain);
260 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
261 }
262
263 static void
264 show_terse(struct device *d)
265 {
266 int c;
267 struct pci_dev *p = d->dev;
268 char classbuf[128], devbuf[128];
269
270 show_slot_name(d);
271 printf(" %s: %s",
272 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
273 PCI_LOOKUP_CLASS,
274 p->device_class),
275 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
276 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
277 p->vendor_id, p->device_id));
278 if (c = get_conf_byte(d, PCI_REVISION_ID))
279 printf(" (rev %02x)", c);
280 if (verbose)
281 {
282 char *x;
283 c = get_conf_byte(d, PCI_CLASS_PROG);
284 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
285 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
286 p->device_class, c);
287 if (c || x)
288 {
289 printf(" (prog-if %02x", c);
290 if (x)
291 printf(" [%s]", x);
292 putchar(')');
293 }
294 }
295 putchar('\n');
296 }
297
298 static void
299 show_size(pciaddr_t x)
300 {
301 if (!x)
302 return;
303 printf(" [size=");
304 if (x < 1024)
305 printf("%d", (int) x);
306 else if (x < 1048576)
307 printf("%dK", (int)(x / 1024));
308 else if (x < 0x80000000)
309 printf("%dM", (int)(x / 1048576));
310 else
311 printf(PCIADDR_T_FMT, x);
312 putchar(']');
313 }
314
315 static void
316 show_bases(struct device *d, int cnt)
317 {
318 struct pci_dev *p = d->dev;
319 word cmd = get_conf_word(d, PCI_COMMAND);
320 int i;
321
322 for(i=0; i<cnt; i++)
323 {
324 pciaddr_t pos = p->base_addr[i];
325 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
326 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
327 if (flg == 0xffffffff)
328 flg = 0;
329 if (!pos && !flg && !len)
330 continue;
331 if (verbose > 1)
332 printf("\tRegion %d: ", i);
333 else
334 putchar('\t');
335 if (pos && !flg) /* Reported by the OS, but not by the device */
336 {
337 printf("[virtual] ");
338 flg = pos;
339 }
340 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
341 {
342 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
343 printf("I/O ports at ");
344 if (a)
345 printf(PCIADDR_PORT_FMT, a);
346 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
347 printf("<ignored>");
348 else
349 printf("<unassigned>");
350 if (!(cmd & PCI_COMMAND_IO))
351 printf(" [disabled]");
352 }
353 else
354 {
355 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
356 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
357 int done = 0;
358 u32 z = 0;
359
360 printf("Memory at ");
361 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
362 {
363 if (i >= cnt - 1)
364 {
365 printf("<invalid-64bit-slot>");
366 done = 1;
367 }
368 else
369 {
370 i++;
371 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
372 if (buscentric_view)
373 {
374 u32 y = a & 0xffffffff;
375 if (a || z)
376 printf("%08x%08x", z, y);
377 else
378 printf("<unassigned>");
379 done = 1;
380 }
381 }
382 }
383 if (!done)
384 {
385 if (a)
386 printf(PCIADDR_T_FMT, a);
387 else
388 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
389 }
390 printf(" (%s, %sprefetchable)",
391 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
392 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
393 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
394 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
395 if (!(cmd & PCI_COMMAND_MEMORY))
396 printf(" [disabled]");
397 }
398 show_size(len);
399 putchar('\n');
400 }
401 }
402
403 static void
404 show_pm(struct device *d, int where, int cap)
405 {
406 int t, b;
407 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
408
409 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
410 if (verbose < 2)
411 return;
412 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
413 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
414 FLAG(cap, PCI_PM_CAP_DSI),
415 FLAG(cap, PCI_PM_CAP_D1),
416 FLAG(cap, PCI_PM_CAP_D2),
417 pm_aux_current[(cap >> 6) & 7],
418 FLAG(cap, PCI_PM_CAP_PME_D0),
419 FLAG(cap, PCI_PM_CAP_PME_D1),
420 FLAG(cap, PCI_PM_CAP_PME_D2),
421 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
422 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
423 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
424 return;
425 t = get_conf_word(d, where + PCI_PM_CTRL);
426 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
427 t & PCI_PM_CTRL_STATE_MASK,
428 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
429 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
430 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
431 FLAG(t, PCI_PM_CTRL_PME_STATUS));
432 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
433 if (b)
434 printf("\t\tBridge: PM%c B3%c\n",
435 FLAG(t, PCI_PM_BPCC_ENABLE),
436 FLAG(~t, PCI_PM_PPB_B2_B3));
437 }
438
439 static void
440 format_agp_rate(int rate, char *buf, int agp3)
441 {
442 char *c = buf;
443 int i;
444
445 for(i=0; i<=2; i++)
446 if (rate & (1 << i))
447 {
448 if (c != buf)
449 *c++ = ',';
450 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
451 }
452 if (c != buf)
453 *c = 0;
454 else
455 strcpy(buf, "<none>");
456 }
457
458 static void
459 show_agp(struct device *d, int where, int cap)
460 {
461 u32 t;
462 char rate[16];
463 int ver, rev;
464 int agp3 = 0;
465
466 ver = (cap >> 4) & 0x0f;
467 rev = cap & 0x0f;
468 printf("AGP version %x.%x\n", ver, rev);
469 if (verbose < 2)
470 return;
471 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
472 return;
473 t = get_conf_long(d, where + PCI_AGP_STATUS);
474 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
475 agp3 = 1;
476 format_agp_rate(t & 7, rate, agp3);
477 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
478 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
479 FLAG(t, PCI_AGP_STATUS_ISOCH),
480 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
481 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
482 FLAG(t, PCI_AGP_STATUS_SBA),
483 FLAG(t, PCI_AGP_STATUS_ITA_COH),
484 FLAG(t, PCI_AGP_STATUS_GART64),
485 FLAG(t, PCI_AGP_STATUS_HTRANS),
486 FLAG(t, PCI_AGP_STATUS_64BIT),
487 FLAG(t, PCI_AGP_STATUS_FW),
488 FLAG(t, PCI_AGP_STATUS_AGP3),
489 rate);
490 t = get_conf_long(d, where + PCI_AGP_COMMAND);
491 format_agp_rate(t & 7, rate, agp3);
492 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
493 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
494 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
495 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
496 FLAG(t, PCI_AGP_COMMAND_SBA),
497 FLAG(t, PCI_AGP_COMMAND_AGP),
498 FLAG(t, PCI_AGP_COMMAND_GART64),
499 FLAG(t, PCI_AGP_COMMAND_64BIT),
500 FLAG(t, PCI_AGP_COMMAND_FW),
501 rate);
502 }
503
504 static void
505 show_pcix_nobridge(struct device *d, int where)
506 {
507 u16 command;
508 u32 status;
509 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
510
511 printf("PCI-X non-bridge device\n");
512
513 if (verbose < 2)
514 return;
515
516 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
517 return;
518
519 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
520 status = get_conf_long(d, where + PCI_PCIX_STATUS);
521 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
522 FLAG(command, PCI_PCIX_COMMAND_DPERE),
523 FLAG(command, PCI_PCIX_COMMAND_ERO),
524 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
525 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
526 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
527 ((status >> 8) & 0xff),
528 ((status >> 3) & 0x1f),
529 (status & PCI_PCIX_STATUS_FUNCTION),
530 FLAG(status, PCI_PCIX_STATUS_64BIT),
531 FLAG(status, PCI_PCIX_STATUS_133MHZ),
532 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
533 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
534 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
535 1 << (9 + ((status >> 21) & 3U)),
536 max_outstanding[(status >> 23) & 7U],
537 1 << (3 + ((status >> 26) & 7U)),
538 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
539 FLAG(status, PCI_PCIX_STATUS_266MHZ),
540 FLAG(status, PCI_PCIX_STATUS_533MHZ));
541 }
542
543 static void
544 show_pcix_bridge(struct device *d, int where)
545 {
546 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
547 u16 secstatus;
548 u32 status, upstcr, downstcr;
549
550 printf("PCI-X bridge device\n");
551
552 if (verbose < 2)
553 return;
554
555 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
556 return;
557
558 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
559 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
560 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
561 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
562 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
563 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
564 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
565 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
566 sec_clock_freq[(secstatus >> 6) & 7]);
567 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
568 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
569 ((status >> 8) & 0xff),
570 ((status >> 3) & 0x1f),
571 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
572 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
573 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
574 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
575 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
576 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
577 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
578 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
579 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
580 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
581 (upstcr >> 16) & 0xffff);
582 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
583 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
584 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
585 (downstcr >> 16) & 0xffff);
586 }
587
588 static void
589 show_pcix(struct device *d, int where)
590 {
591 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
592 {
593 case PCI_HEADER_TYPE_NORMAL:
594 show_pcix_nobridge(d, where);
595 break;
596 case PCI_HEADER_TYPE_BRIDGE:
597 show_pcix_bridge(d, where);
598 break;
599 }
600 }
601
602 static inline char *
603 ht_link_width(unsigned width)
604 {
605 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
606 return widths[width];
607 }
608
609 static inline char *
610 ht_link_freq(unsigned freq)
611 {
612 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
613 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
614 return freqs[freq];
615 }
616
617 static void
618 show_ht_pri(struct device *d, int where, int cmd)
619 {
620 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
621 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
622 char *fmt;
623
624 printf("HyperTransport: Slave or Primary Interface\n");
625 if (verbose < 2)
626 return;
627
628 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
629 return;
630 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
631 if (rid < 0x23 && rid > 0x11)
632 printf("\t\t!!! Possibly incomplete decoding\n");
633
634 if (rid >= 0x23)
635 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
636 else
637 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
638 printf(fmt,
639 (cmd & PCI_HT_PRI_CMD_BUID),
640 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
641 FLAG(cmd, PCI_HT_PRI_CMD_MH),
642 FLAG(cmd, PCI_HT_PRI_CMD_DD),
643 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
644 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
645 if (rid >= 0x23)
646 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
647 else
648 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
649 printf(fmt,
650 FLAG(lctr0, PCI_HT_LCTR_CFLE),
651 FLAG(lctr0, PCI_HT_LCTR_CST),
652 FLAG(lctr0, PCI_HT_LCTR_CFE),
653 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
654 FLAG(lctr0, PCI_HT_LCTR_INIT),
655 FLAG(lctr0, PCI_HT_LCTR_EOC),
656 FLAG(lctr0, PCI_HT_LCTR_TXO),
657 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
658 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
659 FLAG(lctr0, PCI_HT_LCTR_LSEN),
660 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
661 FLAG(lctr0, PCI_HT_LCTR_64B));
662 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
663 if (rid >= 0x23)
664 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
665 else
666 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
667 printf(fmt,
668 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
669 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
670 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
671 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
672 FLAG(lcnf0, PCI_HT_LCNF_DFI),
673 FLAG(lcnf0, PCI_HT_LCNF_DFO),
674 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
675 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
676 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
677 if (rid >= 0x23)
678 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
679 else
680 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
681 printf(fmt,
682 FLAG(lctr1, PCI_HT_LCTR_CFLE),
683 FLAG(lctr1, PCI_HT_LCTR_CST),
684 FLAG(lctr1, PCI_HT_LCTR_CFE),
685 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
686 FLAG(lctr1, PCI_HT_LCTR_INIT),
687 FLAG(lctr1, PCI_HT_LCTR_EOC),
688 FLAG(lctr1, PCI_HT_LCTR_TXO),
689 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
690 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
691 FLAG(lctr1, PCI_HT_LCTR_LSEN),
692 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
693 FLAG(lctr1, PCI_HT_LCTR_64B));
694 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
695 if (rid >= 0x23)
696 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
697 else
698 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
699 printf(fmt,
700 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
701 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
702 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
703 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
704 FLAG(lcnf1, PCI_HT_LCNF_DFI),
705 FLAG(lcnf1, PCI_HT_LCNF_DFO),
706 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
707 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
708 printf("\t\tRevision ID: %u.%02u\n",
709 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
710 if (rid < 0x23)
711 return;
712 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
713 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
714 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
715 FLAG(lfrer0, PCI_HT_LFRER_PROT),
716 FLAG(lfrer0, PCI_HT_LFRER_OV),
717 FLAG(lfrer0, PCI_HT_LFRER_EOC),
718 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
719 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
720 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
721 FLAG(lfcap0, PCI_HT_LFCAP_200),
722 FLAG(lfcap0, PCI_HT_LFCAP_300),
723 FLAG(lfcap0, PCI_HT_LFCAP_400),
724 FLAG(lfcap0, PCI_HT_LFCAP_500),
725 FLAG(lfcap0, PCI_HT_LFCAP_600),
726 FLAG(lfcap0, PCI_HT_LFCAP_800),
727 FLAG(lfcap0, PCI_HT_LFCAP_1000),
728 FLAG(lfcap0, PCI_HT_LFCAP_1200),
729 FLAG(lfcap0, PCI_HT_LFCAP_1400),
730 FLAG(lfcap0, PCI_HT_LFCAP_1600),
731 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
732 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
733 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
734 FLAG(ftr, PCI_HT_FTR_ISOCFC),
735 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
736 FLAG(ftr, PCI_HT_FTR_CRCTM),
737 FLAG(ftr, PCI_HT_FTR_ECTLT),
738 FLAG(ftr, PCI_HT_FTR_64BA),
739 FLAG(ftr, PCI_HT_FTR_UIDRD));
740 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
741 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
742 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
743 FLAG(lfrer1, PCI_HT_LFRER_PROT),
744 FLAG(lfrer1, PCI_HT_LFRER_OV),
745 FLAG(lfrer1, PCI_HT_LFRER_EOC),
746 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
747 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
748 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
749 FLAG(lfcap1, PCI_HT_LFCAP_200),
750 FLAG(lfcap1, PCI_HT_LFCAP_300),
751 FLAG(lfcap1, PCI_HT_LFCAP_400),
752 FLAG(lfcap1, PCI_HT_LFCAP_500),
753 FLAG(lfcap1, PCI_HT_LFCAP_600),
754 FLAG(lfcap1, PCI_HT_LFCAP_800),
755 FLAG(lfcap1, PCI_HT_LFCAP_1000),
756 FLAG(lfcap1, PCI_HT_LFCAP_1200),
757 FLAG(lfcap1, PCI_HT_LFCAP_1400),
758 FLAG(lfcap1, PCI_HT_LFCAP_1600),
759 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
760 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
761 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
762 FLAG(eh, PCI_HT_EH_PFLE),
763 FLAG(eh, PCI_HT_EH_OFLE),
764 FLAG(eh, PCI_HT_EH_PFE),
765 FLAG(eh, PCI_HT_EH_OFE),
766 FLAG(eh, PCI_HT_EH_EOCFE),
767 FLAG(eh, PCI_HT_EH_RFE),
768 FLAG(eh, PCI_HT_EH_CRCFE),
769 FLAG(eh, PCI_HT_EH_SERRFE),
770 FLAG(eh, PCI_HT_EH_CF),
771 FLAG(eh, PCI_HT_EH_RE),
772 FLAG(eh, PCI_HT_EH_PNFE),
773 FLAG(eh, PCI_HT_EH_ONFE),
774 FLAG(eh, PCI_HT_EH_EOCNFE),
775 FLAG(eh, PCI_HT_EH_RNFE),
776 FLAG(eh, PCI_HT_EH_CRCNFE),
777 FLAG(eh, PCI_HT_EH_SERRNFE));
778 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
779 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
780 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
781 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
782 printf("\t\tBus Number: %02x\n", bn);
783 }
784
785 static void
786 show_ht_sec(struct device *d, int where, int cmd)
787 {
788 u16 lctr, lcnf, ftr, eh;
789 u8 rid, lfrer, lfcap, mbu, mlu;
790 char *fmt;
791
792 printf("HyperTransport: Host or Secondary Interface\n");
793 if (verbose < 2)
794 return;
795
796 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
797 return;
798 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
799 if (rid < 0x23 && rid > 0x11)
800 printf("\t\t!!! Possibly incomplete decoding\n");
801
802 if (rid >= 0x23)
803 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
804 else
805 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
806 printf(fmt,
807 FLAG(cmd, PCI_HT_SEC_CMD_WR),
808 FLAG(cmd, PCI_HT_SEC_CMD_DE),
809 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
810 FLAG(cmd, PCI_HT_SEC_CMD_CS),
811 FLAG(cmd, PCI_HT_SEC_CMD_HH),
812 FLAG(cmd, PCI_HT_SEC_CMD_AS),
813 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
814 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
815 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
816 if (rid >= 0x23)
817 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
818 else
819 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
820 printf(fmt,
821 FLAG(lctr, PCI_HT_LCTR_CFLE),
822 FLAG(lctr, PCI_HT_LCTR_CST),
823 FLAG(lctr, PCI_HT_LCTR_CFE),
824 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
825 FLAG(lctr, PCI_HT_LCTR_INIT),
826 FLAG(lctr, PCI_HT_LCTR_EOC),
827 FLAG(lctr, PCI_HT_LCTR_TXO),
828 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
829 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
830 FLAG(lctr, PCI_HT_LCTR_LSEN),
831 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
832 FLAG(lctr, PCI_HT_LCTR_64B));
833 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
834 if (rid >= 0x23)
835 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
836 else
837 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
838 printf(fmt,
839 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
840 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
841 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
842 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
843 FLAG(lcnf, PCI_HT_LCNF_DFI),
844 FLAG(lcnf, PCI_HT_LCNF_DFO),
845 FLAG(lcnf, PCI_HT_LCNF_DFIE),
846 FLAG(lcnf, PCI_HT_LCNF_DFOE));
847 printf("\t\tRevision ID: %u.%02u\n",
848 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
849 if (rid < 0x23)
850 return;
851 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
852 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
853 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
854 FLAG(lfrer, PCI_HT_LFRER_PROT),
855 FLAG(lfrer, PCI_HT_LFRER_OV),
856 FLAG(lfrer, PCI_HT_LFRER_EOC),
857 FLAG(lfrer, PCI_HT_LFRER_CTLT));
858 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
859 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
860 FLAG(lfcap, PCI_HT_LFCAP_200),
861 FLAG(lfcap, PCI_HT_LFCAP_300),
862 FLAG(lfcap, PCI_HT_LFCAP_400),
863 FLAG(lfcap, PCI_HT_LFCAP_500),
864 FLAG(lfcap, PCI_HT_LFCAP_600),
865 FLAG(lfcap, PCI_HT_LFCAP_800),
866 FLAG(lfcap, PCI_HT_LFCAP_1000),
867 FLAG(lfcap, PCI_HT_LFCAP_1200),
868 FLAG(lfcap, PCI_HT_LFCAP_1400),
869 FLAG(lfcap, PCI_HT_LFCAP_1600),
870 FLAG(lfcap, PCI_HT_LFCAP_VEND));
871 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
872 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
873 FLAG(ftr, PCI_HT_FTR_ISOCFC),
874 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
875 FLAG(ftr, PCI_HT_FTR_CRCTM),
876 FLAG(ftr, PCI_HT_FTR_ECTLT),
877 FLAG(ftr, PCI_HT_FTR_64BA),
878 FLAG(ftr, PCI_HT_FTR_UIDRD),
879 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
880 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
881 if (ftr & PCI_HT_SEC_FTR_EXTRS)
882 {
883 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
884 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
885 FLAG(eh, PCI_HT_EH_PFLE),
886 FLAG(eh, PCI_HT_EH_OFLE),
887 FLAG(eh, PCI_HT_EH_PFE),
888 FLAG(eh, PCI_HT_EH_OFE),
889 FLAG(eh, PCI_HT_EH_EOCFE),
890 FLAG(eh, PCI_HT_EH_RFE),
891 FLAG(eh, PCI_HT_EH_CRCFE),
892 FLAG(eh, PCI_HT_EH_SERRFE),
893 FLAG(eh, PCI_HT_EH_CF),
894 FLAG(eh, PCI_HT_EH_RE),
895 FLAG(eh, PCI_HT_EH_PNFE),
896 FLAG(eh, PCI_HT_EH_ONFE),
897 FLAG(eh, PCI_HT_EH_EOCNFE),
898 FLAG(eh, PCI_HT_EH_RNFE),
899 FLAG(eh, PCI_HT_EH_CRCNFE),
900 FLAG(eh, PCI_HT_EH_SERRNFE));
901 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
902 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
903 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
904 }
905 }
906
907 static void
908 show_ht(struct device *d, int where, int cmd)
909 {
910 int type;
911
912 switch (cmd & PCI_HT_CMD_TYP_HI)
913 {
914 case PCI_HT_CMD_TYP_HI_PRI:
915 show_ht_pri(d, where, cmd);
916 return;
917 case PCI_HT_CMD_TYP_HI_SEC:
918 show_ht_sec(d, where, cmd);
919 return;
920 }
921
922 type = cmd & PCI_HT_CMD_TYP;
923 switch (type)
924 {
925 case PCI_HT_CMD_TYP_SW:
926 printf("HyperTransport: Switch\n");
927 break;
928 case PCI_HT_CMD_TYP_IDC:
929 printf("HyperTransport: Interrupt Discovery and Configuration\n");
930 break;
931 case PCI_HT_CMD_TYP_RID:
932 printf("HyperTransport: Revision ID: %u.%02u\n",
933 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
934 break;
935 case PCI_HT_CMD_TYP_UIDC:
936 printf("HyperTransport: UnitID Clumping\n");
937 break;
938 case PCI_HT_CMD_TYP_ECSA:
939 printf("HyperTransport: Extended Configuration Space Access\n");
940 break;
941 case PCI_HT_CMD_TYP_AM:
942 printf("HyperTransport: Address Mapping\n");
943 break;
944 case PCI_HT_CMD_TYP_MSIM:
945 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
946 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
947 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
948 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
949 {
950 u32 offl, offh;
951 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
952 break;
953 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
954 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
955 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
956 }
957 break;
958 case PCI_HT_CMD_TYP_DR:
959 printf("HyperTransport: DirectRoute\n");
960 break;
961 case PCI_HT_CMD_TYP_VCS:
962 printf("HyperTransport: VCSet\n");
963 break;
964 case PCI_HT_CMD_TYP_RM:
965 printf("HyperTransport: Retry Mode\n");
966 break;
967 case PCI_HT_CMD_TYP_X86:
968 printf("HyperTransport: X86 (reserved)\n");
969 break;
970 default:
971 printf("HyperTransport: #%02x\n", type >> 11);
972 }
973 }
974
975 static void
976 show_rom(struct device *d, int reg)
977 {
978 struct pci_dev *p = d->dev;
979 pciaddr_t rom = p->rom_base_addr;
980 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
981 u32 flg = get_conf_long(d, reg);
982 word cmd = get_conf_word(d, PCI_COMMAND);
983
984 if (!rom && !flg && !len)
985 return;
986 putchar('\t');
987 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
988 {
989 printf("[virtual] ");
990 flg = rom;
991 }
992 printf("Expansion ROM at ");
993 if (rom & PCI_ROM_ADDRESS_MASK)
994 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
995 else if (flg & PCI_ROM_ADDRESS_MASK)
996 printf("<ignored>");
997 else
998 printf("<unassigned>");
999 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
1000 printf(" [disabled]");
1001 else if (!(cmd & PCI_COMMAND_MEMORY))
1002 printf(" [disabled by cmd]");
1003 show_size(len);
1004 putchar('\n');
1005 }
1006
1007 static void
1008 show_msi(struct device *d, int where, int cap)
1009 {
1010 int is64;
1011 u32 t;
1012 u16 w;
1013
1014 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
1015 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
1016 FLAG(cap, PCI_MSI_FLAGS_64BIT),
1017 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
1018 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
1019 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
1020 if (verbose < 2)
1021 return;
1022 is64 = cap & PCI_MSI_FLAGS_64BIT;
1023 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1024 return;
1025 printf("\t\tAddress: ");
1026 if (is64)
1027 {
1028 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1029 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1030 printf("%08x", t);
1031 }
1032 else
1033 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1034 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1035 printf("%08x Data: %04x\n", t, w);
1036 if (cap & PCI_MSI_FLAGS_MASK_BIT)
1037 {
1038 u32 mask, pending;
1039
1040 if (is64)
1041 {
1042 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
1043 return;
1044 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
1045 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
1046 }
1047 else
1048 {
1049 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
1050 return;
1051 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
1052 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
1053 }
1054 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
1055 }
1056 }
1057
1058 static void show_vendor(void)
1059 {
1060 printf("Vendor Specific Information\n");
1061 }
1062
1063 static void show_debug(void)
1064 {
1065 printf("Debug port\n");
1066 }
1067
1068 static float power_limit(int value, int scale)
1069 {
1070 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1071 return value * scales[scale];
1072 }
1073
1074 static const char *latency_l0s(int value)
1075 {
1076 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1077 return latencies[value];
1078 }
1079
1080 static const char *latency_l1(int value)
1081 {
1082 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1083 return latencies[value];
1084 }
1085
1086 static void show_express_dev(struct device *d, int where, int type)
1087 {
1088 u32 t;
1089 u16 w;
1090
1091 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1092 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
1093 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1094 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1095 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1096 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1097 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1098 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1099 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1100 printf(" AttnBtn%c AttnInd%c PwrInd%c",
1101 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1102 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1103 printf(" RBE%c FLReset%c",
1104 FLAG(t, PCI_EXP_DEVCAP_RBE),
1105 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
1106 if (type == PCI_EXP_TYPE_UPSTREAM)
1107 printf("SlotPowerLimit %fW",
1108 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1109 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1110 printf("\n");
1111
1112 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1113 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1114 FLAG(w, PCI_EXP_DEVCTL_CERE),
1115 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1116 FLAG(w, PCI_EXP_DEVCTL_FERE),
1117 FLAG(w, PCI_EXP_DEVCTL_URRE));
1118 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1119 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1120 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1121 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1122 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1123 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1124 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1125 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1126 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1127 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1128 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1129 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1130 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1131
1132 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1133 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1134 FLAG(w, PCI_EXP_DEVSTA_CED),
1135 FLAG(w, PCI_EXP_DEVSTA_NFED),
1136 FLAG(w, PCI_EXP_DEVSTA_FED),
1137 FLAG(w, PCI_EXP_DEVSTA_URD),
1138 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1139 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1140
1141 /* FIXME: Second set of control/status registers is not supported yet. */
1142 }
1143
1144 static char *link_speed(int speed)
1145 {
1146 switch (speed)
1147 {
1148 case 1:
1149 return "2.5GT/s";
1150 case 2:
1151 return "5GT/s";
1152 default:
1153 return "unknown";
1154 }
1155 }
1156
1157 static char *aspm_support(int code)
1158 {
1159 switch (code)
1160 {
1161 case 1:
1162 return "L0s";
1163 case 3:
1164 return "L0s L1";
1165 default:
1166 return "unknown";
1167 }
1168 }
1169
1170 static const char *aspm_enabled(int code)
1171 {
1172 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1173 return desc[code];
1174 }
1175
1176 static void show_express_link(struct device *d, int where, int type)
1177 {
1178 u32 t;
1179 u16 w;
1180
1181 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1182 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1183 t >> 24,
1184 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1185 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1186 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1187 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1188 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1189 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1190 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1191 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1192 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1193
1194 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1195 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1196 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1197 (type == PCI_EXP_TYPE_LEG_END))
1198 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1199 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1200 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1201 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1202 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1203 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1204 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1205 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1206 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1207 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1208
1209 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1210 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1211 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1212 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1213 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1214 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1215 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1216 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1217 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1218 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1219 }
1220
1221 static const char *indicator(int code)
1222 {
1223 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1224 return names[code];
1225 }
1226
1227 static void show_express_slot(struct device *d, int where)
1228 {
1229 u32 t;
1230 u16 w;
1231
1232 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1233 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1234 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1235 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1236 FLAG(t, PCI_EXP_SLTCAP_MRL),
1237 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1238 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1239 FLAG(t, PCI_EXP_SLTCAP_HPC),
1240 FLAG(t, PCI_EXP_SLTCAP_HPS));
1241 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1242 t >> 19,
1243 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1244 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1245 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1246
1247 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1248 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1249 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1250 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1251 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1252 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1253 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1254 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1255 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1256 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1257 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1258 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1259 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1260 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1261
1262 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1263 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1264 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1265 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1266 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1267 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1268 FLAG(w, PCI_EXP_SLTSTA_PRES),
1269 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1270 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1271 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1272 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1273 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1274 }
1275
1276 static void show_express_root(struct device *d, int where)
1277 {
1278 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1279 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1280 FLAG(w, PCI_EXP_RTCTL_SECEE),
1281 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1282 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1283 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1284 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1285
1286 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1287 printf("\t\tRootCap: CRSVisible%c\n",
1288 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1289
1290 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1291 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1292 w & PCI_EXP_RTSTA_PME_REQID,
1293 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1294 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1295 }
1296
1297 static void
1298 show_express(struct device *d, int where, int cap)
1299 {
1300 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1301 int size;
1302 int slot = 0;
1303
1304 printf("Express ");
1305 if (verbose >= 2)
1306 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1307 switch (type)
1308 {
1309 case PCI_EXP_TYPE_ENDPOINT:
1310 printf("Endpoint");
1311 break;
1312 case PCI_EXP_TYPE_LEG_END:
1313 printf("Legacy Endpoint");
1314 break;
1315 case PCI_EXP_TYPE_ROOT_PORT:
1316 slot = cap & PCI_EXP_FLAGS_SLOT;
1317 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1318 break;
1319 case PCI_EXP_TYPE_UPSTREAM:
1320 printf("Upstream Port");
1321 break;
1322 case PCI_EXP_TYPE_DOWNSTREAM:
1323 slot = cap & PCI_EXP_FLAGS_SLOT;
1324 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1325 break;
1326 case PCI_EXP_TYPE_PCI_BRIDGE:
1327 printf("PCI/PCI-X Bridge");
1328 break;
1329 case PCI_EXP_TYPE_PCIE_BRIDGE:
1330 printf("PCI/PCI-X to PCI-Express Bridge");
1331 break;
1332 case PCI_EXP_TYPE_ROOT_INT_EP:
1333 printf("Root Complex Integrated Endpoint");
1334 break;
1335 case PCI_EXP_TYPE_ROOT_EC:
1336 printf("Root Complex Event Collector");
1337 break;
1338 default:
1339 printf("Unknown type %d", type);
1340 }
1341 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1342 if (verbose < 2)
1343 return;
1344
1345 size = 16;
1346 if (slot)
1347 size = 24;
1348 if (type == PCI_EXP_TYPE_ROOT_PORT)
1349 size = 32;
1350 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1351 return;
1352
1353 show_express_dev(d, where, type);
1354 show_express_link(d, where, type);
1355 if (slot)
1356 show_express_slot(d, where);
1357 if (type == PCI_EXP_TYPE_ROOT_PORT)
1358 show_express_root(d, where);
1359 }
1360
1361 static void
1362 show_msix(struct device *d, int where, int cap)
1363 {
1364 u32 off;
1365
1366 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1367 FLAG(cap, PCI_MSIX_ENABLE),
1368 FLAG(cap, PCI_MSIX_MASK),
1369 (cap & PCI_MSIX_TABSIZE) + 1);
1370 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1371 return;
1372
1373 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1374 printf("\t\tVector table: BAR=%d offset=%08x\n",
1375 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1376 off = get_conf_long(d, where + PCI_MSIX_PBA);
1377 printf("\t\tPBA: BAR=%d offset=%08x\n",
1378 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1379 }
1380
1381 static void
1382 show_slotid(int cap)
1383 {
1384 int esr = cap & 0xff;
1385 int chs = cap >> 8;
1386
1387 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1388 esr & PCI_SID_ESR_NSLOTS,
1389 FLAG(esr, PCI_SID_ESR_FIC),
1390 chs);
1391 }
1392
1393 static void
1394 show_ssvid(struct device *d, int where)
1395 {
1396 u16 subsys_v, subsys_d;
1397 char ssnamebuf[256];
1398
1399 if (!config_fetch(d, where, 8))
1400 return;
1401 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1402 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1403 printf("Subsystem: %s\n",
1404 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1405 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1406 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1407 }
1408
1409 static void
1410 show_dsn(struct device *d, int where)
1411 {
1412 u32 t1, t2;
1413 if (!config_fetch(d, where + 4, 8))
1414 return;
1415 t1 = get_conf_long(d, where + 4);
1416 t2 = get_conf_long(d, where + 8);
1417 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1418 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1419 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1420 }
1421
1422 static void
1423 show_ext_caps(struct device *d)
1424 {
1425 int where = 0x100;
1426 char been_there[0x1000];
1427 memset(been_there, 0, 0x1000);
1428 do
1429 {
1430 u32 header;
1431 int id;
1432
1433 if (!config_fetch(d, where, 4))
1434 break;
1435 header = get_conf_long(d, where);
1436 if (!header)
1437 break;
1438 id = header & 0xffff;
1439 printf("\tCapabilities: [%03x] ", where);
1440 if (been_there[where++])
1441 {
1442 printf("<chain looped>\n");
1443 break;
1444 }
1445 switch (id)
1446 {
1447 case PCI_EXT_CAP_ID_AER:
1448 printf("Advanced Error Reporting\n");
1449 /* FIXME: Not decoded yet */
1450 break;
1451 case PCI_EXT_CAP_ID_VC:
1452 printf("Virtual Channel\n");
1453 /* FIXME: Not decoded yet */
1454 break;
1455 case PCI_EXT_CAP_ID_DSN:
1456 show_dsn(d, where);
1457 break;
1458 case PCI_EXT_CAP_ID_PB:
1459 printf("Power Budgeting\n");
1460 /* FIXME: Not decoded yet */
1461 break;
1462 case PCI_EXT_CAP_ID_RCLINK:
1463 printf("Root Complex Link\n");
1464 /* FIXME: Not decoded yet */
1465 break;
1466 case PCI_EXT_CAP_ID_RCILINK:
1467 printf("Root Complex Internal Link\n");
1468 /* FIXME: Not decoded yet */
1469 break;
1470 case PCI_EXT_CAP_ID_RCECOLL:
1471 printf("Root Complex Event Collector\n");
1472 /* FIXME: Not decoded yet */
1473 break;
1474 case PCI_EXT_CAP_ID_MFVC:
1475 printf("Multi-Function Virtual Channel\n");
1476 /* FIXME: Not decoded yet */
1477 break;
1478 case PCI_EXT_CAP_ID_RBCB:
1479 printf("Root Bridge Control Block\n");
1480 /* FIXME: Not decoded yet */
1481 break;
1482 case PCI_EXT_CAP_ID_VNDR:
1483 printf("Vendor specific\n");
1484 break;
1485 case PCI_EXT_CAP_ID_ACS:
1486 printf("Access Controls\n");
1487 /* FIXME: Not decoded yet */
1488 break;
1489 default:
1490 printf("#%02x\n", id);
1491 break;
1492 }
1493 where = header >> 20;
1494 } while (where);
1495 }
1496
1497 static void
1498 show_caps(struct device *d)
1499 {
1500 int can_have_ext_caps = 0;
1501
1502 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1503 {
1504 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1505 byte been_there[256];
1506 memset(been_there, 0, 256);
1507 while (where)
1508 {
1509 int id, next, cap;
1510 printf("\tCapabilities: ");
1511 if (!config_fetch(d, where, 4))
1512 {
1513 puts("<access denied>");
1514 break;
1515 }
1516 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1517 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1518 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1519 printf("[%02x] ", where);
1520 if (been_there[where]++)
1521 {
1522 printf("<chain looped>\n");
1523 break;
1524 }
1525 if (id == 0xff)
1526 {
1527 printf("<chain broken>\n");
1528 break;
1529 }
1530 switch (id)
1531 {
1532 case PCI_CAP_ID_PM:
1533 show_pm(d, where, cap);
1534 break;
1535 case PCI_CAP_ID_AGP:
1536 show_agp(d, where, cap);
1537 break;
1538 case PCI_CAP_ID_VPD:
1539 printf("Vital Product Data\n");
1540 break;
1541 case PCI_CAP_ID_SLOTID:
1542 show_slotid(cap);
1543 break;
1544 case PCI_CAP_ID_MSI:
1545 show_msi(d, where, cap);
1546 break;
1547 case PCI_CAP_ID_PCIX:
1548 show_pcix(d, where);
1549 can_have_ext_caps = 1;
1550 break;
1551 case PCI_CAP_ID_HT:
1552 show_ht(d, where, cap);
1553 break;
1554 case PCI_CAP_ID_VNDR:
1555 show_vendor();
1556 break;
1557 case PCI_CAP_ID_DBG:
1558 show_debug();
1559 break;
1560 case PCI_CAP_ID_SSVID:
1561 show_ssvid(d, where);
1562 break;
1563 case PCI_CAP_ID_EXP:
1564 show_express(d, where, cap);
1565 can_have_ext_caps = 1;
1566 break;
1567 case PCI_CAP_ID_MSIX:
1568 show_msix(d, where, cap);
1569 break;
1570 default:
1571 printf("#%02x [%04x]\n", id, cap);
1572 }
1573 where = next;
1574 }
1575 }
1576 if (can_have_ext_caps)
1577 show_ext_caps(d);
1578 }
1579
1580 static void
1581 show_htype0(struct device *d)
1582 {
1583 show_bases(d, 6);
1584 show_rom(d, PCI_ROM_ADDRESS);
1585 show_caps(d);
1586 }
1587
1588 static void
1589 show_htype1(struct device *d)
1590 {
1591 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1592 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1593 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1594 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1595 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1596 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1597 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1598 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1599 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1600 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1601 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1602 int verb = verbose > 2;
1603
1604 show_bases(d, 2);
1605 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1606 get_conf_byte(d, PCI_PRIMARY_BUS),
1607 get_conf_byte(d, PCI_SECONDARY_BUS),
1608 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1609 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1610
1611 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1612 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1613 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1614 else
1615 {
1616 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1617 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1618 if (io_type == PCI_IO_RANGE_TYPE_32)
1619 {
1620 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1621 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1622 }
1623 if (io_base <= io_limit || verb)
1624 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1625 }
1626
1627 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1628 mem_type)
1629 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1630 else
1631 {
1632 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1633 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1634 if (mem_base <= mem_limit || verb)
1635 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1636 }
1637
1638 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1639 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1640 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1641 else
1642 {
1643 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1644 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1645 if (pref_base <= pref_limit || verb)
1646 {
1647 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1648 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1649 else
1650 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1651 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1652 pref_base,
1653 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1654 pref_limit + 0xfffff);
1655 }
1656 }
1657
1658 if (verbose > 1)
1659 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1660 FLAG(sec_stat, PCI_STATUS_66MHZ),
1661 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1662 FLAG(sec_stat, PCI_STATUS_PARITY),
1663 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1664 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1665 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1666 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1667 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1668 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1669 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1670 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1671
1672 show_rom(d, PCI_ROM_ADDRESS1);
1673
1674 if (verbose > 1)
1675 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1676 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1677 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1678 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1679 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1680 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1681 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1682 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1683
1684 show_caps(d);
1685 }
1686
1687 static void
1688 show_htype2(struct device *d)
1689 {
1690 int i;
1691 word cmd = get_conf_word(d, PCI_COMMAND);
1692 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1693 word exca;
1694 int verb = verbose > 2;
1695
1696 show_bases(d, 1);
1697 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1698 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1699 get_conf_byte(d, PCI_CB_CARD_BUS),
1700 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1701 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1702 for(i=0; i<2; i++)
1703 {
1704 int p = 8*i;
1705 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1706 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1707 if (limit > base || verb)
1708 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1709 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1710 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1711 }
1712 for(i=0; i<2; i++)
1713 {
1714 int p = 8*i;
1715 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1716 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1717 if (!(base & PCI_IO_RANGE_TYPE_32))
1718 {
1719 base &= 0xffff;
1720 limit &= 0xffff;
1721 }
1722 base &= PCI_CB_IO_RANGE_MASK;
1723 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1724 if (base <= limit || verb)
1725 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1726 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1727 }
1728
1729 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1730 printf("\tSecondary status: SERR\n");
1731 if (verbose > 1)
1732 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1733 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1734 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1735 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1736 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1737 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1738 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1739 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1740 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1741
1742 if (d->config_cached < 128)
1743 {
1744 printf("\t<access denied to the rest>\n");
1745 return;
1746 }
1747
1748 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1749 if (exca)
1750 printf("\t16-bit legacy interface ports at %04x\n", exca);
1751 }
1752
1753 static void
1754 show_verbose(struct device *d)
1755 {
1756 struct pci_dev *p = d->dev;
1757 word status = get_conf_word(d, PCI_STATUS);
1758 word cmd = get_conf_word(d, PCI_COMMAND);
1759 word class = p->device_class;
1760 byte bist = get_conf_byte(d, PCI_BIST);
1761 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1762 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1763 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1764 byte max_lat, min_gnt;
1765 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1766 unsigned int irq = p->irq;
1767 word subsys_v = 0, subsys_d = 0;
1768 char ssnamebuf[256];
1769
1770 show_terse(d);
1771
1772 switch (htype)
1773 {
1774 case PCI_HEADER_TYPE_NORMAL:
1775 if (class == PCI_CLASS_BRIDGE_PCI)
1776 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1777 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1778 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1779 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1780 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1781 break;
1782 case PCI_HEADER_TYPE_BRIDGE:
1783 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1784 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1785 irq = int_pin = min_gnt = max_lat = 0;
1786 break;
1787 case PCI_HEADER_TYPE_CARDBUS:
1788 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1789 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1790 min_gnt = max_lat = 0;
1791 if (d->config_cached >= 128)
1792 {
1793 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1794 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1795 }
1796 break;
1797 default:
1798 printf("\t!!! Unknown header type %02x\n", htype);
1799 return;
1800 }
1801
1802 if (subsys_v && subsys_v != 0xffff)
1803 printf("\tSubsystem: %s\n",
1804 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1805 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1806 p->vendor_id, p->device_id, subsys_v, subsys_d));
1807
1808 if (verbose > 1)
1809 {
1810 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1811 FLAG(cmd, PCI_COMMAND_IO),
1812 FLAG(cmd, PCI_COMMAND_MEMORY),
1813 FLAG(cmd, PCI_COMMAND_MASTER),
1814 FLAG(cmd, PCI_COMMAND_SPECIAL),
1815 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1816 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1817 FLAG(cmd, PCI_COMMAND_PARITY),
1818 FLAG(cmd, PCI_COMMAND_WAIT),
1819 FLAG(cmd, PCI_COMMAND_SERR),
1820 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1821 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1822 FLAG(status, PCI_STATUS_CAP_LIST),
1823 FLAG(status, PCI_STATUS_66MHZ),
1824 FLAG(status, PCI_STATUS_UDF),
1825 FLAG(status, PCI_STATUS_FAST_BACK),
1826 FLAG(status, PCI_STATUS_PARITY),
1827 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1828 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1829 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1830 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1831 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1832 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1833 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1834 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1835 if (cmd & PCI_COMMAND_MASTER)
1836 {
1837 printf("\tLatency: %d", latency);
1838 if (min_gnt || max_lat)
1839 {
1840 printf(" (");
1841 if (min_gnt)
1842 printf("%dns min", min_gnt*250);
1843 if (min_gnt && max_lat)
1844 printf(", ");
1845 if (max_lat)
1846 printf("%dns max", max_lat*250);
1847 putchar(')');
1848 }
1849 if (cache_line)
1850 printf(", Cache Line Size: %d bytes", cache_line * 4);
1851 putchar('\n');
1852 }
1853 if (int_pin || irq)
1854 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1855 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1856 }
1857 else
1858 {
1859 printf("\tFlags: ");
1860 if (cmd & PCI_COMMAND_MASTER)
1861 printf("bus master, ");
1862 if (cmd & PCI_COMMAND_VGA_PALETTE)
1863 printf("VGA palette snoop, ");
1864 if (cmd & PCI_COMMAND_WAIT)
1865 printf("stepping, ");
1866 if (cmd & PCI_COMMAND_FAST_BACK)
1867 printf("fast Back2Back, ");
1868 if (status & PCI_STATUS_66MHZ)
1869 printf("66MHz, ");
1870 if (status & PCI_STATUS_UDF)
1871 printf("user-definable features, ");
1872 printf("%s devsel",
1873 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1874 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1875 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1876 if (cmd & PCI_COMMAND_MASTER)
1877 printf(", latency %d", latency);
1878 if (irq)
1879 printf(", IRQ " PCIIRQ_FMT, irq);
1880 putchar('\n');
1881 }
1882
1883 if (bist & PCI_BIST_CAPABLE)
1884 {
1885 if (bist & PCI_BIST_START)
1886 printf("\tBIST is running\n");
1887 else
1888 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1889 }
1890
1891 switch (htype)
1892 {
1893 case PCI_HEADER_TYPE_NORMAL:
1894 show_htype0(d);
1895 break;
1896 case PCI_HEADER_TYPE_BRIDGE:
1897 show_htype1(d);
1898 break;
1899 case PCI_HEADER_TYPE_CARDBUS:
1900 show_htype2(d);
1901 break;
1902 }
1903 }
1904
1905 static void
1906 show_hex_dump(struct device *d)
1907 {
1908 unsigned int i, cnt;
1909
1910 cnt = d->config_cached;
1911 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1912 {
1913 cnt = 256;
1914 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1915 cnt = 4096;
1916 }
1917
1918 for(i=0; i<cnt; i++)
1919 {
1920 if (! (i & 15))
1921 printf("%02x:", i);
1922 printf(" %02x", get_conf_byte(d, i));
1923 if ((i & 15) == 15)
1924 putchar('\n');
1925 }
1926 }
1927
1928 static void
1929 print_shell_escaped(char *c)
1930 {
1931 printf(" \"");
1932 while (*c)
1933 {
1934 if (*c == '"' || *c == '\\')
1935 putchar('\\');
1936 putchar(*c++);
1937 }
1938 putchar('"');
1939 }
1940
1941 static void
1942 show_machine(struct device *d)
1943 {
1944 struct pci_dev *p = d->dev;
1945 int c;
1946 word sv_id=0, sd_id=0;
1947 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1948
1949 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1950 {
1951 case PCI_HEADER_TYPE_NORMAL:
1952 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1953 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1954 break;
1955 case PCI_HEADER_TYPE_CARDBUS:
1956 if (d->config_cached >= 128)
1957 {
1958 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1959 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1960 }
1961 break;
1962 }
1963
1964 if (verbose)
1965 {
1966 printf((machine_readable >= 2) ? "Slot:\t" : "Device:\t");
1967 show_slot_name(d);
1968 putchar('\n');
1969 printf("Class:\t%s\n",
1970 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1971 printf("Vendor:\t%s\n",
1972 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1973 printf("Device:\t%s\n",
1974 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1975 if (sv_id && sv_id != 0xffff)
1976 {
1977 printf("SVendor:\t%s\n",
1978 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1979 printf("SDevice:\t%s\n",
1980 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1981 }
1982 if (c = get_conf_byte(d, PCI_REVISION_ID))
1983 printf("Rev:\t%02x\n", c);
1984 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1985 printf("ProgIf:\t%02x\n", c);
1986 }
1987 else
1988 {
1989 show_slot_name(d);
1990 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1991 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1992 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1993 if (c = get_conf_byte(d, PCI_REVISION_ID))
1994 printf(" -r%02x", c);
1995 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1996 printf(" -p%02x", c);
1997 if (sv_id && sv_id != 0xffff)
1998 {
1999 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2000 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2001 }
2002 else
2003 printf(" \"\" \"\"");
2004 putchar('\n');
2005 }
2006 }
2007
2008 static void
2009 show_device(struct device *d)
2010 {
2011 if (machine_readable)
2012 show_machine(d);
2013 else if (verbose)
2014 show_verbose(d);
2015 else
2016 show_terse(d);
2017 if (show_hex)
2018 show_hex_dump(d);
2019 if (verbose || show_hex)
2020 putchar('\n');
2021 }
2022
2023 static void
2024 show(void)
2025 {
2026 struct device *d;
2027
2028 for(d=first_dev; d; d=d->next)
2029 show_device(d);
2030 }
2031
2032 /* Tree output */
2033
2034 struct bridge {
2035 struct bridge *chain; /* Single-linked list of bridges */
2036 struct bridge *next, *child; /* Tree of bridges */
2037 struct bus *first_bus; /* List of buses connected to this bridge */
2038 unsigned int domain;
2039 unsigned int primary, secondary, subordinate; /* Bus numbers */
2040 struct device *br_dev;
2041 };
2042
2043 struct bus {
2044 unsigned int domain;
2045 unsigned int number;
2046 struct bus *sibling;
2047 struct device *first_dev, **last_dev;
2048 };
2049
2050 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2051
2052 static struct bus *
2053 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2054 {
2055 struct bus *bus;
2056
2057 for(bus=b->first_bus; bus; bus=bus->sibling)
2058 if (bus->domain == domain && bus->number == n)
2059 break;
2060 return bus;
2061 }
2062
2063 static struct bus *
2064 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2065 {
2066 struct bus *bus = xmalloc(sizeof(struct bus));
2067 bus->domain = domain;
2068 bus->number = n;
2069 bus->sibling = b->first_bus;
2070 bus->first_dev = NULL;
2071 bus->last_dev = &bus->first_dev;
2072 b->first_bus = bus;
2073 return bus;
2074 }
2075
2076 static void
2077 insert_dev(struct device *d, struct bridge *b)
2078 {
2079 struct pci_dev *p = d->dev;
2080 struct bus *bus;
2081
2082 if (! (bus = find_bus(b, p->domain, p->bus)))
2083 {
2084 struct bridge *c;
2085 for(c=b->child; c; c=c->next)
2086 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2087 {
2088 insert_dev(d, c);
2089 return;
2090 }
2091 bus = new_bus(b, p->domain, p->bus);
2092 }
2093 /* Simple insertion at the end _does_ guarantee the correct order as the
2094 * original device list was sorted by (domain, bus, devfn) lexicographically
2095 * and all devices on the new list have the same bus number.
2096 */
2097 *bus->last_dev = d;
2098 bus->last_dev = &d->next;
2099 d->next = NULL;
2100 }
2101
2102 static void
2103 grow_tree(void)
2104 {
2105 struct device *d, *d2;
2106 struct bridge **last_br, *b;
2107
2108 /* Build list of bridges */
2109
2110 last_br = &host_bridge.chain;
2111 for(d=first_dev; d; d=d->next)
2112 {
2113 word class = d->dev->device_class;
2114 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2115 if (class == PCI_CLASS_BRIDGE_PCI &&
2116 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2117 {
2118 b = xmalloc(sizeof(struct bridge));
2119 b->domain = d->dev->domain;
2120 if (ht == PCI_HEADER_TYPE_BRIDGE)
2121 {
2122 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2123 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2124 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2125 }
2126 else
2127 {
2128 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2129 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2130 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2131 }
2132 *last_br = b;
2133 last_br = &b->chain;
2134 b->next = b->child = NULL;
2135 b->first_bus = NULL;
2136 b->br_dev = d;
2137 }
2138 }
2139 *last_br = NULL;
2140
2141 /* Create a bridge tree */
2142
2143 for(b=&host_bridge; b; b=b->chain)
2144 {
2145 struct bridge *c, *best;
2146 best = NULL;
2147 for(c=&host_bridge; c; c=c->chain)
2148 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2149 b->primary >= c->secondary && b->primary <= c->subordinate &&
2150 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2151 best = c;
2152 if (best)
2153 {
2154 b->next = best->child;
2155 best->child = b;
2156 }
2157 }
2158
2159 /* Insert secondary bus for each bridge */
2160
2161 for(b=&host_bridge; b; b=b->chain)
2162 if (!find_bus(b, b->domain, b->secondary))
2163 new_bus(b, b->domain, b->secondary);
2164
2165 /* Create bus structs and link devices */
2166
2167 for(d=first_dev; d;)
2168 {
2169 d2 = d->next;
2170 insert_dev(d, &host_bridge);
2171 d = d2;
2172 }
2173 }
2174
2175 static void
2176 print_it(char *line, char *p)
2177 {
2178 *p++ = '\n';
2179 *p = 0;
2180 fputs(line, stdout);
2181 for(p=line; *p; p++)
2182 if (*p == '+' || *p == '|')
2183 *p = '|';
2184 else
2185 *p = ' ';
2186 }
2187
2188 static void show_tree_bridge(struct bridge *, char *, char *);
2189
2190 static void
2191 show_tree_dev(struct device *d, char *line, char *p)
2192 {
2193 struct pci_dev *q = d->dev;
2194 struct bridge *b;
2195 char namebuf[256];
2196
2197 p += sprintf(p, "%02x.%x", q->dev, q->func);
2198 for(b=&host_bridge; b; b=b->chain)
2199 if (b->br_dev == d)
2200 {
2201 if (b->secondary == b->subordinate)
2202 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2203 else
2204 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2205 show_tree_bridge(b, line, p);
2206 return;
2207 }
2208 if (verbose)
2209 p += sprintf(p, " %s",
2210 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2211 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2212 q->vendor_id, q->device_id));
2213 print_it(line, p);
2214 }
2215
2216 static void
2217 show_tree_bus(struct bus *b, char *line, char *p)
2218 {
2219 if (!b->first_dev)
2220 print_it(line, p);
2221 else if (!b->first_dev->next)
2222 {
2223 *p++ = '-';
2224 *p++ = '-';
2225 show_tree_dev(b->first_dev, line, p);
2226 }
2227 else
2228 {
2229 struct device *d = b->first_dev;
2230 while (d->next)
2231 {
2232 p[0] = '+';
2233 p[1] = '-';
2234 show_tree_dev(d, line, p+2);
2235 d = d->next;
2236 }
2237 p[0] = '\\';
2238 p[1] = '-';
2239 show_tree_dev(d, line, p+2);
2240 }
2241 }
2242
2243 static void
2244 show_tree_bridge(struct bridge *b, char *line, char *p)
2245 {
2246 *p++ = '-';
2247 if (!b->first_bus->sibling)
2248 {
2249 if (b == &host_bridge)
2250 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2251 show_tree_bus(b->first_bus, line, p);
2252 }
2253 else
2254 {
2255 struct bus *u = b->first_bus;
2256 char *k;
2257
2258 while (u->sibling)
2259 {
2260 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2261 show_tree_bus(u, line, k);
2262 u = u->sibling;
2263 }
2264 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2265 show_tree_bus(u, line, k);
2266 }
2267 }
2268
2269 static void
2270 show_forest(void)
2271 {
2272 char line[256];
2273
2274 grow_tree();
2275 show_tree_bridge(&host_bridge, line, line);
2276 }
2277
2278 /* Bus mapping mode */
2279
2280 struct bus_bridge {
2281 struct bus_bridge *next;
2282 byte this, dev, func, first, last, bug;
2283 };
2284
2285 struct bus_info {
2286 byte exists;
2287 byte guestbook;
2288 struct bus_bridge *bridges, *via;
2289 };
2290
2291 static struct bus_info *bus_info;
2292
2293 static void
2294 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2295 {
2296 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2297 struct pci_dev *p = d->dev;
2298
2299 b->next = bi->bridges;
2300 bi->bridges = b;
2301 b->this = get_conf_byte(d, np);
2302 b->dev = p->dev;
2303 b->func = p->func;
2304 b->first = get_conf_byte(d, ns);
2305 b->last = get_conf_byte(d, nl);
2306 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2307 p->bus, p->dev, p->func, b->this, b->first, b->last);
2308 if (b->this != p->bus)
2309 printf("!!! Bridge points to invalid primary bus.\n");
2310 if (b->first > b->last)
2311 {
2312 printf("!!! Bridge points to invalid bus range.\n");
2313 b->last = b->first;
2314 }
2315 }
2316
2317 static void
2318 do_map_bus(int bus)
2319 {
2320 int dev, func;
2321 int verbose = pacc->debugging;
2322 struct bus_info *bi = bus_info + bus;
2323 struct device *d;
2324
2325 if (verbose)
2326 printf("Mapping bus %02x\n", bus);
2327 for(dev = 0; dev < 32; dev++)
2328 if (filter.slot < 0 || filter.slot == dev)
2329 {
2330 int func_limit = 1;
2331 for(func = 0; func < func_limit; func++)
2332 if (filter.func < 0 || filter.func == func)
2333 {
2334 /* XXX: Bus mapping supports only domain 0 */
2335 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2336 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2337 if (vendor && vendor != 0xffff)
2338 {
2339 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2340 func_limit = 8;
2341 if (verbose)
2342 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2343 bi->exists = 1;
2344 if (d = scan_device(p))
2345 {
2346 show_device(d);
2347 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2348 {
2349 case PCI_HEADER_TYPE_BRIDGE:
2350 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2351 break;
2352 case PCI_HEADER_TYPE_CARDBUS:
2353 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2354 break;
2355 }
2356 free(d);
2357 }
2358 else if (verbose)
2359 printf("But it was filtered out.\n");
2360 }
2361 pci_free_dev(p);
2362 }
2363 }
2364 }
2365
2366 static void
2367 do_map_bridges(int bus, int min, int max)
2368 {
2369 struct bus_info *bi = bus_info + bus;
2370 struct bus_bridge *b;
2371
2372 bi->guestbook = 1;
2373 for(b=bi->bridges; b; b=b->next)
2374 {
2375 if (bus_info[b->first].guestbook)
2376 b->bug = 1;
2377 else if (b->first < min || b->last > max)
2378 b->bug = 2;
2379 else
2380 {
2381 bus_info[b->first].via = b;
2382 do_map_bridges(b->first, b->first, b->last);
2383 }
2384 }
2385 }
2386
2387 static void
2388 map_bridges(void)
2389 {
2390 int i;
2391
2392 printf("\nSummary of buses:\n\n");
2393 for(i=0; i<256; i++)
2394 if (bus_info[i].exists && !bus_info[i].guestbook)
2395 do_map_bridges(i, 0, 255);
2396 for(i=0; i<256; i++)
2397 {
2398 struct bus_info *bi = bus_info + i;
2399 struct bus_bridge *b = bi->via;
2400
2401 if (bi->exists)
2402 {
2403 printf("%02x: ", i);
2404 if (b)
2405 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2406 else if (!i)
2407 printf("Primary host bus\n");
2408 else
2409 printf("Secondary host bus (?)\n");
2410 }
2411 for(b=bi->bridges; b; b=b->next)
2412 {
2413 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2414 switch (b->bug)
2415 {
2416 case 1:
2417 printf(" <overlap bug>");
2418 break;
2419 case 2:
2420 printf(" <crossing bug>");
2421 break;
2422 }
2423 putchar('\n');
2424 }
2425 }
2426 }
2427
2428 static void
2429 map_the_bus(void)
2430 {
2431 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2432 pacc->method == PCI_ACCESS_DUMP)
2433 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2434 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2435 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2436 if (filter.bus >= 0)
2437 do_map_bus(filter.bus);
2438 else
2439 {
2440 int bus;
2441 for(bus=0; bus<256; bus++)
2442 do_map_bus(bus);
2443 }
2444 map_bridges();
2445 }
2446
2447 /* Main */
2448
2449 int
2450 main(int argc, char **argv)
2451 {
2452 int i;
2453 char *msg;
2454
2455 if (argc == 2 && !strcmp(argv[1], "--version"))
2456 {
2457 puts("lspci version " PCIUTILS_VERSION);
2458 return 0;
2459 }
2460
2461 pacc = pci_alloc();
2462 pacc->error = die;
2463 pci_filter_init(pacc, &filter);
2464
2465 while ((i = getopt(argc, argv, options)) != -1)
2466 switch (i)
2467 {
2468 case 'n':
2469 pacc->numeric_ids++;
2470 break;
2471 case 'v':
2472 verbose++;
2473 break;
2474 case 'b':
2475 pacc->buscentric = 1;
2476 buscentric_view = 1;
2477 break;
2478 case 's':
2479 if (msg = pci_filter_parse_slot(&filter, optarg))
2480 die("-s: %s", msg);
2481 break;
2482 case 'd':
2483 if (msg = pci_filter_parse_id(&filter, optarg))
2484 die("-d: %s", msg);
2485 break;
2486 case 'x':
2487 show_hex++;
2488 break;
2489 case 't':
2490 show_tree++;
2491 break;
2492 case 'i':
2493 pci_set_name_list_path(pacc, optarg, 0);
2494 break;
2495 case 'm':
2496 machine_readable++;
2497 break;
2498 case 'M':
2499 map_mode++;
2500 break;
2501 case 'D':
2502 show_domains = 2;
2503 break;
2504 default:
2505 if (parse_generic_option(i, pacc, optarg))
2506 break;
2507 bad:
2508 fprintf(stderr, help_msg, pacc->id_file_name);
2509 return 1;
2510 }
2511 if (optind < argc)
2512 goto bad;
2513
2514 pci_init(pacc);
2515 if (map_mode)
2516 map_the_bus();
2517 else
2518 {
2519 scan_devices();
2520 sort_them();
2521 if (show_tree)
2522 show_forest();
2523 else
2524 show();
2525 }
2526 pci_cleanup(pacc);
2527
2528 return (seen_errors ? 2 : 0);
2529 }
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