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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
b940ca64 2/*
a6f2a6ea
YG
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
87519a9e 5 * Copyright 2017-2018 NXP
b940ca64 6 */
21c69870 7#include <common.h>
7b51b576 8#include <env.h>
b940ca64 9#include <errno.h>
84b8bf6d 10#include <linux/bug.h>
b940ca64 11#include <asm/io.h>
b08c8c48 12#include <linux/libfdt.h>
5707dfb0 13#include <net.h>
21c69870 14#include <fdt_support.h>
7b3bd9a7
GR
15#include <fsl-mc/fsl_mc.h>
16#include <fsl-mc/fsl_mc_sys.h>
a2a55e51 17#include <fsl-mc/fsl_mc_private.h>
7b3bd9a7 18#include <fsl-mc/fsl_dpmng.h>
a2a55e51
PK
19#include <fsl-mc/fsl_dprc.h>
20#include <fsl-mc/fsl_dpio.h>
fb4a87a7 21#include <fsl-mc/fsl_dpni.h>
a2a55e51 22#include <fsl-mc/fsl_qbman_portal.h>
fb4a87a7 23#include <fsl-mc/ldpaa_wriop.h>
b940ca64 24
125e2bc1
GR
25#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
26#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
27#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
28
29#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
30#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
33a8991a 31#define MC_BOOT_ENV_VAR "mcinitcmd"
43ad41e6 32#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
125e2bc1 33
b940ca64 34DECLARE_GLOBAL_DATA_PTR;
87519a9e 35static int mc_memset_resv_ram;
fb4a87a7
PK
36static int mc_boot_status = -1;
37static int mc_dpl_applied = -1;
38#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
39static int mc_aiop_applied = -1;
40#endif
1730a17d
PK
41struct fsl_mc_io *root_mc_io = NULL;
42struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
43uint16_t root_dprc_handle = 0;
a2a55e51 44uint16_t dflt_dprc_handle = 0;
1730a17d 45int child_dprc_id;
a2a55e51
PK
46struct fsl_dpbp_obj *dflt_dpbp = NULL;
47struct fsl_dpio_obj *dflt_dpio = NULL;
1730a17d 48struct fsl_dpni_obj *dflt_dpni = NULL;
b7b8410a 49static u64 mc_lazy_dpl_addr;
125e2bc1
GR
50
51#ifdef DEBUG
52void dump_ram_words(const char *title, void *addr)
53{
54 int i;
55 uint32_t *words = addr;
56
57 printf("Dumping beginning of %s (%p):\n", title, addr);
58 for (i = 0; i < 16; i++)
59 printf("%#x ", words[i]);
60
61 printf("\n");
62}
b940ca64 63
125e2bc1
GR
64void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
65{
66 printf("MC CCSR registers:\n"
67 "reg_gcr1 %#x\n"
68 "reg_gsr %#x\n"
69 "reg_sicbalr %#x\n"
70 "reg_sicbahr %#x\n"
71 "reg_sicapr %#x\n"
72 "reg_mcfbalr %#x\n"
73 "reg_mcfbahr %#x\n"
74 "reg_mcfapr %#x\n"
75 "reg_psr %#x\n",
76 mc_ccsr_regs->reg_gcr1,
77 mc_ccsr_regs->reg_gsr,
78 mc_ccsr_regs->reg_sicbalr,
79 mc_ccsr_regs->reg_sicbahr,
80 mc_ccsr_regs->reg_sicapr,
81 mc_ccsr_regs->reg_mcfbalr,
82 mc_ccsr_regs->reg_mcfbahr,
83 mc_ccsr_regs->reg_mcfapr,
84 mc_ccsr_regs->reg_psr);
85}
86#else
87
88#define dump_ram_words(title, addr)
89#define dump_mc_ccsr_regs(mc_ccsr_regs)
90
91#endif /* DEBUG */
92
93#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
94/**
95 * Copying MC firmware or DPL image to DDR
96 */
97static int mc_copy_image(const char *title,
7b3bd9a7 98 u64 image_addr, u32 image_size, u64 mc_ram_addr)
b940ca64
GR
99{
100 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
101 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
125e2bc1 102 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
b940ca64
GR
103 return 0;
104}
105
106/**
107 * MC firmware FIT image parser checks if the image is in FIT
108 * format, verifies integrity of the image and calculates
109 * raw image address and size values.
7b3bd9a7 110 * Returns 0 on success and a negative errno on error.
b940ca64
GR
111 * task fail.
112 **/
fb4a87a7
PK
113int parse_mc_firmware_fit_image(u64 mc_fw_addr,
114 const void **raw_image_addr,
b940ca64
GR
115 size_t *raw_image_size)
116{
117 int format;
118 void *fit_hdr;
119 int node_offset;
120 const void *data;
121 size_t size;
122 const char *uname = "firmware";
123
fb4a87a7 124 fit_hdr = (void *)mc_fw_addr;
b940ca64
GR
125
126 /* Check if Image is in FIT format */
127 format = genimg_get_format(fit_hdr);
128
129 if (format != IMAGE_FORMAT_FIT) {
fb4a87a7 130 printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
7b3bd9a7 131 return -EINVAL;
b940ca64
GR
132 }
133
134 if (!fit_check_format(fit_hdr)) {
fb4a87a7 135 printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
7b3bd9a7 136 return -EINVAL;
b940ca64
GR
137 }
138
139 node_offset = fit_image_get_node(fit_hdr, uname);
140
141 if (node_offset < 0) {
fb4a87a7 142 printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
7b3bd9a7 143 return -ENOENT;
b940ca64
GR
144 }
145
146 /* Verify MC firmware image */
147 if (!(fit_image_verify(fit_hdr, node_offset))) {
fb4a87a7 148 printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
7b3bd9a7 149 return -EINVAL;
b940ca64
GR
150 }
151
152 /* Get address and size of raw image */
153 fit_image_get_data(fit_hdr, node_offset, &data, &size);
154
155 *raw_image_addr = data;
156 *raw_image_size = size;
157
158 return 0;
159}
125e2bc1
GR
160#endif
161
1161dbcc
BP
162#define MC_DT_INCREASE_SIZE 64
163
164enum mc_fixup_type {
165 MC_FIXUP_DPL,
166 MC_FIXUP_DPC
167};
168
169static int mc_fixup_mac_addr(void *blob, int nodeoffset,
170 const char *propname, struct eth_device *eth_dev,
171 enum mc_fixup_type type)
5707dfb0 172{
1161dbcc
BP
173 int err = 0, len = 0, size, i;
174 unsigned char env_enetaddr[ARP_HLEN];
175 unsigned int enetaddr_32[ARP_HLEN];
176 void *val = NULL;
177
178 switch (type) {
179 case MC_FIXUP_DPL:
180 /* DPL likes its addresses on 32 * ARP_HLEN bits */
181 for (i = 0; i < ARP_HLEN; i++)
182 enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
183 val = enetaddr_32;
184 len = sizeof(enetaddr_32);
185 break;
186
187 case MC_FIXUP_DPC:
188 val = eth_dev->enetaddr;
189 len = ARP_HLEN;
190 break;
191 }
192
193 /* MAC address property present */
194 if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
195 /* u-boot MAC addr randomly assigned - leave the present one */
35affd7a
SG
196 if (!eth_env_get_enetaddr_by_index("eth", eth_dev->index,
197 env_enetaddr))
1161dbcc
BP
198 return err;
199 } else {
200 size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
201 /* make room for mac address property */
202 err = fdt_increase_size(blob, size);
203 if (err) {
204 printf("fdt_increase_size: err=%s\n",
205 fdt_strerror(err));
206 return err;
207 }
208 }
209
210 err = fdt_setprop(blob, nodeoffset, propname, val, len);
211 if (err) {
212 printf("fdt_setprop: err=%s\n", fdt_strerror(err));
213 return err;
214 }
215
216 return err;
217}
218
219#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
220
221const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
222{
223 int connoffset = fdt_path_offset(blob, "/connections"), off;
224 const char *s1, *s2;
225
226 for (off = fdt_first_subnode(blob, connoffset);
227 off >= 0;
228 off = fdt_next_subnode(blob, off)) {
229 s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
230 s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
231
232 if (!s1 || !s2)
233 continue;
234
235 if (strcmp(endpoint, s1) == 0)
236 return s2;
237
238 if (strcmp(endpoint, s2) == 0)
239 return s1;
240 }
241
242 return NULL;
243}
244
245static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
246 struct eth_device *eth_dev)
247{
248 int objoff = fdt_path_offset(blob, "/objects");
249 int dpmacoff = -1, dpnioff = -1;
250 const char *endpoint;
251 char mac_name[10];
252 int err;
253
254 sprintf(mac_name, "dpmac@%d", dpmac_id);
255 dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
256 if (dpmacoff < 0)
257 /* dpmac not defined in DPL, so skip it. */
258 return 0;
259
260 err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
261 MC_FIXUP_DPL);
262 if (err) {
263 printf("Error fixing up dpmac mac_addr in DPL\n");
264 return err;
265 }
266
267 /* now we need to figure out if there is any
268 * DPNI connected to this MAC, so we walk the
269 * connection list
270 */
271 endpoint = dpl_get_connection_endpoint(blob, mac_name);
272 if (!is_dpni(endpoint))
273 return 0;
274
275 /* let's see if we can fixup the DPNI as well */
276 dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
277 if (dpnioff < 0)
278 /* DPNI not defined in DPL in the objects area */
279 return 0;
280
281 return mc_fixup_mac_addr(blob, dpnioff, "mac_addr", eth_dev,
282 MC_FIXUP_DPL);
283}
284
cf0bbbd1
MA
285void fdt_fixup_mc_ddr(u64 *base, u64 *size)
286{
287 u64 mc_size = mc_get_dram_block_size();
288
289 if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
290 *base = mc_get_dram_addr() + mc_size;
291 *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
292 }
293}
294
a78df40c
NG
295void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
296{
297 u32 *prop;
298 u32 iommu_map[4];
299 int offset;
300 int lenp;
301
302 /* find fsl-mc node */
303 offset = fdt_path_offset(blob, "/soc/fsl-mc");
304 if (offset < 0)
305 offset = fdt_path_offset(blob, "/fsl-mc");
306 if (offset < 0) {
307 printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n",
308 __func__, offset);
309 return;
310 }
311
312 prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp);
313 if (!prop) {
314 debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n",
315 __func__);
316 return;
317 }
318
319 iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
320 iommu_map[1] = *++prop;
321 iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
322 iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END -
323 FSL_DPAA2_STREAM_ID_START + 1);
324
325 fdt_setprop_inplace(blob, offset, "iommu-map",
326 iommu_map, sizeof(iommu_map));
327}
328
1161dbcc
BP
329static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
330 struct eth_device *eth_dev)
331{
332 int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
333 int err = 0;
5707dfb0 334 char mac_name[10];
1161dbcc 335 const char link_type_mode[] = "MAC_LINK_TYPE_FIXED";
5707dfb0
BP
336
337 sprintf(mac_name, "mac@%d", dpmac_id);
338
339 /* node not found - create it */
1161dbcc
BP
340 noff = fdt_subnode_offset(blob, nodeoffset, (const char *)mac_name);
341 if (noff < 0) {
5707dfb0
BP
342 err = fdt_increase_size(blob, 200);
343 if (err) {
344 printf("fdt_increase_size: err=%s\n",
345 fdt_strerror(err));
346 return err;
347 }
348
1161dbcc
BP
349 noff = fdt_add_subnode(blob, nodeoffset, mac_name);
350 if (noff < 0) {
351 printf("fdt_add_subnode: err=%s\n",
352 fdt_strerror(err));
353 return err;
354 }
5707dfb0
BP
355
356 /* add default property of fixed link */
1161dbcc 357 err = fdt_appendprop_string(blob, noff,
5707dfb0
BP
358 "link_type", link_type_mode);
359 if (err) {
360 printf("fdt_appendprop_string: err=%s\n",
361 fdt_strerror(err));
362 return err;
363 }
364 }
365
1161dbcc
BP
366 return mc_fixup_mac_addr(blob, noff, "port_mac_address", eth_dev,
367 MC_FIXUP_DPC);
368}
5707dfb0 369
1161dbcc
BP
370static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
371{
372 int i, err = 0, ret = 0;
c022ec03 373 char ethname[ETH_NAME_LEN];
1161dbcc 374 struct eth_device *eth_dev;
5707dfb0 375
1161dbcc
BP
376 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
377 /* port not enabled */
1ed19a14 378 if (wriop_is_enabled_dpmac(i) != 1)
1161dbcc 379 continue;
5707dfb0 380
c022ec03
PB
381 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
382 phy_interface_strings[wriop_get_enet_if(i)]);
5707dfb0 383
1161dbcc
BP
384 eth_dev = eth_get_dev_by_name(ethname);
385 if (eth_dev == NULL)
386 continue;
387
388 switch (type) {
389 case MC_FIXUP_DPL:
390 err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
391 break;
392 case MC_FIXUP_DPC:
393 err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
394 break;
395 default:
396 break;
397 }
398
399 if (err)
400 printf("fsl-mc: ERROR fixing mac address for %s\n",
401 ethname);
402 ret |= err;
5707dfb0
BP
403 }
404
1161dbcc 405 return ret;
5707dfb0
BP
406}
407
21c69870
SY
408static int mc_fixup_dpc(u64 dpc_addr)
409{
410 void *blob = (void *)dpc_addr;
5707dfb0 411 int nodeoffset, err = 0;
21c69870
SY
412
413 /* delete any existing ICID pools */
414 nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
415 if (fdt_del_node(blob, nodeoffset) < 0)
416 printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
417
418 /* add a new pool */
419 nodeoffset = fdt_path_offset(blob, "/resources");
420 if (nodeoffset < 0) {
421 printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
422 return -EINVAL;
423 }
424 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools");
425 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0");
426 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
427 "base_icid", FSL_DPAA2_STREAM_ID_START, 1);
428 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
429 "num",
430 FSL_DPAA2_STREAM_ID_END -
431 FSL_DPAA2_STREAM_ID_START + 1, 1);
432
5707dfb0
BP
433 /* fixup MAC addresses for dpmac ports */
434 nodeoffset = fdt_path_offset(blob, "/board_info/ports");
435 if (nodeoffset < 0)
2e9f1bf5 436 goto out;
5707dfb0 437
1161dbcc 438 err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
2e9f1bf5
ICR
439
440out:
21c69870
SY
441 flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
442
5707dfb0 443 return err;
21c69870
SY
444}
445
fb4a87a7 446static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
125e2bc1
GR
447{
448 u64 mc_dpc_offset;
449#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
450 int error;
451 void *dpc_fdt_hdr;
452 int dpc_size;
453#endif
454
455#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
456 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
457 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
458
459 mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
460#else
461#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
462#endif
463
464 /*
465 * Load the MC DPC blob in the MC private DRAM block:
466 */
467#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
468 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
469#else
470 /*
471 * Get address and size of the DPC blob stored in flash:
472 */
fb4a87a7 473 dpc_fdt_hdr = (void *)mc_dpc_addr;
125e2bc1
GR
474
475 error = fdt_check_header(dpc_fdt_hdr);
476 if (error != 0) {
477 /*
478 * Don't return with error here, since the MC firmware can
479 * still boot without a DPC
480 */
cc088c3a 481 printf("\nfsl-mc: WARNING: No DPC image found");
125e2bc1
GR
482 return 0;
483 }
484
485 dpc_size = fdt_totalsize(dpc_fdt_hdr);
486 if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
cc088c3a 487 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
125e2bc1
GR
488 dpc_size);
489 return -EINVAL;
490 }
491
492 mc_copy_image("MC DPC blob",
493 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
494#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
495
21c69870
SY
496 if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
497 return -EINVAL;
498
125e2bc1
GR
499 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
500 return 0;
501}
502
1161dbcc
BP
503
504static int mc_fixup_dpl(u64 dpl_addr)
505{
506 void *blob = (void *)dpl_addr;
507 u32 ver = fdt_getprop_u32_default(blob, "/", "dpl-version", 0);
508 int err = 0;
509
510 /* The DPL fixup for mac addresses is only relevant
511 * for old-style DPLs
512 */
513 if (ver >= 10)
514 return 0;
515
516 err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPL);
517 flush_dcache_range(dpl_addr, dpl_addr + fdt_totalsize(blob));
518
519 return err;
520}
521
fb4a87a7 522static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
125e2bc1
GR
523{
524 u64 mc_dpl_offset;
525#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
526 int error;
527 void *dpl_fdt_hdr;
528 int dpl_size;
529#endif
530
531#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
532 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
533 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
534
535 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
536#else
537#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
538#endif
539
540 /*
541 * Load the MC DPL blob in the MC private DRAM block:
542 */
543#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
544 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
545#else
546 /*
547 * Get address and size of the DPL blob stored in flash:
548 */
fb4a87a7 549 dpl_fdt_hdr = (void *)mc_dpl_addr;
125e2bc1
GR
550
551 error = fdt_check_header(dpl_fdt_hdr);
552 if (error != 0) {
cc088c3a 553 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
125e2bc1
GR
554 return error;
555 }
556
557 dpl_size = fdt_totalsize(dpl_fdt_hdr);
558 if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
cc088c3a 559 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
125e2bc1
GR
560 dpl_size);
561 return -EINVAL;
562 }
563
564 mc_copy_image("MC DPL blob",
565 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
566#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
567
1161dbcc
BP
568 if (mc_fixup_dpl(mc_ram_addr + mc_dpl_offset))
569 return -EINVAL;
125e2bc1
GR
570 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
571 return 0;
572}
573
574/**
575 * Return the MC boot timeout value in milliseconds
576 */
577static unsigned long get_mc_boot_timeout_ms(void)
578{
579 unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
580
00caae6d 581 char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
125e2bc1
GR
582
583 if (timeout_ms_env_var) {
584 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
585 if (timeout_ms == 0) {
586 printf("fsl-mc: WARNING: Invalid value for \'"
587 MC_BOOT_TIMEOUT_ENV_VAR
588 "\' environment variable: %lu\n",
589 timeout_ms);
590
591 timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
592 }
593 }
594
595 return timeout_ms;
596}
597
fb4a87a7 598#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
3c1d218a
YS
599
600__weak bool soc_has_aiop(void)
601{
602 return false;
603}
604
fb4a87a7 605static int load_mc_aiop_img(u64 aiop_fw_addr)
c1000c12 606{
fb4a87a7
PK
607 u64 mc_ram_addr = mc_get_dram_addr();
608#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
c1000c12 609 void *aiop_img;
fb4a87a7 610#endif
c1000c12 611
3c1d218a
YS
612 /* Check if AIOP is available */
613 if (!soc_has_aiop())
614 return -ENODEV;
c1000c12
GR
615 /*
616 * Load the MC AIOP image in the MC private DRAM block:
617 */
618
fb4a87a7
PK
619#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
620 printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
621 CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
622#else
623 aiop_img = (void *)aiop_fw_addr;
c1000c12
GR
624 mc_copy_image("MC AIOP image",
625 (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
626 mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
fb4a87a7
PK
627#endif
628 mc_aiop_applied = 0;
c1000c12
GR
629
630 return 0;
631}
632#endif
fb4a87a7 633
125e2bc1
GR
634static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
635{
636 u32 reg_gsr;
637 u32 mc_fw_boot_status;
638 unsigned long timeout_ms = get_mc_boot_timeout_ms();
639 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
640
641 dmb();
125e2bc1
GR
642 assert(timeout_ms > 0);
643 for (;;) {
644 udelay(1000); /* throttle polling */
645 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
646 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
647 if (mc_fw_boot_status & 0x1)
648 break;
649
650 timeout_ms--;
651 if (timeout_ms == 0)
652 break;
653 }
654
655 if (timeout_ms == 0) {
cc088c3a 656 printf("ERROR: timeout\n");
125e2bc1
GR
657
658 /* TODO: Get an error status from an MC CCSR register */
659 return -ETIMEDOUT;
660 }
661
662 if (mc_fw_boot_status != 0x1) {
663 /*
664 * TODO: Identify critical errors from the GSR register's FS
665 * field and for those errors, set error to -ENODEV or other
666 * appropriate errno, so that the status property is set to
667 * failure in the fsl,dprc device tree node.
668 */
cc088c3a
GR
669 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
670 reg_gsr);
671 } else {
672 printf("SUCCESS\n");
125e2bc1
GR
673 }
674
cc088c3a 675
125e2bc1
GR
676 *final_reg_gsr = reg_gsr;
677 return 0;
678}
b940ca64 679
fb4a87a7 680int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
b940ca64
GR
681{
682 int error = 0;
a2a55e51 683 int portal_id = 0;
b940ca64 684 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
fb4a87a7 685 u64 mc_ram_addr = mc_get_dram_addr();
b940ca64 686 u32 reg_gsr;
125e2bc1
GR
687 u32 reg_mcfbalr;
688#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
689 const void *raw_image_addr;
690 size_t raw_image_size = 0;
125e2bc1 691#endif
7b3bd9a7 692 struct mc_version mc_ver_info;
125e2bc1
GR
693 u8 mc_ram_num_256mb_blocks;
694 size_t mc_ram_size = mc_get_dram_block_size();
b940ca64 695
437858b6 696 mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
43ad41e6
MA
697
698 if (mc_ram_num_256mb_blocks >= 0xff) {
437858b6
YS
699 error = -EINVAL;
700 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
701 mc_ram_size);
125e2bc1 702 goto out;
437858b6 703 }
125e2bc1 704
43ad41e6
MA
705 /*
706 * To support 128 MB DDR Size for MC
707 */
708 if (mc_ram_num_256mb_blocks == 0)
709 mc_ram_num_256mb_blocks = 0xFF;
710
b940ca64
GR
711 /*
712 * Management Complex cores should be held at reset out of POR.
a187559e 713 * U-Boot should be the first software to touch MC. To be safe,
b940ca64
GR
714 * we reset all cores again by setting GCR1 to 0. It doesn't do
715 * anything if they are held at reset. After we setup the firmware
716 * we kick off MC by deasserting the reset bit for core 0, and
717 * deasserting the reset bits for Command Portal Managers.
718 * The stop bits are not touched here. They are used to stop the
719 * cores when they are active. Setting stop bits doesn't stop the
720 * cores from fetching instructions when they are released from
721 * reset.
722 */
723 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
724 dmb();
725
125e2bc1
GR
726#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
727 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
728#else
fb4a87a7
PK
729 error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
730 &raw_image_size);
b940ca64
GR
731 if (error != 0)
732 goto out;
733 /*
734 * Load the MC FW at the beginning of the MC private DRAM block:
735 */
7b3bd9a7
GR
736 mc_copy_image("MC Firmware",
737 (u64)raw_image_addr, raw_image_size, mc_ram_addr);
7b3bd9a7 738#endif
125e2bc1 739 dump_ram_words("firmware", (void *)mc_ram_addr);
7b3bd9a7 740
fb4a87a7 741 error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
125e2bc1 742 if (error != 0)
b940ca64 743 goto out;
b940ca64
GR
744
745 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
125e2bc1 746 dump_mc_ccsr_regs(mc_ccsr_regs);
b940ca64
GR
747
748 /*
125e2bc1 749 * Tell MC what is the address range of the DRAM block assigned to it:
b940ca64 750 */
43ad41e6
MA
751 if (mc_ram_num_256mb_blocks < 0xFF) {
752 reg_mcfbalr = (u32)mc_ram_addr |
753 (mc_ram_num_256mb_blocks - 1);
754 } else {
755 reg_mcfbalr = (u32)mc_ram_addr |
756 (mc_ram_num_256mb_blocks);
757 }
758
125e2bc1
GR
759 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
760 out_le32(&mc_ccsr_regs->reg_mcfbahr,
437858b6 761 (u32)(mc_ram_addr >> 32));
39da644e 762 out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
b940ca64
GR
763
764 /*
125e2bc1 765 * Tell the MC that we want delayed DPL deployment.
b940ca64 766 */
125e2bc1 767 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
b940ca64 768
cc088c3a 769 printf("\nfsl-mc: Booting Management Complex ... ");
7b3bd9a7 770
b940ca64
GR
771 /*
772 * Deassert reset and release MC core 0 to run
773 */
774 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
125e2bc1
GR
775 error = wait_for_mc(true, &reg_gsr);
776 if (error != 0)
b940ca64 777 goto out;
b940ca64 778
7b3bd9a7
GR
779 /*
780 * TODO: need to obtain the portal_id for the root container from the
781 * DPL
782 */
783 portal_id = 0;
784
785 /*
a2a55e51
PK
786 * Initialize the global default MC portal
787 * And check that the MC firmware is responding portal commands:
7b3bd9a7 788 */
a572fb6b 789 root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
1730a17d 790 if (!root_mc_io) {
a572fb6b 791 printf(" No memory: calloc() failed\n");
a2a55e51
PK
792 return -ENOMEM;
793 }
794
1730a17d 795 root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
7b3bd9a7 796 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
1730a17d 797 portal_id, root_mc_io->mmio_regs);
7b3bd9a7 798
1730a17d 799 error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
7b3bd9a7
GR
800 if (error != 0) {
801 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
802 error);
803 goto out;
804 }
805
7b3bd9a7
GR
806 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
807 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
125e2bc1
GR
808 reg_gsr & GSR_FS_MASK);
809
fb4a87a7
PK
810out:
811 if (error != 0)
812 mc_boot_status = error;
813 else
814 mc_boot_status = 0;
815
816 return error;
817}
818
819int mc_apply_dpl(u64 mc_dpl_addr)
820{
821 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
822 int error = 0;
823 u32 reg_gsr;
824 u64 mc_ram_addr = mc_get_dram_addr();
825 size_t mc_ram_size = mc_get_dram_block_size();
826
b7b8410a
AG
827 if (!mc_dpl_addr)
828 return -1;
829
fb4a87a7
PK
830 error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
831 if (error != 0)
832 return error;
833
125e2bc1
GR
834 /*
835 * Tell the MC to deploy the DPL:
836 */
837 out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
cc088c3a 838 printf("fsl-mc: Deploying data path layout ... ");
125e2bc1 839 error = wait_for_mc(false, &reg_gsr);
cc088c3a 840
fb4a87a7
PK
841 if (!error)
842 mc_dpl_applied = 0;
b940ca64
GR
843
844 return error;
845}
846
847int get_mc_boot_status(void)
848{
849 return mc_boot_status;
850}
851
fb4a87a7
PK
852#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
853int get_aiop_apply_status(void)
854{
855 return mc_aiop_applied;
856}
857#endif
858
859int get_dpl_apply_status(void)
860{
861 return mc_dpl_applied;
862}
863
7e968049
MYK
864int is_lazy_dpl_addr_valid(void)
865{
866 return !!mc_lazy_dpl_addr;
867}
868
033c538e 869/*
fb4a87a7 870 * Return the MC address of private DRAM block.
033c538e
PJ
871 * As per MC design document, MC initial base address
872 * should be least significant 512MB address of MC private
873 * memory, i.e. address should point to end address masked
874 * with 512MB offset in private DRAM block.
fb4a87a7
PK
875 */
876u64 mc_get_dram_addr(void)
877{
033c538e
PJ
878 size_t mc_ram_size = mc_get_dram_block_size();
879
87519a9e
PK
880 if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
881 mc_memset_resv_ram = 1;
882 memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
883 }
884
033c538e
PJ
885 return (gd->arch.resv_ram + mc_ram_size - 1) &
886 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
fb4a87a7
PK
887}
888
b940ca64
GR
889/**
890 * Return the actual size of the MC private DRAM block.
b940ca64
GR
891 */
892unsigned long mc_get_dram_block_size(void)
893{
125e2bc1
GR
894 unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
895
00caae6d 896 char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
125e2bc1
GR
897
898 if (dram_block_size_env_var) {
899 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
f53e12d8 900 16);
125e2bc1
GR
901
902 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
903 printf("fsl-mc: WARNING: Invalid value for \'"
904 MC_MEM_SIZE_ENV_VAR
905 "\' environment variable: %lu\n",
906 dram_block_size);
907
43ad41e6 908 dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
125e2bc1
GR
909 }
910 }
911
912 return dram_block_size;
b940ca64 913}
a2a55e51 914
1730a17d
PK
915int fsl_mc_ldpaa_init(bd_t *bis)
916{
c919ab9e
PK
917 int i;
918
919 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
1ed19a14 920 if (wriop_is_enabled_dpmac(i) == 1)
c919ab9e 921 ldpaa_eth_init(i, wriop_get_enet_if(i));
1730a17d
PK
922 return 0;
923}
924
9a696f56
PK
925static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
926{
9a696f56 927 int error;
2557c5a9 928 uint16_t major_ver, minor_ver;
9a696f56 929
2557c5a9
YG
930 error = dprc_get_api_version(mc_io, 0,
931 &major_ver,
932 &minor_ver);
933 if (error < 0) {
934 printf("dprc_get_api_version() failed: %d\n", error);
935 return error;
936 }
937
938 if (major_ver < DPRC_VER_MAJOR || (major_ver == DPRC_VER_MAJOR &&
939 minor_ver < DPRC_VER_MINOR)) {
940 printf("DPRC version mismatch found %u.%u,",
941 major_ver, minor_ver);
942 printf("supported version is %u.%u\n",
943 DPRC_VER_MAJOR, DPRC_VER_MINOR);
9a696f56 944 }
2557c5a9 945
9a696f56
PK
946 return error;
947}
948
1730a17d 949static int dpio_init(void)
a2a55e51
PK
950{
951 struct qbman_swp_desc p_des;
952 struct dpio_attr attr;
1730a17d 953 struct dpio_cfg dpio_cfg;
a2a55e51 954 int err = 0;
2557c5a9 955 uint16_t major_ver, minor_ver;
a2a55e51 956
a572fb6b
PK
957 dflt_dpio = (struct fsl_dpio_obj *)calloc(
958 sizeof(struct fsl_dpio_obj), 1);
a2a55e51 959 if (!dflt_dpio) {
a572fb6b 960 printf("No memory: calloc() failed\n");
1730a17d 961 err = -ENOMEM;
a572fb6b 962 goto err_calloc;
a2a55e51 963 }
1730a17d
PK
964 dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
965 dpio_cfg.num_priorities = 8;
a2a55e51 966
2557c5a9
YG
967 err = dpio_create(dflt_mc_io,
968 dflt_dprc_handle,
969 MC_CMD_NO_FLAGS,
970 &dpio_cfg,
971 &dflt_dpio->dpio_id);
1730a17d
PK
972 if (err < 0) {
973 printf("dpio_create() failed: %d\n", err);
974 err = -ENODEV;
975 goto err_create;
a2a55e51
PK
976 }
977
2557c5a9
YG
978 err = dpio_get_api_version(dflt_mc_io, 0,
979 &major_ver,
980 &minor_ver);
981 if (err < 0) {
982 printf("dpio_get_api_version() failed: %d\n", err);
983 goto err_get_api_ver;
984 }
985
986 if (major_ver < DPIO_VER_MAJOR || (major_ver == DPIO_VER_MAJOR &&
987 minor_ver < DPIO_VER_MINOR)) {
988 printf("DPRC version mismatch found %u.%u,",
989 major_ver,
990 minor_ver);
991 }
992
993 err = dpio_open(dflt_mc_io,
994 MC_CMD_NO_FLAGS,
995 dflt_dpio->dpio_id,
996 &dflt_dpio->dpio_handle);
997 if (err) {
998 printf("dpio_open() failed\n");
999 goto err_open;
1000 }
1001
1730a17d 1002 memset(&attr, 0, sizeof(struct dpio_attr));
87457d11 1003 err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1730a17d
PK
1004 dflt_dpio->dpio_handle, &attr);
1005 if (err < 0) {
1006 printf("dpio_get_attributes() failed: %d\n", err);
a2a55e51
PK
1007 goto err_get_attr;
1008 }
1009
2557c5a9
YG
1010 if (dflt_dpio->dpio_id != attr.id) {
1011 printf("dnpi object id and attribute id are not same\n");
1012 goto err_attr_not_same;
9a696f56
PK
1013 }
1014
1730a17d
PK
1015#ifdef DEBUG
1016 printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
1017#endif
1730a17d
PK
1018 err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
1019 if (err < 0) {
a2a55e51
PK
1020 printf("dpio_enable() failed %d\n", err);
1021 goto err_get_enable;
1022 }
1f1c25c7
PK
1023 debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
1024 attr.qbman_portal_ce_offset,
1025 attr.qbman_portal_ci_offset,
a2a55e51
PK
1026 attr.qbman_portal_id,
1027 attr.num_priorities);
1028
1f1c25c7
PK
1029 p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
1030 + attr.qbman_portal_ce_offset);
1031 p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
1032 + attr.qbman_portal_ci_offset);
a2a55e51
PK
1033
1034 dflt_dpio->sw_portal = qbman_swp_init(&p_des);
1035 if (dflt_dpio->sw_portal == NULL) {
1036 printf("qbman_swp_init() failed\n");
1037 goto err_get_swp_init;
1038 }
1039 return 0;
1040
1041err_get_swp_init:
1730a17d 1042 dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
a2a55e51 1043err_get_enable:
1730a17d 1044err_get_attr:
2557c5a9 1045err_attr_not_same:
1730a17d 1046 dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
2557c5a9
YG
1047err_open:
1048err_get_api_ver:
1049 dpio_destroy(dflt_mc_io,
1050 dflt_dprc_handle,
1051 MC_CMD_NO_FLAGS,
1052 dflt_dpio->dpio_id);
1730a17d 1053err_create:
cd7b3fbc 1054 free(dflt_dpio);
a572fb6b 1055err_calloc:
1730a17d
PK
1056 return err;
1057}
1058
1059static int dpio_exit(void)
1060{
1061 int err;
1062
1063 err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
1064 if (err < 0) {
1065 printf("dpio_disable() failed: %d\n", err);
1066 goto err;
1067 }
1068
2557c5a9
YG
1069 dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
1070 if (err < 0) {
1071 printf("dpio_close() failed: %d\n", err);
1072 goto err;
1073 }
1074
1075 err = dpio_destroy(dflt_mc_io,
1076 dflt_dprc_handle,
1077 MC_CMD_NO_FLAGS,
1078 dflt_dpio->dpio_id);
1730a17d
PK
1079 if (err < 0) {
1080 printf("dpio_destroy() failed: %d\n", err);
1081 goto err;
1082 }
1083
1084#ifdef DEBUG
1085 printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
1086#endif
1087
1088 if (dflt_dpio)
1089 free(dflt_dpio);
1090
1091 return 0;
1092err:
1093 return err;
1094}
1095
1096static int dprc_init(void)
1097{
1098 int err, child_portal_id, container_id;
1099 struct dprc_cfg cfg;
1100 uint64_t mc_portal_offset;
1101
1102 /* Open root container */
1103 err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
1104 if (err < 0) {
1105 printf("dprc_get_container_id(): Root failed: %d\n", err);
1106 goto err_root_container_id;
1107 }
1108
1109#ifdef DEBUG
1110 printf("Root container id = %d\n", container_id);
1111#endif
1112 err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
1113 &root_dprc_handle);
1114 if (err < 0) {
1115 printf("dprc_open(): Root Container failed: %d\n", err);
1116 goto err_root_open;
1117 }
1118
1119 if (!root_dprc_handle) {
1120 printf("dprc_open(): Root Container Handle is not valid\n");
1121 goto err_root_open;
1122 }
1123
9a696f56
PK
1124 err = dprc_version_check(root_mc_io, root_dprc_handle);
1125 if (err < 0) {
1126 printf("dprc_version_check() failed: %d\n", err);
1127 goto err_root_open;
1128 }
1129
5373b204 1130 memset(&cfg, 0, sizeof(struct dprc_cfg));
1730a17d
PK
1131 cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
1132 DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
1133 DPRC_CFG_OPT_ALLOC_ALLOWED;
1134 cfg.icid = DPRC_GET_ICID_FROM_POOL;
335b1936 1135 cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
1730a17d
PK
1136 err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
1137 root_dprc_handle,
1138 &cfg,
1139 &child_dprc_id,
1140 &mc_portal_offset);
1141 if (err < 0) {
1142 printf("dprc_create_container() failed: %d\n", err);
1143 goto err_create;
1144 }
1145
a572fb6b 1146 dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
1730a17d
PK
1147 if (!dflt_mc_io) {
1148 err = -ENOMEM;
a572fb6b
PK
1149 printf(" No memory: calloc() failed\n");
1150 goto err_calloc;
1730a17d
PK
1151 }
1152
1153 child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
1154 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
2557c5a9 1155
1730a17d
PK
1156#ifdef DEBUG
1157 printf("MC portal of child DPRC container: %d, physical addr %p)\n",
1158 child_dprc_id, dflt_mc_io->mmio_regs);
1159#endif
1160
1161 err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
1162 &dflt_dprc_handle);
1163 if (err < 0) {
1164 printf("dprc_open(): Child container failed: %d\n", err);
1165 goto err_child_open;
1166 }
1167
1168 if (!dflt_dprc_handle) {
1169 printf("dprc_open(): Child container Handle is not valid\n");
1170 goto err_child_open;
1171 }
1172
1173 return 0;
1174err_child_open:
1175 free(dflt_mc_io);
a572fb6b 1176err_calloc:
1730a17d
PK
1177 dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
1178 root_dprc_handle, child_dprc_id);
1179err_create:
1180 dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
1181err_root_open:
1182err_root_container_id:
1183 return err;
1184}
1185
1186static int dprc_exit(void)
1187{
1188 int err;
1189
1190 err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
1191 if (err < 0) {
1192 printf("dprc_close(): Child failed: %d\n", err);
1193 goto err;
1194 }
1195
1196 err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
1197 root_dprc_handle, child_dprc_id);
1198 if (err < 0) {
1199 printf("dprc_destroy_container() failed: %d\n", err);
1200 goto err;
1201 }
1202
1203 err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
1204 if (err < 0) {
1205 printf("dprc_close(): Root failed: %d\n", err);
1206 goto err;
1207 }
1208
1209 if (dflt_mc_io)
1210 free(dflt_mc_io);
1211
1212 if (root_mc_io)
1213 free(root_mc_io);
1214
1215 return 0;
1216
1217err:
a2a55e51
PK
1218 return err;
1219}
1220
1730a17d 1221static int dpbp_init(void)
a2a55e51 1222{
1730a17d
PK
1223 int err;
1224 struct dpbp_attr dpbp_attr;
1225 struct dpbp_cfg dpbp_cfg;
2557c5a9 1226 uint16_t major_ver, minor_ver;
1730a17d 1227
a572fb6b
PK
1228 dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
1229 sizeof(struct fsl_dpbp_obj), 1);
a2a55e51 1230 if (!dflt_dpbp) {
a572fb6b 1231 printf("No memory: calloc() failed\n");
1730a17d 1232 err = -ENOMEM;
a572fb6b 1233 goto err_calloc;
1730a17d
PK
1234 }
1235
1236 dpbp_cfg.options = 512;
1237
2557c5a9
YG
1238 err = dpbp_create(dflt_mc_io,
1239 dflt_dprc_handle,
1240 MC_CMD_NO_FLAGS,
1241 &dpbp_cfg,
1242 &dflt_dpbp->dpbp_id);
1730a17d
PK
1243
1244 if (err < 0) {
1245 err = -ENODEV;
1246 printf("dpbp_create() failed: %d\n", err);
1247 goto err_create;
1248 }
1249
2557c5a9
YG
1250 err = dpbp_get_api_version(dflt_mc_io, 0,
1251 &major_ver,
1252 &minor_ver);
1253 if (err < 0) {
1254 printf("dpbp_get_api_version() failed: %d\n", err);
1255 goto err_get_api_ver;
1256 }
1257
1258 if (major_ver < DPBP_VER_MAJOR || (major_ver == DPBP_VER_MAJOR &&
1259 minor_ver < DPBP_VER_MINOR)) {
1260 printf("DPBP version mismatch found %u.%u,",
1261 major_ver, minor_ver);
1262 printf("supported version is %u.%u\n",
1263 DPBP_VER_MAJOR, DPBP_VER_MINOR);
1264 }
1265
1266 err = dpbp_open(dflt_mc_io,
1267 MC_CMD_NO_FLAGS,
1268 dflt_dpbp->dpbp_id,
1269 &dflt_dpbp->dpbp_handle);
1270 if (err) {
1271 printf("dpbp_open() failed\n");
1272 goto err_open;
1273 }
1274
1730a17d
PK
1275 memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
1276 err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1277 dflt_dpbp->dpbp_handle,
1278 &dpbp_attr);
1279 if (err < 0) {
1280 printf("dpbp_get_attributes() failed: %d\n", err);
1281 goto err_get_attr;
1282 }
1283
2557c5a9
YG
1284 if (dflt_dpbp->dpbp_id != dpbp_attr.id) {
1285 printf("dpbp object id and attribute id are not same\n");
1286 goto err_attr_not_same;
9a696f56
PK
1287 }
1288
1730a17d 1289#ifdef DEBUG
2557c5a9 1290 printf("Init: DPBP id=0x%x\n", dflt_dpbp->dpbp_attr.id);
1730a17d
PK
1291#endif
1292
1293 err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
1294 if (err < 0) {
1295 printf("dpbp_close() failed: %d\n", err);
1296 goto err_close;
a2a55e51 1297 }
a2a55e51
PK
1298
1299 return 0;
1730a17d 1300
1730a17d 1301err_get_attr:
2557c5a9 1302err_attr_not_same:
1730a17d 1303 dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
2557c5a9
YG
1304 dpbp_destroy(dflt_mc_io,
1305 dflt_dprc_handle,
1306 MC_CMD_NO_FLAGS,
1307 dflt_dpbp->dpbp_id);
1308err_get_api_ver:
1309err_close:
1310err_open:
1730a17d 1311err_create:
2557c5a9 1312 free(dflt_dpbp);
a572fb6b 1313err_calloc:
1730a17d 1314 return err;
a2a55e51
PK
1315}
1316
1730a17d
PK
1317static int dpbp_exit(void)
1318{
1319 int err;
1320
2557c5a9
YG
1321 err = dpbp_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
1322 dflt_dpbp->dpbp_id);
1730a17d
PK
1323 if (err < 0) {
1324 printf("dpbp_destroy() failed: %d\n", err);
1325 goto err;
1326 }
1327
1328#ifdef DEBUG
1329 printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
1330#endif
1331
1332 if (dflt_dpbp)
1333 free(dflt_dpbp);
1334 return 0;
1335
1336err:
1337 return err;
1338}
1339
1340static int dpni_init(void)
1341{
1342 int err;
2557c5a9 1343 uint8_t cfg_buf[256] = {0};
1730a17d 1344 struct dpni_cfg dpni_cfg;
2557c5a9 1345 uint16_t major_ver, minor_ver;
1730a17d 1346
a572fb6b
PK
1347 dflt_dpni = (struct fsl_dpni_obj *)calloc(
1348 sizeof(struct fsl_dpni_obj), 1);
1730a17d 1349 if (!dflt_dpni) {
a572fb6b 1350 printf("No memory: calloc() failed\n");
1730a17d 1351 err = -ENOMEM;
a572fb6b 1352 goto err_calloc;
1730a17d
PK
1353 }
1354
2557c5a9
YG
1355 memset(&dpni_cfg, 0, sizeof(dpni_cfg));
1356 err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]);
879a59ac
PK
1357 if (err < 0) {
1358 err = -ENODEV;
2557c5a9
YG
1359 printf("dpni_prepare_cfg() failed: %d\n", err);
1360 goto err_prepare_cfg;
879a59ac
PK
1361 }
1362
2557c5a9
YG
1363 err = dpni_create(dflt_mc_io,
1364 dflt_dprc_handle,
1365 MC_CMD_NO_FLAGS,
1366 &dpni_cfg,
1367 &dflt_dpni->dpni_id);
1730a17d
PK
1368 if (err < 0) {
1369 err = -ENODEV;
2557c5a9 1370 printf("dpni create() failed: %d\n", err);
1730a17d
PK
1371 goto err_create;
1372 }
1373
2557c5a9
YG
1374 err = dpni_get_api_version(dflt_mc_io, 0,
1375 &major_ver,
1376 &minor_ver);
1730a17d 1377 if (err < 0) {
2557c5a9
YG
1378 printf("dpni_get_api_version() failed: %d\n", err);
1379 goto err_get_version;
1730a17d
PK
1380 }
1381
2557c5a9
YG
1382 if (major_ver < DPNI_VER_MAJOR || (major_ver == DPNI_VER_MAJOR &&
1383 minor_ver < DPNI_VER_MINOR)) {
9a696f56 1384 printf("DPNI version mismatch found %u.%u,",
2557c5a9 1385 major_ver, minor_ver);
9a696f56
PK
1386 printf("supported version is %u.%u\n",
1387 DPNI_VER_MAJOR, DPNI_VER_MINOR);
1388 }
1389
2557c5a9
YG
1390 err = dpni_open(dflt_mc_io,
1391 MC_CMD_NO_FLAGS,
1392 dflt_dpni->dpni_id,
1393 &dflt_dpni->dpni_handle);
1394 if (err) {
1395 printf("dpni_open() failed\n");
1396 goto err_open;
1397 }
1398
1730a17d
PK
1399#ifdef DEBUG
1400 printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
1401#endif
1730a17d
PK
1402 err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
1403 if (err < 0) {
1404 printf("dpni_close() failed: %d\n", err);
1405 goto err_close;
1406 }
1407
1408 return 0;
1409
1410err_close:
1730a17d 1411 dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
2557c5a9
YG
1412err_open:
1413err_get_version:
1414 dpni_destroy(dflt_mc_io,
1415 dflt_dprc_handle,
1416 MC_CMD_NO_FLAGS,
1417 dflt_dpni->dpni_id);
1730a17d 1418err_create:
2557c5a9 1419err_prepare_cfg:
879a59ac 1420 free(dflt_dpni);
a572fb6b 1421err_calloc:
1730a17d
PK
1422 return err;
1423}
1424
1425static int dpni_exit(void)
1426{
1427 int err;
1428
2557c5a9
YG
1429 err = dpni_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
1430 dflt_dpni->dpni_id);
1730a17d
PK
1431 if (err < 0) {
1432 printf("dpni_destroy() failed: %d\n", err);
1433 goto err;
1434 }
1435
1436#ifdef DEBUG
1437 printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
1438#endif
1439
1440 if (dflt_dpni)
1441 free(dflt_dpni);
1442 return 0;
1443
1444err:
1445 return err;
1446}
1447
1448static int mc_init_object(void)
a2a55e51 1449{
1730a17d
PK
1450 int err = 0;
1451
1452 err = dprc_init();
1453 if (err < 0) {
1454 printf("dprc_init() failed: %d\n", err);
1455 goto err;
1456 }
1457
1458 err = dpbp_init();
1459 if (err < 0) {
1460 printf("dpbp_init() failed: %d\n", err);
1461 goto err;
1462 }
1463
1464 err = dpio_init();
1465 if (err < 0) {
1466 printf("dpio_init() failed: %d\n", err);
1467 goto err;
1468 }
1469
1470 err = dpni_init();
1471 if (err < 0) {
1472 printf("dpni_init() failed: %d\n", err);
1473 goto err;
1474 }
a2a55e51 1475
fb4a87a7 1476 return 0;
1730a17d
PK
1477err:
1478 return err;
a2a55e51
PK
1479}
1480
1730a17d 1481int fsl_mc_ldpaa_exit(bd_t *bd)
a2a55e51 1482{
1730a17d 1483 int err = 0;
42e81790 1484 bool is_dpl_apply_status = false;
06651b94 1485 bool mc_boot_status = false;
1730a17d 1486
b7b8410a 1487 if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
f9747a5a
YG
1488 err = mc_apply_dpl(mc_lazy_dpl_addr);
1489 if (!err)
1490 fdt_fixup_board_enet(working_fdt);
b7b8410a
AG
1491 mc_lazy_dpl_addr = 0;
1492 }
1493
06651b94
SK
1494 if (!get_mc_boot_status())
1495 mc_boot_status = true;
1496
6dedcedd 1497 /* MC is not loaded intentionally, So return success. */
06651b94 1498 if (bd && !mc_boot_status)
1730a17d
PK
1499 return 0;
1500
42e81790
YG
1501 /* If DPL is deployed, set is_dpl_apply_status as TRUE. */
1502 if (!get_dpl_apply_status())
1503 is_dpl_apply_status = true;
1730a17d 1504
42e81790
YG
1505 /*
1506 * For case MC is loaded but DPL is not deployed, return success and
1507 * print message on console. Else FDT fix-up code execution hanged.
1508 */
06651b94 1509 if (bd && mc_boot_status && !is_dpl_apply_status) {
42e81790 1510 printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
73fa206a 1511 goto mc_obj_cleanup;
42e81790 1512 }
1730a17d 1513
06651b94
SK
1514 if (bd && mc_boot_status && is_dpl_apply_status)
1515 return 0;
1516
73fa206a 1517mc_obj_cleanup:
1730a17d
PK
1518 err = dpbp_exit();
1519 if (err < 0) {
a2a4dc56 1520 printf("dpbp_exit() failed: %d\n", err);
1730a17d
PK
1521 goto err;
1522 }
1523
1524 err = dpio_exit();
1525 if (err < 0) {
1526 printf("dpio_exit() failed: %d\n", err);
1527 goto err;
1528 }
1529
1530 err = dpni_exit();
1531 if (err < 0) {
1532 printf("dpni_exit() failed: %d\n", err);
1533 goto err;
1534 }
1535
1536 err = dprc_exit();
1537 if (err < 0) {
1538 printf("dprc_exit() failed: %d\n", err);
1539 goto err;
1540 }
1541
1542 return 0;
1543err:
1544 return err;
a2a55e51
PK
1545}
1546
fb4a87a7 1547static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a2a55e51 1548{
fb4a87a7
PK
1549 int err = 0;
1550 if (argc < 3)
1551 goto usage;
1552
1553 switch (argv[1][0]) {
1554 case 's': {
1555 char sub_cmd;
44937214
PK
1556 u64 mc_fw_addr, mc_dpc_addr;
1557#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1558 u64 aiop_fw_addr;
1559#endif
fb4a87a7
PK
1560
1561 sub_cmd = argv[2][0];
2557c5a9 1562
fb4a87a7
PK
1563 switch (sub_cmd) {
1564 case 'm':
1565 if (argc < 5)
1566 goto usage;
1567
1568 if (get_mc_boot_status() == 0) {
1569 printf("fsl-mc: MC is already booted");
1570 printf("\n");
1571 return err;
1572 }
1573 mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
1574 mc_dpc_addr = simple_strtoull(argv[4], NULL,
1575 16);
1730a17d
PK
1576
1577 if (!mc_init(mc_fw_addr, mc_dpc_addr))
1578 err = mc_init_object();
fb4a87a7
PK
1579 break;
1580
1581#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
1582 case 'a':
1583 if (argc < 4)
1584 goto usage;
1585 if (get_aiop_apply_status() == 0) {
1586 printf("fsl-mc: AIOP FW is already");
1587 printf(" applied\n");
1588 return err;
1589 }
1590
1591 aiop_fw_addr = simple_strtoull(argv[3], NULL,
1592 16);
1593
3c1d218a 1594 /* if SoC doesn't have AIOP, err = -ENODEV */
fb4a87a7
PK
1595 err = load_mc_aiop_img(aiop_fw_addr);
1596 if (!err)
1597 printf("fsl-mc: AIOP FW applied\n");
1598 break;
1599#endif
1600 default:
1601 printf("Invalid option: %s\n", argv[2]);
1602 goto usage;
a2a55e51 1603
fb4a87a7
PK
1604 break;
1605 }
125e2bc1 1606 }
fb4a87a7
PK
1607 break;
1608
b7b8410a 1609 case 'l':
fb4a87a7
PK
1610 case 'a': {
1611 u64 mc_dpl_addr;
1612
1613 if (argc < 4)
1614 goto usage;
1615
1616 if (get_dpl_apply_status() == 0) {
1617 printf("fsl-mc: DPL already applied\n");
1618 return err;
1619 }
1620
1621 mc_dpl_addr = simple_strtoull(argv[3], NULL,
1622 16);
1730a17d 1623
fb4a87a7
PK
1624 if (get_mc_boot_status() != 0) {
1625 printf("fsl-mc: Deploying data path layout ..");
1626 printf("ERROR (MC is not booted)\n");
1627 return -ENODEV;
1628 }
1730a17d 1629
b7b8410a
AG
1630 if (argv[1][0] == 'l') {
1631 /*
1632 * We will do the actual dpaa exit and dpl apply
1633 * later from announce_and_cleanup().
1634 */
1635 mc_lazy_dpl_addr = mc_dpl_addr;
1636 } else {
1637 /* The user wants it applied now */
1638 if (!fsl_mc_ldpaa_exit(NULL))
1639 err = mc_apply_dpl(mc_dpl_addr);
1640 }
fb4a87a7 1641 break;
125e2bc1 1642 }
fb4a87a7
PK
1643 default:
1644 printf("Invalid option: %s\n", argv[1]);
1645 goto usage;
1646 break;
a2a55e51 1647 }
fb4a87a7
PK
1648 return err;
1649 usage:
1650 return CMD_RET_USAGE;
a2a55e51 1651}
fb4a87a7
PK
1652
1653U_BOOT_CMD(
1654 fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc,
1655 "DPAA2 command to manage Management Complex (MC)",
1656 "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
1657 "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
b7b8410a 1658 "fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
fb4a87a7
PK
1659 "fsl_mc start aiop [FW_addr] - Start AIOP\n"
1660);
33a8991a
BP
1661
1662void mc_env_boot(void)
1663{
1664#if defined(CONFIG_FSL_MC_ENET)
1665 char *mc_boot_env_var;
1666 /* The MC may only be initialized in the reset PHY function
1667 * because otherwise U-Boot has not yet set up all the MAC
1668 * address info properly. Without MAC addresses, the MC code
1669 * can not properly initialize the DPC.
1670 */
00caae6d 1671 mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
33a8991a
BP
1672 if (mc_boot_env_var)
1673 run_command_list(mc_boot_env_var, -1, 0);
1674#endif /* CONFIG_FSL_MC_ENET */
1675}