sys-utils/lscpu-arm.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0-or-later
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Copyright (C) 2018 Riku Voipio <riku.voipio@iki.fi>
  10  *
  11  * The information here is gathered from
  12  *  - ARM manuals
  13  *  - Linux kernel: arch/armX/include/asm/cputype.h
  14  *  - GCC sources: config/arch/arch-cores.def
  15  *  - Ancient wisdom
  16  *  - SMBIOS tables (if applicable)
  17  */
  18 #include "lscpu.h"
  19
  20 struct id_part {
  21     const int id;
  22     const char* name;
  23 };
  24
  25 static const struct id_part arm_part[] = {
  26     { 0x810, "ARM810" },
  27     { 0x920, "ARM920" },
  28     { 0x922, "ARM922" },
  29     { 0x926, "ARM926" },
  30     { 0x940, "ARM940" },
  31     { 0x946, "ARM946" },
  32     { 0x966, "ARM966" },
  33     { 0xa20, "ARM1020" },
  34     { 0xa22, "ARM1022" },
  35     { 0xa26, "ARM1026" },
  36     { 0xb02, "ARM11 MPCore" },
  37     { 0xb36, "ARM1136" },
  38     { 0xb56, "ARM1156" },
  39     { 0xb76, "ARM1176" },
  40     { 0xc05, "Cortex-A5" },
  41     { 0xc07, "Cortex-A7" },
  42     { 0xc08, "Cortex-A8" },
  43     { 0xc09, "Cortex-A9" },
  44     { 0xc0d, "Cortex-A17" },    /* Originally A12 */
  45     { 0xc0f, "Cortex-A15" },
  46     { 0xc0e, "Cortex-A17" },
  47     { 0xc14, "Cortex-R4" },
  48     { 0xc15, "Cortex-R5" },
  49     { 0xc17, "Cortex-R7" },
  50     { 0xc18, "Cortex-R8" },
  51     { 0xc20, "Cortex-M0" },
  52     { 0xc21, "Cortex-M1" },
  53     { 0xc23, "Cortex-M3" },
  54     { 0xc24, "Cortex-M4" },
  55     { 0xc27, "Cortex-M7" },
  56     { 0xc60, "Cortex-M0+" },
  57     { 0xd01, "Cortex-A32" },
  58     { 0xd02, "Cortex-A34" },
  59     { 0xd03, "Cortex-A53" },
  60     { 0xd04, "Cortex-A35" },
  61     { 0xd05, "Cortex-A55" },
  62     { 0xd06, "Cortex-A65" },
  63     { 0xd07, "Cortex-A57" },
  64     { 0xd08, "Cortex-A72" },
  65     { 0xd09, "Cortex-A73" },
  66     { 0xd0a, "Cortex-A75" },
  67     { 0xd0b, "Cortex-A76" },
  68     { 0xd0c, "Neoverse-N1" },
  69     { 0xd0d, "Cortex-A77" },
  70     { 0xd0e, "Cortex-A76AE" },
  71     { 0xd13, "Cortex-R52" },
  72     { 0xd15, "Cortex-R82" },
  73     { 0xd16, "Cortex-R52+" },
  74     { 0xd20, "Cortex-M23" },
  75     { 0xd21, "Cortex-M33" },
  76     { 0xd22, "Cortex-M55" },
  77     { 0xd23, "Cortex-M85" },
  78     { 0xd40, "Neoverse-V1" },
  79     { 0xd41, "Cortex-A78" },
  80     { 0xd42, "Cortex-A78AE" },
  81     { 0xd43, "Cortex-A65AE" },
  82     { 0xd44, "Cortex-X1" },
  83     { 0xd46, "Cortex-A510" },
  84     { 0xd47, "Cortex-A710" },
  85     { 0xd48, "Cortex-X2" },
  86     { 0xd49, "Neoverse-N2" },
  87     { 0xd4a, "Neoverse-E1" },
  88     { 0xd4b, "Cortex-A78C" },
  89     { 0xd4c, "Cortex-X1C" },
  90     { 0xd4d, "Cortex-A715" },
  91     { 0xd4e, "Cortex-X3" },
  92     { 0xd4f, "Neoverse-V2" },
  93     { 0xd80, "Cortex-A520" },
  94     { 0xd81, "Cortex-A720" },
  95     { 0xd82, "Cortex-X4" },
  96     { -1, "unknown" },
  97 };
  98
  99 static const struct id_part brcm_part[] = {
 100     { 0x0f, "Brahma-B15" },
 101     { 0x100, "Brahma-B53" },
 102     { 0x516, "ThunderX2" },
 103     { -1, "unknown" },
 104 };
 105
 106 static const struct id_part dec_part[] = {
 107     { 0xa10, "SA110" },
 108     { 0xa11, "SA1100" },
 109     { -1, "unknown" },
 110 };
 111
 112 static const struct id_part cavium_part[] = {
 113     { 0x0a0, "ThunderX" },
 114     { 0x0a1, "ThunderX-88XX" },
 115     { 0x0a2, "ThunderX-81XX" },
 116     { 0x0a3, "ThunderX-83XX" },
 117     { 0x0af, "ThunderX2-99xx" },
 118     { 0x0b0, "OcteonTX2" },
 119     { 0x0b1, "OcteonTX2-98XX" },
 120     { 0x0b2, "OcteonTX2-96XX" },
 121     { 0x0b3, "OcteonTX2-95XX" },
 122     { 0x0b4, "OcteonTX2-95XXN" },
 123     { 0x0b5, "OcteonTX2-95XXMM" },
 124     { 0x0b6, "OcteonTX2-95XXO" },
 125     { 0x0b8, "ThunderX3-T110" },
 126     { -1, "unknown" },
 127 };
 128
 129 static const struct id_part apm_part[] = {
 130     { 0x000, "X-Gene" },
 131     { -1, "unknown" },
 132 };
 133
 134 static const struct id_part qcom_part[] = {
 135     { 0x00f, "Scorpion" },
 136     { 0x02d, "Scorpion" },
 137     { 0x04d, "Krait" },
 138     { 0x06f, "Krait" },
 139     { 0x201, "Kryo" },
 140     { 0x205, "Kryo" },
 141     { 0x211, "Kryo" },
 142     { 0x800, "Falkor-V1/Kryo" },
 143     { 0x801, "Kryo-V2" },
 144     { 0x802, "Kryo-3XX-Gold" },
 145     { 0x803, "Kryo-3XX-Silver" },
 146     { 0x804, "Kryo-4XX-Gold" },
 147     { 0x805, "Kryo-4XX-Silver" },
 148     { 0xc00, "Falkor" },
 149     { 0xc01, "Saphira" },
 150     { -1, "unknown" },
 151 };
 152
 153 static const struct id_part samsung_part[] = {
 154     { 0x001, "exynos-m1" },
 155     { 0x002, "exynos-m3" },
 156     { 0x003, "exynos-m4" },
 157     { 0x004, "exynos-m5" },
 158     { -1, "unknown" },
 159 };
 160
 161 static const struct id_part nvidia_part[] = {
 162     { 0x000, "Denver" },
 163     { 0x003, "Denver 2" },
 164     { 0x004, "Carmel" },
 165     { -1, "unknown" },
 166 };
 167
 168 static const struct id_part marvell_part[] = {
 169     { 0x131, "Feroceon-88FR131" },
 170     { 0x581, "PJ4/PJ4b" },
 171     { 0x584, "PJ4B-MP" },
 172     { -1, "unknown" },
 173 };
 174
 175 static const struct id_part apple_part[] = {
 176     { 0x000, "Swift" },
 177     { 0x001, "Cyclone" },
 178     { 0x002, "Typhoon" },
 179     { 0x003, "Typhoon/Capri" },
 180     { 0x004, "Twister" },
 181     { 0x005, "Twister/Elba/Malta" },
 182     { 0x006, "Hurricane" },
 183     { 0x007, "Hurricane/Myst" },
 184     { 0x008, "Monsoon" },
 185     { 0x009, "Mistral" },
 186     { 0x00b, "Vortex" },
 187     { 0x00c, "Tempest" },
 188     { 0x00f, "Tempest-M9" },
 189     { 0x010, "Vortex/Aruba" },
 190     { 0x011, "Tempest/Aruba" },
 191     { 0x012, "Lightning" },
 192     { 0x013, "Thunder" },
 193     { 0x020, "Icestorm-A14" },
 194     { 0x021, "Firestorm-A14" },
 195     { 0x022, "Icestorm-M1" },
 196     { 0x023, "Firestorm-M1" },
 197     { 0x024, "Icestorm-M1-Pro" },
 198     { 0x025, "Firestorm-M1-Pro" },
 199     { 0x026, "Thunder-M10" },
 200     { 0x028, "Icestorm-M1-Max" },
 201     { 0x029, "Firestorm-M1-Max" },
 202     { 0x030, "Blizzard-A15" },
 203     { 0x031, "Avalanche-A15" },
 204     { 0x032, "Blizzard-M2" },
 205     { 0x033, "Avalanche-M2" },
 206     { 0x034, "Blizzard-M2-Pro" },
 207     { 0x035, "Avalanche-M2-Pro" },
 208     { 0x036, "Sawtooth-A16" },
 209     { 0x037, "Everest-A16" },
 210     { 0x038, "Blizzard-M2-Max" },
 211     { 0x039, "Avalanche-M2-Max" },
 212     { -1, "unknown" },
 213 };
 214
 215 static const struct id_part faraday_part[] = {
 216     { 0x526, "FA526" },
 217     { 0x626, "FA626" },
 218     { -1, "unknown" },
 219 };
 220
 221 static const struct id_part intel_part[] = {
 222     { 0x200, "i80200" },
 223     { 0x210, "PXA250A" },
 224     { 0x212, "PXA210A" },
 225     { 0x242, "i80321-400" },
 226     { 0x243, "i80321-600" },
 227     { 0x290, "PXA250B/PXA26x" },
 228     { 0x292, "PXA210B" },
 229     { 0x2c2, "i80321-400-B0" },
 230     { 0x2c3, "i80321-600-B0" },
 231     { 0x2d0, "PXA250C/PXA255/PXA26x" },
 232     { 0x2d2, "PXA210C" },
 233     { 0x411, "PXA27x" },
 234     { 0x41c, "IPX425-533" },
 235     { 0x41d, "IPX425-400" },
 236     { 0x41f, "IPX425-266" },
 237     { 0x682, "PXA32x" },
 238     { 0x683, "PXA930/PXA935" },
 239     { 0x688, "PXA30x" },
 240     { 0x689, "PXA31x" },
 241     { 0xb11, "SA1110" },
 242     { 0xc12, "IPX1200" },
 243     { -1, "unknown" },
 244 };
 245
 246 static const struct id_part fujitsu_part[] = {
 247     { 0x001, "A64FX" },
 248     { -1, "unknown" },
 249 };
 250
 251 static const struct id_part hisi_part[] = {
 252     { 0xd01, "TaiShan-v110" },  /* used in Kunpeng-920 SoC */
 253     { 0xd02, "TaiShan-v120" },  /* used in Kirin 990A and 9000S SoCs */
 254     { 0xd40, "Cortex-A76" },    /* HiSilicon uses this ID though advertises A76 */
 255     { 0xd41, "Cortex-A77" },    /* HiSilicon uses this ID though advertises A77 */
 256     { -1, "unknown" },
 257 };
 258
 259 static const struct id_part ampere_part[] = {
 260     { 0xac3, "Ampere-1" },
 261     { 0xac4, "Ampere-1a" },
 262     { -1, "unknown" },
 263 };
 264
 265 static const struct id_part ft_part[] = {
 266     { 0x303, "FTC310" },
 267     { 0x660, "FTC660" },
 268     { 0x661, "FTC661" },
 269     { 0x662, "FTC662" },
 270     { 0x663, "FTC663" },
 271     { 0x664, "FTC664" },
 272     { 0x862, "FTC862" },
 273     { -1, "unknown" },
 274 };
 275
 276 static const struct id_part unknown_part[] = {
 277     { -1, "unknown" },
 278 };
 279
 280 struct hw_impl {
 281    const int    id;
 282    const struct id_part     *parts;
 283    const char   *name;
 284 };
 285
 286 static const struct hw_impl hw_implementer[] = {
 287     { 0x41, arm_part,     "ARM" },
 288     { 0x42, brcm_part,    "Broadcom" },
 289     { 0x43, cavium_part,  "Cavium" },
 290     { 0x44, dec_part,     "DEC" },
 291     { 0x46, fujitsu_part, "FUJITSU" },
 292     { 0x48, hisi_part,    "HiSilicon" },
 293     { 0x49, unknown_part, "Infineon" },
 294     { 0x4d, unknown_part, "Motorola/Freescale" },
 295     { 0x4e, nvidia_part,  "NVIDIA" },
 296     { 0x50, apm_part,     "APM" },
 297     { 0x51, qcom_part,    "Qualcomm" },
 298     { 0x53, samsung_part, "Samsung" },
 299     { 0x56, marvell_part, "Marvell" },
 300     { 0x61, apple_part,   "Apple" },
 301     { 0x66, faraday_part, "Faraday" },
 302     { 0x69, intel_part,   "Intel" },
 303     { 0x70, ft_part,      "Phytium" },
 304     { 0xc0, ampere_part,  "Ampere" },
 305     { -1,   unknown_part, "unknown" },
 306 };
 307
 308 static int parse_id(const char *str)
 309 {
 310         int id;
 311         char *end = NULL;
 312
 313         if (!str || strncmp(str, "0x",2) != 0)
 314                 return -EINVAL;
 315
 316         errno = 0;
 317         id = (int) strtol(str, &end, 0);
 318         if (errno || str == end)
 319                 return -EINVAL;
 320
 321         return id;
 322 }
 323
 324 #define parse_model_id(_cxt)            (parse_id((_cxt)->model))
 325
 326 static inline int parse_implementer_id(struct lscpu_cputype *ct)
 327 {
 328         if (ct->vendor_id)
 329                 return ct->vendor_id;
 330         ct->vendor_id = parse_id(ct->vendor);
 331         return ct->vendor_id;
 332 }
 333
 334 /*
 335  * Use model and vendor IDs to decode to human readable names.
 336  */
 337 static int arm_ids_decode(struct lscpu_cputype *ct)
 338 {
 339         int impl, part, j;
 340         const struct id_part *parts = NULL;
 341
 342         impl = parse_implementer_id(ct);
 343         if (impl <= 0)
 344                 return -EINVAL; /* no ARM or missing ID */
 345
 346         /* decode vendor */
 347         for (j = 0; hw_implementer[j].id != -1; j++) {
 348                 if (hw_implementer[j].id == impl) {
 349                         parts = hw_implementer[j].parts;
 350                         free(ct->vendor);
 351                         ct->vendor = xstrdup(hw_implementer[j].name);
 352                         break;
 353                 }
 354         }
 355
 356         /* decode model */
 357         if (!parts)
 358                 goto done;
 359
 360         part = parse_model_id(ct);
 361         if (part <= 0)
 362                 goto done;
 363
 364         for (j = 0; parts[j].id != -1; j++) {
 365                 if (parts[j].id == part) {
 366                         free(ct->modelname);
 367                         ct->modelname = xstrdup(parts[j].name);
 368                         break;
 369                 }
 370         }
 371 done:
 372         return 0;
 373 }
 374
 375 /* use "rXpY" string as stepping */
 376 static int arm_rXpY_decode(struct lscpu_cputype *ct)
 377 {
 378         int impl, revision, variant;
 379         char *end = NULL;
 380         char buf[8];
 381
 382         impl = parse_implementer_id(ct);
 383
 384         if (impl != 0x41 || !ct->revision || !ct->stepping)
 385                 return -EINVAL;
 386
 387         errno = 0;
 388         revision = (int) strtol(ct->revision, &end, 10);
 389         if (errno || ct->revision == end)
 390                 return -EINVAL;
 391
 392         errno = 0;
 393         variant = (int) strtol(ct->stepping, &end, 0);
 394         if (errno || ct->stepping == end)
 395                 return -EINVAL;
 396
 397         snprintf(buf, sizeof(buf), "r%dp%d", variant, revision);
 398         free(ct->stepping);
 399         ct->stepping = xstrdup(buf);
 400
 401         return 0;
 402 }
 403
 404 static void arm_decode(struct lscpu_cxt *cxt, struct lscpu_cputype *ct)
 405 {
 406         if (!cxt->noalive && access(_PATH_SYS_DMI, R_OK) == 0)
 407                 dmi_decode_cputype(ct);
 408
 409         arm_ids_decode(ct);
 410         arm_rXpY_decode(ct);
 411
 412         if (!cxt->noalive && cxt->is_cluster)
 413                 ct->nr_socket_on_cluster = get_number_of_physical_sockets_from_dmi();
 414 }
 415
 416 static int is_cluster_arm(struct lscpu_cxt *cxt)
 417 {
 418         struct stat st;
 419
 420         if (!cxt->noalive
 421             && strcmp(cxt->arch->name, "aarch64") == 0
 422             && stat(_PATH_ACPI_PPTT, &st) < 0 && cxt->ncputypes == 1)
 423                 return 1;
 424         else
 425                 return 0;
 426 }
 427
 428 void lscpu_decode_arm(struct lscpu_cxt *cxt)
 429 {
 430         size_t i;
 431
 432         cxt->is_cluster = is_cluster_arm(cxt);
 433
 434         for (i = 0; i < cxt->ncputypes; i++)
 435                 arm_decode(cxt, cxt->cputypes[i]);
 436 }