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[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
57fec1fe 26#include "tcg-op.h"
f08b6170 27#include "exec/cpu_ldst.h"
7a3f1944 28
2ef6175a 29#include "exec/helper-gen.h"
a7812ae4 30
a7e30d84
LV		 31#include "trace-tcg.h"
32
33
7a3f1944
FB		 34#define DEBUG_DISAS
35
72cbca10
FB		 36#define DYNAMIC_PC 1 /* dynamic pc value */
37#define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
39
1a2fb1c0 40/* global register indexes */
a7812ae4 41static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 42static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 44static TCGv_i32 cpu_psr;
45static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 46static TCGv cpu_y;
47#ifndef CONFIG_USER_ONLY
48static TCGv cpu_tbr;
49#endif
5793f2a4 50static TCGv cpu_cond;
dc99a3f2 51#ifdef TARGET_SPARC64
a7812ae4
PB		 52static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
53static TCGv cpu_gsr;
255e1fcb 54static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 55static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
56static TCGv_i32 cpu_softint;
255e1fcb
BS		 57#else
58static TCGv cpu_wim;
dc99a3f2 59#endif
714547bb 60/* Floating point registers */
30038fd8 61static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 62
022c62cb 63#include "exec/gen-icount.h"
2e70f6ef 64
7a3f1944 65typedef struct DisasContext {
0f8a249a
BS		 66 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
67 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 68 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 69 int is_br;
e8af50a3 70 int mem_idx;
a80dde08 71 int fpu_enabled;
2cade6a3 72 int address_mask_32bit;
060718c1 73 int singlestep;
8393617c 74 uint32_t cc_op; /* current CC operation */
cf495bcf 75 struct TranslationBlock *tb;
5578ceab 76 sparc_def_t *def;
30038fd8 77 TCGv_i32 t32[3];
88023616 78 TCGv ttl[5];
30038fd8 79 int n_t32;
88023616 80 int n_ttl;
7a3f1944
FB		 81} DisasContext;
82
416fcaea
RH		 83typedef struct {
84 TCGCond cond;
85 bool is_bool;
86 bool g1, g2;
87 TCGv c1, c2;
88} DisasCompare;
89
3475187d 90// This function uses non-native bit order
dc1a6971
BS		 91#define GET_FIELD(X, FROM, TO) \
92 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 93
3475187d 94// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 95#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 96 GET_FIELD(X, 31 - (TO), 31 - (FROM))
97
98#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 99#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 100
101#ifdef TARGET_SPARC64
0387d928 102#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 103#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 104#else
c185970a 105#define DFPREG(r) (r & 0x1e)
1f587329 106#define QFPREG(r) (r & 0x1c)
3475187d
FB		 107#endif
108
b158a785
BS		 109#define UA2005_HTRAP_MASK 0xff
110#define V8_TRAP_MASK 0x7f
111
3475187d
FB		 112static int sign_extend(int x, int len)
113{
114 len = 32 - len;
115 return (x << len) >> len;
116}
117
7a3f1944
FB		 118#define IS_IMM (insn & (1<<13))
119
2ae23e17
RH		 120static inline TCGv_i32 get_temp_i32(DisasContext *dc)
121{
122 TCGv_i32 t;
123 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
124 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
125 return t;
126}
127
128static inline TCGv get_temp_tl(DisasContext *dc)
129{
130 TCGv t;
131 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
132 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
133 return t;
134}
135
141ae5c1
RH		 136static inline void gen_update_fprs_dirty(int rd)
137{
138#if defined(TARGET_SPARC64)
139 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
140#endif
141}
142
ff07ec83 143/* floating point registers moves */
208ae657
RH		 144static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
145{
30038fd8
RH		 146#if TCG_TARGET_REG_BITS == 32
147 if (src & 1) {
148 return TCGV_LOW(cpu_fpr[src / 2]);
149 } else {
150 return TCGV_HIGH(cpu_fpr[src / 2]);
151 }
152#else
153 if (src & 1) {
154 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
155 } else {
2ae23e17 156 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 157 TCGv_i64 t = tcg_temp_new_i64();
158
159 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 160 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 161 tcg_temp_free_i64(t);
162
30038fd8
RH		 163 return ret;
164 }
165#endif
208ae657
RH		 166}
167
168static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
169{
30038fd8
RH		 170#if TCG_TARGET_REG_BITS == 32
171 if (dst & 1) {
172 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
173 } else {
174 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
175 }
176#else
177 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
178 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
179 (dst & 1 ? 0 : 32), 32);
180#endif
141ae5c1 181 gen_update_fprs_dirty(dst);
208ae657
RH		 182}
183
ba5f5179 184static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 185{
ba5f5179 186 return get_temp_i32(dc);
208ae657
RH		 187}
188
96eda024
RH		 189static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
190{
96eda024 191 src = DFPREG(src);
30038fd8 192 return cpu_fpr[src / 2];
96eda024
RH		 193}
194
195static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
196{
197 dst = DFPREG(dst);
30038fd8 198 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 199 gen_update_fprs_dirty(dst);
200}
201
3886b8a3 202static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 203{
3886b8a3 204 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 205}
206
ff07ec83
BS		 207static void gen_op_load_fpr_QT0(unsigned int src)
208{
30038fd8
RH		 209 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
210 offsetof(CPU_QuadU, ll.upper));
211 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
212 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 213}
214
215static void gen_op_load_fpr_QT1(unsigned int src)
216{
30038fd8
RH		 217 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
218 offsetof(CPU_QuadU, ll.upper));
219 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
220 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 221}
222
223static void gen_op_store_QT0_fpr(unsigned int dst)
224{
30038fd8
RH		 225 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
226 offsetof(CPU_QuadU, ll.upper));
227 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
228 offsetof(CPU_QuadU, ll.lower));
ff07ec83 229}
1f587329 230
ac11f776 231#ifdef TARGET_SPARC64
30038fd8 232static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 233{
234 rd = QFPREG(rd);
235 rs = QFPREG(rs);
236
30038fd8
RH		 237 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
238 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 239 gen_update_fprs_dirty(rd);
240}
241#endif
242
81ad8ba2
BS		 243/* moves */
244#ifdef CONFIG_USER_ONLY
3475187d 245#define supervisor(dc) 0
81ad8ba2 246#ifdef TARGET_SPARC64
e9ebed4d 247#define hypervisor(dc) 0
81ad8ba2 248#endif
3475187d 249#else
2aae2b8e 250#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 251#ifdef TARGET_SPARC64
2aae2b8e 252#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 253#else
3475187d 254#endif
81ad8ba2
BS		 255#endif
256
2cade6a3
BS		 257#ifdef TARGET_SPARC64
258#ifndef TARGET_ABI32
259#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 260#else
2cade6a3
BS		 261#define AM_CHECK(dc) (1)
262#endif
1a2fb1c0 263#endif
3391c818 264
2cade6a3
BS		 265static inline void gen_address_mask(DisasContext *dc, TCGv addr)
266{
267#ifdef TARGET_SPARC64
268 if (AM_CHECK(dc))
269 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
270#endif
271}
272
88023616
RH		 273static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
274{
275 if (reg == 0 || reg >= 8) {
276 TCGv t = get_temp_tl(dc);
277 if (reg == 0) {
278 tcg_gen_movi_tl(t, 0);
279 } else {
280 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
281 }
282 return t;
283 } else {
284 return cpu_gregs[reg];
285 }
286}
287
288static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
289{
290 if (reg > 0) {
291 if (reg < 8) {
292 tcg_gen_mov_tl(cpu_gregs[reg], v);
293 } else {
294 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
295 }
296 }
297}
298
299static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
300{
301 if (reg == 0 || reg >= 8) {
302 return get_temp_tl(dc);
303 } else {
304 return cpu_gregs[reg];
305 }
306}
307
5fafdf24 308static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 309 target_ulong pc, target_ulong npc)
310{
311 TranslationBlock *tb;
312
313 tb = s->tb;
314 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 315 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
316 !s->singlestep) {
6e256c93 317 /* jump to same page: we can use a direct jump */
57fec1fe 318 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 319 tcg_gen_movi_tl(cpu_pc, pc);
320 tcg_gen_movi_tl(cpu_npc, npc);
8cfd0495 321 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
6e256c93
FB		 322 } else {
323 /* jump to another page: currently not optimized */
2f5680ee
BS		 324 tcg_gen_movi_tl(cpu_pc, pc);
325 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 326 tcg_gen_exit_tb(0);
6e256c93
FB		 327 }
328}
329
19f329ad 330// XXX suboptimal
a7812ae4 331static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 332{
8911f501 333 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 334 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 335 tcg_gen_andi_tl(reg, reg, 0x1);
336}
337
a7812ae4 338static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 339{
8911f501 340 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 341 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 342 tcg_gen_andi_tl(reg, reg, 0x1);
343}
344
a7812ae4 345static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 346{
8911f501 347 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 348 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 349 tcg_gen_andi_tl(reg, reg, 0x1);
350}
351
a7812ae4 352static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 353{
8911f501 354 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 355 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 356 tcg_gen_andi_tl(reg, reg, 0x1);
357}
358
4af984a7 359static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 360{
4af984a7 361 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 362 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 363 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 364 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 365}
366
70c48285 367static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 368{
70c48285
RH		 369 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
370
371 /* Carry is computed from a previous add: (dst < src) */
372#if TARGET_LONG_BITS == 64
373 cc_src1_32 = tcg_temp_new_i32();
374 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 375 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
376 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 377#else
378 cc_src1_32 = cpu_cc_dst;
379 cc_src2_32 = cpu_cc_src;
380#endif
381
382 carry_32 = tcg_temp_new_i32();
383 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
384
385#if TARGET_LONG_BITS == 64
386 tcg_temp_free_i32(cc_src1_32);
387 tcg_temp_free_i32(cc_src2_32);
388#endif
389
390 return carry_32;
41d72852
BS		 391}
392
70c48285 393static TCGv_i32 gen_sub32_carry32(void)
41d72852 394{
70c48285
RH		 395 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
396
397 /* Carry is computed from a previous borrow: (src1 < src2) */
398#if TARGET_LONG_BITS == 64
399 cc_src1_32 = tcg_temp_new_i32();
400 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 401 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
402 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 403#else
404 cc_src1_32 = cpu_cc_src;
405 cc_src2_32 = cpu_cc_src2;
406#endif
407
408 carry_32 = tcg_temp_new_i32();
409 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
410
411#if TARGET_LONG_BITS == 64
412 tcg_temp_free_i32(cc_src1_32);
413 tcg_temp_free_i32(cc_src2_32);
414#endif
415
416 return carry_32;
417}
418
419static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
420 TCGv src2, int update_cc)
421{
422 TCGv_i32 carry_32;
423 TCGv carry;
424
425 switch (dc->cc_op) {
426 case CC_OP_DIV:
427 case CC_OP_LOGIC:
428 /* Carry is known to be zero. Fall back to plain ADD. */
429 if (update_cc) {
430 gen_op_add_cc(dst, src1, src2);
431 } else {
432 tcg_gen_add_tl(dst, src1, src2);
433 }
434 return;
435
436 case CC_OP_ADD:
437 case CC_OP_TADD:
438 case CC_OP_TADDTV:
15fe216f
RH		 439 if (TARGET_LONG_BITS == 32) {
440 /* We can re-use the host's hardware carry generation by using
441 an ADD2 opcode. We discard the low part of the output.
442 Ideally we'd combine this operation with the add that
443 generated the carry in the first place. */
444 carry = tcg_temp_new();
445 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
446 tcg_temp_free(carry);
70c48285
RH		 447 goto add_done;
448 }
70c48285
RH		 449 carry_32 = gen_add32_carry32();
450 break;
451
452 case CC_OP_SUB:
453 case CC_OP_TSUB:
454 case CC_OP_TSUBTV:
455 carry_32 = gen_sub32_carry32();
456 break;
457
458 default:
459 /* We need external help to produce the carry. */
460 carry_32 = tcg_temp_new_i32();
2ffd9176 461 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 462 break;
463 }
464
465#if TARGET_LONG_BITS == 64
466 carry = tcg_temp_new();
467 tcg_gen_extu_i32_i64(carry, carry_32);
468#else
469 carry = carry_32;
470#endif
471
472 tcg_gen_add_tl(dst, src1, src2);
473 tcg_gen_add_tl(dst, dst, carry);
474
475 tcg_temp_free_i32(carry_32);
476#if TARGET_LONG_BITS == 64
477 tcg_temp_free(carry);
478#endif
479
70c48285 480 add_done:
70c48285
RH		 481 if (update_cc) {
482 tcg_gen_mov_tl(cpu_cc_src, src1);
483 tcg_gen_mov_tl(cpu_cc_src2, src2);
484 tcg_gen_mov_tl(cpu_cc_dst, dst);
485 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
486 dc->cc_op = CC_OP_ADDX;
487 }
dc99a3f2
BS		 488}
489
41d72852 490static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 491{
4af984a7 492 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 493 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 494 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 495 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 496}
497
70c48285
RH		 498static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
499 TCGv src2, int update_cc)
41d72852 500{
70c48285
RH		 501 TCGv_i32 carry_32;
502 TCGv carry;
41d72852 503
70c48285
RH		 504 switch (dc->cc_op) {
505 case CC_OP_DIV:
506 case CC_OP_LOGIC:
507 /* Carry is known to be zero. Fall back to plain SUB. */
508 if (update_cc) {
509 gen_op_sub_cc(dst, src1, src2);
510 } else {
511 tcg_gen_sub_tl(dst, src1, src2);
512 }
513 return;
514
515 case CC_OP_ADD:
516 case CC_OP_TADD:
517 case CC_OP_TADDTV:
518 carry_32 = gen_add32_carry32();
519 break;
520
521 case CC_OP_SUB:
522 case CC_OP_TSUB:
523 case CC_OP_TSUBTV:
15fe216f
RH		 524 if (TARGET_LONG_BITS == 32) {
525 /* We can re-use the host's hardware carry generation by using
526 a SUB2 opcode. We discard the low part of the output.
527 Ideally we'd combine this operation with the add that
528 generated the carry in the first place. */
529 carry = tcg_temp_new();
530 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
531 tcg_temp_free(carry);
70c48285
RH		 532 goto sub_done;
533 }
70c48285
RH		 534 carry_32 = gen_sub32_carry32();
535 break;
536
537 default:
538 /* We need external help to produce the carry. */
539 carry_32 = tcg_temp_new_i32();
2ffd9176 540 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 541 break;
542 }
543
544#if TARGET_LONG_BITS == 64
545 carry = tcg_temp_new();
546 tcg_gen_extu_i32_i64(carry, carry_32);
547#else
548 carry = carry_32;
549#endif
550
551 tcg_gen_sub_tl(dst, src1, src2);
552 tcg_gen_sub_tl(dst, dst, carry);
553
554 tcg_temp_free_i32(carry_32);
555#if TARGET_LONG_BITS == 64
556 tcg_temp_free(carry);
557#endif
558
70c48285 559 sub_done:
70c48285
RH		 560 if (update_cc) {
561 tcg_gen_mov_tl(cpu_cc_src, src1);
562 tcg_gen_mov_tl(cpu_cc_src2, src2);
563 tcg_gen_mov_tl(cpu_cc_dst, dst);
564 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
565 dc->cc_op = CC_OP_SUBX;
566 }
dc99a3f2
BS		 567}
568
4af984a7 569static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 570{
de9e9d9f 571 TCGv r_temp, zero, t0;
d9bdab86 572
a7812ae4 573 r_temp = tcg_temp_new();
de9e9d9f 574 t0 = tcg_temp_new();
d9bdab86
BS		 575
576 /* old op:
577 if (!(env->y & 1))
578 T1 = 0;
579 */
6cb675b0 580 zero = tcg_const_tl(0);
72ccba79 581 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 582 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 583 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 584 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
585 zero, cpu_cc_src2);
586 tcg_temp_free(zero);
d9bdab86
BS		 587
588 // b2 = T0 & 1;
589 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 590 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
591 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 592 tcg_gen_shri_tl(t0, cpu_y, 1);
593 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
594 tcg_gen_or_tl(t0, t0, r_temp);
595 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 596
597 // b1 = N ^ V;
de9e9d9f 598 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 599 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 600 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 601 tcg_temp_free(r_temp);
d9bdab86
BS		 602
603 // T0 = (b1 << 31) | (T0 >> 1);
604 // src1 = T0;
de9e9d9f 605 tcg_gen_shli_tl(t0, t0, 31);
6f551262 606 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 607 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
608 tcg_temp_free(t0);
d9bdab86 609
5c6a0628 610 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 611
5c6a0628 612 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 613}
614
fb170183 615static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 616{
528692a8 617#if TARGET_LONG_BITS == 32
fb170183 618 if (sign_ext) {
528692a8 619 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 620 } else {
528692a8 621 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 622 }
528692a8
RH		 623#else
624 TCGv t0 = tcg_temp_new_i64();
625 TCGv t1 = tcg_temp_new_i64();
fb170183 626
528692a8
RH		 627 if (sign_ext) {
628 tcg_gen_ext32s_i64(t0, src1);
629 tcg_gen_ext32s_i64(t1, src2);
630 } else {
631 tcg_gen_ext32u_i64(t0, src1);
632 tcg_gen_ext32u_i64(t1, src2);
633 }
fb170183 634
528692a8
RH		 635 tcg_gen_mul_i64(dst, t0, t1);
636 tcg_temp_free(t0);
637 tcg_temp_free(t1);
fb170183 638
528692a8
RH		 639 tcg_gen_shri_i64(cpu_y, dst, 32);
640#endif
8879d139
BS		 641}
642
fb170183 643static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 644{
fb170183
IK		 645 /* zero-extend truncated operands before multiplication */
646 gen_op_multiply(dst, src1, src2, 0);
647}
8879d139 648
fb170183
IK		 649static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
650{
651 /* sign-extend truncated operands before multiplication */
652 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 653}
654
19f329ad
BS		 655// 1
656static inline void gen_op_eval_ba(TCGv dst)
657{
658 tcg_gen_movi_tl(dst, 1);
659}
660
661// Z
a7812ae4 662static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 663{
664 gen_mov_reg_Z(dst, src);
665}
666
667// Z | (N ^ V)
a7812ae4 668static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 669{
de9e9d9f
RH		 670 TCGv t0 = tcg_temp_new();
671 gen_mov_reg_N(t0, src);
19f329ad 672 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 673 tcg_gen_xor_tl(dst, dst, t0);
674 gen_mov_reg_Z(t0, src);
675 tcg_gen_or_tl(dst, dst, t0);
676 tcg_temp_free(t0);
19f329ad
BS		 677}
678
679// N ^ V
a7812ae4 680static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 681{
de9e9d9f
RH		 682 TCGv t0 = tcg_temp_new();
683 gen_mov_reg_V(t0, src);
19f329ad 684 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 685 tcg_gen_xor_tl(dst, dst, t0);
686 tcg_temp_free(t0);
19f329ad
BS		 687}
688
689// C | Z
a7812ae4 690static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 691{
de9e9d9f
RH		 692 TCGv t0 = tcg_temp_new();
693 gen_mov_reg_Z(t0, src);
19f329ad 694 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 695 tcg_gen_or_tl(dst, dst, t0);
696 tcg_temp_free(t0);
19f329ad
BS		 697}
698
699// C
a7812ae4 700static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 701{
702 gen_mov_reg_C(dst, src);
703}
704
705// V
a7812ae4 706static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 707{
708 gen_mov_reg_V(dst, src);
709}
710
711// 0
712static inline void gen_op_eval_bn(TCGv dst)
713{
714 tcg_gen_movi_tl(dst, 0);
715}
716
717// N
a7812ae4 718static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 719{
720 gen_mov_reg_N(dst, src);
721}
722
723// !Z
a7812ae4 724static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 725{
726 gen_mov_reg_Z(dst, src);
727 tcg_gen_xori_tl(dst, dst, 0x1);
728}
729
730// !(Z | (N ^ V))
a7812ae4 731static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 732{
de9e9d9f 733 gen_op_eval_ble(dst, src);
19f329ad
BS		 734 tcg_gen_xori_tl(dst, dst, 0x1);
735}
736
737// !(N ^ V)
a7812ae4 738static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 739{
de9e9d9f 740 gen_op_eval_bl(dst, src);
19f329ad
BS		 741 tcg_gen_xori_tl(dst, dst, 0x1);
742}
743
744// !(C | Z)
a7812ae4 745static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 746{
de9e9d9f 747 gen_op_eval_bleu(dst, src);
19f329ad
BS		 748 tcg_gen_xori_tl(dst, dst, 0x1);
749}
750
751// !C
a7812ae4 752static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 753{
754 gen_mov_reg_C(dst, src);
755 tcg_gen_xori_tl(dst, dst, 0x1);
756}
757
758// !N
a7812ae4 759static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 760{
761 gen_mov_reg_N(dst, src);
762 tcg_gen_xori_tl(dst, dst, 0x1);
763}
764
765// !V
a7812ae4 766static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 767{
768 gen_mov_reg_V(dst, src);
769 tcg_gen_xori_tl(dst, dst, 0x1);
770}
771
772/*
773 FPSR bit field FCC1 | FCC0:
774 0 =
775 1 <
776 2 >
777 3 unordered
778*/
779static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
780 unsigned int fcc_offset)
781{
ba6a9d8c 782 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 783 tcg_gen_andi_tl(reg, reg, 0x1);
784}
785
786static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
787 unsigned int fcc_offset)
788{
ba6a9d8c 789 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 790 tcg_gen_andi_tl(reg, reg, 0x1);
791}
792
793// !0: FCC0 | FCC1
794static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
795 unsigned int fcc_offset)
796{
de9e9d9f 797 TCGv t0 = tcg_temp_new();
19f329ad 798 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 799 gen_mov_reg_FCC1(t0, src, fcc_offset);
800 tcg_gen_or_tl(dst, dst, t0);
801 tcg_temp_free(t0);
19f329ad
BS		 802}
803
804// 1 or 2: FCC0 ^ FCC1
805static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
806 unsigned int fcc_offset)
807{
de9e9d9f 808 TCGv t0 = tcg_temp_new();
19f329ad 809 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 810 gen_mov_reg_FCC1(t0, src, fcc_offset);
811 tcg_gen_xor_tl(dst, dst, t0);
812 tcg_temp_free(t0);
19f329ad
BS		 813}
814
815// 1 or 3: FCC0
816static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
817 unsigned int fcc_offset)
818{
819 gen_mov_reg_FCC0(dst, src, fcc_offset);
820}
821
822// 1: FCC0 & !FCC1
823static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
824 unsigned int fcc_offset)
825{
de9e9d9f 826 TCGv t0 = tcg_temp_new();
19f329ad 827 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 828 gen_mov_reg_FCC1(t0, src, fcc_offset);
829 tcg_gen_andc_tl(dst, dst, t0);
830 tcg_temp_free(t0);
19f329ad
BS		 831}
832
833// 2 or 3: FCC1
834static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
835 unsigned int fcc_offset)
836{
837 gen_mov_reg_FCC1(dst, src, fcc_offset);
838}
839
840// 2: !FCC0 & FCC1
841static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
842 unsigned int fcc_offset)
843{
de9e9d9f 844 TCGv t0 = tcg_temp_new();
19f329ad 845 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 846 gen_mov_reg_FCC1(t0, src, fcc_offset);
847 tcg_gen_andc_tl(dst, t0, dst);
848 tcg_temp_free(t0);
19f329ad
BS		 849}
850
851// 3: FCC0 & FCC1
852static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
853 unsigned int fcc_offset)
854{
de9e9d9f 855 TCGv t0 = tcg_temp_new();
19f329ad 856 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 857 gen_mov_reg_FCC1(t0, src, fcc_offset);
858 tcg_gen_and_tl(dst, dst, t0);
859 tcg_temp_free(t0);
19f329ad
BS		 860}
861
862// 0: !(FCC0 | FCC1)
863static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
864 unsigned int fcc_offset)
865{
de9e9d9f 866 TCGv t0 = tcg_temp_new();
19f329ad 867 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 868 gen_mov_reg_FCC1(t0, src, fcc_offset);
869 tcg_gen_or_tl(dst, dst, t0);
19f329ad 870 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 871 tcg_temp_free(t0);
19f329ad
BS		 872}
873
874// 0 or 3: !(FCC0 ^ FCC1)
875static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
876 unsigned int fcc_offset)
877{
de9e9d9f 878 TCGv t0 = tcg_temp_new();
19f329ad 879 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 880 gen_mov_reg_FCC1(t0, src, fcc_offset);
881 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 882 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 883 tcg_temp_free(t0);
19f329ad
BS		 884}
885
886// 0 or 2: !FCC0
887static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
888 unsigned int fcc_offset)
889{
890 gen_mov_reg_FCC0(dst, src, fcc_offset);
891 tcg_gen_xori_tl(dst, dst, 0x1);
892}
893
894// !1: !(FCC0 & !FCC1)
895static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
896 unsigned int fcc_offset)
897{
de9e9d9f 898 TCGv t0 = tcg_temp_new();
19f329ad 899 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 900 gen_mov_reg_FCC1(t0, src, fcc_offset);
901 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 902 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 903 tcg_temp_free(t0);
19f329ad
BS		 904}
905
906// 0 or 1: !FCC1
907static inline void gen_op_eval_fble(TCGv dst, TCGv src,
908 unsigned int fcc_offset)
909{
910 gen_mov_reg_FCC1(dst, src, fcc_offset);
911 tcg_gen_xori_tl(dst, dst, 0x1);
912}
913
914// !2: !(!FCC0 & FCC1)
915static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
916 unsigned int fcc_offset)
917{
de9e9d9f 918 TCGv t0 = tcg_temp_new();
19f329ad 919 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 920 gen_mov_reg_FCC1(t0, src, fcc_offset);
921 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 922 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 923 tcg_temp_free(t0);
19f329ad
BS		 924}
925
926// !3: !(FCC0 & FCC1)
927static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
928 unsigned int fcc_offset)
929{
de9e9d9f 930 TCGv t0 = tcg_temp_new();
19f329ad 931 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 932 gen_mov_reg_FCC1(t0, src, fcc_offset);
933 tcg_gen_and_tl(dst, dst, t0);
19f329ad 934 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 935 tcg_temp_free(t0);
19f329ad
BS		 936}
937
46525e1f 938static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 939 target_ulong pc2, TCGv r_cond)
83469015 940{
42a268c2 941 TCGLabel *l1 = gen_new_label();
83469015 942
cb63669a 943 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 944
6e256c93 945 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 946
947 gen_set_label(l1);
6e256c93 948 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 949}
950
bfa31b76 951static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 952{
42a268c2 953 TCGLabel *l1 = gen_new_label();
bfa31b76 954 target_ulong npc = dc->npc;
83469015 955
bfa31b76 956 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 957
bfa31b76 958 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 959
960 gen_set_label(l1);
bfa31b76
RH		 961 gen_goto_tb(dc, 1, npc + 4, npc + 8);
962
963 dc->is_br = 1;
83469015
FB		 964}
965
2bf2e019
RH		 966static void gen_branch_n(DisasContext *dc, target_ulong pc1)
967{
968 target_ulong npc = dc->npc;
969
970 if (likely(npc != DYNAMIC_PC)) {
971 dc->pc = npc;
972 dc->jump_pc[0] = pc1;
973 dc->jump_pc[1] = npc + 4;
974 dc->npc = JUMP_PC;
975 } else {
976 TCGv t, z;
977
978 tcg_gen_mov_tl(cpu_pc, cpu_npc);
979
980 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
981 t = tcg_const_tl(pc1);
982 z = tcg_const_tl(0);
983 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
984 tcg_temp_free(t);
985 tcg_temp_free(z);
986
987 dc->pc = DYNAMIC_PC;
988 }
989}
990
2e655fe7 991static inline void gen_generic_branch(DisasContext *dc)
83469015 992{
61316742
RH		 993 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
994 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
995 TCGv zero = tcg_const_tl(0);
19f329ad 996
61316742 997 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 998
61316742
RH		 999 tcg_temp_free(npc0);
1000 tcg_temp_free(npc1);
1001 tcg_temp_free(zero);
83469015
FB		 1002}
1003
4af984a7
BS		 1004/* call this function before using the condition register as it may
1005 have been set for a jump */
dee8913c 1006static inline void flush_cond(DisasContext *dc)
83469015
FB		 1007{
1008 if (dc->npc == JUMP_PC) {
2e655fe7 1009 gen_generic_branch(dc);
83469015
FB		 1010 dc->npc = DYNAMIC_PC;
1011 }
1012}
1013
934da7ee 1014static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1015{
1016 if (dc->npc == JUMP_PC) {
2e655fe7 1017 gen_generic_branch(dc);
72cbca10
FB		 1018 dc->npc = DYNAMIC_PC;
1019 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1020 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1021 }
1022}
1023
20132b96 1024static inline void update_psr(DisasContext *dc)
72cbca10 1025{
cfa90513
BS		 1026 if (dc->cc_op != CC_OP_FLAGS) {
1027 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1028 gen_helper_compute_psr(cpu_env);
cfa90513 1029 }
20132b96
RH		 1030}
1031
1032static inline void save_state(DisasContext *dc)
1033{
1034 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1035 save_npc(dc);
72cbca10
FB		 1036}
1037
13a6dd00 1038static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1039{
1040 if (dc->npc == JUMP_PC) {
2e655fe7 1041 gen_generic_branch(dc);
48d5c82b 1042 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1043 dc->pc = DYNAMIC_PC;
1044 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1045 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1046 dc->pc = DYNAMIC_PC;
1047 } else {
1048 dc->pc = dc->npc;
1049 }
1050}
1051
38bc628b
BS		 1052static inline void gen_op_next_insn(void)
1053{
48d5c82b
BS		 1054 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1055 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1056}
1057
416fcaea
RH		 1058static void free_compare(DisasCompare *cmp)
1059{
1060 if (!cmp->g1) {
1061 tcg_temp_free(cmp->c1);
1062 }
1063 if (!cmp->g2) {
1064 tcg_temp_free(cmp->c2);
1065 }
1066}
1067
2a484ecf 1068static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1069 DisasContext *dc)
19f329ad 1070{
2a484ecf 1071 static int subcc_cond[16] = {
96b5a3d3 1072 TCG_COND_NEVER,
2a484ecf
RH		 1073 TCG_COND_EQ,
1074 TCG_COND_LE,
1075 TCG_COND_LT,
1076 TCG_COND_LEU,
1077 TCG_COND_LTU,
1078 -1, /* neg */
1079 -1, /* overflow */
96b5a3d3 1080 TCG_COND_ALWAYS,
2a484ecf
RH		 1081 TCG_COND_NE,
1082 TCG_COND_GT,
1083 TCG_COND_GE,
1084 TCG_COND_GTU,
1085 TCG_COND_GEU,
1086 -1, /* pos */
1087 -1, /* no overflow */
1088 };
1089
96b5a3d3
RH		 1090 static int logic_cond[16] = {
1091 TCG_COND_NEVER,
1092 TCG_COND_EQ, /* eq: Z */
1093 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1094 TCG_COND_LT, /* lt: N ^ V -> N */
1095 TCG_COND_EQ, /* leu: C | Z -> Z */
1096 TCG_COND_NEVER, /* ltu: C -> 0 */
1097 TCG_COND_LT, /* neg: N */
1098 TCG_COND_NEVER, /* vs: V -> 0 */
1099 TCG_COND_ALWAYS,
1100 TCG_COND_NE, /* ne: !Z */
1101 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1102 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1103 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1104 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1105 TCG_COND_GE, /* pos: !N */
1106 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1107 };
1108
a7812ae4 1109 TCGv_i32 r_src;
416fcaea
RH		 1110 TCGv r_dst;
1111
3475187d 1112#ifdef TARGET_SPARC64
2a484ecf 1113 if (xcc) {
dc99a3f2 1114 r_src = cpu_xcc;
2a484ecf 1115 } else {
dc99a3f2 1116 r_src = cpu_psr;
2a484ecf 1117 }
3475187d 1118#else
dc99a3f2 1119 r_src = cpu_psr;
3475187d 1120#endif
2a484ecf 1121
8393617c 1122 switch (dc->cc_op) {
96b5a3d3
RH		 1123 case CC_OP_LOGIC:
1124 cmp->cond = logic_cond[cond];
1125 do_compare_dst_0:
1126 cmp->is_bool = false;
1127 cmp->g2 = false;
1128 cmp->c2 = tcg_const_tl(0);
1129#ifdef TARGET_SPARC64
1130 if (!xcc) {
1131 cmp->g1 = false;
1132 cmp->c1 = tcg_temp_new();
1133 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1134 break;
1135 }
1136#endif
1137 cmp->g1 = true;
1138 cmp->c1 = cpu_cc_dst;
1139 break;
1140
2a484ecf
RH		 1141 case CC_OP_SUB:
1142 switch (cond) {
1143 case 6: /* neg */
1144 case 14: /* pos */
1145 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1146 goto do_compare_dst_0;
2a484ecf 1147
2a484ecf
RH		 1148 case 7: /* overflow */
1149 case 15: /* !overflow */
1150 goto do_dynamic;
1151
1152 default:
1153 cmp->cond = subcc_cond[cond];
1154 cmp->is_bool = false;
1155#ifdef TARGET_SPARC64
1156 if (!xcc) {
1157 /* Note that sign-extension works for unsigned compares as
1158 long as both operands are sign-extended. */
1159 cmp->g1 = cmp->g2 = false;
1160 cmp->c1 = tcg_temp_new();
1161 cmp->c2 = tcg_temp_new();
1162 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1163 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1164 break;
2a484ecf
RH		 1165 }
1166#endif
1167 cmp->g1 = cmp->g2 = true;
1168 cmp->c1 = cpu_cc_src;
1169 cmp->c2 = cpu_cc_src2;
1170 break;
1171 }
8393617c 1172 break;
2a484ecf 1173
8393617c 1174 default:
2a484ecf 1175 do_dynamic:
2ffd9176 1176 gen_helper_compute_psr(cpu_env);
8393617c 1177 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1178 /* FALLTHRU */
1179
1180 case CC_OP_FLAGS:
1181 /* We're going to generate a boolean result. */
1182 cmp->cond = TCG_COND_NE;
1183 cmp->is_bool = true;
1184 cmp->g1 = cmp->g2 = false;
1185 cmp->c1 = r_dst = tcg_temp_new();
1186 cmp->c2 = tcg_const_tl(0);
1187
1188 switch (cond) {
1189 case 0x0:
1190 gen_op_eval_bn(r_dst);
1191 break;
1192 case 0x1:
1193 gen_op_eval_be(r_dst, r_src);
1194 break;
1195 case 0x2:
1196 gen_op_eval_ble(r_dst, r_src);
1197 break;
1198 case 0x3:
1199 gen_op_eval_bl(r_dst, r_src);
1200 break;
1201 case 0x4:
1202 gen_op_eval_bleu(r_dst, r_src);
1203 break;
1204 case 0x5:
1205 gen_op_eval_bcs(r_dst, r_src);
1206 break;
1207 case 0x6:
1208 gen_op_eval_bneg(r_dst, r_src);
1209 break;
1210 case 0x7:
1211 gen_op_eval_bvs(r_dst, r_src);
1212 break;
1213 case 0x8:
1214 gen_op_eval_ba(r_dst);
1215 break;
1216 case 0x9:
1217 gen_op_eval_bne(r_dst, r_src);
1218 break;
1219 case 0xa:
1220 gen_op_eval_bg(r_dst, r_src);
1221 break;
1222 case 0xb:
1223 gen_op_eval_bge(r_dst, r_src);
1224 break;
1225 case 0xc:
1226 gen_op_eval_bgu(r_dst, r_src);
1227 break;
1228 case 0xd:
1229 gen_op_eval_bcc(r_dst, r_src);
1230 break;
1231 case 0xe:
1232 gen_op_eval_bpos(r_dst, r_src);
1233 break;
1234 case 0xf:
1235 gen_op_eval_bvc(r_dst, r_src);
1236 break;
1237 }
19f329ad
BS		 1238 break;
1239 }
1240}
7a3f1944 1241
416fcaea 1242static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1243{
19f329ad 1244 unsigned int offset;
416fcaea
RH		 1245 TCGv r_dst;
1246
1247 /* For now we still generate a straight boolean result. */
1248 cmp->cond = TCG_COND_NE;
1249 cmp->is_bool = true;
1250 cmp->g1 = cmp->g2 = false;
1251 cmp->c1 = r_dst = tcg_temp_new();
1252 cmp->c2 = tcg_const_tl(0);
19f329ad 1253
19f329ad
BS		 1254 switch (cc) {
1255 default:
1256 case 0x0:
1257 offset = 0;
1258 break;
1259 case 0x1:
1260 offset = 32 - 10;
1261 break;
1262 case 0x2:
1263 offset = 34 - 10;
1264 break;
1265 case 0x3:
1266 offset = 36 - 10;
1267 break;
1268 }
1269
1270 switch (cond) {
1271 case 0x0:
1272 gen_op_eval_bn(r_dst);
1273 break;
1274 case 0x1:
87e92502 1275 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1276 break;
1277 case 0x2:
87e92502 1278 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1279 break;
1280 case 0x3:
87e92502 1281 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1282 break;
1283 case 0x4:
87e92502 1284 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1285 break;
1286 case 0x5:
87e92502 1287 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1288 break;
1289 case 0x6:
87e92502 1290 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1291 break;
1292 case 0x7:
87e92502 1293 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1294 break;
1295 case 0x8:
1296 gen_op_eval_ba(r_dst);
1297 break;
1298 case 0x9:
87e92502 1299 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1300 break;
1301 case 0xa:
87e92502 1302 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1303 break;
1304 case 0xb:
87e92502 1305 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1306 break;
1307 case 0xc:
87e92502 1308 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1309 break;
1310 case 0xd:
87e92502 1311 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1312 break;
1313 case 0xe:
87e92502 1314 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1315 break;
1316 case 0xf:
87e92502 1317 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1318 break;
1319 }
e8af50a3 1320}
00f219bf 1321
416fcaea
RH		 1322static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1323 DisasContext *dc)
1324{
1325 DisasCompare cmp;
1326 gen_compare(&cmp, cc, cond, dc);
1327
1328 /* The interface is to return a boolean in r_dst. */
1329 if (cmp.is_bool) {
1330 tcg_gen_mov_tl(r_dst, cmp.c1);
1331 } else {
1332 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1333 }
1334
1335 free_compare(&cmp);
1336}
1337
1338static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1339{
1340 DisasCompare cmp;
1341 gen_fcompare(&cmp, cc, cond);
1342
1343 /* The interface is to return a boolean in r_dst. */
1344 if (cmp.is_bool) {
1345 tcg_gen_mov_tl(r_dst, cmp.c1);
1346 } else {
1347 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1348 }
1349
1350 free_compare(&cmp);
1351}
1352
19f329ad 1353#ifdef TARGET_SPARC64
00f219bf
BS		 1354// Inverted logic
1355static const int gen_tcg_cond_reg[8] = {
1356 -1,
1357 TCG_COND_NE,
1358 TCG_COND_GT,
1359 TCG_COND_GE,
1360 -1,
1361 TCG_COND_EQ,
1362 TCG_COND_LE,
1363 TCG_COND_LT,
1364};
19f329ad 1365
416fcaea
RH		 1366static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1367{
1368 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1369 cmp->is_bool = false;
1370 cmp->g1 = true;
1371 cmp->g2 = false;
1372 cmp->c1 = r_src;
1373 cmp->c2 = tcg_const_tl(0);
1374}
1375
4af984a7 1376static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1377{
416fcaea
RH		 1378 DisasCompare cmp;
1379 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1380
416fcaea
RH		 1381 /* The interface is to return a boolean in r_dst. */
1382 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1383
1384 free_compare(&cmp);
19f329ad 1385}
3475187d 1386#endif
cf495bcf 1387
d4a288ef 1388static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1389{
cf495bcf 1390 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1391 target_ulong target = dc->pc + offset;
5fafdf24 1392
22036a49
AT		 1393#ifdef TARGET_SPARC64
1394 if (unlikely(AM_CHECK(dc))) {
1395 target &= 0xffffffffULL;
1396 }
1397#endif
cf495bcf 1398 if (cond == 0x0) {
0f8a249a
BS		 1399 /* unconditional not taken */
1400 if (a) {
1401 dc->pc = dc->npc + 4;
1402 dc->npc = dc->pc + 4;
1403 } else {
1404 dc->pc = dc->npc;
1405 dc->npc = dc->pc + 4;
1406 }
cf495bcf 1407 } else if (cond == 0x8) {
0f8a249a
BS		 1408 /* unconditional taken */
1409 if (a) {
1410 dc->pc = target;
1411 dc->npc = dc->pc + 4;
1412 } else {
1413 dc->pc = dc->npc;
1414 dc->npc = target;
c27e2752 1415 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1416 }
cf495bcf 1417 } else {
dee8913c 1418 flush_cond(dc);
d4a288ef 1419 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1420 if (a) {
bfa31b76 1421 gen_branch_a(dc, target);
0f8a249a 1422 } else {
2bf2e019 1423 gen_branch_n(dc, target);
0f8a249a 1424 }
cf495bcf 1425 }
7a3f1944
FB		 1426}
1427
d4a288ef 1428static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1429{
1430 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1431 target_ulong target = dc->pc + offset;
1432
22036a49
AT		 1433#ifdef TARGET_SPARC64
1434 if (unlikely(AM_CHECK(dc))) {
1435 target &= 0xffffffffULL;
1436 }
1437#endif
e8af50a3 1438 if (cond == 0x0) {
0f8a249a
BS		 1439 /* unconditional not taken */
1440 if (a) {
1441 dc->pc = dc->npc + 4;
1442 dc->npc = dc->pc + 4;
1443 } else {
1444 dc->pc = dc->npc;
1445 dc->npc = dc->pc + 4;
1446 }
e8af50a3 1447 } else if (cond == 0x8) {
0f8a249a
BS		 1448 /* unconditional taken */
1449 if (a) {
1450 dc->pc = target;
1451 dc->npc = dc->pc + 4;
1452 } else {
1453 dc->pc = dc->npc;
1454 dc->npc = target;
c27e2752 1455 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1456 }
e8af50a3 1457 } else {
dee8913c 1458 flush_cond(dc);
d4a288ef 1459 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1460 if (a) {
bfa31b76 1461 gen_branch_a(dc, target);
0f8a249a 1462 } else {
2bf2e019 1463 gen_branch_n(dc, target);
0f8a249a 1464 }
e8af50a3
FB		 1465 }
1466}
1467
3475187d 1468#ifdef TARGET_SPARC64
4af984a7 1469static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1470 TCGv r_reg)
7a3f1944 1471{
3475187d
FB		 1472 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1473 target_ulong target = dc->pc + offset;
1474
22036a49
AT		 1475 if (unlikely(AM_CHECK(dc))) {
1476 target &= 0xffffffffULL;
1477 }
dee8913c 1478 flush_cond(dc);
d4a288ef 1479 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1480 if (a) {
bfa31b76 1481 gen_branch_a(dc, target);
3475187d 1482 } else {
2bf2e019 1483 gen_branch_n(dc, target);
3475187d 1484 }
7a3f1944
FB		 1485}
1486
a7812ae4 1487static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1488{
714547bb
BS		 1489 switch (fccno) {
1490 case 0:
2e2f4ade 1491 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1492 break;
1493 case 1:
2e2f4ade 1494 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1495 break;
1496 case 2:
2e2f4ade 1497 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1498 break;
1499 case 3:
2e2f4ade 1500 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1501 break;
1502 }
7e8c2b6c
BS		 1503}
1504
03fb8cfc 1505static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1506{
a7812ae4
PB		 1507 switch (fccno) {
1508 case 0:
03fb8cfc 1509 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1510 break;
1511 case 1:
03fb8cfc 1512 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1513 break;
1514 case 2:
03fb8cfc 1515 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1516 break;
1517 case 3:
03fb8cfc 1518 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1519 break;
1520 }
7e8c2b6c
BS		 1521}
1522
7e8c2b6c
BS		 1523static inline void gen_op_fcmpq(int fccno)
1524{
a7812ae4
PB		 1525 switch (fccno) {
1526 case 0:
2e2f4ade 1527 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1528 break;
1529 case 1:
2e2f4ade 1530 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1531 break;
1532 case 2:
2e2f4ade 1533 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1534 break;
1535 case 3:
2e2f4ade 1536 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1537 break;
1538 }
7e8c2b6c 1539}
7e8c2b6c 1540
a7812ae4 1541static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1542{
714547bb
BS		 1543 switch (fccno) {
1544 case 0:
2e2f4ade 1545 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1546 break;
1547 case 1:
2e2f4ade 1548 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1549 break;
1550 case 2:
2e2f4ade 1551 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1552 break;
1553 case 3:
2e2f4ade 1554 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1555 break;
1556 }
7e8c2b6c
BS		 1557}
1558
03fb8cfc 1559static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1560{
a7812ae4
PB		 1561 switch (fccno) {
1562 case 0:
03fb8cfc 1563 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1564 break;
1565 case 1:
03fb8cfc 1566 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1567 break;
1568 case 2:
03fb8cfc 1569 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1570 break;
1571 case 3:
03fb8cfc 1572 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1573 break;
1574 }
7e8c2b6c
BS		 1575}
1576
7e8c2b6c
BS		 1577static inline void gen_op_fcmpeq(int fccno)
1578{
a7812ae4
PB		 1579 switch (fccno) {
1580 case 0:
2e2f4ade 1581 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1582 break;
1583 case 1:
2e2f4ade 1584 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1585 break;
1586 case 2:
2e2f4ade 1587 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1588 break;
1589 case 3:
2e2f4ade 1590 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1591 break;
1592 }
7e8c2b6c 1593}
7e8c2b6c
BS		 1594
1595#else
1596
714547bb 1597static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1598{
2e2f4ade 1599 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1600}
1601
03fb8cfc 1602static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1603{
03fb8cfc 1604 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1605}
1606
7e8c2b6c
BS		 1607static inline void gen_op_fcmpq(int fccno)
1608{
2e2f4ade 1609 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1610}
7e8c2b6c 1611
714547bb 1612static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1613{
2e2f4ade 1614 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1615}
1616
03fb8cfc 1617static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1618{
03fb8cfc 1619 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1620}
1621
7e8c2b6c
BS		 1622static inline void gen_op_fcmpeq(int fccno)
1623{
2e2f4ade 1624 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1625}
1626#endif
1627
134d77a1
BS		 1628static inline void gen_op_fpexception_im(int fsr_flags)
1629{
a7812ae4 1630 TCGv_i32 r_const;
2ea815ca 1631
47ad35f1 1632 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1633 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1634 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1635 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1636 tcg_temp_free_i32(r_const);
134d77a1
BS		 1637}
1638
5b12f1e8 1639static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1640{
1641#if !defined(CONFIG_USER_ONLY)
1642 if (!dc->fpu_enabled) {
a7812ae4 1643 TCGv_i32 r_const;
2ea815ca 1644
66442b07 1645 save_state(dc);
2ea815ca 1646 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1647 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1648 tcg_temp_free_i32(r_const);
a80dde08
FB		 1649 dc->is_br = 1;
1650 return 1;
1651 }
1652#endif
1653 return 0;
1654}
1655
7e8c2b6c
BS		 1656static inline void gen_op_clear_ieee_excp_and_FTT(void)
1657{
47ad35f1 1658 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1659}
1660
61f17f6e
RH		 1661static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1662 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1663{
1664 TCGv_i32 dst, src;
1665
61f17f6e 1666 src = gen_load_fpr_F(dc, rs);
ba5f5179 1667 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1668
1669 gen(dst, cpu_env, src);
1670
61f17f6e
RH		 1671 gen_store_fpr_F(dc, rd, dst);
1672}
1673
1674static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1675 void (*gen)(TCGv_i32, TCGv_i32))
1676{
1677 TCGv_i32 dst, src;
1678
1679 src = gen_load_fpr_F(dc, rs);
ba5f5179 1680 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1681
1682 gen(dst, src);
1683
1684 gen_store_fpr_F(dc, rd, dst);
1685}
1686
1687static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1688 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1689{
1690 TCGv_i32 dst, src1, src2;
1691
61f17f6e
RH		 1692 src1 = gen_load_fpr_F(dc, rs1);
1693 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1694 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1695
1696 gen(dst, cpu_env, src1, src2);
1697
61f17f6e
RH		 1698 gen_store_fpr_F(dc, rd, dst);
1699}
1700
1701#ifdef TARGET_SPARC64
1702static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1703 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1704{
1705 TCGv_i32 dst, src1, src2;
1706
1707 src1 = gen_load_fpr_F(dc, rs1);
1708 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1709 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1710
1711 gen(dst, src1, src2);
1712
1713 gen_store_fpr_F(dc, rd, dst);
1714}
1715#endif
1716
1717static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1718 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1719{
1720 TCGv_i64 dst, src;
1721
61f17f6e 1722 src = gen_load_fpr_D(dc, rs);
3886b8a3 1723 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1724
1725 gen(dst, cpu_env, src);
1726
61f17f6e
RH		 1727 gen_store_fpr_D(dc, rd, dst);
1728}
1729
1730#ifdef TARGET_SPARC64
1731static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1732 void (*gen)(TCGv_i64, TCGv_i64))
1733{
1734 TCGv_i64 dst, src;
1735
1736 src = gen_load_fpr_D(dc, rs);
3886b8a3 1737 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1738
1739 gen(dst, src);
1740
1741 gen_store_fpr_D(dc, rd, dst);
1742}
1743#endif
1744
1745static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1746 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1747{
1748 TCGv_i64 dst, src1, src2;
1749
61f17f6e
RH		 1750 src1 = gen_load_fpr_D(dc, rs1);
1751 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1752 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1753
1754 gen(dst, cpu_env, src1, src2);
1755
61f17f6e
RH		 1756 gen_store_fpr_D(dc, rd, dst);
1757}
1758
1759#ifdef TARGET_SPARC64
1760static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1761 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1762{
1763 TCGv_i64 dst, src1, src2;
1764
1765 src1 = gen_load_fpr_D(dc, rs1);
1766 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1767 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1768
1769 gen(dst, src1, src2);
1770
1771 gen_store_fpr_D(dc, rd, dst);
1772}
f888300b 1773
2dedf314
RH		 1774static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1775 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1776{
1777 TCGv_i64 dst, src1, src2;
1778
1779 src1 = gen_load_fpr_D(dc, rs1);
1780 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1781 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1782
1783 gen(dst, cpu_gsr, src1, src2);
1784
1785 gen_store_fpr_D(dc, rd, dst);
1786}
1787
f888300b
RH		 1788static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1789 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1790{
1791 TCGv_i64 dst, src0, src1, src2;
1792
1793 src1 = gen_load_fpr_D(dc, rs1);
1794 src2 = gen_load_fpr_D(dc, rs2);
1795 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1796 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1797
1798 gen(dst, src0, src1, src2);
1799
1800 gen_store_fpr_D(dc, rd, dst);
1801}
61f17f6e
RH		 1802#endif
1803
1804static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1805 void (*gen)(TCGv_ptr))
1806{
61f17f6e
RH		 1807 gen_op_load_fpr_QT1(QFPREG(rs));
1808
1809 gen(cpu_env);
1810
61f17f6e
RH		 1811 gen_op_store_QT0_fpr(QFPREG(rd));
1812 gen_update_fprs_dirty(QFPREG(rd));
1813}
1814
1815#ifdef TARGET_SPARC64
1816static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1817 void (*gen)(TCGv_ptr))
1818{
1819 gen_op_load_fpr_QT1(QFPREG(rs));
1820
1821 gen(cpu_env);
1822
1823 gen_op_store_QT0_fpr(QFPREG(rd));
1824 gen_update_fprs_dirty(QFPREG(rd));
1825}
1826#endif
1827
1828static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1829 void (*gen)(TCGv_ptr))
1830{
61f17f6e
RH		 1831 gen_op_load_fpr_QT0(QFPREG(rs1));
1832 gen_op_load_fpr_QT1(QFPREG(rs2));
1833
1834 gen(cpu_env);
1835
61f17f6e
RH		 1836 gen_op_store_QT0_fpr(QFPREG(rd));
1837 gen_update_fprs_dirty(QFPREG(rd));
1838}
1839
1840static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1841 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1842{
1843 TCGv_i64 dst;
1844 TCGv_i32 src1, src2;
1845
61f17f6e
RH		 1846 src1 = gen_load_fpr_F(dc, rs1);
1847 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1848 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1849
1850 gen(dst, cpu_env, src1, src2);
1851
61f17f6e
RH		 1852 gen_store_fpr_D(dc, rd, dst);
1853}
1854
1855static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1856 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1857{
1858 TCGv_i64 src1, src2;
1859
61f17f6e
RH		 1860 src1 = gen_load_fpr_D(dc, rs1);
1861 src2 = gen_load_fpr_D(dc, rs2);
1862
1863 gen(cpu_env, src1, src2);
1864
61f17f6e
RH		 1865 gen_op_store_QT0_fpr(QFPREG(rd));
1866 gen_update_fprs_dirty(QFPREG(rd));
1867}
1868
1869#ifdef TARGET_SPARC64
1870static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1871 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1872{
1873 TCGv_i64 dst;
1874 TCGv_i32 src;
1875
61f17f6e 1876 src = gen_load_fpr_F(dc, rs);
3886b8a3 1877 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1878
1879 gen(dst, cpu_env, src);
1880
61f17f6e
RH		 1881 gen_store_fpr_D(dc, rd, dst);
1882}
1883#endif
1884
1885static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1886 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1887{
1888 TCGv_i64 dst;
1889 TCGv_i32 src;
1890
1891 src = gen_load_fpr_F(dc, rs);
3886b8a3 1892 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1893
1894 gen(dst, cpu_env, src);
1895
1896 gen_store_fpr_D(dc, rd, dst);
1897}
1898
1899static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1900 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1901{
1902 TCGv_i32 dst;
1903 TCGv_i64 src;
1904
61f17f6e 1905 src = gen_load_fpr_D(dc, rs);
ba5f5179 1906 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1907
1908 gen(dst, cpu_env, src);
1909
61f17f6e
RH		 1910 gen_store_fpr_F(dc, rd, dst);
1911}
1912
1913static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1914 void (*gen)(TCGv_i32, TCGv_ptr))
1915{
1916 TCGv_i32 dst;
1917
61f17f6e 1918 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1919 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1920
1921 gen(dst, cpu_env);
1922
61f17f6e
RH		 1923 gen_store_fpr_F(dc, rd, dst);
1924}
1925
1926static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1927 void (*gen)(TCGv_i64, TCGv_ptr))
1928{
1929 TCGv_i64 dst;
1930
61f17f6e 1931 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1932 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1933
1934 gen(dst, cpu_env);
1935
61f17f6e
RH		 1936 gen_store_fpr_D(dc, rd, dst);
1937}
1938
1939static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1940 void (*gen)(TCGv_ptr, TCGv_i32))
1941{
1942 TCGv_i32 src;
1943
1944 src = gen_load_fpr_F(dc, rs);
1945
1946 gen(cpu_env, src);
1947
1948 gen_op_store_QT0_fpr(QFPREG(rd));
1949 gen_update_fprs_dirty(QFPREG(rd));
1950}
1951
1952static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1953 void (*gen)(TCGv_ptr, TCGv_i64))
1954{
1955 TCGv_i64 src;
1956
1957 src = gen_load_fpr_D(dc, rs);
1958
1959 gen(cpu_env, src);
1960
1961 gen_op_store_QT0_fpr(QFPREG(rd));
1962 gen_update_fprs_dirty(QFPREG(rd));
1963}
1964
1a2fb1c0
BS		 1965/* asi moves */
1966#ifdef TARGET_SPARC64
a7812ae4 1967static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1968{
95f9397c 1969 int asi;
a7812ae4 1970 TCGv_i32 r_asi;
1a2fb1c0 1971
1a2fb1c0 1972 if (IS_IMM) {
a7812ae4 1973 r_asi = tcg_temp_new_i32();
255e1fcb 1974 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1975 } else {
1976 asi = GET_FIELD(insn, 19, 26);
0425bee5 1977 r_asi = tcg_const_i32(asi);
1a2fb1c0 1978 }
0425bee5
BS		 1979 return r_asi;
1980}
1981
77f193da
BS		 1982static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1983 int sign)
0425bee5 1984{
a7812ae4 1985 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1986
4af984a7 1987 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1988 r_size = tcg_const_i32(size);
1989 r_sign = tcg_const_i32(sign);
fe8d8f0f 1990 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4
PB		 1991 tcg_temp_free_i32(r_sign);
1992 tcg_temp_free_i32(r_size);
1993 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1994}
1995
4af984a7 1996static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1997{
a7812ae4 1998 TCGv_i32 r_asi, r_size;
1a2fb1c0 1999
4af984a7 2000 r_asi = gen_get_asi(insn, addr);
2ea815ca 2001 r_size = tcg_const_i32(size);
fe8d8f0f 2002 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2003 tcg_temp_free_i32(r_size);
2004 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2005}
2006
4af984a7 2007static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2008{
a7812ae4 2009 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2010
4af984a7 2011 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2012 r_size = tcg_const_i32(size);
2013 r_rd = tcg_const_i32(rd);
fe8d8f0f 2014 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2015 tcg_temp_free_i32(r_rd);
2016 tcg_temp_free_i32(r_size);
2017 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2018}
2019
4af984a7 2020static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2021{
a7812ae4 2022 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2023
31741a27 2024 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2025 r_size = tcg_const_i32(size);
2026 r_rd = tcg_const_i32(rd);
fe8d8f0f 2027 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2028 tcg_temp_free_i32(r_rd);
2029 tcg_temp_free_i32(r_size);
2030 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2031}
2032
06828032 2033static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2034{
a7812ae4 2035 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2036 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2037
4af984a7 2038 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2039 r_size = tcg_const_i32(4);
2040 r_sign = tcg_const_i32(0);
1ec789ab 2041 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4 2042 tcg_temp_free_i32(r_sign);
06828032 2043 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2044 tcg_temp_free_i32(r_size);
2045 tcg_temp_free_i32(r_asi);
1ec789ab
RH		 2046 tcg_gen_trunc_i64_tl(dst, t64);
2047 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2048}
2049
c7785e16
RH		 2050static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2051 int insn, int rd)
1a2fb1c0 2052{
a7812ae4 2053 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2054
4af984a7 2055 r_asi = gen_get_asi(insn, addr);
db166940 2056 r_rd = tcg_const_i32(rd);
fe8d8f0f 2057 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2058 tcg_temp_free_i32(r_rd);
2059 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2060}
2061
c7785e16
RH		 2062static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2063 int insn, int rd)
0425bee5 2064{
a7812ae4 2065 TCGv_i32 r_asi, r_size;
c7785e16 2066 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2067 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2068
1ec789ab 2069 tcg_gen_concat_tl_i64(t64, lo, hi);
4af984a7 2070 r_asi = gen_get_asi(insn, addr);
2ea815ca 2071 r_size = tcg_const_i32(8);
1ec789ab 2072 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2073 tcg_temp_free_i32(r_size);
2074 tcg_temp_free_i32(r_asi);
1ec789ab 2075 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2076}
2077
81634eea 2078static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
c7785e16 2079 TCGv val2, int insn, int rd)
1a2fb1c0 2080{
81634eea
RH		 2081 TCGv val1 = gen_load_gpr(dc, rd);
2082 TCGv dst = gen_dest_gpr(dc, rd);
c7785e16 2083 TCGv_i32 r_asi = gen_get_asi(insn, addr);
1a2fb1c0 2084
81634eea 2085 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2086 tcg_temp_free_i32(r_asi);
81634eea 2087 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2088}
2089
2090#elif !defined(CONFIG_USER_ONLY)
2091
77f193da
BS		 2092static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2093 int sign)
1a2fb1c0 2094{
a7812ae4 2095 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2096 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2097
2ea815ca
BS		 2098 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2099 r_size = tcg_const_i32(size);
2100 r_sign = tcg_const_i32(sign);
1ec789ab
RH		 2101 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2102 tcg_temp_free_i32(r_sign);
2103 tcg_temp_free_i32(r_size);
2104 tcg_temp_free_i32(r_asi);
2105 tcg_gen_trunc_i64_tl(dst, t64);
2106 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2107}
2108
4af984a7 2109static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2110{
a7812ae4 2111 TCGv_i32 r_asi, r_size;
1ec789ab 2112 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2113
1ec789ab 2114 tcg_gen_extu_tl_i64(t64, src);
2ea815ca
BS		 2115 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2116 r_size = tcg_const_i32(size);
1ec789ab
RH		 2117 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2118 tcg_temp_free_i32(r_size);
2119 tcg_temp_free_i32(r_asi);
2120 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2121}
2122
06828032 2123static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2124{
a7812ae4 2125 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2126 TCGv_i64 r_val, t64;
1a2fb1c0 2127
2ea815ca
BS		 2128 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2129 r_size = tcg_const_i32(4);
2130 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2131 t64 = tcg_temp_new_i64();
2132 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2ea815ca 2133 tcg_temp_free(r_sign);
a7812ae4 2134 r_val = tcg_temp_new_i64();
06828032 2135 tcg_gen_extu_tl_i64(r_val, src);
fe8d8f0f 2136 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4 2137 tcg_temp_free_i64(r_val);
1ec789ab
RH		 2138 tcg_temp_free_i32(r_size);
2139 tcg_temp_free_i32(r_asi);
2140 tcg_gen_trunc_i64_tl(dst, t64);
2141 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2142}
2143
c7785e16
RH		 2144static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2145 int insn, int rd)
1a2fb1c0 2146{
a7812ae4 2147 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2148 TCGv t;
1ec789ab 2149 TCGv_i64 t64;
1a2fb1c0 2150
2ea815ca
BS		 2151 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2152 r_size = tcg_const_i32(8);
2153 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2154 t64 = tcg_temp_new_i64();
2155 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2156 tcg_temp_free_i32(r_sign);
2157 tcg_temp_free_i32(r_size);
2158 tcg_temp_free_i32(r_asi);
c7785e16
RH		 2159
2160 t = gen_dest_gpr(dc, rd + 1);
1ec789ab 2161 tcg_gen_trunc_i64_tl(t, t64);
c7785e16
RH		 2162 gen_store_gpr(dc, rd + 1, t);
2163
1ec789ab
RH		 2164 tcg_gen_shri_i64(t64, t64, 32);
2165 tcg_gen_trunc_i64_tl(hi, t64);
2166 tcg_temp_free_i64(t64);
c7785e16 2167 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2168}
2169
c7785e16
RH		 2170static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2171 int insn, int rd)
0425bee5 2172{
a7812ae4 2173 TCGv_i32 r_asi, r_size;
c7785e16 2174 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2175 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2176
1ec789ab 2177 tcg_gen_concat_tl_i64(t64, lo, hi);
2ea815ca
BS		 2178 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2179 r_size = tcg_const_i32(8);
1ec789ab
RH		 2180 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2181 tcg_temp_free_i32(r_size);
2182 tcg_temp_free_i32(r_asi);
2183 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2184}
2185#endif
2186
2187#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
16c358e9
SH		 2188static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2189 TCGv val2, int insn, int rd)
2190{
2191 TCGv val1 = gen_load_gpr(dc, rd);
2192 TCGv dst = gen_dest_gpr(dc, rd);
2193#ifdef TARGET_SPARC64
2194 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2195#else
2196 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2197#endif
2198
2199 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2200 tcg_temp_free_i32(r_asi);
2201 gen_store_gpr(dc, rd, dst);
2202}
2203
4af984a7 2204static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2205{
a7812ae4
PB		 2206 TCGv_i64 r_val;
2207 TCGv_i32 r_asi, r_size;
1a2fb1c0 2208
4af984a7 2209 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2210
2ea815ca
BS		 2211 r_val = tcg_const_i64(0xffULL);
2212 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2213 r_size = tcg_const_i32(1);
fe8d8f0f 2214 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4
PB		 2215 tcg_temp_free_i32(r_size);
2216 tcg_temp_free_i32(r_asi);
2217 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2218}
2219#endif
2220
9d1d4e34 2221static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2222{
9d1d4e34
RH		 2223 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2224 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2225}
2226
9d1d4e34 2227static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2228{
a49d9390 2229 if (IS_IMM) { /* immediate */
42a8aa83 2230 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2231 TCGv t = get_temp_tl(dc);
2232 tcg_gen_movi_tl(t, simm);
2233 return t;
2234 } else { /* register */
42a8aa83 2235 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2236 return gen_load_gpr(dc, rs2);
a49d9390 2237 }
a49d9390
BS		 2238}
2239
8194f35a 2240#ifdef TARGET_SPARC64
7e480893
RH		 2241static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2242{
2243 TCGv_i32 c32, zero, dst, s1, s2;
2244
2245 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2246 or fold the comparison down to 32 bits and use movcond_i32. Choose
2247 the later. */
2248 c32 = tcg_temp_new_i32();
2249 if (cmp->is_bool) {
ecc7b3aa 2250 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2251 } else {
2252 TCGv_i64 c64 = tcg_temp_new_i64();
2253 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2254 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2255 tcg_temp_free_i64(c64);
2256 }
2257
2258 s1 = gen_load_fpr_F(dc, rs);
2259 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2260 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2261 zero = tcg_const_i32(0);
2262
2263 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2264
2265 tcg_temp_free_i32(c32);
2266 tcg_temp_free_i32(zero);
2267 gen_store_fpr_F(dc, rd, dst);
2268}
2269
2270static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2271{
3886b8a3 2272 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2273 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2274 gen_load_fpr_D(dc, rs),
2275 gen_load_fpr_D(dc, rd));
2276 gen_store_fpr_D(dc, rd, dst);
2277}
2278
2279static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2280{
2281 int qd = QFPREG(rd);
2282 int qs = QFPREG(rs);
2283
2284 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2285 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2286 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2287 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2288
2289 gen_update_fprs_dirty(qd);
2290}
2291
a2035e83 2292#ifndef CONFIG_USER_ONLY
8194f35a
IK		 2293static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2294{
b551ec04 2295 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2296
2297 /* load env->tl into r_tl */
b551ec04 2298 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2299
2300 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2301 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2302
2303 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2304 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2305 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2306
2307 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2308 {
2309 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2310 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2311 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2312 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2313 }
8194f35a 2314
b551ec04 2315 tcg_temp_free_i32(r_tl);
8194f35a 2316}
a2035e83 2317#endif
6c073553
RH		 2318
2319static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2320 int width, bool cc, bool left)
2321{
2322 TCGv lo1, lo2, t1, t2;
2323 uint64_t amask, tabl, tabr;
2324 int shift, imask, omask;
2325
2326 if (cc) {
2327 tcg_gen_mov_tl(cpu_cc_src, s1);
2328 tcg_gen_mov_tl(cpu_cc_src2, s2);
2329 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2330 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2331 dc->cc_op = CC_OP_SUB;
2332 }
2333
2334 /* Theory of operation: there are two tables, left and right (not to
2335 be confused with the left and right versions of the opcode). These
2336 are indexed by the low 3 bits of the inputs. To make things "easy",
2337 these tables are loaded into two constants, TABL and TABR below.
2338 The operation index = (input & imask) << shift calculates the index
2339 into the constant, while val = (table >> index) & omask calculates
2340 the value we're looking for. */
2341 switch (width) {
2342 case 8:
2343 imask = 0x7;
2344 shift = 3;
2345 omask = 0xff;
2346 if (left) {
2347 tabl = 0x80c0e0f0f8fcfeffULL;
2348 tabr = 0xff7f3f1f0f070301ULL;
2349 } else {
2350 tabl = 0x0103070f1f3f7fffULL;
2351 tabr = 0xfffefcf8f0e0c080ULL;
2352 }
2353 break;
2354 case 16:
2355 imask = 0x6;
2356 shift = 1;
2357 omask = 0xf;
2358 if (left) {
2359 tabl = 0x8cef;
2360 tabr = 0xf731;
2361 } else {
2362 tabl = 0x137f;
2363 tabr = 0xfec8;
2364 }
2365 break;
2366 case 32:
2367 imask = 0x4;
2368 shift = 0;
2369 omask = 0x3;
2370 if (left) {
2371 tabl = (2 << 2) | 3;
2372 tabr = (3 << 2) | 1;
2373 } else {
2374 tabl = (1 << 2) | 3;
2375 tabr = (3 << 2) | 2;
2376 }
2377 break;
2378 default:
2379 abort();
2380 }
2381
2382 lo1 = tcg_temp_new();
2383 lo2 = tcg_temp_new();
2384 tcg_gen_andi_tl(lo1, s1, imask);
2385 tcg_gen_andi_tl(lo2, s2, imask);
2386 tcg_gen_shli_tl(lo1, lo1, shift);
2387 tcg_gen_shli_tl(lo2, lo2, shift);
2388
2389 t1 = tcg_const_tl(tabl);
2390 t2 = tcg_const_tl(tabr);
2391 tcg_gen_shr_tl(lo1, t1, lo1);
2392 tcg_gen_shr_tl(lo2, t2, lo2);
2393 tcg_gen_andi_tl(dst, lo1, omask);
2394 tcg_gen_andi_tl(lo2, lo2, omask);
2395
2396 amask = -8;
2397 if (AM_CHECK(dc)) {
2398 amask &= 0xffffffffULL;
2399 }
2400 tcg_gen_andi_tl(s1, s1, amask);
2401 tcg_gen_andi_tl(s2, s2, amask);
2402
2403 /* We want to compute
2404 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2405 We've already done dst = lo1, so this reduces to
2406 dst &= (s1 == s2 ? -1 : lo2)
2407 Which we perform by
2408 lo2 |= -(s1 == s2)
2409 dst &= lo2
2410 */
2411 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2412 tcg_gen_neg_tl(t1, t1);
2413 tcg_gen_or_tl(lo2, lo2, t1);
2414 tcg_gen_and_tl(dst, dst, lo2);
2415
2416 tcg_temp_free(lo1);
2417 tcg_temp_free(lo2);
2418 tcg_temp_free(t1);
2419 tcg_temp_free(t2);
2420}
add545ab
RH		 2421
2422static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2423{
2424 TCGv tmp = tcg_temp_new();
2425
2426 tcg_gen_add_tl(tmp, s1, s2);
2427 tcg_gen_andi_tl(dst, tmp, -8);
2428 if (left) {
2429 tcg_gen_neg_tl(tmp, tmp);
2430 }
2431 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2432
2433 tcg_temp_free(tmp);
2434}
50c796f9
RH		 2435
2436static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2437{
2438 TCGv t1, t2, shift;
2439
2440 t1 = tcg_temp_new();
2441 t2 = tcg_temp_new();
2442 shift = tcg_temp_new();
2443
2444 tcg_gen_andi_tl(shift, gsr, 7);
2445 tcg_gen_shli_tl(shift, shift, 3);
2446 tcg_gen_shl_tl(t1, s1, shift);
2447
2448 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2449 shift of (up to 63) followed by a constant shift of 1. */
2450 tcg_gen_xori_tl(shift, shift, 63);
2451 tcg_gen_shr_tl(t2, s2, shift);
2452 tcg_gen_shri_tl(t2, t2, 1);
2453
2454 tcg_gen_or_tl(dst, t1, t2);
2455
2456 tcg_temp_free(t1);
2457 tcg_temp_free(t2);
2458 tcg_temp_free(shift);
2459}
8194f35a
IK		 2460#endif
2461
64a88d5d 2462#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2463 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2464 goto illegal_insn;
2465#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2466 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2467 goto nfpu_insn;
2468
0bee699e 2469/* before an instruction, dc->pc must be static */
0184e266 2470static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2471{
0184e266 2472 unsigned int opc, rs1, rs2, rd;
a4273524 2473 TCGv cpu_src1, cpu_src2;
208ae657 2474 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2475 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2476 target_long simm;
7a3f1944 2477
cf495bcf 2478 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2479 rd = GET_FIELD(insn, 2, 6);
6ae20372 2480
cf495bcf 2481 switch (opc) {
0f8a249a
BS		 2482 case 0: /* branches/sethi */
2483 {
2484 unsigned int xop = GET_FIELD(insn, 7, 9);
2485 int32_t target;
2486 switch (xop) {
3475187d 2487#ifdef TARGET_SPARC64
0f8a249a
BS		 2488 case 0x1: /* V9 BPcc */
2489 {
2490 int cc;
2491
2492 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2493 target = sign_extend(target, 19);
0f8a249a
BS		 2494 target <<= 2;
2495 cc = GET_FIELD_SP(insn, 20, 21);
2496 if (cc == 0)
d4a288ef 2497 do_branch(dc, target, insn, 0);
0f8a249a 2498 else if (cc == 2)
d4a288ef 2499 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2500 else
2501 goto illegal_insn;
2502 goto jmp_insn;
2503 }
2504 case 0x3: /* V9 BPr */
2505 {
2506 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2507 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2508 target = sign_extend(target, 16);
2509 target <<= 2;
9d1d4e34 2510 cpu_src1 = get_src1(dc, insn);
d4a288ef 2511 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2512 goto jmp_insn;
2513 }
2514 case 0x5: /* V9 FBPcc */
2515 {
2516 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2517 if (gen_trap_ifnofpu(dc)) {
a80dde08 2518 goto jmp_insn;
5b12f1e8 2519 }
0f8a249a
BS		 2520 target = GET_FIELD_SP(insn, 0, 18);
2521 target = sign_extend(target, 19);
2522 target <<= 2;
d4a288ef 2523 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2524 goto jmp_insn;
2525 }
a4d17f19 2526#else
0f8a249a
BS		 2527 case 0x7: /* CBN+x */
2528 {
2529 goto ncp_insn;
2530 }
2531#endif
2532 case 0x2: /* BN+x */
2533 {
2534 target = GET_FIELD(insn, 10, 31);
2535 target = sign_extend(target, 22);
2536 target <<= 2;
d4a288ef 2537 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2538 goto jmp_insn;
2539 }
2540 case 0x6: /* FBN+x */
2541 {
5b12f1e8 2542 if (gen_trap_ifnofpu(dc)) {
a80dde08 2543 goto jmp_insn;
5b12f1e8 2544 }
0f8a249a
BS		 2545 target = GET_FIELD(insn, 10, 31);
2546 target = sign_extend(target, 22);
2547 target <<= 2;
d4a288ef 2548 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2549 goto jmp_insn;
2550 }
2551 case 0x4: /* SETHI */
97ea2859
RH		 2552 /* Special-case %g0 because that's the canonical nop. */
2553 if (rd) {
0f8a249a 2554 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2555 TCGv t = gen_dest_gpr(dc, rd);
2556 tcg_gen_movi_tl(t, value << 10);
2557 gen_store_gpr(dc, rd, t);
0f8a249a 2558 }
0f8a249a
BS		 2559 break;
2560 case 0x0: /* UNIMPL */
2561 default:
3475187d 2562 goto illegal_insn;
0f8a249a
BS		 2563 }
2564 break;
2565 }
2566 break;
dc1a6971
BS		 2567 case 1: /*CALL*/
2568 {
0f8a249a 2569 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2570 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2571
97ea2859
RH		 2572 tcg_gen_movi_tl(o7, dc->pc);
2573 gen_store_gpr(dc, 15, o7);
0f8a249a 2574 target += dc->pc;
13a6dd00 2575 gen_mov_pc_npc(dc);
22036a49
AT		 2576#ifdef TARGET_SPARC64
2577 if (unlikely(AM_CHECK(dc))) {
2578 target &= 0xffffffffULL;
2579 }
2580#endif
0f8a249a
BS		 2581 dc->npc = target;
2582 }
2583 goto jmp_insn;
2584 case 2: /* FPU & Logical Operations */
2585 {
2586 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2587 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2588 TCGv cpu_tmp0;
5793f2a4 2589
0f8a249a 2590 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2591 int cond = GET_FIELD(insn, 3, 6);
2592 TCGv_i32 trap;
42a268c2
RH		 2593 TCGLabel *l1 = NULL;
2594 int mask;
3475187d 2595
bd49ed41
RH		 2596 if (cond == 0) {
2597 /* Trap never. */
2598 break;
cf495bcf 2599 }
b04d9890 2600
bd49ed41 2601 save_state(dc);
b04d9890 2602
bd49ed41
RH		 2603 if (cond != 8) {
2604 /* Conditional trap. */
3a49e759 2605 DisasCompare cmp;
3475187d 2606#ifdef TARGET_SPARC64
0f8a249a
BS		 2607 /* V9 icc/xcc */
2608 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2609 if (cc == 0) {
2610 gen_compare(&cmp, 0, cond, dc);
2611 } else if (cc == 2) {
2612 gen_compare(&cmp, 1, cond, dc);
2613 } else {
0f8a249a 2614 goto illegal_insn;
3a49e759 2615 }
3475187d 2616#else
3a49e759 2617 gen_compare(&cmp, 0, cond, dc);
3475187d 2618#endif
b158a785 2619 l1 = gen_new_label();
3a49e759
RH		 2620 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2621 cmp.c1, cmp.c2, l1);
2622 free_compare(&cmp);
bd49ed41 2623 }
b158a785 2624
bd49ed41
RH		 2625 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2626 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2627
2628 /* Don't use the normal temporaries, as they may well have
2629 gone out of scope with the branch above. While we're
2630 doing that we might as well pre-truncate to 32-bit. */
2631 trap = tcg_temp_new_i32();
2632
2633 rs1 = GET_FIELD_SP(insn, 14, 18);
2634 if (IS_IMM) {
2635 rs2 = GET_FIELD_SP(insn, 0, 6);
2636 if (rs1 == 0) {
2637 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2638 /* Signal that the trap value is fully constant. */
2639 mask = 0;
2640 } else {
97ea2859 2641 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2642 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2643 tcg_gen_addi_i32(trap, trap, rs2);
2644 }
2645 } else {
97ea2859 2646 TCGv t1, t2;
bd49ed41 2647 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2648 t1 = gen_load_gpr(dc, rs1);
2649 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2650 tcg_gen_add_tl(t1, t1, t2);
2651 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2652 }
2653 if (mask != 0) {
2654 tcg_gen_andi_i32(trap, trap, mask);
2655 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2656 }
2657
2658 gen_helper_raise_exception(cpu_env, trap);
2659 tcg_temp_free_i32(trap);
b158a785 2660
fe1755cb
RH		 2661 if (cond == 8) {
2662 /* An unconditional trap ends the TB. */
2663 dc->is_br = 1;
2664 goto jmp_insn;
2665 } else {
2666 /* A conditional trap falls through to the next insn. */
b158a785 2667 gen_set_label(l1);
fe1755cb 2668 break;
cf495bcf
FB		 2669 }
2670 } else if (xop == 0x28) {
2671 rs1 = GET_FIELD(insn, 13, 17);
2672 switch(rs1) {
2673 case 0: /* rdy */
65fe7b09
BS		 2674#ifndef TARGET_SPARC64
2675 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2676 manual, rdy on the microSPARC
2677 II */
2678 case 0x0f: /* stbar in the SPARCv8 manual,
2679 rdy on the microSPARC II */
2680 case 0x10 ... 0x1f: /* implementation-dependent in the
2681 SPARCv8 manual, rdy on the
2682 microSPARC II */
4a2ba232
FC		 2683 /* Read Asr17 */
2684 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2685 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2686 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2687 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2688 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2689 break;
2690 }
65fe7b09 2691#endif
97ea2859 2692 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2693 break;
3475187d 2694#ifdef TARGET_SPARC64
0f8a249a 2695 case 0x2: /* V9 rdccr */
20132b96 2696 update_psr(dc);
063c3675 2697 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2698 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2699 break;
0f8a249a 2700 case 0x3: /* V9 rdasi */
255e1fcb 2701 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
97ea2859 2702 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2703 break;
0f8a249a 2704 case 0x4: /* V9 rdtick */
ccd4a219 2705 {
a7812ae4 2706 TCGv_ptr r_tickptr;
c9a46442 2707 TCGv_i32 r_const;
ccd4a219 2708
a7812ae4 2709 r_tickptr = tcg_temp_new_ptr();
c9a46442 2710 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2711 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2712 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2713 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2714 r_const);
a7812ae4 2715 tcg_temp_free_ptr(r_tickptr);
c9a46442 2716 tcg_temp_free_i32(r_const);
97ea2859 2717 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2718 }
3475187d 2719 break;
0f8a249a 2720 case 0x5: /* V9 rdpc */
2ea815ca 2721 {
97ea2859 2722 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2723 if (unlikely(AM_CHECK(dc))) {
97ea2859 2724 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2725 } else {
97ea2859 2726 tcg_gen_movi_tl(t, dc->pc);
22036a49 2727 }
97ea2859 2728 gen_store_gpr(dc, rd, t);
2ea815ca 2729 }
0f8a249a
BS		 2730 break;
2731 case 0x6: /* V9 rdfprs */
255e1fcb 2732 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2733 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2734 break;
65fe7b09
BS		 2735 case 0xf: /* V9 membar */
2736 break; /* no effect */
0f8a249a 2737 case 0x13: /* Graphics Status */
5b12f1e8 2738 if (gen_trap_ifnofpu(dc)) {
725cb90b 2739 goto jmp_insn;
5b12f1e8 2740 }
97ea2859 2741 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2742 break;
9d926598
BS		 2743 case 0x16: /* Softint */
2744 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
97ea2859 2745 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2746 break;
0f8a249a 2747 case 0x17: /* Tick compare */
97ea2859 2748 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2749 break;
0f8a249a 2750 case 0x18: /* System tick */
ccd4a219 2751 {
a7812ae4 2752 TCGv_ptr r_tickptr;
c9a46442 2753 TCGv_i32 r_const;
ccd4a219 2754
a7812ae4 2755 r_tickptr = tcg_temp_new_ptr();
c9a46442 2756 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2757 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2758 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 2759 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2760 r_const);
a7812ae4 2761 tcg_temp_free_ptr(r_tickptr);
c9a46442 2762 tcg_temp_free_i32(r_const);
97ea2859 2763 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2764 }
83469015 2765 break;
0f8a249a 2766 case 0x19: /* System tick compare */
97ea2859 2767 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2768 break;
0f8a249a
BS		 2769 case 0x10: /* Performance Control */
2770 case 0x11: /* Performance Instrumentation Counter */
2771 case 0x12: /* Dispatch Control */
2772 case 0x14: /* Softint set, WO */
2773 case 0x15: /* Softint clear, WO */
3475187d
FB		 2774#endif
2775 default:
cf495bcf
FB		 2776 goto illegal_insn;
2777 }
e8af50a3 2778#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2779 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2780#ifndef TARGET_SPARC64
20132b96 2781 if (!supervisor(dc)) {
0f8a249a 2782 goto priv_insn;
20132b96
RH		 2783 }
2784 update_psr(dc);
063c3675 2785 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2786#else
fb79ceb9 2787 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2788 if (!hypervisor(dc))
2789 goto priv_insn;
2790 rs1 = GET_FIELD(insn, 13, 17);
2791 switch (rs1) {
2792 case 0: // hpstate
2793 // gen_op_rdhpstate();
2794 break;
2795 case 1: // htstate
2796 // gen_op_rdhtstate();
2797 break;
2798 case 3: // hintp
255e1fcb 2799 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2800 break;
2801 case 5: // htba
255e1fcb 2802 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2803 break;
2804 case 6: // hver
255e1fcb 2805 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2806 break;
2807 case 31: // hstick_cmpr
255e1fcb 2808 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2809 break;
2810 default:
2811 goto illegal_insn;
2812 }
2813#endif
97ea2859 2814 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2815 break;
3475187d 2816 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2817 if (!supervisor(dc)) {
0f8a249a 2818 goto priv_insn;
de9e9d9f
RH		 2819 }
2820 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2821#ifdef TARGET_SPARC64
2822 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2823 switch (rs1) {
2824 case 0: // tpc
375ee38b 2825 {
a7812ae4 2826 TCGv_ptr r_tsptr;
375ee38b 2827
a7812ae4 2828 r_tsptr = tcg_temp_new_ptr();
8194f35a 2829 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2830 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2831 offsetof(trap_state, tpc));
a7812ae4 2832 tcg_temp_free_ptr(r_tsptr);
375ee38b 2833 }
0f8a249a
BS		 2834 break;
2835 case 1: // tnpc
375ee38b 2836 {
a7812ae4 2837 TCGv_ptr r_tsptr;
375ee38b 2838
a7812ae4 2839 r_tsptr = tcg_temp_new_ptr();
8194f35a 2840 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2841 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2842 offsetof(trap_state, tnpc));
a7812ae4 2843 tcg_temp_free_ptr(r_tsptr);
375ee38b 2844 }
0f8a249a
BS		 2845 break;
2846 case 2: // tstate
375ee38b 2847 {
a7812ae4 2848 TCGv_ptr r_tsptr;
375ee38b 2849
a7812ae4 2850 r_tsptr = tcg_temp_new_ptr();
8194f35a 2851 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2852 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2853 offsetof(trap_state, tstate));
a7812ae4 2854 tcg_temp_free_ptr(r_tsptr);
375ee38b 2855 }
0f8a249a
BS		 2856 break;
2857 case 3: // tt
375ee38b 2858 {
45778f99 2859 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2860
8194f35a 2861 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2862 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2863 offsetof(trap_state, tt));
a7812ae4 2864 tcg_temp_free_ptr(r_tsptr);
375ee38b 2865 }
0f8a249a
BS		 2866 break;
2867 case 4: // tick
ccd4a219 2868 {
a7812ae4 2869 TCGv_ptr r_tickptr;
c9a46442 2870 TCGv_i32 r_const;
ccd4a219 2871
a7812ae4 2872 r_tickptr = tcg_temp_new_ptr();
c9a46442 2873 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2874 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2875 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2876 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
2877 r_tickptr, r_const);
a7812ae4 2878 tcg_temp_free_ptr(r_tickptr);
c9a46442 2879 tcg_temp_free_i32(r_const);
ccd4a219 2880 }
0f8a249a
BS		 2881 break;
2882 case 5: // tba
255e1fcb 2883 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2884 break;
2885 case 6: // pstate
45778f99
RH		 2886 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2887 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2888 break;
2889 case 7: // tl
45778f99
RH		 2890 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2891 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2892 break;
2893 case 8: // pil
45778f99
RH		 2894 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2895 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2896 break;
2897 case 9: // cwp
063c3675 2898 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2899 break;
2900 case 10: // cansave
45778f99
RH		 2901 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2902 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2903 break;
2904 case 11: // canrestore
45778f99
RH		 2905 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2906 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2907 break;
2908 case 12: // cleanwin
45778f99
RH		 2909 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2910 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2911 break;
2912 case 13: // otherwin
45778f99
RH		 2913 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2914 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2915 break;
2916 case 14: // wstate
45778f99
RH		 2917 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2918 offsetof(CPUSPARCState, wstate));
0f8a249a 2919 break;
e9ebed4d 2920 case 16: // UA2005 gl
fb79ceb9 2921 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2922 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2923 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2924 break;
2925 case 26: // UA2005 strand status
fb79ceb9 2926 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2927 if (!hypervisor(dc))
2928 goto priv_insn;
527067d8 2929 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2930 break;
0f8a249a 2931 case 31: // ver
255e1fcb 2932 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2933 break;
2934 case 15: // fq
2935 default:
2936 goto illegal_insn;
2937 }
3475187d 2938#else
255e1fcb 2939 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2940#endif
97ea2859 2941 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2942 break;
3475187d
FB		 2943 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2944#ifdef TARGET_SPARC64
66442b07 2945 save_state(dc);
063c3675 2946 gen_helper_flushw(cpu_env);
3475187d 2947#else
0f8a249a
BS		 2948 if (!supervisor(dc))
2949 goto priv_insn;
97ea2859 2950 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2951#endif
e8af50a3
FB		 2952 break;
2953#endif
0f8a249a 2954 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2955 if (gen_trap_ifnofpu(dc)) {
a80dde08 2956 goto jmp_insn;
5b12f1e8 2957 }
0f8a249a 2958 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2959 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2960 rs2 = GET_FIELD(insn, 27, 31);
2961 xop = GET_FIELD(insn, 18, 26);
66442b07 2962 save_state(dc);
0f8a249a 2963 switch (xop) {
dc1a6971 2964 case 0x1: /* fmovs */
208ae657
RH		 2965 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2966 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2967 break;
2968 case 0x5: /* fnegs */
61f17f6e 2969 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2970 break;
2971 case 0x9: /* fabss */
61f17f6e 2972 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2973 break;
2974 case 0x29: /* fsqrts */
2975 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2976 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2977 break;
2978 case 0x2a: /* fsqrtd */
2979 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2980 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2981 break;
2982 case 0x2b: /* fsqrtq */
2983 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2984 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2985 break;
2986 case 0x41: /* fadds */
61f17f6e 2987 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2988 break;
2989 case 0x42: /* faddd */
61f17f6e 2990 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2991 break;
2992 case 0x43: /* faddq */
2993 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2994 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2995 break;
2996 case 0x45: /* fsubs */
61f17f6e 2997 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2998 break;
2999 case 0x46: /* fsubd */
61f17f6e 3000 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3001 break;
3002 case 0x47: /* fsubq */
3003 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3004 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3005 break;
3006 case 0x49: /* fmuls */
3007 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3008 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3009 break;
3010 case 0x4a: /* fmuld */
3011 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3012 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3013 break;
3014 case 0x4b: /* fmulq */
3015 CHECK_FPU_FEATURE(dc, FLOAT128);
3016 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3017 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3018 break;
3019 case 0x4d: /* fdivs */
61f17f6e 3020 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3021 break;
3022 case 0x4e: /* fdivd */
61f17f6e 3023 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3024 break;
3025 case 0x4f: /* fdivq */
3026 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3027 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3028 break;
3029 case 0x69: /* fsmuld */
3030 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3031 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3032 break;
3033 case 0x6e: /* fdmulq */
3034 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3035 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3036 break;
3037 case 0xc4: /* fitos */
61f17f6e 3038 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3039 break;
3040 case 0xc6: /* fdtos */
61f17f6e 3041 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3042 break;
3043 case 0xc7: /* fqtos */
3044 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3045 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3046 break;
3047 case 0xc8: /* fitod */
61f17f6e 3048 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3049 break;
3050 case 0xc9: /* fstod */
61f17f6e 3051 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3052 break;
3053 case 0xcb: /* fqtod */
3054 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3055 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3056 break;
3057 case 0xcc: /* fitoq */
3058 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3059 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3060 break;
3061 case 0xcd: /* fstoq */
3062 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3063 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3064 break;
3065 case 0xce: /* fdtoq */
3066 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3067 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3068 break;
3069 case 0xd1: /* fstoi */
61f17f6e 3070 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3071 break;
3072 case 0xd2: /* fdtoi */
61f17f6e 3073 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3074 break;
3075 case 0xd3: /* fqtoi */
3076 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3077 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3078 break;
3475187d 3079#ifdef TARGET_SPARC64
dc1a6971 3080 case 0x2: /* V9 fmovd */
96eda024
RH		 3081 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3082 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3083 break;
3084 case 0x3: /* V9 fmovq */
3085 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3086 gen_move_Q(rd, rs2);
dc1a6971
BS		 3087 break;
3088 case 0x6: /* V9 fnegd */
61f17f6e 3089 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3090 break;
3091 case 0x7: /* V9 fnegq */
3092 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3093 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3094 break;
3095 case 0xa: /* V9 fabsd */
61f17f6e 3096 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3097 break;
3098 case 0xb: /* V9 fabsq */
3099 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3100 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3101 break;
3102 case 0x81: /* V9 fstox */
61f17f6e 3103 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3104 break;
3105 case 0x82: /* V9 fdtox */
61f17f6e 3106 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3107 break;
3108 case 0x83: /* V9 fqtox */
3109 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3110 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3111 break;
3112 case 0x84: /* V9 fxtos */
61f17f6e 3113 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3114 break;
3115 case 0x88: /* V9 fxtod */
61f17f6e 3116 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3117 break;
3118 case 0x8c: /* V9 fxtoq */
3119 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3120 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3121 break;
0f8a249a 3122#endif
dc1a6971
BS		 3123 default:
3124 goto illegal_insn;
0f8a249a
BS		 3125 }
3126 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3127#ifdef TARGET_SPARC64
0f8a249a 3128 int cond;
3475187d 3129#endif
5b12f1e8 3130 if (gen_trap_ifnofpu(dc)) {
a80dde08 3131 goto jmp_insn;
5b12f1e8 3132 }
0f8a249a 3133 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3134 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3135 rs2 = GET_FIELD(insn, 27, 31);
3136 xop = GET_FIELD(insn, 18, 26);
66442b07 3137 save_state(dc);
dcf24905 3138
690995a6
RH		 3139#ifdef TARGET_SPARC64
3140#define FMOVR(sz) \
3141 do { \
3142 DisasCompare cmp; \
e7c8afb9 3143 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3144 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3145 gen_compare_reg(&cmp, cond, cpu_src1); \
3146 gen_fmov##sz(dc, &cmp, rd, rs2); \
3147 free_compare(&cmp); \
3148 } while (0)
3149
3150 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3151 FMOVR(s);
0f8a249a
BS		 3152 break;
3153 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3154 FMOVR(d);
0f8a249a
BS		 3155 break;
3156 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3157 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3158 FMOVR(q);
1f587329 3159 break;
0f8a249a 3160 }
690995a6 3161#undef FMOVR
0f8a249a
BS		 3162#endif
3163 switch (xop) {
3475187d 3164#ifdef TARGET_SPARC64
7e480893
RH		 3165#define FMOVCC(fcc, sz) \
3166 do { \
3167 DisasCompare cmp; \
714547bb 3168 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3169 gen_fcompare(&cmp, fcc, cond); \
3170 gen_fmov##sz(dc, &cmp, rd, rs2); \
3171 free_compare(&cmp); \
3172 } while (0)
3173
0f8a249a 3174 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3175 FMOVCC(0, s);
0f8a249a
BS		 3176 break;
3177 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3178 FMOVCC(0, d);
0f8a249a
BS		 3179 break;
3180 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3181 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3182 FMOVCC(0, q);
1f587329 3183 break;
0f8a249a 3184 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3185 FMOVCC(1, s);
0f8a249a
BS		 3186 break;
3187 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3188 FMOVCC(1, d);
0f8a249a
BS		 3189 break;
3190 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3191 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3192 FMOVCC(1, q);
1f587329 3193 break;
0f8a249a 3194 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3195 FMOVCC(2, s);
0f8a249a
BS		 3196 break;
3197 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3198 FMOVCC(2, d);
0f8a249a
BS		 3199 break;
3200 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3201 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3202 FMOVCC(2, q);
1f587329 3203 break;
0f8a249a 3204 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3205 FMOVCC(3, s);
0f8a249a
BS		 3206 break;
3207 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3208 FMOVCC(3, d);
0f8a249a
BS		 3209 break;
3210 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3211 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3212 FMOVCC(3, q);
1f587329 3213 break;
7e480893
RH		 3214#undef FMOVCC
3215#define FMOVCC(xcc, sz) \
3216 do { \
3217 DisasCompare cmp; \
714547bb 3218 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3219 gen_compare(&cmp, xcc, cond, dc); \
3220 gen_fmov##sz(dc, &cmp, rd, rs2); \
3221 free_compare(&cmp); \
3222 } while (0)
19f329ad 3223
0f8a249a 3224 case 0x101: /* V9 fmovscc %icc */
7e480893 3225 FMOVCC(0, s);
0f8a249a
BS		 3226 break;
3227 case 0x102: /* V9 fmovdcc %icc */
7e480893 3228 FMOVCC(0, d);
b7d69dc2 3229 break;
0f8a249a 3230 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3231 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3232 FMOVCC(0, q);
1f587329 3233 break;
0f8a249a 3234 case 0x181: /* V9 fmovscc %xcc */
7e480893 3235 FMOVCC(1, s);
0f8a249a
BS		 3236 break;
3237 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3238 FMOVCC(1, d);
0f8a249a
BS		 3239 break;
3240 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3241 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3242 FMOVCC(1, q);
1f587329 3243 break;
7e480893 3244#undef FMOVCC
1f587329
BS		 3245#endif
3246 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3247 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3248 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3249 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3250 break;
1f587329 3251 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3252 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3253 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3254 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3255 break;
1f587329 3256 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3257 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3258 gen_op_load_fpr_QT0(QFPREG(rs1));
3259 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3260 gen_op_fcmpq(rd & 3);
1f587329 3261 break;
0f8a249a 3262 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3263 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3264 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3265 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3266 break;
3267 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3268 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3269 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3270 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3271 break;
1f587329 3272 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3273 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3274 gen_op_load_fpr_QT0(QFPREG(rs1));
3275 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3276 gen_op_fcmpeq(rd & 3);
1f587329 3277 break;
0f8a249a
BS		 3278 default:
3279 goto illegal_insn;
3280 }
0f8a249a 3281 } else if (xop == 0x2) {
97ea2859 3282 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3283 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3284 if (rs1 == 0) {
97ea2859 3285 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3286 if (IS_IMM) { /* immediate */
67526b20 3287 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3288 tcg_gen_movi_tl(dst, simm);
3289 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3290 } else { /* register */
3291 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3292 if (rs2 == 0) {
3293 tcg_gen_movi_tl(dst, 0);
3294 gen_store_gpr(dc, rd, dst);
3295 } else {
3296 cpu_src2 = gen_load_gpr(dc, rs2);
3297 gen_store_gpr(dc, rd, cpu_src2);
3298 }
0f8a249a 3299 }
0f8a249a 3300 } else {
9d1d4e34 3301 cpu_src1 = get_src1(dc, insn);
0f8a249a 3302 if (IS_IMM) { /* immediate */
67526b20 3303 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3304 tcg_gen_ori_tl(dst, cpu_src1, simm);
3305 gen_store_gpr(dc, rd, dst);
0f8a249a 3306 } else { /* register */
0f8a249a 3307 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3308 if (rs2 == 0) {
3309 /* mov shortcut: or x, %g0, y -> mov x, y */
3310 gen_store_gpr(dc, rd, cpu_src1);
3311 } else {
3312 cpu_src2 = gen_load_gpr(dc, rs2);
3313 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3314 gen_store_gpr(dc, rd, dst);
3315 }
0f8a249a 3316 }
0f8a249a 3317 }
83469015 3318#ifdef TARGET_SPARC64
0f8a249a 3319 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3320 cpu_src1 = get_src1(dc, insn);
0f8a249a 3321 if (IS_IMM) { /* immediate */
67526b20 3322 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3323 if (insn & (1 << 12)) {
67526b20 3324 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3325 } else {
67526b20 3326 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3327 }
0f8a249a 3328 } else { /* register */
83469015 3329 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3330 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3331 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3332 if (insn & (1 << 12)) {
6ae20372 3333 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3334 } else {
6ae20372 3335 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3336 }
01b1fa6d 3337 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3338 }
97ea2859 3339 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3340 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3341 cpu_src1 = get_src1(dc, insn);
0f8a249a 3342 if (IS_IMM) { /* immediate */
67526b20 3343 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3344 if (insn & (1 << 12)) {
67526b20 3345 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3346 } else {
6ae20372 3347 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3348 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3349 }
0f8a249a 3350 } else { /* register */
83469015 3351 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3352 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3353 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3354 if (insn & (1 << 12)) {
6ae20372
BS		 3355 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3356 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3357 } else {
6ae20372
BS		 3358 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3359 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3360 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3361 }
83469015 3362 }
97ea2859 3363 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3364 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3365 cpu_src1 = get_src1(dc, insn);
0f8a249a 3366 if (IS_IMM) { /* immediate */
67526b20 3367 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3368 if (insn & (1 << 12)) {
67526b20 3369 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3370 } else {
97ea2859 3371 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3372 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3373 }
0f8a249a 3374 } else { /* register */
83469015 3375 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3376 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3377 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3378 if (insn & (1 << 12)) {
6ae20372
BS		 3379 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3380 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3381 } else {
6ae20372 3382 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3383 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3384 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3385 }
83469015 3386 }
97ea2859 3387 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3388#endif
fcc72045 3389 } else if (xop < 0x36) {
cf495bcf 3390 if (xop < 0x20) {
9d1d4e34
RH		 3391 cpu_src1 = get_src1(dc, insn);
3392 cpu_src2 = get_src2(dc, insn);
cf495bcf 3393 switch (xop & ~0x10) {
b89e94af 3394 case 0x0: /* add */
97ea2859
RH		 3395 if (xop & 0x10) {
3396 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3397 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3398 dc->cc_op = CC_OP_ADD;
41d72852 3399 } else {
97ea2859 3400 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3401 }
cf495bcf 3402 break;
b89e94af 3403 case 0x1: /* and */
97ea2859 3404 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3405 if (xop & 0x10) {
38482a77
BS		 3406 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3407 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3408 dc->cc_op = CC_OP_LOGIC;
41d72852 3409 }
cf495bcf 3410 break;
b89e94af 3411 case 0x2: /* or */
97ea2859 3412 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3413 if (xop & 0x10) {
38482a77
BS		 3414 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3415 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3416 dc->cc_op = CC_OP_LOGIC;
8393617c 3417 }
0f8a249a 3418 break;
b89e94af 3419 case 0x3: /* xor */
97ea2859 3420 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3421 if (xop & 0x10) {
38482a77
BS		 3422 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3423 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3424 dc->cc_op = CC_OP_LOGIC;
8393617c 3425 }
cf495bcf 3426 break;
b89e94af 3427 case 0x4: /* sub */
97ea2859
RH		 3428 if (xop & 0x10) {
3429 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3430 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3431 dc->cc_op = CC_OP_SUB;
41d72852 3432 } else {
97ea2859 3433 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3434 }
cf495bcf 3435 break;
b89e94af 3436 case 0x5: /* andn */
97ea2859 3437 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3438 if (xop & 0x10) {
38482a77
BS		 3439 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3440 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3441 dc->cc_op = CC_OP_LOGIC;
8393617c 3442 }
cf495bcf 3443 break;
b89e94af 3444 case 0x6: /* orn */
97ea2859 3445 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3446 if (xop & 0x10) {
38482a77
BS		 3447 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3448 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3449 dc->cc_op = CC_OP_LOGIC;
8393617c 3450 }
cf495bcf 3451 break;
b89e94af 3452 case 0x7: /* xorn */
97ea2859 3453 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3454 if (xop & 0x10) {
38482a77
BS		 3455 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3456 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3457 dc->cc_op = CC_OP_LOGIC;
8393617c 3458 }
cf495bcf 3459 break;
b89e94af 3460 case 0x8: /* addx, V9 addc */
70c48285
RH		 3461 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3462 (xop & 0x10));
cf495bcf 3463 break;
ded3ab80 3464#ifdef TARGET_SPARC64
0f8a249a 3465 case 0x9: /* V9 mulx */
97ea2859 3466 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3467 break;
3468#endif
b89e94af 3469 case 0xa: /* umul */
64a88d5d 3470 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3471 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3472 if (xop & 0x10) {
38482a77
BS		 3473 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3474 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3475 dc->cc_op = CC_OP_LOGIC;
8393617c 3476 }
cf495bcf 3477 break;
b89e94af 3478 case 0xb: /* smul */
64a88d5d 3479 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3480 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3481 if (xop & 0x10) {
38482a77
BS		 3482 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3483 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3484 dc->cc_op = CC_OP_LOGIC;
8393617c 3485 }
cf495bcf 3486 break;
b89e94af 3487 case 0xc: /* subx, V9 subc */
70c48285
RH		 3488 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3489 (xop & 0x10));
cf495bcf 3490 break;
ded3ab80 3491#ifdef TARGET_SPARC64
0f8a249a 3492 case 0xd: /* V9 udivx */
c28ae41e 3493 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3494 break;
3495#endif
b89e94af 3496 case 0xe: /* udiv */
64a88d5d 3497 CHECK_IU_FEATURE(dc, DIV);
8393617c 3498 if (xop & 0x10) {
7a5e4488
BS		 3499 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3500 cpu_src2);
6c78ea32 3501 dc->cc_op = CC_OP_DIV;
0fcec41e 3502 } else {
7a5e4488
BS		 3503 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3504 cpu_src2);
8393617c 3505 }
cf495bcf 3506 break;
b89e94af 3507 case 0xf: /* sdiv */
64a88d5d 3508 CHECK_IU_FEATURE(dc, DIV);
8393617c 3509 if (xop & 0x10) {
7a5e4488
BS		 3510 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3511 cpu_src2);
6c78ea32 3512 dc->cc_op = CC_OP_DIV;
0fcec41e 3513 } else {
7a5e4488
BS		 3514 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3515 cpu_src2);
8393617c 3516 }
cf495bcf
FB		 3517 break;
3518 default:
3519 goto illegal_insn;
3520 }
97ea2859 3521 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3522 } else {
9d1d4e34
RH		 3523 cpu_src1 = get_src1(dc, insn);
3524 cpu_src2 = get_src2(dc, insn);
cf495bcf 3525 switch (xop) {
0f8a249a 3526 case 0x20: /* taddcc */
a2ea4aa9 3527 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3528 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3529 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3530 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3531 break;
3532 case 0x21: /* tsubcc */
a2ea4aa9 3533 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3534 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3535 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3536 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3537 break;
3538 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3539 gen_helper_taddcctv(cpu_dst, cpu_env,
3540 cpu_src1, cpu_src2);
97ea2859 3541 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3542 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3543 break;
3544 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3545 gen_helper_tsubcctv(cpu_dst, cpu_env,
3546 cpu_src1, cpu_src2);
97ea2859 3547 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3548 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3549 break;
cf495bcf 3550 case 0x24: /* mulscc */
20132b96 3551 update_psr(dc);
6ae20372 3552 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3553 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3554 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3555 dc->cc_op = CC_OP_ADD;
cf495bcf 3556 break;
83469015 3557#ifndef TARGET_SPARC64
0f8a249a 3558 case 0x25: /* sll */
e35298cd 3559 if (IS_IMM) { /* immediate */
67526b20
BS		 3560 simm = GET_FIELDs(insn, 20, 31);
3561 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3562 } else { /* register */
de9e9d9f 3563 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3564 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3565 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3566 }
97ea2859 3567 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3568 break;
83469015 3569 case 0x26: /* srl */
e35298cd 3570 if (IS_IMM) { /* immediate */
67526b20
BS		 3571 simm = GET_FIELDs(insn, 20, 31);
3572 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3573 } else { /* register */
de9e9d9f 3574 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3575 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3576 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3577 }
97ea2859 3578 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3579 break;
83469015 3580 case 0x27: /* sra */
e35298cd 3581 if (IS_IMM) { /* immediate */
67526b20
BS		 3582 simm = GET_FIELDs(insn, 20, 31);
3583 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3584 } else { /* register */
de9e9d9f 3585 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3586 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3587 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3588 }
97ea2859 3589 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3590 break;
83469015 3591#endif
cf495bcf
FB		 3592 case 0x30:
3593 {
de9e9d9f 3594 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3595 switch(rd) {
3475187d 3596 case 0: /* wry */
5068cbd9
BS		 3597 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3598 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3599 break;
65fe7b09
BS		 3600#ifndef TARGET_SPARC64
3601 case 0x01 ... 0x0f: /* undefined in the
3602 SPARCv8 manual, nop
3603 on the microSPARC
3604 II */
3605 case 0x10 ... 0x1f: /* implementation-dependent
3606 in the SPARCv8
3607 manual, nop on the
3608 microSPARC II */
d1c36ba7
RH		 3609 if ((rd == 0x13) && (dc->def->features &
3610 CPU_FEATURE_POWERDOWN)) {
3611 /* LEON3 power-down */
1cf892ca 3612 save_state(dc);
d1c36ba7
RH		 3613 gen_helper_power_down(cpu_env);
3614 }
65fe7b09
BS		 3615 break;
3616#else
0f8a249a 3617 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3618 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3619 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3620 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3621 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3622 break;
3623 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3624 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3625 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3626 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
0f8a249a
BS		 3627 break;
3628 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3629 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3630 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3631 save_state(dc);
3299908c 3632 gen_op_next_insn();
57fec1fe 3633 tcg_gen_exit_tb(0);
3299908c 3634 dc->is_br = 1;
0f8a249a
BS		 3635 break;
3636 case 0xf: /* V9 sir, nop if user */
3475187d 3637#if !defined(CONFIG_USER_ONLY)
6ad6135d 3638 if (supervisor(dc)) {
1a2fb1c0 3639 ; // XXX
6ad6135d 3640 }
3475187d 3641#endif
0f8a249a
BS		 3642 break;
3643 case 0x13: /* Graphics Status */
5b12f1e8 3644 if (gen_trap_ifnofpu(dc)) {
725cb90b 3645 goto jmp_insn;
5b12f1e8 3646 }
255e1fcb 3647 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3648 break;
9d926598
BS		 3649 case 0x14: /* Softint set */
3650 if (!supervisor(dc))
3651 goto illegal_insn;
aeff993c
RH		 3652 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3653 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3654 break;
3655 case 0x15: /* Softint clear */
3656 if (!supervisor(dc))
3657 goto illegal_insn;
aeff993c
RH		 3658 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3659 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3660 break;
3661 case 0x16: /* Softint write */
3662 if (!supervisor(dc))
3663 goto illegal_insn;
aeff993c
RH		 3664 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3665 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3666 break;
0f8a249a 3667 case 0x17: /* Tick compare */
83469015 3668#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3669 if (!supervisor(dc))
3670 goto illegal_insn;
83469015 3671#endif
ccd4a219 3672 {
a7812ae4 3673 TCGv_ptr r_tickptr;
ccd4a219 3674
255e1fcb 3675 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3676 cpu_src2);
a7812ae4 3677 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3678 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3679 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3680 gen_helper_tick_set_limit(r_tickptr,
3681 cpu_tick_cmpr);
3682 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3683 }
0f8a249a
BS		 3684 break;
3685 case 0x18: /* System tick */
83469015 3686#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3687 if (!supervisor(dc))
3688 goto illegal_insn;
83469015 3689#endif
ccd4a219 3690 {
a7812ae4 3691 TCGv_ptr r_tickptr;
ccd4a219 3692
7b04bd5c 3693 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3694 cpu_src2);
a7812ae4 3695 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3696 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3697 offsetof(CPUSPARCState, stick));
a7812ae4 3698 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3699 cpu_tmp0);
a7812ae4 3700 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3701 }
0f8a249a
BS		 3702 break;
3703 case 0x19: /* System tick compare */
83469015 3704#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3705 if (!supervisor(dc))
3706 goto illegal_insn;
3475187d 3707#endif
ccd4a219 3708 {
a7812ae4 3709 TCGv_ptr r_tickptr;
ccd4a219 3710
255e1fcb 3711 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3712 cpu_src2);
a7812ae4 3713 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3714 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3715 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3716 gen_helper_tick_set_limit(r_tickptr,
3717 cpu_stick_cmpr);
3718 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3719 }
0f8a249a 3720 break;
83469015 3721
0f8a249a 3722 case 0x10: /* Performance Control */
77f193da
BS		 3723 case 0x11: /* Performance Instrumentation
3724 Counter */
0f8a249a 3725 case 0x12: /* Dispatch Control */
83469015 3726#endif
3475187d 3727 default:
cf495bcf
FB		 3728 goto illegal_insn;
3729 }
3730 }
3731 break;
e8af50a3 3732#if !defined(CONFIG_USER_ONLY)
af7bf89b 3733 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3734 {
0f8a249a
BS		 3735 if (!supervisor(dc))
3736 goto priv_insn;
3475187d 3737#ifdef TARGET_SPARC64
0f8a249a
BS		 3738 switch (rd) {
3739 case 0:
063c3675 3740 gen_helper_saved(cpu_env);
0f8a249a
BS		 3741 break;
3742 case 1:
063c3675 3743 gen_helper_restored(cpu_env);
0f8a249a 3744 break;
e9ebed4d
BS		 3745 case 2: /* UA2005 allclean */
3746 case 3: /* UA2005 otherw */
3747 case 4: /* UA2005 normalw */
3748 case 5: /* UA2005 invalw */
3749 // XXX
0f8a249a 3750 default:
3475187d
FB		 3751 goto illegal_insn;
3752 }
3753#else
de9e9d9f 3754 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3755 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3756 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3757 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3758 dc->cc_op = CC_OP_FLAGS;
66442b07 3759 save_state(dc);
9e61bde5 3760 gen_op_next_insn();
57fec1fe 3761 tcg_gen_exit_tb(0);
0f8a249a 3762 dc->is_br = 1;
3475187d 3763#endif
e8af50a3
FB		 3764 }
3765 break;
af7bf89b 3766 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3767 {
0f8a249a
BS		 3768 if (!supervisor(dc))
3769 goto priv_insn;
de9e9d9f 3770 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3771 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3772#ifdef TARGET_SPARC64
0f8a249a
BS		 3773 switch (rd) {
3774 case 0: // tpc
375ee38b 3775 {
a7812ae4 3776 TCGv_ptr r_tsptr;
375ee38b 3777
a7812ae4 3778 r_tsptr = tcg_temp_new_ptr();
8194f35a 3779 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3780 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3781 offsetof(trap_state, tpc));
a7812ae4 3782 tcg_temp_free_ptr(r_tsptr);
375ee38b 3783 }
0f8a249a
BS		 3784 break;
3785 case 1: // tnpc
375ee38b 3786 {
a7812ae4 3787 TCGv_ptr r_tsptr;
375ee38b 3788
a7812ae4 3789 r_tsptr = tcg_temp_new_ptr();
8194f35a 3790 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3791 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3792 offsetof(trap_state, tnpc));
a7812ae4 3793 tcg_temp_free_ptr(r_tsptr);
375ee38b 3794 }
0f8a249a
BS		 3795 break;
3796 case 2: // tstate
375ee38b 3797 {
a7812ae4 3798 TCGv_ptr r_tsptr;
375ee38b 3799
a7812ae4 3800 r_tsptr = tcg_temp_new_ptr();
8194f35a 3801 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3802 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3803 offsetof(trap_state,
3804 tstate));
a7812ae4 3805 tcg_temp_free_ptr(r_tsptr);
375ee38b 3806 }
0f8a249a
BS		 3807 break;
3808 case 3: // tt
375ee38b 3809 {
a7812ae4 3810 TCGv_ptr r_tsptr;
375ee38b 3811
a7812ae4 3812 r_tsptr = tcg_temp_new_ptr();
8194f35a 3813 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3814 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3815 offsetof(trap_state, tt));
a7812ae4 3816 tcg_temp_free_ptr(r_tsptr);
375ee38b 3817 }
0f8a249a
BS		 3818 break;
3819 case 4: // tick
ccd4a219 3820 {
a7812ae4 3821 TCGv_ptr r_tickptr;
ccd4a219 3822
a7812ae4 3823 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3824 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3825 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3826 gen_helper_tick_set_count(r_tickptr,
3827 cpu_tmp0);
3828 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3829 }
0f8a249a
BS		 3830 break;
3831 case 5: // tba
255e1fcb 3832 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3833 break;
3834 case 6: // pstate
6234ac09
RH		 3835 save_state(dc);
3836 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3837 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3838 break;
3839 case 7: // tl
6234ac09 3840 save_state(dc);
7b9e066b 3841 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3842 offsetof(CPUSPARCState, tl));
3843 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3844 break;
3845 case 8: // pil
063c3675 3846 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3847 break;
3848 case 9: // cwp
063c3675 3849 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3850 break;
3851 case 10: // cansave
7b9e066b
RH		 3852 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3853 offsetof(CPUSPARCState,
3854 cansave));
0f8a249a
BS		 3855 break;
3856 case 11: // canrestore
7b9e066b
RH		 3857 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3858 offsetof(CPUSPARCState,
3859 canrestore));
0f8a249a
BS		 3860 break;
3861 case 12: // cleanwin
7b9e066b
RH		 3862 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3863 offsetof(CPUSPARCState,
3864 cleanwin));
0f8a249a
BS		 3865 break;
3866 case 13: // otherwin
7b9e066b
RH		 3867 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3868 offsetof(CPUSPARCState,
3869 otherwin));
0f8a249a
BS		 3870 break;
3871 case 14: // wstate
7b9e066b
RH		 3872 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3873 offsetof(CPUSPARCState,
3874 wstate));
0f8a249a 3875 break;
e9ebed4d 3876 case 16: // UA2005 gl
fb79ceb9 3877 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3878 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3879 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3880 break;
3881 case 26: // UA2005 strand status
fb79ceb9 3882 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3883 if (!hypervisor(dc))
3884 goto priv_insn;
527067d8 3885 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3886 break;
0f8a249a
BS		 3887 default:
3888 goto illegal_insn;
3889 }
3475187d 3890#else
7b9e066b
RH		 3891 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3892 if (dc->def->nwindows != 32) {
3893 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3894 (1 << dc->def->nwindows) - 1);
7b9e066b 3895 }
3475187d 3896#endif
e8af50a3
FB		 3897 }
3898 break;
e9ebed4d 3899 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3900 {
e9ebed4d 3901#ifndef TARGET_SPARC64
0f8a249a
BS		 3902 if (!supervisor(dc))
3903 goto priv_insn;
255e1fcb 3904 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3905#else
fb79ceb9 3906 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3907 if (!hypervisor(dc))
3908 goto priv_insn;
de9e9d9f 3909 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3910 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3911 switch (rd) {
3912 case 0: // hpstate
3913 // XXX gen_op_wrhpstate();
66442b07 3914 save_state(dc);
e9ebed4d 3915 gen_op_next_insn();
57fec1fe 3916 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3917 dc->is_br = 1;
3918 break;
3919 case 1: // htstate
3920 // XXX gen_op_wrhtstate();
3921 break;
3922 case 3: // hintp
255e1fcb 3923 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3924 break;
3925 case 5: // htba
255e1fcb 3926 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3927 break;
3928 case 31: // hstick_cmpr
ccd4a219 3929 {
a7812ae4 3930 TCGv_ptr r_tickptr;
ccd4a219 3931
255e1fcb 3932 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3933 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3934 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3935 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3936 gen_helper_tick_set_limit(r_tickptr,
3937 cpu_hstick_cmpr);
3938 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3939 }
e9ebed4d
BS		 3940 break;
3941 case 6: // hver readonly
3942 default:
3943 goto illegal_insn;
3944 }
3945#endif
e8af50a3
FB		 3946 }
3947 break;
3948#endif
3475187d 3949#ifdef TARGET_SPARC64
0f8a249a
BS		 3950 case 0x2c: /* V9 movcc */
3951 {
3952 int cc = GET_FIELD_SP(insn, 11, 12);
3953 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3954 DisasCompare cmp;
97ea2859 3955 TCGv dst;
00f219bf 3956
0f8a249a 3957 if (insn & (1 << 18)) {
f52879b4
RH		 3958 if (cc == 0) {
3959 gen_compare(&cmp, 0, cond, dc);
3960 } else if (cc == 2) {
3961 gen_compare(&cmp, 1, cond, dc);
3962 } else {
0f8a249a 3963 goto illegal_insn;
f52879b4 3964 }
0f8a249a 3965 } else {
f52879b4 3966 gen_fcompare(&cmp, cc, cond);
0f8a249a 3967 }
00f219bf 3968
f52879b4
RH		 3969 /* The get_src2 above loaded the normal 13-bit
3970 immediate field, not the 11-bit field we have
3971 in movcc. But it did handle the reg case. */
3972 if (IS_IMM) {
67526b20 3973 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3974 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3975 }
f52879b4 3976
97ea2859
RH		 3977 dst = gen_load_gpr(dc, rd);
3978 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3979 cmp.c1, cmp.c2,
97ea2859 3980 cpu_src2, dst);
f52879b4 3981 free_compare(&cmp);
97ea2859 3982 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3983 break;
3984 }
3985 case 0x2d: /* V9 sdivx */
c28ae41e 3986 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3987 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3988 break;
3989 case 0x2e: /* V9 popc */
97ea2859
RH		 3990 gen_helper_popc(cpu_dst, cpu_src2);
3991 gen_store_gpr(dc, rd, cpu_dst);
3992 break;
0f8a249a
BS		 3993 case 0x2f: /* V9 movr */
3994 {
3995 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3996 DisasCompare cmp;
97ea2859 3997 TCGv dst;
00f219bf 3998
c33f80f5 3999 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4000
c33f80f5
RH		 4001 /* The get_src2 above loaded the normal 13-bit
4002 immediate field, not the 10-bit field we have
4003 in movr. But it did handle the reg case. */
4004 if (IS_IMM) {
67526b20 4005 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4006 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4007 }
c33f80f5 4008
97ea2859
RH		 4009 dst = gen_load_gpr(dc, rd);
4010 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4011 cmp.c1, cmp.c2,
97ea2859 4012 cpu_src2, dst);
c33f80f5 4013 free_compare(&cmp);
97ea2859 4014 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4015 break;
4016 }
4017#endif
4018 default:
4019 goto illegal_insn;
4020 }
4021 }
3299908c
BS		 4022 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4023#ifdef TARGET_SPARC64
4024 int opf = GET_FIELD_SP(insn, 5, 13);
4025 rs1 = GET_FIELD(insn, 13, 17);
4026 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4027 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4028 goto jmp_insn;
5b12f1e8 4029 }
3299908c
BS		 4030
4031 switch (opf) {
e9ebed4d 4032 case 0x000: /* VIS I edge8cc */
6c073553 4033 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4034 cpu_src1 = gen_load_gpr(dc, rs1);
4035 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4036 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4037 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4038 break;
e9ebed4d 4039 case 0x001: /* VIS II edge8n */
6c073553 4040 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4041 cpu_src1 = gen_load_gpr(dc, rs1);
4042 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4043 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4044 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4045 break;
e9ebed4d 4046 case 0x002: /* VIS I edge8lcc */
6c073553 4047 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4048 cpu_src1 = gen_load_gpr(dc, rs1);
4049 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4050 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4051 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4052 break;
e9ebed4d 4053 case 0x003: /* VIS II edge8ln */
6c073553 4054 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4055 cpu_src1 = gen_load_gpr(dc, rs1);
4056 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4057 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4058 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4059 break;
e9ebed4d 4060 case 0x004: /* VIS I edge16cc */
6c073553 4061 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4062 cpu_src1 = gen_load_gpr(dc, rs1);
4063 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4064 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4065 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4066 break;
e9ebed4d 4067 case 0x005: /* VIS II edge16n */
6c073553 4068 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4069 cpu_src1 = gen_load_gpr(dc, rs1);
4070 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4071 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4072 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4073 break;
e9ebed4d 4074 case 0x006: /* VIS I edge16lcc */
6c073553 4075 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4076 cpu_src1 = gen_load_gpr(dc, rs1);
4077 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4078 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4079 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4080 break;
e9ebed4d 4081 case 0x007: /* VIS II edge16ln */
6c073553 4082 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4083 cpu_src1 = gen_load_gpr(dc, rs1);
4084 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4085 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4086 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4087 break;
e9ebed4d 4088 case 0x008: /* VIS I edge32cc */
6c073553 4089 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4090 cpu_src1 = gen_load_gpr(dc, rs1);
4091 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4092 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4093 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4094 break;
e9ebed4d 4095 case 0x009: /* VIS II edge32n */
6c073553 4096 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4097 cpu_src1 = gen_load_gpr(dc, rs1);
4098 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4099 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4100 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4101 break;
e9ebed4d 4102 case 0x00a: /* VIS I edge32lcc */
6c073553 4103 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4104 cpu_src1 = gen_load_gpr(dc, rs1);
4105 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4106 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4107 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4108 break;
e9ebed4d 4109 case 0x00b: /* VIS II edge32ln */
6c073553 4110 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4111 cpu_src1 = gen_load_gpr(dc, rs1);
4112 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4113 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4114 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4115 break;
e9ebed4d 4116 case 0x010: /* VIS I array8 */
64a88d5d 4117 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4118 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4119 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4120 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4121 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4122 break;
4123 case 0x012: /* VIS I array16 */
64a88d5d 4124 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4125 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4126 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4127 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4128 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4129 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4130 break;
4131 case 0x014: /* VIS I array32 */
64a88d5d 4132 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4133 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4134 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4135 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4136 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4137 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4138 break;
3299908c 4139 case 0x018: /* VIS I alignaddr */
64a88d5d 4140 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4141 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4142 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4143 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4144 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4145 break;
4146 case 0x01a: /* VIS I alignaddrl */
add545ab 4147 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4148 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4149 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4150 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4151 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4152 break;
4153 case 0x019: /* VIS II bmask */
793a137a 4154 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4155 cpu_src1 = gen_load_gpr(dc, rs1);
4156 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4157 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4158 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4159 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4160 break;
e9ebed4d 4161 case 0x020: /* VIS I fcmple16 */
64a88d5d 4162 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4163 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4164 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4165 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4166 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4167 break;
4168 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4169 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4170 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4171 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4172 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4173 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4174 break;
e9ebed4d 4175 case 0x024: /* VIS I fcmple32 */
64a88d5d 4176 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4177 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4178 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4179 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4180 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4181 break;
4182 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4183 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4184 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4185 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4186 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4187 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4188 break;
4189 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4190 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4191 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4192 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4193 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4194 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4195 break;
4196 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4197 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4198 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4199 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4200 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4201 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4202 break;
4203 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4204 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4205 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4206 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4207 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4208 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4209 break;
4210 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4211 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4212 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4213 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4214 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4215 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4216 break;
4217 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4218 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4219 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4220 break;
4221 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4222 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4223 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4224 break;
4225 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4226 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4227 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4228 break;
4229 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4230 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4231 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4232 break;
4233 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4234 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4235 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4236 break;
4237 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4238 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4239 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4240 break;
4241 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4242 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4243 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4244 break;
4245 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4246 CHECK_FPU_FEATURE(dc, VIS1);
4247 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4248 break;
e9ebed4d 4249 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4250 CHECK_FPU_FEATURE(dc, VIS1);
4251 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4252 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4253 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4254 gen_store_fpr_F(dc, rd, cpu_dst_32);
4255 break;
e9ebed4d 4256 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4257 CHECK_FPU_FEATURE(dc, VIS1);
4258 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4259 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4260 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4261 gen_store_fpr_F(dc, rd, cpu_dst_32);
4262 break;
f888300b
RH		 4263 case 0x03e: /* VIS I pdist */
4264 CHECK_FPU_FEATURE(dc, VIS1);
4265 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4266 break;
3299908c 4267 case 0x048: /* VIS I faligndata */
64a88d5d 4268 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4269 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4270 break;
e9ebed4d 4271 case 0x04b: /* VIS I fpmerge */
64a88d5d 4272 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4273 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4274 break;
4275 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4276 CHECK_FPU_FEATURE(dc, VIS2);
4277 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4278 break;
e9ebed4d 4279 case 0x04d: /* VIS I fexpand */
64a88d5d 4280 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4281 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4282 break;
4283 case 0x050: /* VIS I fpadd16 */
64a88d5d 4284 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4285 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4286 break;
4287 case 0x051: /* VIS I fpadd16s */
64a88d5d 4288 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4289 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4290 break;
4291 case 0x052: /* VIS I fpadd32 */
64a88d5d 4292 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4293 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4294 break;
4295 case 0x053: /* VIS I fpadd32s */
64a88d5d 4296 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4297 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4298 break;
4299 case 0x054: /* VIS I fpsub16 */
64a88d5d 4300 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4301 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4302 break;
4303 case 0x055: /* VIS I fpsub16s */
64a88d5d 4304 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4305 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4306 break;
4307 case 0x056: /* VIS I fpsub32 */
64a88d5d 4308 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4309 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4310 break;
4311 case 0x057: /* VIS I fpsub32s */
64a88d5d 4312 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4313 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4314 break;
3299908c 4315 case 0x060: /* VIS I fzero */
64a88d5d 4316 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4317 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4318 tcg_gen_movi_i64(cpu_dst_64, 0);
4319 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4320 break;
4321 case 0x061: /* VIS I fzeros */
64a88d5d 4322 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4323 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4324 tcg_gen_movi_i32(cpu_dst_32, 0);
4325 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4326 break;
e9ebed4d 4327 case 0x062: /* VIS I fnor */
64a88d5d 4328 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4329 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4330 break;
4331 case 0x063: /* VIS I fnors */
64a88d5d 4332 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4333 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4334 break;
4335 case 0x064: /* VIS I fandnot2 */
64a88d5d 4336 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4337 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4338 break;
4339 case 0x065: /* VIS I fandnot2s */
64a88d5d 4340 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4341 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4342 break;
4343 case 0x066: /* VIS I fnot2 */
64a88d5d 4344 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4345 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4346 break;
4347 case 0x067: /* VIS I fnot2s */
64a88d5d 4348 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4349 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4350 break;
4351 case 0x068: /* VIS I fandnot1 */
64a88d5d 4352 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4353 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4354 break;
4355 case 0x069: /* VIS I fandnot1s */
64a88d5d 4356 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4357 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4358 break;
4359 case 0x06a: /* VIS I fnot1 */
64a88d5d 4360 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4361 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4362 break;
4363 case 0x06b: /* VIS I fnot1s */
64a88d5d 4364 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4365 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4366 break;
4367 case 0x06c: /* VIS I fxor */
64a88d5d 4368 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4369 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4370 break;
4371 case 0x06d: /* VIS I fxors */
64a88d5d 4372 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4373 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4374 break;
4375 case 0x06e: /* VIS I fnand */
64a88d5d 4376 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4377 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4378 break;
4379 case 0x06f: /* VIS I fnands */
64a88d5d 4380 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4381 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4382 break;
4383 case 0x070: /* VIS I fand */
64a88d5d 4384 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4385 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4386 break;
4387 case 0x071: /* VIS I fands */
64a88d5d 4388 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4389 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4390 break;
4391 case 0x072: /* VIS I fxnor */
64a88d5d 4392 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4393 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4394 break;
4395 case 0x073: /* VIS I fxnors */
64a88d5d 4396 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4397 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4398 break;
3299908c 4399 case 0x074: /* VIS I fsrc1 */
64a88d5d 4400 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4401 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4402 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4403 break;
4404 case 0x075: /* VIS I fsrc1s */
64a88d5d 4405 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4406 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4407 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4408 break;
e9ebed4d 4409 case 0x076: /* VIS I fornot2 */
64a88d5d 4410 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4411 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4412 break;
4413 case 0x077: /* VIS I fornot2s */
64a88d5d 4414 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4415 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4416 break;
3299908c 4417 case 0x078: /* VIS I fsrc2 */
64a88d5d 4418 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4419 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4420 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4421 break;
4422 case 0x079: /* VIS I fsrc2s */
64a88d5d 4423 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4424 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4425 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4426 break;
e9ebed4d 4427 case 0x07a: /* VIS I fornot1 */
64a88d5d 4428 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4429 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4430 break;
4431 case 0x07b: /* VIS I fornot1s */
64a88d5d 4432 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4433 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4434 break;
4435 case 0x07c: /* VIS I for */
64a88d5d 4436 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4437 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4438 break;
4439 case 0x07d: /* VIS I fors */
64a88d5d 4440 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4441 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4442 break;
3299908c 4443 case 0x07e: /* VIS I fone */
64a88d5d 4444 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4445 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4446 tcg_gen_movi_i64(cpu_dst_64, -1);
4447 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4448 break;
4449 case 0x07f: /* VIS I fones */
64a88d5d 4450 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4451 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4452 tcg_gen_movi_i32(cpu_dst_32, -1);
4453 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4454 break;
e9ebed4d
BS		 4455 case 0x080: /* VIS I shutdown */
4456 case 0x081: /* VIS II siam */
4457 // XXX
4458 goto illegal_insn;
3299908c
BS		 4459 default:
4460 goto illegal_insn;
4461 }
4462#else
0f8a249a 4463 goto ncp_insn;
3299908c
BS		 4464#endif
4465 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4466#ifdef TARGET_SPARC64
0f8a249a 4467 goto illegal_insn;
fcc72045 4468#else
0f8a249a 4469 goto ncp_insn;
fcc72045 4470#endif
3475187d 4471#ifdef TARGET_SPARC64
0f8a249a 4472 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4473 TCGv_i32 r_const;
2ea815ca 4474
66442b07 4475 save_state(dc);
9d1d4e34 4476 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4477 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4478 if (IS_IMM) { /* immediate */
67526b20 4479 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4480 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4481 } else { /* register */
3475187d 4482 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4483 if (rs2) {
97ea2859 4484 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4485 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4486 } else {
7b04bd5c 4487 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4488 }
3475187d 4489 }
063c3675 4490 gen_helper_restore(cpu_env);
13a6dd00 4491 gen_mov_pc_npc(dc);
2ea815ca 4492 r_const = tcg_const_i32(3);
7b04bd5c 4493 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4494 tcg_temp_free_i32(r_const);
7b04bd5c 4495 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4496 dc->npc = DYNAMIC_PC;
4497 goto jmp_insn;
3475187d 4498#endif
0f8a249a 4499 } else {
9d1d4e34 4500 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4501 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4502 if (IS_IMM) { /* immediate */
67526b20 4503 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4504 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4505 } else { /* register */
e80cfcfc 4506 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4507 if (rs2) {
97ea2859 4508 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4509 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4510 } else {
7b04bd5c 4511 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4512 }
cf495bcf 4513 }
0f8a249a
BS		 4514 switch (xop) {
4515 case 0x38: /* jmpl */
4516 {
97ea2859 4517 TCGv t;
a7812ae4 4518 TCGv_i32 r_const;
2ea815ca 4519
97ea2859
RH		 4520 t = gen_dest_gpr(dc, rd);
4521 tcg_gen_movi_tl(t, dc->pc);
4522 gen_store_gpr(dc, rd, t);
13a6dd00 4523 gen_mov_pc_npc(dc);
2ea815ca 4524 r_const = tcg_const_i32(3);
7b04bd5c 4525 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4526 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4527 gen_address_mask(dc, cpu_tmp0);
4528 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4529 dc->npc = DYNAMIC_PC;
4530 }
4531 goto jmp_insn;
3475187d 4532#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4533 case 0x39: /* rett, V9 return */
4534 {
a7812ae4 4535 TCGv_i32 r_const;
2ea815ca 4536
0f8a249a
BS		 4537 if (!supervisor(dc))
4538 goto priv_insn;
13a6dd00 4539 gen_mov_pc_npc(dc);
2ea815ca 4540 r_const = tcg_const_i32(3);
7b04bd5c 4541 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4542 tcg_temp_free_i32(r_const);
7b04bd5c 4543 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4544 dc->npc = DYNAMIC_PC;
063c3675 4545 gen_helper_rett(cpu_env);
0f8a249a
BS		 4546 }
4547 goto jmp_insn;
4548#endif
4549 case 0x3b: /* flush */
5578ceab 4550 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4551 goto unimp_flush;
dcfd14b3 4552 /* nop */
0f8a249a
BS		 4553 break;
4554 case 0x3c: /* save */
66442b07 4555 save_state(dc);
063c3675 4556 gen_helper_save(cpu_env);
7b04bd5c 4557 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4558 break;
4559 case 0x3d: /* restore */
66442b07 4560 save_state(dc);
063c3675 4561 gen_helper_restore(cpu_env);
7b04bd5c 4562 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4563 break;
3475187d 4564#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4565 case 0x3e: /* V9 done/retry */
4566 {
4567 switch (rd) {
4568 case 0:
4569 if (!supervisor(dc))
4570 goto priv_insn;
4571 dc->npc = DYNAMIC_PC;
4572 dc->pc = DYNAMIC_PC;
063c3675 4573 gen_helper_done(cpu_env);
0f8a249a
BS		 4574 goto jmp_insn;
4575 case 1:
4576 if (!supervisor(dc))
4577 goto priv_insn;
4578 dc->npc = DYNAMIC_PC;
4579 dc->pc = DYNAMIC_PC;
063c3675 4580 gen_helper_retry(cpu_env);
0f8a249a
BS		 4581 goto jmp_insn;
4582 default:
4583 goto illegal_insn;
4584 }
4585 }
4586 break;
4587#endif
4588 default:
4589 goto illegal_insn;
4590 }
cf495bcf 4591 }
0f8a249a
BS		 4592 break;
4593 }
4594 break;
4595 case 3: /* load/store instructions */
4596 {
4597 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4598 /* ??? gen_address_mask prevents us from using a source
4599 register directly. Always generate a temporary. */
4600 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4601
5e6ed439
RH		 4602 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4603 if (xop == 0x3c || xop == 0x3e) {
4604 /* V9 casa/casxa : no offset */
71817e48 4605 } else if (IS_IMM) { /* immediate */
67526b20 4606 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4607 if (simm != 0) {
4608 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4609 }
0f8a249a
BS		 4610 } else { /* register */
4611 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4612 if (rs2 != 0) {
5e6ed439 4613 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4614 }
0f8a249a 4615 }
2f2ecb83
BS		 4616 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4617 (xop > 0x17 && xop <= 0x1d ) ||
4618 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4619 TCGv cpu_val = gen_dest_gpr(dc, rd);
4620
0f8a249a 4621 switch (xop) {
b89e94af 4622 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4623 gen_address_mask(dc, cpu_addr);
6ae20372 4624 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4625 break;
b89e94af 4626 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4627 gen_address_mask(dc, cpu_addr);
6ae20372 4628 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4629 break;
b89e94af 4630 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4631 gen_address_mask(dc, cpu_addr);
6ae20372 4632 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4633 break;
b89e94af 4634 case 0x3: /* ldd, load double word */
0f8a249a 4635 if (rd & 1)
d4218d99 4636 goto illegal_insn;
1a2fb1c0 4637 else {
a7812ae4 4638 TCGv_i32 r_const;
abcc7191 4639 TCGv_i64 t64;
2ea815ca 4640
66442b07 4641 save_state(dc);
2ea815ca 4642 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4643 /* XXX remove alignment check */
4644 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4645 tcg_temp_free_i32(r_const);
2cade6a3 4646 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4647 t64 = tcg_temp_new_i64();
4648 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4649 tcg_gen_trunc_i64_tl(cpu_val, t64);
4650 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4651 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4652 tcg_gen_shri_i64(t64, t64, 32);
4653 tcg_gen_trunc_i64_tl(cpu_val, t64);
4654 tcg_temp_free_i64(t64);
de9e9d9f 4655 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4656 }
0f8a249a 4657 break;
b89e94af 4658 case 0x9: /* ldsb, load signed byte */
2cade6a3 4659 gen_address_mask(dc, cpu_addr);
6ae20372 4660 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4661 break;
b89e94af 4662 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4663 gen_address_mask(dc, cpu_addr);
6ae20372 4664 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4665 break;
4666 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4667 {
4668 TCGv r_const;
4669
2cade6a3 4670 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4671 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4672 r_const = tcg_const_tl(0xff);
4673 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4674 tcg_temp_free(r_const);
4675 }
0f8a249a 4676 break;
de9e9d9f
RH		 4677 case 0x0f:
4678 /* swap, swap register with memory. Also atomically */
4679 {
4680 TCGv t0 = get_temp_tl(dc);
4681 CHECK_IU_FEATURE(dc, SWAP);
4682 cpu_src1 = gen_load_gpr(dc, rd);
4683 gen_address_mask(dc, cpu_addr);
4684 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4685 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4686 tcg_gen_mov_tl(cpu_val, t0);
4687 }
0f8a249a 4688 break;
3475187d 4689#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4690 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4691#ifndef TARGET_SPARC64
0f8a249a
BS		 4692 if (IS_IMM)
4693 goto illegal_insn;
4694 if (!supervisor(dc))
4695 goto priv_insn;
6ea4a6c8 4696#endif
66442b07 4697 save_state(dc);
6ae20372 4698 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4699 break;
b89e94af 4700 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4701#ifndef TARGET_SPARC64
0f8a249a
BS		 4702 if (IS_IMM)
4703 goto illegal_insn;
4704 if (!supervisor(dc))
4705 goto priv_insn;
4706#endif
66442b07 4707 save_state(dc);
6ae20372 4708 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4709 break;
b89e94af 4710 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4711#ifndef TARGET_SPARC64
0f8a249a
BS		 4712 if (IS_IMM)
4713 goto illegal_insn;
4714 if (!supervisor(dc))
4715 goto priv_insn;
3475187d 4716#endif
66442b07 4717 save_state(dc);
6ae20372 4718 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4719 break;
b89e94af 4720 case 0x13: /* ldda, load double word alternate */
3475187d 4721#ifndef TARGET_SPARC64
0f8a249a
BS		 4722 if (IS_IMM)
4723 goto illegal_insn;
4724 if (!supervisor(dc))
4725 goto priv_insn;
3475187d 4726#endif
0f8a249a 4727 if (rd & 1)
d4218d99 4728 goto illegal_insn;
66442b07 4729 save_state(dc);
c7785e16 4730 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4731 goto skip_move;
b89e94af 4732 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4733#ifndef TARGET_SPARC64
0f8a249a
BS		 4734 if (IS_IMM)
4735 goto illegal_insn;
4736 if (!supervisor(dc))
4737 goto priv_insn;
4738#endif
66442b07 4739 save_state(dc);
6ae20372 4740 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4741 break;
b89e94af 4742 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4743#ifndef TARGET_SPARC64
0f8a249a
BS		 4744 if (IS_IMM)
4745 goto illegal_insn;
4746 if (!supervisor(dc))
4747 goto priv_insn;
3475187d 4748#endif
66442b07 4749 save_state(dc);
6ae20372 4750 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4751 break;
4752 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4753#ifndef TARGET_SPARC64
0f8a249a
BS		 4754 if (IS_IMM)
4755 goto illegal_insn;
4756 if (!supervisor(dc))
4757 goto priv_insn;
4758#endif
66442b07 4759 save_state(dc);
6ae20372 4760 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4761 break;
b89e94af 4762 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4763 atomically */
64a88d5d 4764 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4765#ifndef TARGET_SPARC64
0f8a249a
BS		 4766 if (IS_IMM)
4767 goto illegal_insn;
4768 if (!supervisor(dc))
4769 goto priv_insn;
6ea4a6c8 4770#endif
66442b07 4771 save_state(dc);
06828032
RH		 4772 cpu_src1 = gen_load_gpr(dc, rd);
4773 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4774 break;
3475187d
FB		 4775
4776#ifndef TARGET_SPARC64
0f8a249a
BS		 4777 case 0x30: /* ldc */
4778 case 0x31: /* ldcsr */
4779 case 0x33: /* lddc */
4780 goto ncp_insn;
3475187d
FB		 4781#endif
4782#endif
4783#ifdef TARGET_SPARC64
0f8a249a 4784 case 0x08: /* V9 ldsw */
2cade6a3 4785 gen_address_mask(dc, cpu_addr);
6ae20372 4786 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4787 break;
4788 case 0x0b: /* V9 ldx */
2cade6a3 4789 gen_address_mask(dc, cpu_addr);
6ae20372 4790 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4791 break;
4792 case 0x18: /* V9 ldswa */
66442b07 4793 save_state(dc);
6ae20372 4794 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4795 break;
4796 case 0x1b: /* V9 ldxa */
66442b07 4797 save_state(dc);
6ae20372 4798 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4799 break;
4800 case 0x2d: /* V9 prefetch, no effect */
4801 goto skip_move;
4802 case 0x30: /* V9 ldfa */
5b12f1e8 4803 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4804 goto jmp_insn;
4805 }
66442b07 4806 save_state(dc);
6ae20372 4807 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4808 gen_update_fprs_dirty(rd);
81ad8ba2 4809 goto skip_move;
0f8a249a 4810 case 0x33: /* V9 lddfa */
5b12f1e8 4811 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4812 goto jmp_insn;
4813 }
66442b07 4814 save_state(dc);
6ae20372 4815 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4816 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4817 goto skip_move;
0f8a249a
BS		 4818 case 0x3d: /* V9 prefetcha, no effect */
4819 goto skip_move;
4820 case 0x32: /* V9 ldqfa */
64a88d5d 4821 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4822 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4823 goto jmp_insn;
4824 }
66442b07 4825 save_state(dc);
6ae20372 4826 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4827 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4828 goto skip_move;
0f8a249a
BS		 4829#endif
4830 default:
4831 goto illegal_insn;
4832 }
97ea2859 4833 gen_store_gpr(dc, rd, cpu_val);
db166940 4834#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4835 skip_move: ;
3475187d 4836#endif
0f8a249a 4837 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4838 TCGv t0;
4839
5b12f1e8 4840 if (gen_trap_ifnofpu(dc)) {
a80dde08 4841 goto jmp_insn;
5b12f1e8 4842 }
66442b07 4843 save_state(dc);
0f8a249a 4844 switch (xop) {
b89e94af 4845 case 0x20: /* ldf, load fpreg */
2cade6a3 4846 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4847 t0 = get_temp_tl(dc);
4848 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4849 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4850 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4851 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4852 break;
3a3b925d
BS		 4853 case 0x21: /* ldfsr, V9 ldxfsr */
4854#ifdef TARGET_SPARC64
2cade6a3 4855 gen_address_mask(dc, cpu_addr);
3a3b925d 4856 if (rd == 1) {
abcc7191
RH		 4857 TCGv_i64 t64 = tcg_temp_new_i64();
4858 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4859 gen_helper_ldxfsr(cpu_env, t64);
4860 tcg_temp_free_i64(t64);
f8641947 4861 break;
fe987e23 4862 }
f8641947 4863#endif
de9e9d9f
RH		 4864 cpu_dst_32 = get_temp_i32(dc);
4865 t0 = get_temp_tl(dc);
4866 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4867 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4868 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4869 break;
b89e94af 4870 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4871 {
a7812ae4 4872 TCGv_i32 r_const;
2ea815ca
BS		 4873
4874 CHECK_FPU_FEATURE(dc, FLOAT128);
4875 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4876 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4877 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4878 tcg_temp_free_i32(r_const);
2ea815ca 4879 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4880 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4881 }
1f587329 4882 break;
b89e94af 4883 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4884 gen_address_mask(dc, cpu_addr);
3886b8a3 4885 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4886 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4887 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4888 break;
4889 default:
4890 goto illegal_insn;
4891 }
dc1a6971 4892 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4893 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4894 TCGv cpu_val = gen_load_gpr(dc, rd);
4895
0f8a249a 4896 switch (xop) {
b89e94af 4897 case 0x4: /* st, store word */
2cade6a3 4898 gen_address_mask(dc, cpu_addr);
6ae20372 4899 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4900 break;
b89e94af 4901 case 0x5: /* stb, store byte */
2cade6a3 4902 gen_address_mask(dc, cpu_addr);
6ae20372 4903 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4904 break;
b89e94af 4905 case 0x6: /* sth, store halfword */
2cade6a3 4906 gen_address_mask(dc, cpu_addr);
6ae20372 4907 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4908 break;
b89e94af 4909 case 0x7: /* std, store double word */
0f8a249a 4910 if (rd & 1)
d4218d99 4911 goto illegal_insn;
1a2fb1c0 4912 else {
a7812ae4 4913 TCGv_i32 r_const;
abcc7191 4914 TCGv_i64 t64;
81634eea 4915 TCGv lo;
1a2fb1c0 4916
66442b07 4917 save_state(dc);
2cade6a3 4918 gen_address_mask(dc, cpu_addr);
2ea815ca 4919 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4920 /* XXX remove alignment check */
4921 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4922 tcg_temp_free_i32(r_const);
81634eea 4923 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4924
4925 t64 = tcg_temp_new_i64();
4926 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4927 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4928 tcg_temp_free_i64(t64);
7fa76c0b 4929 }
0f8a249a 4930 break;
3475187d 4931#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4932 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4933#ifndef TARGET_SPARC64
0f8a249a
BS		 4934 if (IS_IMM)
4935 goto illegal_insn;
4936 if (!supervisor(dc))
4937 goto priv_insn;
6ea4a6c8 4938#endif
66442b07 4939 save_state(dc);
6ae20372 4940 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4941 dc->npc = DYNAMIC_PC;
d39c0b99 4942 break;
b89e94af 4943 case 0x15: /* stba, store byte alternate */
3475187d 4944#ifndef TARGET_SPARC64
0f8a249a
BS		 4945 if (IS_IMM)
4946 goto illegal_insn;
4947 if (!supervisor(dc))
4948 goto priv_insn;
3475187d 4949#endif
66442b07 4950 save_state(dc);
6ae20372 4951 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4952 dc->npc = DYNAMIC_PC;
d39c0b99 4953 break;
b89e94af 4954 case 0x16: /* stha, store halfword alternate */
3475187d 4955#ifndef TARGET_SPARC64
0f8a249a
BS		 4956 if (IS_IMM)
4957 goto illegal_insn;
4958 if (!supervisor(dc))
4959 goto priv_insn;
6ea4a6c8 4960#endif
66442b07 4961 save_state(dc);
6ae20372 4962 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4963 dc->npc = DYNAMIC_PC;
d39c0b99 4964 break;
b89e94af 4965 case 0x17: /* stda, store double word alternate */
3475187d 4966#ifndef TARGET_SPARC64
0f8a249a
BS		 4967 if (IS_IMM)
4968 goto illegal_insn;
4969 if (!supervisor(dc))
4970 goto priv_insn;
3475187d 4971#endif
0f8a249a 4972 if (rd & 1)
d4218d99 4973 goto illegal_insn;
1a2fb1c0 4974 else {
66442b07 4975 save_state(dc);
c7785e16 4976 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4977 }
d39c0b99 4978 break;
e80cfcfc 4979#endif
3475187d 4980#ifdef TARGET_SPARC64
0f8a249a 4981 case 0x0e: /* V9 stx */
2cade6a3 4982 gen_address_mask(dc, cpu_addr);
6ae20372 4983 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4984 break;
4985 case 0x1e: /* V9 stxa */
66442b07 4986 save_state(dc);
6ae20372 4987 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4988 dc->npc = DYNAMIC_PC;
0f8a249a 4989 break;
3475187d 4990#endif
0f8a249a
BS		 4991 default:
4992 goto illegal_insn;
4993 }
4994 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4995 if (gen_trap_ifnofpu(dc)) {
a80dde08 4996 goto jmp_insn;
5b12f1e8 4997 }
66442b07 4998 save_state(dc);
0f8a249a 4999 switch (xop) {
b89e94af 5000 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 5001 {
5002 TCGv t = get_temp_tl(dc);
5003 gen_address_mask(dc, cpu_addr);
5004 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5005 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5006 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5007 }
0f8a249a
BS		 5008 break;
5009 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5010 {
5011 TCGv t = get_temp_tl(dc);
5012
5013 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5014#ifdef TARGET_SPARC64
f8641947
RH		 5015 gen_address_mask(dc, cpu_addr);
5016 if (rd == 1) {
5017 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5018 break;
5019 }
3a3b925d 5020#endif
f8641947
RH		 5021 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5022 }
0f8a249a 5023 break;
1f587329
BS		 5024 case 0x26:
5025#ifdef TARGET_SPARC64
1f587329 5026 /* V9 stqf, store quad fpreg */
2ea815ca 5027 {
a7812ae4 5028 TCGv_i32 r_const;
2ea815ca
BS		 5029
5030 CHECK_FPU_FEATURE(dc, FLOAT128);
5031 gen_op_load_fpr_QT0(QFPREG(rd));
5032 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5033 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5034 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5035 tcg_temp_free_i32(r_const);
2ea815ca 5036 }
1f587329 5037 break;
1f587329
BS		 5038#else /* !TARGET_SPARC64 */
5039 /* stdfq, store floating point queue */
5040#if defined(CONFIG_USER_ONLY)
5041 goto illegal_insn;
5042#else
0f8a249a
BS		 5043 if (!supervisor(dc))
5044 goto priv_insn;
5b12f1e8 5045 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5046 goto jmp_insn;
5b12f1e8 5047 }
0f8a249a 5048 goto nfq_insn;
1f587329 5049#endif
0f8a249a 5050#endif
b89e94af 5051 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5052 gen_address_mask(dc, cpu_addr);
5053 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5054 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5055 break;
5056 default:
5057 goto illegal_insn;
5058 }
5059 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5060 save_state(dc);
0f8a249a 5061 switch (xop) {
a4d17f19 5062#ifdef TARGET_SPARC64
0f8a249a 5063 case 0x34: /* V9 stfa */
5b12f1e8 5064 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5065 goto jmp_insn;
5066 }
6ae20372 5067 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5068 break;
1f587329 5069 case 0x36: /* V9 stqfa */
2ea815ca 5070 {
a7812ae4 5071 TCGv_i32 r_const;
2ea815ca
BS		 5072
5073 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5074 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5075 goto jmp_insn;
5076 }
2ea815ca 5077 r_const = tcg_const_i32(7);
fe8d8f0f 5078 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5079 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5080 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5081 }
1f587329 5082 break;
0f8a249a 5083 case 0x37: /* V9 stdfa */
5b12f1e8 5084 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5085 goto jmp_insn;
5086 }
6ae20372 5087 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5088 break;
0f8a249a 5089 case 0x3e: /* V9 casxa */
a4273524
RH		 5090 rs2 = GET_FIELD(insn, 27, 31);
5091 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5092 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5093 break;
a4d17f19 5094#else
0f8a249a
BS		 5095 case 0x34: /* stc */
5096 case 0x35: /* stcsr */
5097 case 0x36: /* stdcq */
5098 case 0x37: /* stdc */
5099 goto ncp_insn;
16c358e9
SH		 5100#endif
5101#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5102 case 0x3c: /* V9 or LEON3 casa */
5103#ifndef TARGET_SPARC64
5104 CHECK_IU_FEATURE(dc, CASA);
5105 if (IS_IMM) {
5106 goto illegal_insn;
5107 }
bd4e097a
AZ		 5108 /* LEON3 allows CASA from user space with ASI 0xa */
5109 if ((GET_FIELD(insn, 19, 26) != 0xa) && !supervisor(dc)) {
16c358e9
SH		 5110 goto priv_insn;
5111 }
5112#endif
5113 rs2 = GET_FIELD(insn, 27, 31);
5114 cpu_src2 = gen_load_gpr(dc, rs2);
5115 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5116 break;
0f8a249a
BS		 5117#endif
5118 default:
5119 goto illegal_insn;
5120 }
a4273524 5121 } else {
0f8a249a 5122 goto illegal_insn;
a4273524 5123 }
0f8a249a
BS		 5124 }
5125 break;
cf495bcf
FB		 5126 }
5127 /* default case for non jump instructions */
72cbca10 5128 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5129 dc->pc = DYNAMIC_PC;
5130 gen_op_next_insn();
72cbca10
FB		 5131 } else if (dc->npc == JUMP_PC) {
5132 /* we can do a static jump */
6ae20372 5133 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5134 dc->is_br = 1;
5135 } else {
0f8a249a
BS		 5136 dc->pc = dc->npc;
5137 dc->npc = dc->npc + 4;
cf495bcf 5138 }
e80cfcfc 5139 jmp_insn:
42a8aa83 5140 goto egress;
cf495bcf 5141 illegal_insn:
2ea815ca 5142 {
a7812ae4 5143 TCGv_i32 r_const;
2ea815ca 5144
66442b07 5145 save_state(dc);
2ea815ca 5146 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5147 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5148 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5149 dc->is_br = 1;
5150 }
42a8aa83 5151 goto egress;
64a88d5d 5152 unimp_flush:
2ea815ca 5153 {
a7812ae4 5154 TCGv_i32 r_const;
2ea815ca 5155
66442b07 5156 save_state(dc);
2ea815ca 5157 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5158 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5159 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5160 dc->is_br = 1;
5161 }
42a8aa83 5162 goto egress;
e80cfcfc 5163#if !defined(CONFIG_USER_ONLY)
e8af50a3 5164 priv_insn:
2ea815ca 5165 {
a7812ae4 5166 TCGv_i32 r_const;
2ea815ca 5167
66442b07 5168 save_state(dc);
2ea815ca 5169 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5170 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5171 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5172 dc->is_br = 1;
5173 }
42a8aa83 5174 goto egress;
64a88d5d 5175#endif
e80cfcfc 5176 nfpu_insn:
66442b07 5177 save_state(dc);
e80cfcfc
FB		 5178 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5179 dc->is_br = 1;
42a8aa83 5180 goto egress;
64a88d5d 5181#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5182 nfq_insn:
66442b07 5183 save_state(dc);
9143e598
BS		 5184 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5185 dc->is_br = 1;
42a8aa83 5186 goto egress;
9143e598 5187#endif
fcc72045
BS		 5188#ifndef TARGET_SPARC64
5189 ncp_insn:
2ea815ca
BS		 5190 {
5191 TCGv r_const;
5192
66442b07 5193 save_state(dc);
2ea815ca 5194 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5195 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5196 tcg_temp_free(r_const);
5197 dc->is_br = 1;
5198 }
42a8aa83 5199 goto egress;
fcc72045 5200#endif
42a8aa83 5201 egress:
30038fd8
RH		 5202 if (dc->n_t32 != 0) {
5203 int i;
5204 for (i = dc->n_t32 - 1; i >= 0; --i) {
5205 tcg_temp_free_i32(dc->t32[i]);
5206 }
5207 dc->n_t32 = 0;
5208 }
88023616
RH		 5209 if (dc->n_ttl != 0) {
5210 int i;
5211 for (i = dc->n_ttl - 1; i >= 0; --i) {
5212 tcg_temp_free(dc->ttl[i]);
5213 }
5214 dc->n_ttl = 0;
5215 }
7a3f1944
FB		 5216}
5217
4e5e1215 5218void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5219{
4e5e1215 5220 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5221 CPUState *cs = CPU(cpu);
72cbca10 5222 target_ulong pc_start, last_pc;
cf495bcf 5223 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5224 int num_insns;
5225 int max_insns;
0184e266 5226 unsigned int insn;
cf495bcf
FB		 5227
5228 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5229 dc->tb = tb;
72cbca10 5230 pc_start = tb->pc;
cf495bcf 5231 dc->pc = pc_start;
e80cfcfc 5232 last_pc = dc->pc;
72cbca10 5233 dc->npc = (target_ulong) tb->cs_base;
8393617c 5234 dc->cc_op = CC_OP_DYNAMIC;
97ed5ccd 5235 dc->mem_idx = cpu_mmu_index(env, false);
5578ceab 5236 dc->def = env->def;
f838e2c5
BS		 5237 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5238 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5239 dc->singlestep = (cs->singlestep_enabled || singlestep);
cf495bcf 5240
2e70f6ef
PB		 5241 num_insns = 0;
5242 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5243 if (max_insns == 0) {
2e70f6ef 5244 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5245 }
5246 if (max_insns > TCG_MAX_INSNS) {
5247 max_insns = TCG_MAX_INSNS;
5248 }
5249
cd42d5b2 5250 gen_tb_start(tb);
cf495bcf 5251 do {
a3d5ad76
RH		 5252 if (dc->npc & JUMP_PC) {
5253 assert(dc->jump_pc[1] == dc->pc + 4);
5254 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5255 } else {
5256 tcg_gen_insn_start(dc->pc, dc->npc);
5257 }
959082fc 5258 num_insns++;
522a0d4e 5259 last_pc = dc->pc;
667b8e29 5260
b933066a
RH		 5261 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5262 if (dc->pc != pc_start) {
5263 save_state(dc);
5264 }
5265 gen_helper_debug(cpu_env);
5266 tcg_gen_exit_tb(0);
5267 dc->is_br = 1;
5268 goto exit_gen_loop;
5269 }
5270
959082fc 5271 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5272 gen_io_start();
667b8e29
RH		 5273 }
5274
0184e266 5275 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5276
0184e266 5277 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5278
5279 if (dc->is_br)
5280 break;
5281 /* if the next PC is different, we abort now */
5282 if (dc->pc != (last_pc + 4))
5283 break;
d39c0b99
FB		 5284 /* if we reach a page boundary, we stop generation so that the
5285 PC of a TT_TFAULT exception is always in the right page */
5286 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5287 break;
e80cfcfc
FB		 5288 /* if single step mode, we generate only one instruction and
5289 generate an exception */
060718c1 5290 if (dc->singlestep) {
e80cfcfc
FB		 5291 break;
5292 }
fe700adb 5293 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5294 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5295 num_insns < max_insns);
e80cfcfc
FB		 5296
5297 exit_gen_loop:
b09b2fd3 5298 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5299 gen_io_end();
b09b2fd3 5300 }
72cbca10 5301 if (!dc->is_br) {
5fafdf24 5302 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5303 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5304 /* static PC and NPC: we can use direct chaining */
2f5680ee 5305 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5306 } else {
b09b2fd3 5307 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5308 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5309 }
934da7ee 5310 save_npc(dc);
57fec1fe 5311 tcg_gen_exit_tb(0);
72cbca10
FB		 5312 }
5313 }
806f352d 5314 gen_tb_end(tb, num_insns);
0a7df5da 5315
4e5e1215
RH		 5316 tb->size = last_pc + 4 - pc_start;
5317 tb->icount = num_insns;
5318
7a3f1944 5319#ifdef DEBUG_DISAS
8fec2b8c 5320 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5321 qemu_log("--------------\n");
5322 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5323 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5324 qemu_log("\n");
cf495bcf 5325 }
7a3f1944 5326#endif
7a3f1944
FB		 5327}
5328
c48fcb47 5329void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5330{
f5069b26 5331 unsigned int i;
c48fcb47 5332 static int inited;
f5069b26
BS		 5333 static const char * const gregnames[8] = {
5334 NULL, // g0 not used
5335 "g1",
5336 "g2",
5337 "g3",
5338 "g4",
5339 "g5",
5340 "g6",
5341 "g7",
5342 };
30038fd8
RH		 5343 static const char * const fregnames[32] = {
5344 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5345 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5346 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5347 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5348 };
aaed909a 5349
1a2fb1c0
BS		 5350 /* init various static tables */
5351 if (!inited) {
5352 inited = 1;
5353
a7812ae4
PB		 5354 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5355 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
c5f9864e 5356 offsetof(CPUSPARCState, regwptr),
a7812ae4 5357 "regwptr");
1a2fb1c0 5358#ifdef TARGET_SPARC64
c5f9864e 5359 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
a7812ae4 5360 "xcc");
c5f9864e 5361 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
a7812ae4 5362 "asi");
c5f9864e 5363 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
a7812ae4 5364 "fprs");
c5f9864e 5365 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
255e1fcb 5366 "gsr");
a7812ae4 5367 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5368 offsetof(CPUSPARCState, tick_cmpr),
255e1fcb 5369 "tick_cmpr");
a7812ae4 5370 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5371 offsetof(CPUSPARCState, stick_cmpr),
255e1fcb 5372 "stick_cmpr");
a7812ae4 5373 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5374 offsetof(CPUSPARCState, hstick_cmpr),
255e1fcb 5375 "hstick_cmpr");
c5f9864e 5376 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
255e1fcb 5377 "hintp");
c5f9864e 5378 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
a7812ae4 5379 "htba");
c5f9864e 5380 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
a7812ae4
PB		 5381 "hver");
5382 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5383 offsetof(CPUSPARCState, ssr), "ssr");
a7812ae4 5384 cpu_ver = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5385 offsetof(CPUSPARCState, version), "ver");
a7812ae4 5386 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
c5f9864e 5387 offsetof(CPUSPARCState, softint),
a7812ae4 5388 "softint");
255e1fcb 5389#else
c5f9864e 5390 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
255e1fcb 5391 "wim");
1a2fb1c0 5392#endif
c5f9864e 5393 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
77f193da 5394 "cond");
c5f9864e 5395 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
dc99a3f2 5396 "cc_src");
a7812ae4 5397 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5398 offsetof(CPUSPARCState, cc_src2),
d9bdab86 5399 "cc_src2");
c5f9864e 5400 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
dc99a3f2 5401 "cc_dst");
c5f9864e 5402 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
8393617c 5403 "cc_op");
c5f9864e 5404 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
a7812ae4 5405 "psr");
c5f9864e 5406 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
87e92502 5407 "fsr");
c5f9864e 5408 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
48d5c82b 5409 "pc");
c5f9864e 5410 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
a7812ae4 5411 "npc");
c5f9864e 5412 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
255e1fcb 5413#ifndef CONFIG_USER_ONLY
c5f9864e 5414 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
255e1fcb
BS		 5415 "tbr");
5416#endif
30038fd8 5417 for (i = 1; i < 8; i++) {
a7812ae4 5418 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5419 offsetof(CPUSPARCState, gregs[i]),
f5069b26 5420 gregnames[i]);
30038fd8
RH		 5421 }
5422 for (i = 0; i < TARGET_DPREGS; i++) {
5423 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
c5f9864e 5424 offsetof(CPUSPARCState, fpr[i]),
45c7b743 5425 fregnames[i]);
30038fd8 5426 }
1a2fb1c0 5427 }
658138bc 5428}
d2856f1a 5429
bad729e2
RH		 5430void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5431 target_ulong *data)
d2856f1a 5432{
bad729e2
RH		 5433 target_ulong pc = data[0];
5434 target_ulong npc = data[1];
5435
5436 env->pc = pc;
6c42444f 5437 if (npc == DYNAMIC_PC) {
d2856f1a 5438 /* dynamic NPC: already stored */
6c42444f 5439 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5440 /* jump PC: use 'cond' and the jump targets of the translation */
5441 if (env->cond) {
6c42444f 5442 env->npc = npc & ~3;
d7da2a10 5443 } else {
6c42444f 5444 env->npc = pc + 4;
d7da2a10 5445 }
d2856f1a
AJ		 5446 } else {
5447 env->npc = npc;
5448 }
5449}
Mirror of https://git.qemu.org/git/qemu.git