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2000-04-07 J.T. Conklin <jtc@redback.com>: lynx-nat.c
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
cb7450ea
FCE		 12000-03-21 Frank Ch. Eigler <fche@redhat.com>
2
3 * interp.c (sim_open): Sort & extend dummy memory regions for
4 --board=jmr3904 for eCos.
5
a3027dd7
FCE		 62000-03-02 Frank Ch. Eigler <fche@redhat.com>
7
8 * configure: Regenerated.
9
10Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
11
12 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
13 calls, conditional on the simulator being in verbose mode.
14
dfcd3bfb
JM		 15Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
16
17 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
18 cache don't get ReservedInstruction traps.
19
c2d11a7d
JM		 201999-11-29 Mark Salter <msalter@cygnus.com>
21
22 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
23 to clear status bits in sdisr register. This is how the hardware works.
24
25 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
26 being used by cygmon.
27
4ce44c66
JM		 281999-11-11 Andrew Haley <aph@cygnus.com>
29
30 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
31 instructions.
32
cff3e48b
JM		 33Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
34
35 * mips.igen (MULT): Correct previous mis-applied patch.
36
d4f3574e
SS		 37Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
38
39 * mips.igen (delayslot32): Handle sequence like
40 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
41 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
42 (MULT): Actually pass the third register...
43
441999-09-03 Mark Salter <msalter@cygnus.com>
45
46 * interp.c (sim_open): Added more memory aliases for additional
47 hardware being touched by cygmon on jmr3904 board.
48
49Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
50
51 * configure: Regenerated to track ../common/aclocal.m4 changes.
52
a0b3c4fd
JM		 53Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
54
55 * interp.c (sim_store_register): Handle case where client - GDB -
56 specifies that a 4 byte register is 8 bytes in size.
57 (sim_fetch_register): Ditto.
58
adf40b2e
JM		 591999-07-14 Frank Ch. Eigler <fche@cygnus.com>
60
61 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
62 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
63 (idt_monitor_base): Base address for IDT monitor traps.
64 (pmon_monitor_base): Ditto for PMON.
65 (lsipmon_monitor_base): Ditto for LSI PMON.
66 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
67 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
68 (sim_firmware_command): New function.
69 (mips_option_handler): Call it for OPTION_FIRMWARE.
70 (sim_open): Allocate memory for idt_monitor region. If "--board"
71 option was given, add no monitor by default. Add BREAK hooks only if
72 monitors are also there.
73
43e526b9
JM		 74Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
75
76 * interp.c (sim_monitor): Flush output before reading input.
77
78Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
79
80 * tconfig.in (SIM_HANDLES_LMA): Always define.
81
82Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
83
84 From Mark Salter <msalter@cygnus.com>:
85 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
86 (sim_open): Add setup for BSP board.
87
9846de1b
JM		 88Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
89
90 * mips.igen (MULT, MULTU): Add syntax for two operand version.
91 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
92 them as unimplemented.
93
cd0fc7c3
SS		 941999-05-08 Felix Lee <flee@cygnus.com>
95
96 * configure: Regenerated to track ../common/aclocal.m4 changes.
97
7a292a7a
SS		 981999-04-21 Frank Ch. Eigler <fche@cygnus.com>
99
100 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
101
102Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
103
104 * configure.in: Any mips64vr5*-*-* target should have
105 -DTARGET_ENABLE_FR=1.
106 (default_endian): Any mips64vr*el-*-* target should default to
107 LITTLE_ENDIAN.
108 * configure: Re-generate.
109
1101999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
111
112 * mips.igen (ldl): Extend from _16_, not 32.
113
114Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
115
116 * interp.c (sim_store_register): Force registers written to by GDB
117 into an un-interpreted state.
118
c906108c
SS		 1191999-02-05 Frank Ch. Eigler <fche@cygnus.com>
120
121 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
122 CPU, start periodic background I/O polls.
123 (tx3904sio_poll): New function: periodic I/O poller.
124
1251998-12-30 Frank Ch. Eigler <fche@cygnus.com>
126
127 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
128
129Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
130
131 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
132 case statement.
133
1341998-12-29 Frank Ch. Eigler <fche@cygnus.com>
135
136 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
137 (load_word): Call SIM_CORE_SIGNAL hook on error.
138 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
139 starting. For exception dispatching, pass PC instead of NULL_CIA.
140 (decode_coproc): Use COP0_BADVADDR to store faulting address.
141 * sim-main.h (COP0_BADVADDR): Define.
142 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
143 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
144 (_sim_cpu): Add exc_* fields to store register value snapshots.
145 * mips.igen (*): Replace memory-related SignalException* calls
146 with references to SIM_CORE_SIGNAL hook.
147
148 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
149 fix.
150 * sim-main.c (*): Minor warning cleanups.
151
1521998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
153
154 * m16.igen (DADDIU5): Correct type-o.
155
156Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
157
158 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
159 variables.
160
161Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
162
163 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
164 to include path.
165 (interp.o): Add dependency on itable.h
166 (oengine.c, gencode): Delete remaining references.
167 (BUILT_SRC_FROM_GEN): Clean up.
168
1691998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
170
171 * vr4run.c: New.
172 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
173 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
174 tmp-run-hack) : New.
175 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
176 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
177 Drop the "64" qualifier to get the HACK generator working.
178 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
179 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
180 qualifier to get the hack generator working.
181 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
182 (DSLL): Use do_dsll.
183 (DSLLV): Use do_dsllv.
184 (DSRA): Use do_dsra.
185 (DSRL): Use do_dsrl.
186 (DSRLV): Use do_dsrlv.
187 (BC1): Move *vr4100 to get the HACK generator working.
188 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
189 get the HACK generator working.
190 (MACC) Rename to get the HACK generator working.
191 (DMACC,MACCS,DMACCS): Add the 64.
192
1931998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
194
195 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
196 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
197
1981998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
199
200 * mips/interp.c (DEBUG): Cleanups.
201
2021998-12-10 Frank Ch. Eigler <fche@cygnus.com>
203
204 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
205 (tx3904sio_tickle): fflush after a stdout character output.
206
2071998-12-03 Frank Ch. Eigler <fche@cygnus.com>
208
209 * interp.c (sim_close): Uninstall modules.
210
211Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
212
213 * sim-main.h, interp.c (sim_monitor): Change to global
214 function.
215
216Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
217
218 * configure.in (vr4100): Only include vr4100 instructions in
219 simulator.
220 * configure: Re-generate.
221 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
222
223Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
224
225 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
226 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
227 true alternative.
228
229 * configure.in (sim_default_gen, sim_use_gen): Replace with
230 sim_gen.
231 (--enable-sim-igen): Delete config option. Always using IGEN.
232 * configure: Re-generate.
233
234 * Makefile.in (gencode): Kill, kill, kill.
235 * gencode.c: Ditto.
236
237Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
238
239 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
240 bit mips16 igen simulator.
241 * configure: Re-generate.
242
243 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
244 as part of vr4100 ISA.
245 * vr.igen: Mark all instructions as 64 bit only.
246
247Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
248
249 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
250 Pacify GCC.
251
252Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
253
254 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
255 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
256 * configure: Re-generate.
257
258 * m16.igen (BREAK): Define breakpoint instruction.
259 (JALX32): Mark instruction as mips16 and not r3900.
260 * mips.igen (C.cond.fmt): Fix typo in instruction format.
261
262 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
263
264Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
265
266 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
267 insn as a debug breakpoint.
268
269 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
270 pending.slot_size.
271 (PENDING_SCHED): Clean up trace statement.
272 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
273 (PENDING_FILL): Delay write by only one cycle.
274 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
275
276 * sim-main.c (pending_tick): Clean up trace statements. Add trace
277 of pending writes.
278 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
279 32 & 64.
280 (pending_tick): Move incrementing of index to FOR statement.
281 (pending_tick): Only update PENDING_OUT after a write has occured.
282
283 * configure.in: Add explicit mips-lsi-* target. Use gencode to
284 build simulator.
285 * configure: Re-generate.
286
287 * interp.c (sim_engine_run OLD): Delete explicit call to
288 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
289
290Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
291
292 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
293 interrupt level number to match changed SignalExceptionInterrupt
294 macro.
295
296Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
297
298 * interp.c: #include "itable.h" if WITH_IGEN.
299 (get_insn_name): New function.
300 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
301 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
302
303Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
304
305 * configure: Rebuilt to inhale new common/aclocal.m4.
306
307Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
308
309 * dv-tx3904sio.c: Include sim-assert.h.
310
311Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
312
313 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
314 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
315 Reorganize target-specific sim-hardware checks.
316 * configure: rebuilt.
317 * interp.c (sim_open): For tx39 target boards, set
318 OPERATING_ENVIRONMENT, add tx3904sio devices.
319 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
320 ROM executables. Install dv-sockser into sim-modules list.
321
322 * dv-tx3904irc.c: Compiler warning clean-up.
323 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
324 frequent hw-trace messages.
325
326Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
327
328 * vr.igen (MulAcc): Identify as a vr4100 specific function.
329
330Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
331
332 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
333
334 * vr.igen: New file.
335 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
336 * mips.igen: Define vr4100 model. Include vr.igen.
337Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
338
339 * mips.igen (check_mf_hilo): Correct check.
340
341Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
342
343 * sim-main.h (interrupt_event): Add prototype.
344
345 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
346 register_ptr, register_value.
347 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
348
349 * sim-main.h (tracefh): Make extern.
350
351Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
352
353 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
354 Reduce unnecessarily high timer event frequency.
355 * dv-tx3904cpu.c: Ditto for interrupt event.
356
357Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
358
359 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
360 to allay warnings.
361 (interrupt_event): Made non-static.
362
363 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
364 interchange of configuration values for external vs. internal
365 clock dividers.
366
367Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
368
369 * mips.igen (BREAK): Moved code to here for
370 simulator-reserved break instructions.
371 * gencode.c (build_instruction): Ditto.
372 * interp.c (signal_exception): Code moved from here. Non-
373 reserved instructions now use exception vector, rather
374 than halting sim.
375 * sim-main.h: Moved magic constants to here.
376
377Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
378
379 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
380 register upon non-zero interrupt event level, clear upon zero
381 event value.
382 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
383 by passing zero event value.
384 (*_io_{read,write}_buffer): Endianness fixes.
385 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
386 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
387
388 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
389 serial I/O and timer module at base address 0xFFFF0000.
390
391Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
392
393 * mips.igen (SWC1) : Correct the handling of ReverseEndian
394 and BigEndianCPU.
395
396Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
397
398 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
399 parts.
400 * configure: Update.
401
402Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
403
404 * dv-tx3904tmr.c: New file - implements tx3904 timer.
405 * dv-tx3904{irc,cpu}.c: Mild reformatting.
406 * configure.in: Include tx3904tmr in hw_device list.
407 * configure: Rebuilt.
408 * interp.c (sim_open): Instantiate three timer instances.
409 Fix address typo of tx3904irc instance.
410
411Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
412
413 * interp.c (signal_exception): SystemCall exception now uses
414 the exception vector.
415
416Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
417
418 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
419 to allay warnings.
420
421Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
422
423 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
424
425Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
426
427 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
428
429 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
430 sim-main.h. Declare a struct hw_descriptor instead of struct
431 hw_device_descriptor.
432
433Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
434
435 * mips.igen (do_store_left, do_load_left): Compute nr of left and
436 right bits and then re-align left hand bytes to correct byte
437 lanes. Fix incorrect computation in do_store_left when loading
438 bytes from second word.
439
440Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
441
442 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
443 * interp.c (sim_open): Only create a device tree when HW is
444 enabled.
445
446 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
447 * interp.c (signal_exception): Ditto.
448
449Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
450
451 * gencode.c: Mark BEGEZALL as LIKELY.
452
453Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
454
455 * sim-main.h (ALU32_END): Sign extend 32 bit results.
456 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
457
458Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
459
460 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
461 modules. Recognize TX39 target with "mips*tx39" pattern.
462 * configure: Rebuilt.
463 * sim-main.h (*): Added many macros defining bits in
464 TX39 control registers.
465 (SignalInterrupt): Send actual PC instead of NULL.
466 (SignalNMIReset): New exception type.
467 * interp.c (board): New variable for future use to identify
468 a particular board being simulated.
469 (mips_option_handler,mips_options): Added "--board" option.
470 (interrupt_event): Send actual PC.
471 (sim_open): Make memory layout conditional on board setting.
472 (signal_exception): Initial implementation of hardware interrupt
473 handling. Accept another break instruction variant for simulator
474 exit.
475 (decode_coproc): Implement RFE instruction for TX39.
476 (mips.igen): Decode RFE instruction as such.
477 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
478 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
479 bbegin to implement memory map.
480 * dv-tx3904cpu.c: New file.
481 * dv-tx3904irc.c: New file.
482
483Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
484
485 * mips.igen (check_mt_hilo): Create a separate r3900 version.
486
487Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
488
489 * tx.igen (madd,maddu): Replace calls to check_op_hilo
490 with calls to check_div_hilo.
491
492Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
493
494 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
495 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
496 Add special r3900 version of do_mult_hilo.
497 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
498 with calls to check_mult_hilo.
499 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
500 with calls to check_div_hilo.
501
502Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
503
504 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
505 Document a replacement.
506
507Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
508
509 * interp.c (sim_monitor): Make mon_printf work.
510
511Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
512
513 * sim-main.h (INSN_NAME): New arg `cpu'.
514
515Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
516
517 * configure: Regenerated to track ../common/aclocal.m4 changes.
518
519Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
520
521 * configure: Regenerated to track ../common/aclocal.m4 changes.
522 * config.in: Ditto.
523
524Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
525
526 * acconfig.h: New file.
527 * configure.in: Reverted change of Apr 24; use sinclude again.
528
529Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
530
531 * configure: Regenerated to track ../common/aclocal.m4 changes.
532 * config.in: Ditto.
533
534Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
535
536 * configure.in: Don't call sinclude.
537
538Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
539
540 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
541
542Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
543
544 * mips.igen (ERET): Implement.
545
546 * interp.c (decode_coproc): Return sign-extended EPC.
547
548 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
549
550 * interp.c (signal_exception): Do not ignore Trap.
551 (signal_exception): On TRAP, restart at exception address.
552 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
553 (signal_exception): Update.
554 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
555 so that TRAP instructions are caught.
556
557Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
558
559 * sim-main.h (struct hilo_access, struct hilo_history): Define,
560 contains HI/LO access history.
561 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
562 (HIACCESS, LOACCESS): Delete, replace with
563 (HIHISTORY, LOHISTORY): New macros.
564 (CHECKHILO): Delete all, moved to mips.igen
565
566 * gencode.c (build_instruction): Do not generate checks for
567 correct HI/LO register usage.
568
569 * interp.c (old_engine_run): Delete checks for correct HI/LO
570 register usage.
571
572 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
573 check_mf_cycles): New functions.
574 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
575 do_divu, domultx, do_mult, do_multu): Use.
576
577 * tx.igen ("madd", "maddu"): Use.
578
579Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
580
581 * mips.igen (DSRAV): Use function do_dsrav.
582 (SRAV): Use new function do_srav.
583
584 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
585 (B): Sign extend 11 bit immediate.
586 (EXT-B*): Shift 16 bit immediate left by 1.
587 (ADDIU*): Don't sign extend immediate value.
588
589Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
590
591 * m16run.c (sim_engine_run): Restore CIA after handling an event.
592
593 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
594 functions.
595
596 * mips.igen (delayslot32, nullify_next_insn): New functions.
597 (m16.igen): Always include.
598 (do_*): Add more tracing.
599
600 * m16.igen (delayslot16): Add NIA argument, could be called by a
601 32 bit MIPS16 instruction.
602
603 * interp.c (ifetch16): Move function from here.
604 * sim-main.c (ifetch16): To here.
605
606 * sim-main.c (ifetch16, ifetch32): Update to match current
607 implementations of LH, LW.
608 (signal_exception): Don't print out incorrect hex value of illegal
609 instruction.
610
611Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
612
613 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
614 instruction.
615
616 * m16.igen: Implement MIPS16 instructions.
617
618 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
619 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
620 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
621 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
622 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
623 bodies of corresponding code from 32 bit insn to these. Also used
624 by MIPS16 versions of functions.
625
626 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
627 (IMEM16): Drop NR argument from macro.
628
629Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
630
631 * Makefile.in (SIM_OBJS): Add sim-main.o.
632
633 * sim-main.h (address_translation, load_memory, store_memory,
634 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
635 as INLINE_SIM_MAIN.
636 (pr_addr, pr_uword64): Declare.
637 (sim-main.c): Include when H_REVEALS_MODULE_P.
638
639 * interp.c (address_translation, load_memory, store_memory,
640 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
641 from here.
642 * sim-main.c: To here. Fix compilation problems.
643
644 * configure.in: Enable inlining.
645 * configure: Re-config.
646
647Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
648
649 * configure: Regenerated to track ../common/aclocal.m4 changes.
650
651Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
652
653 * mips.igen: Include tx.igen.
654 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
655 * tx.igen: New file, contains MADD and MADDU.
656
657 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
658 the hardwired constant `7'.
659 (store_memory): Ditto.
660 (LOADDRMASK): Move definition to sim-main.h.
661
662 mips.igen (MTC0): Enable for r3900.
663 (ADDU): Add trace.
664
665 mips.igen (do_load_byte): Delete.
666 (do_load, do_store, do_load_left, do_load_write, do_store_left,
667 do_store_right): New functions.
668 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
669
670 configure.in: Let the tx39 use igen again.
671 configure: Update.
672
673Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
674
675 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
676 not an address sized quantity. Return zero for cache sizes.
677
678Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * mips.igen (r3900): r3900 does not support 64 bit integer
681 operations.
682
683Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
684
685 * configure.in (mipstx39*-*-*): Use gencode simulator rather
686 than igen one.
687 * configure : Rebuild.
688
689Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
690
691 * configure: Regenerated to track ../common/aclocal.m4 changes.
692
693Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
696
697Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
698
699 * configure: Regenerated to track ../common/aclocal.m4 changes.
700 * config.in: Regenerated to track ../common/aclocal.m4 changes.
701
702Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * configure: Regenerated to track ../common/aclocal.m4 changes.
705
706Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
707
708 * interp.c (Max, Min): Comment out functions. Not yet used.
709
710Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
711
712 * configure: Regenerated to track ../common/aclocal.m4 changes.
713
714Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
715
716 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
717 configurable settings for stand-alone simulator.
718
719 * configure.in: Added X11 search, just in case.
720
721 * configure: Regenerated.
722
723Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * interp.c (sim_write, sim_read, load_memory, store_memory):
726 Replace sim_core_*_map with read_map, write_map, exec_map resp.
727
728Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * sim-main.h (GETFCC): Return an unsigned value.
731
732Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
733
734 * mips.igen (DIV): Fix check for -1 / MIN_INT.
735 (DADD): Result destination is RD not RT.
736
737Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
738
739 * sim-main.h (HIACCESS, LOACCESS): Always define.
740
741 * mdmx.igen (Maxi, Mini): Rename Max, Min.
742
743 * interp.c (sim_info): Delete.
744
745Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
746
747 * interp.c (DECLARE_OPTION_HANDLER): Use it.
748 (mips_option_handler): New argument `cpu'.
749 (sim_open): Update call to sim_add_option_table.
750
751Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
752
753 * mips.igen (CxC1): Add tracing.
754
755Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
756
757 * sim-main.h (Max, Min): Declare.
758
759 * interp.c (Max, Min): New functions.
760
761 * mips.igen (BC1): Add tracing.
762
763Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
764
765 * interp.c Added memory map for stack in vr4100
766
767Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
768
769 * interp.c (load_memory): Add missing "break"'s.
770
771Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
772
773 * interp.c (sim_store_register, sim_fetch_register): Pass in
774 length parameter. Return -1.
775
776Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
777
778 * interp.c: Added hardware init hook, fixed warnings.
779
780Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
781
782 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
783
784Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * interp.c (ifetch16): New function.
787
788 * sim-main.h (IMEM32): Rename IMEM.
789 (IMEM16_IMMED): Define.
790 (IMEM16): Define.
791 (DELAY_SLOT): Update.
792
793 * m16run.c (sim_engine_run): New file.
794
795 * m16.igen: All instructions except LB.
796 (LB): Call do_load_byte.
797 * mips.igen (do_load_byte): New function.
798 (LB): Call do_load_byte.
799
800 * mips.igen: Move spec for insn bit size and high bit from here.
801 * Makefile.in (tmp-igen, tmp-m16): To here.
802
803 * m16.dc: New file, decode mips16 instructions.
804
805 * Makefile.in (SIM_NO_ALL): Define.
806 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
807
808Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
809
810 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
811 point unit to 32 bit registers.
812 * configure: Re-generate.
813
814Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
815
816 * configure.in (sim_use_gen): Make IGEN the default simulator
817 generator for generic 32 and 64 bit mips targets.
818 * configure: Re-generate.
819
820Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
821
822 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
823 bitsize.
824
825 * interp.c (sim_fetch_register, sim_store_register): Read/write
826 FGR from correct location.
827 (sim_open): Set size of FGR's according to
828 WITH_TARGET_FLOATING_POINT_BITSIZE.
829
830 * sim-main.h (FGR): Store floating point registers in a separate
831 array.
832
833Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
834
835 * configure: Regenerated to track ../common/aclocal.m4 changes.
836
837Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
838
839 * interp.c (ColdReset): Call PENDING_INVALIDATE.
840
841 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
842
843 * interp.c (pending_tick): New function. Deliver pending writes.
844
845 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
846 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
847 it can handle mixed sized quantites and single bits.
848
849Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
850
851 * interp.c (oengine.h): Do not include when building with IGEN.
852 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
853 (sim_info): Ditto for PROCESSOR_64BIT.
854 (sim_monitor): Replace ut_reg with unsigned_word.
855 (*): Ditto for t_reg.
856 (LOADDRMASK): Define.
857 (sim_open): Remove defunct check that host FP is IEEE compliant,
858 using software to emulate floating point.
859 (value_fpr, ...): Always compile, was conditional on HASFPU.
860
861Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
862
863 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
864 size.
865
866 * interp.c (SD, CPU): Define.
867 (mips_option_handler): Set flags in each CPU.
868 (interrupt_event): Assume CPU 0 is the one being iterrupted.
869 (sim_close): Do not clear STATE, deleted anyway.
870 (sim_write, sim_read): Assume CPU zero's vm should be used for
871 data transfers.
872 (sim_create_inferior): Set the PC for all processors.
873 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
874 argument.
875 (mips16_entry): Pass correct nr of args to store_word, load_word.
876 (ColdReset): Cold reset all cpu's.
877 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
878 (sim_monitor, load_memory, store_memory, signal_exception): Use
879 `CPU' instead of STATE_CPU.
880
881
882 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
883 SD or CPU_.
884
885 * sim-main.h (signal_exception): Add sim_cpu arg.
886 (SignalException*): Pass both SD and CPU to signal_exception.
887 * interp.c (signal_exception): Update.
888
889 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
890 Ditto
891 (sync_operation, prefetch, cache_op, store_memory, load_memory,
892 address_translation): Ditto
893 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
894
895Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * configure: Regenerated to track ../common/aclocal.m4 changes.
898
899Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
900
901 * interp.c (sim_engine_run): Add `nr_cpus' argument.
902
903 * mips.igen (model): Map processor names onto BFD name.
904
905 * sim-main.h (CPU_CIA): Delete.
906 (SET_CIA, GET_CIA): Define
907
908Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
909
910 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
911 regiser.
912
913 * configure.in (default_endian): Configure a big-endian simulator
914 by default.
915 * configure: Re-generate.
916
917Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
918
919 * configure: Regenerated to track ../common/aclocal.m4 changes.
920
921Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
922
923 * interp.c (sim_monitor): Handle Densan monitor outbyte
924 and inbyte functions.
925
9261997-12-29 Felix Lee <flee@cygnus.com>
927
928 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
929
930Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
931
932 * Makefile.in (tmp-igen): Arrange for $zero to always be
933 reset to zero after every instruction.
934
935Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
936
937 * configure: Regenerated to track ../common/aclocal.m4 changes.
938 * config.in: Ditto.
939
940Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
941
942 * mips.igen (MSUB): Fix to work like MADD.
943 * gencode.c (MSUB): Similarly.
944
945Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
946
947 * configure: Regenerated to track ../common/aclocal.m4 changes.
948
949Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
950
951 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
952
953Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
954
955 * sim-main.h (sim-fpu.h): Include.
956
957 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
958 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
959 using host independant sim_fpu module.
960
961Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
962
963 * interp.c (signal_exception): Report internal errors with SIGABRT
964 not SIGQUIT.
965
966 * sim-main.h (C0_CONFIG): New register.
967 (signal.h): No longer include.
968
969 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
970
971Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
972
973 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
974
975Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
976
977 * mips.igen: Tag vr5000 instructions.
978 (ANDI): Was missing mipsIV model, fix assembler syntax.
979 (do_c_cond_fmt): New function.
980 (C.cond.fmt): Handle mips I-III which do not support CC field
981 separatly.
982 (bc1): Handle mips IV which do not have a delaed FCC separatly.
983 (SDR): Mask paddr when BigEndianMem, not the converse as specified
984 in IV3.2 spec.
985 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
986 vr5000 which saves LO in a GPR separatly.
987
988 * configure.in (enable-sim-igen): For vr5000, select vr5000
989 specific instructions.
990 * configure: Re-generate.
991
992Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
993
994 * Makefile.in (SIM_OBJS): Add sim-fpu module.
995
996 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
997 fmt_uninterpreted_64 bit cases to switch. Convert to
998 fmt_formatted,
999
1000 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1001
1002 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1003 as specified in IV3.2 spec.
1004 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1005
1006Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1007
1008 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1009 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1010 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1011 PENDING_FILL versions of instructions. Simplify.
1012 (X): New function.
1013 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1014 instructions.
1015 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1016 a signed value.
1017 (MTHI, MFHI): Disable code checking HI-LO.
1018
1019 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1020 global.
1021 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1022
1023Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1024
1025 * gencode.c (build_mips16_operands): Replace IPC with cia.
1026
1027 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1028 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1029 IPC to `cia'.
1030 (UndefinedResult): Replace function with macro/function
1031 combination.
1032 (sim_engine_run): Don't save PC in IPC.
1033
1034 * sim-main.h (IPC): Delete.
1035
1036
1037 * interp.c (signal_exception, store_word, load_word,
1038 address_translation, load_memory, store_memory, cache_op,
1039 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1040 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1041 current instruction address - cia - argument.
1042 (sim_read, sim_write): Call address_translation directly.
1043 (sim_engine_run): Rename variable vaddr to cia.
1044 (signal_exception): Pass cia to sim_monitor
1045
1046 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1047 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1048 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1049
1050 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1051 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1052 SIM_ASSERT.
1053
1054 * interp.c (signal_exception): Pass restart address to
1055 sim_engine_restart.
1056
1057 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1058 idecode.o): Add dependency.
1059
1060 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1061 Delete definitions
1062 (DELAY_SLOT): Update NIA not PC with branch address.
1063 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1064
1065 * mips.igen: Use CIA not PC in branch calculations.
1066 (illegal): Call SignalException.
1067 (BEQ, ADDIU): Fix assembler.
1068
1069Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * m16.igen (JALX): Was missing.
1072
1073 * configure.in (enable-sim-igen): New configuration option.
1074 * configure: Re-generate.
1075
1076 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1077
1078 * interp.c (load_memory, store_memory): Delete parameter RAW.
1079 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1080 bypassing {load,store}_memory.
1081
1082 * sim-main.h (ByteSwapMem): Delete definition.
1083
1084 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1085
1086 * interp.c (sim_do_command, sim_commands): Delete mips specific
1087 commands. Handled by module sim-options.
1088
1089 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1090 (WITH_MODULO_MEMORY): Define.
1091
1092 * interp.c (sim_info): Delete code printing memory size.
1093
1094 * interp.c (mips_size): Nee sim_size, delete function.
1095 (power2): Delete.
1096 (monitor, monitor_base, monitor_size): Delete global variables.
1097 (sim_open, sim_close): Delete code creating monitor and other
1098 memory regions. Use sim-memopts module, via sim_do_commandf, to
1099 manage memory regions.
1100 (load_memory, store_memory): Use sim-core for memory model.
1101
1102 * interp.c (address_translation): Delete all memory map code
1103 except line forcing 32 bit addresses.
1104
1105Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1106
1107 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1108 trace options.
1109
1110 * interp.c (logfh, logfile): Delete globals.
1111 (sim_open, sim_close): Delete code opening & closing log file.
1112 (mips_option_handler): Delete -l and -n options.
1113 (OPTION mips_options): Ditto.
1114
1115 * interp.c (OPTION mips_options): Rename option trace to dinero.
1116 (mips_option_handler): Update.
1117
1118Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1119
1120 * interp.c (fetch_str): New function.
1121 (sim_monitor): Rewrite using sim_read & sim_write.
1122 (sim_open): Check magic number.
1123 (sim_open): Write monitor vectors into memory using sim_write.
1124 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1125 (sim_read, sim_write): Simplify - transfer data one byte at a
1126 time.
1127 (load_memory, store_memory): Clarify meaning of parameter RAW.
1128
1129 * sim-main.h (isHOST): Defete definition.
1130 (isTARGET): Mark as depreciated.
1131 (address_translation): Delete parameter HOST.
1132
1133 * interp.c (address_translation): Delete parameter HOST.
1134
1135Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1136
1137 * mips.igen:
1138
1139 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1140 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1141
1142Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * mips.igen: Add model filter field to records.
1145
1146Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1149
1150 interp.c (sim_engine_run): Do not compile function sim_engine_run
1151 when WITH_IGEN == 1.
1152
1153 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1154 target architecture.
1155
1156 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1157 igen. Replace with configuration variables sim_igen_flags /
1158 sim_m16_flags.
1159
1160 * m16.igen: New file. Copy mips16 insns here.
1161 * mips.igen: From here.
1162
1163Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1166 to top.
1167 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1168
1169Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1170
1171 * gencode.c (build_instruction): Follow sim_write's lead in using
1172 BigEndianMem instead of !ByteSwapMem.
1173
1174Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 * configure.in (sim_gen): Dependent on target, select type of
1177 generator. Always select old style generator.
1178
1179 configure: Re-generate.
1180
1181 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1182 targets.
1183 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1184 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1185 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1186 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1187 SIM_@sim_gen@_*, set by autoconf.
1188
1189Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1190
1191 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1192
1193 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1194 CURRENT_FLOATING_POINT instead.
1195
1196 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1197 (address_translation): Raise exception InstructionFetch when
1198 translation fails and isINSTRUCTION.
1199
1200 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1201 sim_engine_run): Change type of of vaddr and paddr to
1202 address_word.
1203 (address_translation, prefetch, load_memory, store_memory,
1204 cache_op): Change type of vAddr and pAddr to address_word.
1205
1206 * gencode.c (build_instruction): Change type of vaddr and paddr to
1207 address_word.
1208
1209Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1210
1211 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1212 macro to obtain result of ALU op.
1213
1214Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1215
1216 * interp.c (sim_info): Call profile_print.
1217
1218Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219
1220 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1221
1222 * sim-main.h (WITH_PROFILE): Do not define, defined in
1223 common/sim-config.h. Use sim-profile module.
1224 (simPROFILE): Delete defintion.
1225
1226 * interp.c (PROFILE): Delete definition.
1227 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1228 (sim_close): Delete code writing profile histogram.
1229 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1230 Delete.
1231 (sim_engine_run): Delete code profiling the PC.
1232
1233Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1234
1235 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1236
1237 * interp.c (sim_monitor): Make register pointers of type
1238 unsigned_word*.
1239
1240 * sim-main.h: Make registers of type unsigned_word not
1241 signed_word.
1242
1243Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244
1245 * interp.c (sync_operation): Rename from SyncOperation, make
1246 global, add SD argument.
1247 (prefetch): Rename from Prefetch, make global, add SD argument.
1248 (decode_coproc): Make global.
1249
1250 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1251
1252 * gencode.c (build_instruction): Generate DecodeCoproc not
1253 decode_coproc calls.
1254
1255 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1256 (SizeFGR): Move to sim-main.h
1257 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1258 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1259 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1260 sim-main.h.
1261 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1262 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1263 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1264 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1265 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1266 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1267
1268 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1269 exception.
1270 (sim-alu.h): Include.
1271 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1272 (sim_cia): Typedef to instruction_address.
1273
1274Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1275
1276 * Makefile.in (interp.o): Rename generated file engine.c to
1277 oengine.c.
1278
1279 * interp.c: Update.
1280
1281Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1284
1285Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * gencode.c (build_instruction): For "FPSQRT", output correct
1288 number of arguments to Recip.
1289
1290Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * Makefile.in (interp.o): Depends on sim-main.h
1293
1294 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1295
1296 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1297 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1298 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1299 STATE, DSSTATE): Define
1300 (GPR, FGRIDX, ..): Define.
1301
1302 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1303 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1304 (GPR, FGRIDX, ...): Delete macros.
1305
1306 * interp.c: Update names to match defines from sim-main.h
1307
1308Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1309
1310 * interp.c (sim_monitor): Add SD argument.
1311 (sim_warning): Delete. Replace calls with calls to
1312 sim_io_eprintf.
1313 (sim_error): Delete. Replace calls with sim_io_error.
1314 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1315 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1316 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1317 argument.
1318 (mips_size): Rename from sim_size. Add SD argument.
1319
1320 * interp.c (simulator): Delete global variable.
1321 (callback): Delete global variable.
1322 (mips_option_handler, sim_open, sim_write, sim_read,
1323 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1324 sim_size,sim_monitor): Use sim_io_* not callback->*.
1325 (sim_open): ZALLOC simulator struct.
1326 (PROFILE): Do not define.
1327
1328Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1331 support.h with corresponding code.
1332
1333 * sim-main.h (word64, uword64), support.h: Move definition to
1334 sim-main.h.
1335 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1336
1337 * support.h: Delete
1338 * Makefile.in: Update dependencies
1339 * interp.c: Do not include.
1340
1341Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * interp.c (address_translation, load_memory, store_memory,
1344 cache_op): Rename to from AddressTranslation et.al., make global,
1345 add SD argument
1346
1347 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1348 CacheOp): Define.
1349
1350 * interp.c (SignalException): Rename to signal_exception, make
1351 global.
1352
1353 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1354
1355 * sim-main.h (SignalException, SignalExceptionInterrupt,
1356 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1357 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1358 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1359 Define.
1360
1361 * interp.c, support.h: Use.
1362
1363Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1364
1365 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1366 to value_fpr / store_fpr. Add SD argument.
1367 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1368 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1369
1370 * sim-main.h (ValueFPR, StoreFPR): Define.
1371
1372Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1373
1374 * interp.c (sim_engine_run): Check consistency between configure
1375 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1376 and HASFPU.
1377
1378 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1379 (mips_fpu): Configure WITH_FLOATING_POINT.
1380 (mips_endian): Configure WITH_TARGET_ENDIAN.
1381 * configure: Update.
1382
1383Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1384
1385 * configure: Regenerated to track ../common/aclocal.m4 changes.
1386
1387Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1388
1389 * configure: Regenerated.
1390
1391Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1392
1393 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1394
1395Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * gencode.c (print_igen_insn_models): Assume certain architectures
1398 include all mips* instructions.
1399 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1400 instruction.
1401
1402 * Makefile.in (tmp.igen): Add target. Generate igen input from
1403 gencode file.
1404
1405 * gencode.c (FEATURE_IGEN): Define.
1406 (main): Add --igen option. Generate output in igen format.
1407 (process_instructions): Format output according to igen option.
1408 (print_igen_insn_format): New function.
1409 (print_igen_insn_models): New function.
1410 (process_instructions): Only issue warnings and ignore
1411 instructions when no FEATURE_IGEN.
1412
1413Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1416 MIPS targets.
1417
1418Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1419
1420 * configure: Regenerated to track ../common/aclocal.m4 changes.
1421
1422Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1425 SIM_RESERVED_BITS): Delete, moved to common.
1426 (SIM_EXTRA_CFLAGS): Update.
1427
1428Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * configure.in: Configure non-strict memory alignment.
1431 * configure: Regenerated to track ../common/aclocal.m4 changes.
1432
1433Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * configure: Regenerated to track ../common/aclocal.m4 changes.
1436
1437Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1438
1439 * gencode.c (SDBBP,DERET): Added (3900) insns.
1440 (RFE): Turn on for 3900.
1441 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1442 (dsstate): Made global.
1443 (SUBTARGET_R3900): Added.
1444 (CANCELDELAYSLOT): New.
1445 (SignalException): Ignore SystemCall rather than ignore and
1446 terminate. Add DebugBreakPoint handling.
1447 (decode_coproc): New insns RFE, DERET; and new registers Debug
1448 and DEPC protected by SUBTARGET_R3900.
1449 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1450 bits explicitly.
1451 * Makefile.in,configure.in: Add mips subtarget option.
1452 * configure: Update.
1453
1454Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1455
1456 * gencode.c: Add r3900 (tx39).
1457
1458
1459Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1460
1461 * gencode.c (build_instruction): Don't need to subtract 4 for
1462 JALR, just 2.
1463
1464Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1465
1466 * interp.c: Correct some HASFPU problems.
1467
1468Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * configure: Regenerated to track ../common/aclocal.m4 changes.
1471
1472Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * interp.c (mips_options): Fix samples option short form, should
1475 be `x'.
1476
1477Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1478
1479 * interp.c (sim_info): Enable info code. Was just returning.
1480
1481Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1484 MFC0.
1485
1486Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1489 constants.
1490 (build_instruction): Ditto for LL.
1491
1492Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1493
1494 * configure: Regenerated to track ../common/aclocal.m4 changes.
1495
1496Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497
1498 * configure: Regenerated to track ../common/aclocal.m4 changes.
1499 * config.in: Ditto.
1500
1501Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * interp.c (sim_open): Add call to sim_analyze_program, update
1504 call to sim_config.
1505
1506Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * interp.c (sim_kill): Delete.
1509 (sim_create_inferior): Add ABFD argument. Set PC from same.
1510 (sim_load): Move code initializing trap handlers from here.
1511 (sim_open): To here.
1512 (sim_load): Delete, use sim-hload.c.
1513
1514 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1515
1516Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * configure: Regenerated to track ../common/aclocal.m4 changes.
1519 * config.in: Ditto.
1520
1521Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * interp.c (sim_open): Add ABFD argument.
1524 (sim_load): Move call to sim_config from here.
1525 (sim_open): To here. Check return status.
1526
1527Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1528
1529 * gencode.c (build_instruction): Two arg MADD should
1530 not assign result to $0.
1531
1532Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1533
1534 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1535 * sim/mips/configure.in: Regenerate.
1536
1537Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1538
1539 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1540 signed8, unsigned8 et.al. types.
1541
1542 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1543 hosts when selecting subreg.
1544
1545Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1546
1547 * interp.c (sim_engine_run): Reset the ZERO register to zero
1548 regardless of FEATURE_WARN_ZERO.
1549 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1550
1551Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1554 (SignalException): For BreakPoints ignore any mode bits and just
1555 save the PC.
1556 (SignalException): Always set the CAUSE register.
1557
1558Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1561 exception has been taken.
1562
1563 * interp.c: Implement the ERET and mt/f sr instructions.
1564
1565Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1566
1567 * interp.c (SignalException): Don't bother restarting an
1568 interrupt.
1569
1570Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * interp.c (SignalException): Really take an interrupt.
1573 (interrupt_event): Only deliver interrupts when enabled.
1574
1575Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * interp.c (sim_info): Only print info when verbose.
1578 (sim_info) Use sim_io_printf for output.
1579
1580Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1583 mips architectures.
1584
1585Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * interp.c (sim_do_command): Check for common commands if a
1588 simulator specific command fails.
1589
1590Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1591
1592 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1593 and simBE when DEBUG is defined.
1594
1595Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * interp.c (interrupt_event): New function. Pass exception event
1598 onto exception handler.
1599
1600 * configure.in: Check for stdlib.h.
1601 * configure: Regenerate.
1602
1603 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1604 variable declaration.
1605 (build_instruction): Initialize memval1.
1606 (build_instruction): Add UNUSED attribute to byte, bigend,
1607 reverse.
1608 (build_operands): Ditto.
1609
1610 * interp.c: Fix GCC warnings.
1611 (sim_get_quit_code): Delete.
1612
1613 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1614 * Makefile.in: Ditto.
1615 * configure: Re-generate.
1616
1617 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1618
1619Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * interp.c (mips_option_handler): New function parse argumes using
1622 sim-options.
1623 (myname): Replace with STATE_MY_NAME.
1624 (sim_open): Delete check for host endianness - performed by
1625 sim_config.
1626 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1627 (sim_open): Move much of the initialization from here.
1628 (sim_load): To here. After the image has been loaded and
1629 endianness set.
1630 (sim_open): Move ColdReset from here.
1631 (sim_create_inferior): To here.
1632 (sim_open): Make FP check less dependant on host endianness.
1633
1634 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1635 run.
1636 * interp.c (sim_set_callbacks): Delete.
1637
1638 * interp.c (membank, membank_base, membank_size): Replace with
1639 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1640 (sim_open): Remove call to callback->init. gdb/run do this.
1641
1642 * interp.c: Update
1643
1644 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1645
1646 * interp.c (big_endian_p): Delete, replaced by
1647 current_target_byte_order.
1648
1649Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * interp.c (host_read_long, host_read_word, host_swap_word,
1652 host_swap_long): Delete. Using common sim-endian.
1653 (sim_fetch_register, sim_store_register): Use H2T.
1654 (pipeline_ticks): Delete. Handled by sim-events.
1655 (sim_info): Update.
1656 (sim_engine_run): Update.
1657
1658Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1661 reason from here.
1662 (SignalException): To here. Signal using sim_engine_halt.
1663 (sim_stop_reason): Delete, moved to common.
1664
1665Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1666
1667 * interp.c (sim_open): Add callback argument.
1668 (sim_set_callbacks): Delete SIM_DESC argument.
1669 (sim_size): Ditto.
1670
1671Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672
1673 * Makefile.in (SIM_OBJS): Add common modules.
1674
1675 * interp.c (sim_set_callbacks): Also set SD callback.
1676 (set_endianness, xfer_*, swap_*): Delete.
1677 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1678 Change to functions using sim-endian macros.
1679 (control_c, sim_stop): Delete, use common version.
1680 (simulate): Convert into.
1681 (sim_engine_run): This function.
1682 (sim_resume): Delete.
1683
1684 * interp.c (simulation): New variable - the simulator object.
1685 (sim_kind): Delete global - merged into simulation.
1686 (sim_load): Cleanup. Move PC assignment from here.
1687 (sim_create_inferior): To here.
1688
1689 * sim-main.h: New file.
1690 * interp.c (sim-main.h): Include.
1691
1692Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1693
1694 * configure: Regenerated to track ../common/aclocal.m4 changes.
1695
1696Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1697
1698 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1699
1700Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1701
1702 * gencode.c (build_instruction): DIV instructions: check
1703 for division by zero and integer overflow before using
1704 host's division operation.
1705
1706Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1707
1708 * Makefile.in (SIM_OBJS): Add sim-load.o.
1709 * interp.c: #include bfd.h.
1710 (target_byte_order): Delete.
1711 (sim_kind, myname, big_endian_p): New static locals.
1712 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1713 after argument parsing. Recognize -E arg, set endianness accordingly.
1714 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1715 load file into simulator. Set PC from bfd.
1716 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1717 (set_endianness): Use big_endian_p instead of target_byte_order.
1718
1719Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * interp.c (sim_size): Delete prototype - conflicts with
1722 definition in remote-sim.h. Correct definition.
1723
1724Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1725
1726 * configure: Regenerated to track ../common/aclocal.m4 changes.
1727 * config.in: Ditto.
1728
1729Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1730
1731 * interp.c (sim_open): New arg `kind'.
1732
1733 * configure: Regenerated to track ../common/aclocal.m4 changes.
1734
1735Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1736
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1738
1739Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1740
1741 * interp.c (sim_open): Set optind to 0 before calling getopt.
1742
1743Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1744
1745 * configure: Regenerated to track ../common/aclocal.m4 changes.
1746
1747Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1748
1749 * interp.c : Replace uses of pr_addr with pr_uword64
1750 where the bit length is always 64 independent of SIM_ADDR.
1751 (pr_uword64) : added.
1752
1753Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1754
1755 * configure: Re-generate.
1756
1757Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1758
1759 * configure: Regenerate to track ../common/aclocal.m4 changes.
1760
1761Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1762
1763 * interp.c (sim_open): New SIM_DESC result. Argument is now
1764 in argv form.
1765 (other sim_*): New SIM_DESC argument.
1766
1767Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1768
1769 * interp.c: Fix printing of addresses for non-64-bit targets.
1770 (pr_addr): Add function to print address based on size.
1771
1772Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1773
1774 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1775
1776Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1777
1778 * gencode.c (build_mips16_operands): Correct computation of base
1779 address for extended PC relative instruction.
1780
1781Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1782
1783 * interp.c (mips16_entry): Add support for floating point cases.
1784 (SignalException): Pass floating point cases to mips16_entry.
1785 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1786 registers.
1787 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1788 or fmt_word.
1789 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1790 and then set the state to fmt_uninterpreted.
1791 (COP_SW): Temporarily set the state to fmt_word while calling
1792 ValueFPR.
1793
1794Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1795
1796 * gencode.c (build_instruction): The high order may be set in the
1797 comparison flags at any ISA level, not just ISA 4.
1798
1799Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1800
1801 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1802 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1803 * configure.in: sinclude ../common/aclocal.m4.
1804 * configure: Regenerated.
1805
1806Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1807
1808 * configure: Rebuild after change to aclocal.m4.
1809
1810Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1811
1812 * configure configure.in Makefile.in: Update to new configure
1813 scheme which is more compatible with WinGDB builds.
1814 * configure.in: Improve comment on how to run autoconf.
1815 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1816 * Makefile.in: Use autoconf substitution to install common
1817 makefile fragment.
1818
1819Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1820
1821 * gencode.c (build_instruction): Use BigEndianCPU instead of
1822 ByteSwapMem.
1823
1824Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1825
1826 * interp.c (sim_monitor): Make output to stdout visible in
1827 wingdb's I/O log window.
1828
1829Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1830
1831 * support.h: Undo previous change to SIGTRAP
1832 and SIGQUIT values.
1833
1834Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1835
1836 * interp.c (store_word, load_word): New static functions.
1837 (mips16_entry): New static function.
1838 (SignalException): Look for mips16 entry and exit instructions.
1839 (simulate): Use the correct index when setting fpr_state after
1840 doing a pending move.
1841
1842Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1843
1844 * interp.c: Fix byte-swapping code throughout to work on
1845 both little- and big-endian hosts.
1846
1847Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1848
1849 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1850 with gdb/config/i386/xm-windows.h.
1851
1852Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1853
1854 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1855 that messes up arithmetic shifts.
1856
1857Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1858
1859 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1860 SIGTRAP and SIGQUIT for _WIN32.
1861
1862Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1863
1864 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1865 force a 64 bit multiplication.
1866 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1867 destination register is 0, since that is the default mips16 nop
1868 instruction.
1869
1870Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1871
1872 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1873 (build_endian_shift): Don't check proc64.
1874 (build_instruction): Always set memval to uword64. Cast op2 to
1875 uword64 when shifting it left in memory instructions. Always use
1876 the same code for stores--don't special case proc64.
1877
1878 * gencode.c (build_mips16_operands): Fix base PC value for PC
1879 relative operands.
1880 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1881 jal instruction.
1882 * interp.c (simJALDELAYSLOT): Define.
1883 (JALDELAYSLOT): Define.
1884 (INDELAYSLOT, INJALDELAYSLOT): Define.
1885 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1886
1887Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1888
1889 * interp.c (sim_open): add flush_cache as a PMON routine
1890 (sim_monitor): handle flush_cache by ignoring it
1891
1892Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1893
1894 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1895 BigEndianMem.
1896 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1897 (BigEndianMem): Rename to ByteSwapMem and change sense.
1898 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1899 BigEndianMem references to !ByteSwapMem.
1900 (set_endianness): New function, with prototype.
1901 (sim_open): Call set_endianness.
1902 (sim_info): Use simBE instead of BigEndianMem.
1903 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1904 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1905 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1906 ifdefs, keeping the prototype declaration.
1907 (swap_word): Rewrite correctly.
1908 (ColdReset): Delete references to CONFIG. Delete endianness related
1909 code; moved to set_endianness.
1910
1911Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1912
1913 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1914 * interp.c (CHECKHILO): Define away.
1915 (simSIGINT): New macro.
1916 (membank_size): Increase from 1MB to 2MB.
1917 (control_c): New function.
1918 (sim_resume): Rename parameter signal to signal_number. Add local
1919 variable prev. Call signal before and after simulate.
1920 (sim_stop_reason): Add simSIGINT support.
1921 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1922 functions always.
1923 (sim_warning): Delete call to SignalException. Do call printf_filtered
1924 if logfh is NULL.
1925 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1926 a call to sim_warning.
1927
1928Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1929
1930 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1931 16 bit instructions.
1932
1933Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1934
1935 Add support for mips16 (16 bit MIPS implementation):
1936 * gencode.c (inst_type): Add mips16 instruction encoding types.
1937 (GETDATASIZEINSN): Define.
1938 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1939 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1940 mtlo.
1941 (MIPS16_DECODE): New table, for mips16 instructions.
1942 (bitmap_val): New static function.
1943 (struct mips16_op): Define.
1944 (mips16_op_table): New table, for mips16 operands.
1945 (build_mips16_operands): New static function.
1946 (process_instructions): If PC is odd, decode a mips16
1947 instruction. Break out instruction handling into new
1948 build_instruction function.
1949 (build_instruction): New static function, broken out of
1950 process_instructions. Check modifiers rather than flags for SHIFT
1951 bit count and m[ft]{hi,lo} direction.
1952 (usage): Pass program name to fprintf.
1953 (main): Remove unused variable this_option_optind. Change
1954 ``*loptarg++'' to ``loptarg++''.
1955 (my_strtoul): Parenthesize && within ||.
1956 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1957 (simulate): If PC is odd, fetch a 16 bit instruction, and
1958 increment PC by 2 rather than 4.
1959 * configure.in: Add case for mips16*-*-*.
1960 * configure: Rebuild.
1961
1962Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1963
1964 * interp.c: Allow -t to enable tracing in standalone simulator.
1965 Fix garbage output in trace file and error messages.
1966
1967Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1968
1969 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1970 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1971 * configure.in: Simplify using macros in ../common/aclocal.m4.
1972 * configure: Regenerated.
1973 * tconfig.in: New file.
1974
1975Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1976
1977 * interp.c: Fix bugs in 64-bit port.
1978 Use ansi function declarations for msvc compiler.
1979 Initialize and test file pointer in trace code.
1980 Prevent duplicate definition of LAST_EMED_REGNUM.
1981
1982Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1983
1984 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1985
1986Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1987
1988 * interp.c (SignalException): Check for explicit terminating
1989 breakpoint value.
1990 * gencode.c: Pass instruction value through SignalException()
1991 calls for Trap, Breakpoint and Syscall.
1992
1993Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1994
1995 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1996 only used on those hosts that provide it.
1997 * configure.in: Add sqrt() to list of functions to be checked for.
1998 * config.in: Re-generated.
1999 * configure: Re-generated.
2000
2001Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2002
2003 * gencode.c (process_instructions): Call build_endian_shift when
2004 expanding STORE RIGHT, to fix swr.
2005 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2006 clear the high bits.
2007 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2008 Fix float to int conversions to produce signed values.
2009
2010Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2011
2012 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2013 (process_instructions): Correct handling of nor instruction.
2014 Correct shift count for 32 bit shift instructions. Correct sign
2015 extension for arithmetic shifts to not shift the number of bits in
2016 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2017 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2018 Fix madd.
2019 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2020 It's OK to have a mult follow a mult. What's not OK is to have a
2021 mult follow an mfhi.
2022 (Convert): Comment out incorrect rounding code.
2023
2024Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2025
2026 * interp.c (sim_monitor): Improved monitor printf
2027 simulation. Tidied up simulator warnings, and added "--log" option
2028 for directing warning message output.
2029 * gencode.c: Use sim_warning() rather than WARNING macro.
2030
2031Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2032
2033 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2034 getopt1.o, rather than on gencode.c. Link objects together.
2035 Don't link against -liberty.
2036 (gencode.o, getopt.o, getopt1.o): New targets.
2037 * gencode.c: Include <ctype.h> and "ansidecl.h".
2038 (AND): Undefine after including "ansidecl.h".
2039 (ULONG_MAX): Define if not defined.
2040 (OP_*): Don't define macros; now defined in opcode/mips.h.
2041 (main): Call my_strtoul rather than strtoul.
2042 (my_strtoul): New static function.
2043
2044Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2045
2046 * gencode.c (process_instructions): Generate word64 and uword64
2047 instead of `long long' and `unsigned long long' data types.
2048 * interp.c: #include sysdep.h to get signals, and define default
2049 for SIGBUS.
2050 * (Convert): Work around for Visual-C++ compiler bug with type
2051 conversion.
2052 * support.h: Make things compile under Visual-C++ by using
2053 __int64 instead of `long long'. Change many refs to long long
2054 into word64/uword64 typedefs.
2055
2056Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2057
2058 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2059 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2060 (docdir): Removed.
2061 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2062 (AC_PROG_INSTALL): Added.
2063 (AC_PROG_CC): Moved to before configure.host call.
2064 * configure: Rebuilt.
2065
2066Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2067
2068 * configure.in: Define @SIMCONF@ depending on mips target.
2069 * configure: Rebuild.
2070 * Makefile.in (run): Add @SIMCONF@ to control simulator
2071 construction.
2072 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2073 * interp.c: Remove some debugging, provide more detailed error
2074 messages, update memory accesses to use LOADDRMASK.
2075
2076Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2077
2078 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2079 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2080 stamp-h.
2081 * configure: Rebuild.
2082 * config.in: New file, generated by autoheader.
2083 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2084 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2085 HAVE_ANINT and HAVE_AINT, as appropriate.
2086 * Makefile.in (run): Use @LIBS@ rather than -lm.
2087 (interp.o): Depend upon config.h.
2088 (Makefile): Just rebuild Makefile.
2089 (clean): Remove stamp-h.
2090 (mostlyclean): Make the same as clean, not as distclean.
2091 (config.h, stamp-h): New targets.
2092
2093Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2094
2095 * interp.c (ColdReset): Fix boolean test. Make all simulator
2096 globals static.
2097
2098Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2099
2100 * interp.c (xfer_direct_word, xfer_direct_long,
2101 swap_direct_word, swap_direct_long, xfer_big_word,
2102 xfer_big_long, xfer_little_word, xfer_little_long,
2103 swap_word,swap_long): Added.
2104 * interp.c (ColdReset): Provide function indirection to
2105 host<->simulated_target transfer routines.
2106 * interp.c (sim_store_register, sim_fetch_register): Updated to
2107 make use of indirected transfer routines.
2108
2109Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2110
2111 * gencode.c (process_instructions): Ensure FP ABS instruction
2112 recognised.
2113 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2114 system call support.
2115
2116Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2117
2118 * interp.c (sim_do_command): Complain if callback structure not
2119 initialised.
2120
2121Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2122
2123 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2124 support for Sun hosts.
2125 * Makefile.in (gencode): Ensure the host compiler and libraries
2126 used for cross-hosted build.
2127
2128Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2129
2130 * interp.c, gencode.c: Some more (TODO) tidying.
2131
2132Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2133
2134 * gencode.c, interp.c: Replaced explicit long long references with
2135 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2136 * support.h (SET64LO, SET64HI): Macros added.
2137
2138Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2139
2140 * configure: Regenerate with autoconf 2.7.
2141
2142Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2143
2144 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2145 * support.h: Remove superfluous "1" from #if.
2146 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2147
2148Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2149
2150 * interp.c (StoreFPR): Control UndefinedResult() call on
2151 WARN_RESULT manifest.
2152
2153Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2154
2155 * gencode.c: Tidied instruction decoding, and added FP instruction
2156 support.
2157
2158 * interp.c: Added dineroIII, and BSD profiling support. Also
2159 run-time FP handling.
2160
2161Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2162
2163 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2164 gencode.c, interp.c, support.h: created.
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