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hw/sd: sdhci: Limit block size only when SDHC_BLKSIZE register is writable
[thirdparty/qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
598a40b3
PMD		 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf
5 *
d7dfca08
IM		 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
7 * Mitsyanko Igor <i.mitsyanko@samsung.com>
8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
9 *
10 * Based on MMC controller for Samsung S5PC1xx-based board emulation
11 * by Alexey Merkulov and Vladimir Monakhov.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
21 * See the GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 */
26
0430891c 27#include "qemu/osdep.h"
4c8f9735 28#include "qemu/units.h"
6ff37c3d 29#include "qemu/error-report.h"
b635d98c 30#include "qapi/error.h"
64552b6b 31#include "hw/irq.h"
a27bd6c7 32#include "hw/qdev-properties.h"
d7dfca08
IM		 33#include "sysemu/dma.h"
34#include "qemu/timer.h"
d7dfca08 35#include "qemu/bitops.h"
f82a0f44 36#include "hw/sd/sdhci.h"
d6454270 37#include "migration/vmstate.h"
637d23be 38#include "sdhci-internal.h"
03dd024f 39#include "qemu/log.h"
0b8fa32f 40#include "qemu/module.h"
8be487d8 41#include "trace.h"
db1015e9 42#include "qom/object.h"
d7dfca08 43
40bbc194 44#define TYPE_SDHCI_BUS "sdhci-bus"
fa34a3c5
EH		 45/* This is reusing the SDBus typedef from SD_BUS */
46DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS,
47 TYPE_SDHCI_BUS)
40bbc194 48
aa164fbf
PMD		 49#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
50
09b738ff
PMD		 51static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
52{
53 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
54}
55
6ff37c3d
PMD		 56/* return true on error */
57static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
58 uint8_t freq, Error **errp)
59{
4d67852d
PMD		 60 if (s->sd_spec_version >= 3) {
61 return false;
62 }
6ff37c3d
PMD		 63 switch (freq) {
64 case 0:
65 case 10 ... 63:
66 break;
67 default:
68 error_setg(errp, "SD %s clock frequency can have value"
69 "in range 0-63 only", desc);
70 return true;
71 }
72 return false;
73}
74
75static void sdhci_check_capareg(SDHCIState *s, Error **errp)
76{
77 uint64_t msk = s->capareg;
78 uint32_t val;
79 bool y;
80
81 switch (s->sd_spec_version) {
1e23b63f
PMD		 82 case 4:
83 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
84 trace_sdhci_capareg("64-bit system bus (v4)", val);
85 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
86
87 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
88 trace_sdhci_capareg("UHS-II", val);
89 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
90
91 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
92 trace_sdhci_capareg("ADMA3", val);
93 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
94
95 /* fallthrough */
4d67852d
PMD		 96 case 3:
97 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
98 trace_sdhci_capareg("async interrupt", val);
99 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
100
101 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
102 if (val) {
103 error_setg(errp, "slot-type not supported");
104 return;
105 }
106 trace_sdhci_capareg("slot type", val);
107 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
108
109 if (val != 2) {
110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
111 trace_sdhci_capareg("8-bit bus", val);
112 }
113 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
114
115 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
116 trace_sdhci_capareg("bus speed mask", val);
117 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
118
119 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
120 trace_sdhci_capareg("driver strength mask", val);
121 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
122
123 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
124 trace_sdhci_capareg("timer re-tuning", val);
125 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
126
127 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
128 trace_sdhci_capareg("use SDR50 tuning", val);
129 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
130
131 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
132 trace_sdhci_capareg("re-tuning mode", val);
133 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
134
135 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
136 trace_sdhci_capareg("clock multiplier", val);
137 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
138
139 /* fallthrough */
6ff37c3d 140 case 2: /* default version */
0540fba9
PMD		 141 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
142 trace_sdhci_capareg("ADMA2", val);
143 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
144
145 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
146 trace_sdhci_capareg("ADMA1", val);
147 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
148
149 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
1e23b63f 150 trace_sdhci_capareg("64-bit system bus (v3)", val);
0540fba9 151 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
6ff37c3d
PMD		 152
153 /* fallthrough */
154 case 1:
155 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
156 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
157
158 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
159 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
160 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
161 return;
162 }
163 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
164
165 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
166 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
167 if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
168 return;
169 }
170 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
171
172 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
173 if (val >= 3) {
174 error_setg(errp, "block size can be 512, 1024 or 2048 only");
175 return;
176 }
177 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
178 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
179
180 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
181 trace_sdhci_capareg("high speed", val);
182 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
183
184 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
185 trace_sdhci_capareg("SDMA", val);
186 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
187
188 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
189 trace_sdhci_capareg("suspend/resume", val);
190 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
191
192 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
193 trace_sdhci_capareg("3.3v", val);
194 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
195
196 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
197 trace_sdhci_capareg("3.0v", val);
198 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
199
200 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
201 trace_sdhci_capareg("1.8v", val);
202 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
203 break;
204
205 default:
206 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
207 }
208 if (msk) {
209 qemu_log_mask(LOG_UNIMP,
210 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
211 }
212}
213
d7dfca08
IM		 214static uint8_t sdhci_slotint(SDHCIState *s)
215{
216 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
217 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
218 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
219}
220
2bd9ae7e
PMD		 221/* Return true if IRQ was pending and delivered */
222static bool sdhci_update_irq(SDHCIState *s)
d7dfca08 223{
2bd9ae7e
PMD		 224 bool pending = sdhci_slotint(s);
225
226 qemu_set_irq(s->irq, pending);
227
228 return pending;
d7dfca08
IM		 229}
230
231static void sdhci_raise_insertion_irq(void *opaque)
232{
233 SDHCIState *s = (SDHCIState *)opaque;
234
235 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 236 timer_mod(s->insert_timer,
237 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 238 } else {
239 s->prnsts = 0x1ff0000;
240 if (s->norintstsen & SDHC_NISEN_INSERT) {
241 s->norintsts |= SDHC_NIS_INSERT;
242 }
243 sdhci_update_irq(s);
244 }
245}
246
40bbc194 247static void sdhci_set_inserted(DeviceState *dev, bool level)
d7dfca08 248{
40bbc194 249 SDHCIState *s = (SDHCIState *)dev;
d7dfca08 250
8be487d8 251 trace_sdhci_set_inserted(level ? "insert" : "eject");
d7dfca08
IM		 252 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
253 /* Give target some time to notice card ejection */
bc72ad67
AB		 254 timer_mod(s->insert_timer,
255 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 256 } else {
257 if (level) {
258 s->prnsts = 0x1ff0000;
259 if (s->norintstsen & SDHC_NISEN_INSERT) {
260 s->norintsts |= SDHC_NIS_INSERT;
261 }
262 } else {
263 s->prnsts = 0x1fa0000;
264 s->pwrcon &= ~SDHC_POWER_ON;
265 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
266 if (s->norintstsen & SDHC_NISEN_REMOVE) {
267 s->norintsts |= SDHC_NIS_REMOVE;
268 }
269 }
270 sdhci_update_irq(s);
271 }
272}
273
40bbc194 274static void sdhci_set_readonly(DeviceState *dev, bool level)
d7dfca08 275{
40bbc194 276 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 277
278 if (level) {
279 s->prnsts &= ~SDHC_WRITE_PROTECT;
280 } else {
281 /* Write enabled */
282 s->prnsts |= SDHC_WRITE_PROTECT;
283 }
284}
285
286static void sdhci_reset(SDHCIState *s)
287{
40bbc194
PM		 288 DeviceState *dev = DEVICE(s);
289
bc72ad67
AB		 290 timer_del(s->insert_timer);
291 timer_del(s->transfer_timer);
aceb5b06
PMD		 292
293 /* Set all registers to 0. Capabilities/Version registers are not cleared
d7dfca08
IM		 294 * and assumed to always preserve their value, given to them during
295 * initialization */
296 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
297
5c1bc9a2
AB		 298 /* Reset other state based on current card insertion/readonly status */
299 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
300 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
40bbc194 301
d7dfca08
IM		 302 s->data_count = 0;
303 s->stopped_state = sdhc_not_stopped;
0a7ac9f9 304 s->pending_insert_state = false;
d7dfca08
IM		 305}
306
8b41c305
PM		 307static void sdhci_poweron_reset(DeviceState *dev)
308{
309 /* QOM (ie power-on) reset. This is identical to reset
310 * commanded via device register apart from handling of the
311 * 'pending insert on powerup' quirk.
312 */
313 SDHCIState *s = (SDHCIState *)dev;
314
315 sdhci_reset(s);
316
317 if (s->pending_insert_quirk) {
318 s->pending_insert_state = true;
319 }
320}
321
d368ba43 322static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 323
324static void sdhci_send_command(SDHCIState *s)
325{
326 SDRequest request;
327 uint8_t response[16];
328 int rlen;
b263d8f9 329 bool timeout = false;
d7dfca08
IM		 330
331 s->errintsts = 0;
332 s->acmd12errsts = 0;
333 request.cmd = s->cmdreg >> 8;
334 request.arg = s->argument;
8be487d8
PMD		 335
336 trace_sdhci_send_command(request.cmd, request.arg);
40bbc194 337 rlen = sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 338
339 if (s->cmdreg & SDHC_CMD_RESPONSE) {
340 if (rlen == 4) {
b3141c06 341 s->rspreg[0] = ldl_be_p(response);
d7dfca08 342 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
8be487d8 343 trace_sdhci_response4(s->rspreg[0]);
d7dfca08 344 } else if (rlen == 16) {
b3141c06
PMD		 345 s->rspreg[0] = ldl_be_p(&response[11]);
346 s->rspreg[1] = ldl_be_p(&response[7]);
347 s->rspreg[2] = ldl_be_p(&response[3]);
d7dfca08
IM		 348 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
349 response[2];
8be487d8
PMD		 350 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
351 s->rspreg[1], s->rspreg[0]);
d7dfca08 352 } else {
b263d8f9 353 timeout = true;
8be487d8 354 trace_sdhci_error("timeout waiting for command response");
d7dfca08
IM		 355 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
356 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
357 s->norintsts |= SDHC_NIS_ERR;
358 }
359 }
360
fd1e5c81
AS		 361 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
362 (s->norintstsen & SDHC_NISEN_TRSCMP) &&
d7dfca08
IM		 363 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
364 s->norintsts |= SDHC_NIS_TRSCMP;
365 }
d7dfca08
IM		 366 }
367
368 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
369 s->norintsts |= SDHC_NIS_CMDCMP;
370 }
371
372 sdhci_update_irq(s);
373
b263d8f9 374 if (!timeout && s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 375 s->data_count = 0;
d368ba43 376 sdhci_data_transfer(s);
d7dfca08
IM		 377 }
378}
379
380static void sdhci_end_transfer(SDHCIState *s)
381{
382 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
383 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
384 SDRequest request;
385 uint8_t response[16];
386
387 request.cmd = 0x0C;
388 request.arg = 0;
8be487d8 389 trace_sdhci_end_transfer(request.cmd, request.arg);
40bbc194 390 sdbus_do_command(&s->sdbus, &request, response);
d7dfca08 391 /* Auto CMD12 response goes to the upper Response register */
b3141c06 392 s->rspreg[3] = ldl_be_p(response);
d7dfca08
IM		 393 }
394
395 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
396 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
397 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
398
399 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
400 s->norintsts |= SDHC_NIS_TRSCMP;
401 }
402
403 sdhci_update_irq(s);
404}
405
406/*
407 * Programmed i/o data transfer
408 */
d23b6caa 409#define BLOCK_SIZE_MASK (4 * KiB - 1)
d7dfca08
IM		 410
411/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
412static void sdhci_read_block_from_card(SDHCIState *s)
413{
ea55a221 414 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 415
416 if ((s->trnmod & SDHC_TRNS_MULTI) &&
417 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
418 return;
419 }
420
618e0be1
PMD		 421 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
422 /* Device is not in tuning */
423 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size);
ea55a221
PMD		 424 }
425
426 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
08022a91 427 /* Device is in tuning */
ea55a221
PMD		 428 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
429 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
430 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
431 SDHC_DATA_INHIBIT);
432 goto read_done;
d7dfca08
IM		 433 }
434
435 /* New data now available for READ through Buffer Port Register */
436 s->prnsts |= SDHC_DATA_AVAILABLE;
437 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
438 s->norintsts |= SDHC_NIS_RBUFRDY;
439 }
440
441 /* Clear DAT line active status if that was the last block */
442 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
443 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
444 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
445 }
446
447 /* If stop at block gap request was set and it's not the last block of
448 * data - generate Block Event interrupt */
449 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
450 s->blkcnt != 1) {
451 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
452 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
453 s->norintsts |= SDHC_EIS_BLKGAP;
454 }
455 }
456
ea55a221 457read_done:
d7dfca08
IM		 458 sdhci_update_irq(s);
459}
460
461/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
462static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
463{
464 uint32_t value = 0;
465 int i;
466
467 /* first check that a valid data exists in host controller input buffer */
468 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
8be487d8 469 trace_sdhci_error("read from empty buffer");
d7dfca08
IM		 470 return 0;
471 }
472
473 for (i = 0; i < size; i++) {
474 value |= s->fifo_buffer[s->data_count] << i * 8;
475 s->data_count++;
476 /* check if we've read all valid data (blksize bytes) from buffer */
bf8ec38e 477 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 478 trace_sdhci_read_dataport(s->data_count);
d7dfca08
IM		 479 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
480 s->data_count = 0; /* next buff read must start at position [0] */
481
482 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
483 s->blkcnt--;
484 }
485
486 /* if that was the last block of data */
487 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
488 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
489 /* stop at gap request */
490 (s->stopped_state == sdhc_gap_read &&
491 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 492 sdhci_end_transfer(s);
d7dfca08 493 } else { /* if there are more data, read next block from card */
d368ba43 494 sdhci_read_block_from_card(s);
d7dfca08
IM		 495 }
496 break;
497 }
498 }
499
500 return value;
501}
502
503/* Write data from host controller FIFO to card */
504static void sdhci_write_block_to_card(SDHCIState *s)
505{
d7dfca08
IM		 506 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
507 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
508 s->norintsts |= SDHC_NIS_WBUFRDY;
509 }
510 sdhci_update_irq(s);
511 return;
512 }
513
514 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
515 if (s->blkcnt == 0) {
516 return;
517 } else {
518 s->blkcnt--;
519 }
520 }
521
62a21be6 522 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK);
d7dfca08
IM		 523
524 /* Next data can be written through BUFFER DATORT register */
525 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 526
527 /* Finish transfer if that was the last block of data */
528 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
529 ((s->trnmod & SDHC_TRNS_MULTI) &&
530 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 531 sdhci_end_transfer(s);
dcdb4cd8
PC		 532 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
533 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 534 }
535
536 /* Generate Block Gap Event if requested and if not the last block */
537 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
538 s->blkcnt > 0) {
539 s->prnsts &= ~SDHC_DOING_WRITE;
540 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
541 s->norintsts |= SDHC_EIS_BLKGAP;
542 }
d368ba43 543 sdhci_end_transfer(s);
d7dfca08
IM		 544 }
545
546 sdhci_update_irq(s);
547}
548
549/* Write @size bytes of @value data to host controller @s Buffer Data Port
550 * register */
551static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
552{
553 unsigned i;
554
555 /* Check that there is free space left in a buffer */
556 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
8be487d8 557 trace_sdhci_error("Can't write to data buffer: buffer full");
d7dfca08
IM		 558 return;
559 }
560
561 for (i = 0; i < size; i++) {
562 s->fifo_buffer[s->data_count] = value & 0xFF;
563 s->data_count++;
564 value >>= 8;
bf8ec38e 565 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 566 trace_sdhci_write_dataport(s->data_count);
d7dfca08
IM		 567 s->data_count = 0;
568 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
569 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 570 sdhci_write_block_to_card(s);
d7dfca08
IM		 571 }
572 }
573 }
574}
575
576/*
577 * Single DMA data transfer
578 */
579
580/* Multi block SDMA transfer */
581static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
582{
583 bool page_aligned = false;
618e0be1 584 unsigned int begin;
bf8ec38e
PMD		 585 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
586 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
d7dfca08
IM		 587 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
588
6e86d903
PP		 589 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
590 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
591 return;
592 }
593
d7dfca08
IM		 594 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
595 * possible stop at page boundary if initial address is not page aligned,
596 * allow them to work properly */
597 if ((s->sdmasysad % boundary_chk) == 0) {
598 page_aligned = true;
599 }
600
8bc1f1aa 601 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE;
d7dfca08 602 if (s->trnmod & SDHC_TRNS_READ) {
8bc1f1aa 603 s->prnsts |= SDHC_DOING_READ;
d7dfca08
IM		 604 while (s->blkcnt) {
605 if (s->data_count == 0) {
618e0be1 606 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 607 }
608 begin = s->data_count;
609 if (((boundary_count + begin) < block_size) && page_aligned) {
610 s->data_count = boundary_count + begin;
611 boundary_count = 0;
612 } else {
613 s->data_count = block_size;
614 boundary_count -= block_size - begin;
615 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
616 s->blkcnt--;
617 }
618 }
dd55c485 619 dma_memory_write(s->dma_as, s->sdmasysad,
d7dfca08
IM		 620 &s->fifo_buffer[begin], s->data_count - begin);
621 s->sdmasysad += s->data_count - begin;
622 if (s->data_count == block_size) {
623 s->data_count = 0;
624 }
625 if (page_aligned && boundary_count == 0) {
626 break;
627 }
628 }
629 } else {
8bc1f1aa 630 s->prnsts |= SDHC_DOING_WRITE;
d7dfca08
IM		 631 while (s->blkcnt) {
632 begin = s->data_count;
633 if (((boundary_count + begin) < block_size) && page_aligned) {
634 s->data_count = boundary_count + begin;
635 boundary_count = 0;
636 } else {
637 s->data_count = block_size;
638 boundary_count -= block_size - begin;
639 }
dd55c485 640 dma_memory_read(s->dma_as, s->sdmasysad,
42922105 641 &s->fifo_buffer[begin], s->data_count - begin);
d7dfca08
IM		 642 s->sdmasysad += s->data_count - begin;
643 if (s->data_count == block_size) {
62a21be6 644 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 645 s->data_count = 0;
646 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
647 s->blkcnt--;
648 }
649 }
650 if (page_aligned && boundary_count == 0) {
651 break;
652 }
653 }
654 }
655
656 if (s->blkcnt == 0) {
d368ba43 657 sdhci_end_transfer(s);
d7dfca08
IM		 658 } else {
659 if (s->norintstsen & SDHC_NISEN_DMA) {
660 s->norintsts |= SDHC_NIS_DMA;
661 }
662 sdhci_update_irq(s);
663 }
664}
665
666/* single block SDMA transfer */
d7dfca08
IM		 667static void sdhci_sdma_transfer_single_block(SDHCIState *s)
668{
bf8ec38e 669 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 670
671 if (s->trnmod & SDHC_TRNS_READ) {
618e0be1 672 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt);
dd55c485 673 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
d7dfca08 674 } else {
dd55c485 675 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
62a21be6 676 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt);
d7dfca08 677 }
241999bf 678 s->blkcnt--;
d7dfca08 679
d368ba43 680 sdhci_end_transfer(s);
d7dfca08
IM		 681}
682
683typedef struct ADMADescr {
684 hwaddr addr;
685 uint16_t length;
686 uint8_t attr;
687 uint8_t incr;
688} ADMADescr;
689
690static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
691{
692 uint32_t adma1 = 0;
693 uint64_t adma2 = 0;
694 hwaddr entry_addr = (hwaddr)s->admasysaddr;
06c5120b 695 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 696 case SDHC_CTRL_ADMA2_32:
18610bfd 697 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2));
d7dfca08
IM		 698 adma2 = le64_to_cpu(adma2);
699 /* The spec does not specify endianness of descriptor table.
700 * We currently assume that it is LE.
701 */
702 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
703 dscr->length = (uint16_t)extract64(adma2, 16, 16);
704 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
705 dscr->incr = 8;
706 break;
707 case SDHC_CTRL_ADMA1_32:
18610bfd 708 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1));
d7dfca08
IM		 709 adma1 = le32_to_cpu(adma1);
710 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
711 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
712 dscr->incr = 4;
713 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
714 dscr->length = (uint16_t)extract32(adma1, 12, 16);
715 } else {
4c8f9735 716 dscr->length = 4 * KiB;
d7dfca08
IM		 717 }
718 break;
719 case SDHC_CTRL_ADMA2_64:
18610bfd
PMD		 720 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1);
721 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2);
d7dfca08 722 dscr->length = le16_to_cpu(dscr->length);
18610bfd 723 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8);
04654b5a
SPB		 724 dscr->addr = le64_to_cpu(dscr->addr);
725 dscr->attr &= (uint8_t) ~0xC0;
d7dfca08
IM		 726 dscr->incr = 12;
727 break;
728 }
729}
730
731/* Advanced DMA data transfer */
732
733static void sdhci_do_adma(SDHCIState *s)
734{
618e0be1 735 unsigned int begin, length;
bf8ec38e 736 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
8be487d8 737 ADMADescr dscr = {};
d7dfca08
IM		 738 int i;
739
6a9e5cc6
PMD		 740 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) {
741 /* Stop Multiple Transfer */
742 sdhci_end_transfer(s);
743 return;
744 }
745
d7dfca08
IM		 746 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
747 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
748
749 get_adma_description(s, &dscr);
8be487d8 750 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
d7dfca08
IM		 751
752 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
753 /* Indicate that error occurred in ST_FDS state */
754 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
755 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
756
757 /* Generate ADMA error interrupt */
758 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
759 s->errintsts |= SDHC_EIS_ADMAERR;
760 s->norintsts |= SDHC_NIS_ERR;
761 }
762
763 sdhci_update_irq(s);
764 return;
765 }
766
4c8f9735 767 length = dscr.length ? dscr.length : 64 * KiB;
d7dfca08
IM		 768
769 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
770 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
bc6f2899 771 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE;
d7dfca08 772 if (s->trnmod & SDHC_TRNS_READ) {
bc6f2899 773 s->prnsts |= SDHC_DOING_READ;
d7dfca08
IM		 774 while (length) {
775 if (s->data_count == 0) {
618e0be1 776 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 777 }
778 begin = s->data_count;
779 if ((length + begin) < block_size) {
780 s->data_count = length + begin;
781 length = 0;
782 } else {
783 s->data_count = block_size;
784 length -= block_size - begin;
785 }
dd55c485 786 dma_memory_write(s->dma_as, dscr.addr,
d7dfca08
IM		 787 &s->fifo_buffer[begin],
788 s->data_count - begin);
789 dscr.addr += s->data_count - begin;
790 if (s->data_count == block_size) {
791 s->data_count = 0;
792 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
793 s->blkcnt--;
794 if (s->blkcnt == 0) {
795 break;
796 }
797 }
798 }
799 }
800 } else {
bc6f2899 801 s->prnsts |= SDHC_DOING_WRITE;
d7dfca08
IM		 802 while (length) {
803 begin = s->data_count;
804 if ((length + begin) < block_size) {
805 s->data_count = length + begin;
806 length = 0;
807 } else {
808 s->data_count = block_size;
809 length -= block_size - begin;
810 }
dd55c485 811 dma_memory_read(s->dma_as, dscr.addr,
9db11cef
PC		 812 &s->fifo_buffer[begin],
813 s->data_count - begin);
d7dfca08
IM		 814 dscr.addr += s->data_count - begin;
815 if (s->data_count == block_size) {
62a21be6 816 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
d7dfca08
IM		 817 s->data_count = 0;
818 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
819 s->blkcnt--;
820 if (s->blkcnt == 0) {
821 break;
822 }
823 }
824 }
825 }
826 }
827 s->admasysaddr += dscr.incr;
828 break;
829 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
830 s->admasysaddr = dscr.addr;
8be487d8 831 trace_sdhci_adma("link", s->admasysaddr);
d7dfca08
IM		 832 break;
833 default:
834 s->admasysaddr += dscr.incr;
835 break;
836 }
837
1d32c26f 838 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
8be487d8 839 trace_sdhci_adma("interrupt", s->admasysaddr);
1d32c26f
PC		 840 if (s->norintstsen & SDHC_NISEN_DMA) {
841 s->norintsts |= SDHC_NIS_DMA;
842 }
843
9321c1f2
PMD		 844 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) {
845 /* IRQ delivered, reschedule current transfer */
846 break;
847 }
1d32c26f
PC		 848 }
849
d7dfca08
IM		 850 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
851 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
852 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
8be487d8 853 trace_sdhci_adma_transfer_completed();
d7dfca08
IM		 854 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
855 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
856 s->blkcnt != 0)) {
8be487d8 857 trace_sdhci_error("SD/MMC host ADMA length mismatch");
d7dfca08
IM		 858 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
859 SDHC_ADMAERR_STATE_ST_TFR;
860 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
8be487d8 861 trace_sdhci_error("Set ADMA error flag");
d7dfca08
IM		 862 s->errintsts |= SDHC_EIS_ADMAERR;
863 s->norintsts |= SDHC_NIS_ERR;
864 }
865
866 sdhci_update_irq(s);
867 }
d368ba43 868 sdhci_end_transfer(s);
d7dfca08
IM		 869 return;
870 }
871
d7dfca08
IM		 872 }
873
085d8134 874 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 875 timer_mod(s->transfer_timer,
876 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 877}
878
879/* Perform data transfer according to controller configuration */
880
d368ba43 881static void sdhci_data_transfer(void *opaque)
d7dfca08 882{
d368ba43 883 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 884
885 if (s->trnmod & SDHC_TRNS_DMA) {
06c5120b 886 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 887 case SDHC_CTRL_SDMA:
d7dfca08 888 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 889 sdhci_sdma_transfer_single_block(s);
d7dfca08 890 } else {
d368ba43 891 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 892 }
893
894 break;
895 case SDHC_CTRL_ADMA1_32:
0540fba9 896 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
8be487d8 897 trace_sdhci_error("ADMA1 not supported");
d7dfca08
IM		 898 break;
899 }
900
d368ba43 901 sdhci_do_adma(s);
d7dfca08
IM		 902 break;
903 case SDHC_CTRL_ADMA2_32:
0540fba9 904 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
8be487d8 905 trace_sdhci_error("ADMA2 not supported");
d7dfca08
IM		 906 break;
907 }
908
d368ba43 909 sdhci_do_adma(s);
d7dfca08
IM		 910 break;
911 case SDHC_CTRL_ADMA2_64:
0540fba9
PMD		 912 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
913 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
8be487d8 914 trace_sdhci_error("64 bit ADMA not supported");
d7dfca08
IM		 915 break;
916 }
917
d368ba43 918 sdhci_do_adma(s);
d7dfca08
IM		 919 break;
920 default:
8be487d8 921 trace_sdhci_error("Unsupported DMA type");
d7dfca08
IM		 922 break;
923 }
924 } else {
40bbc194 925 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
d7dfca08
IM		 926 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
927 SDHC_DAT_LINE_ACTIVE;
d368ba43 928 sdhci_read_block_from_card(s);
d7dfca08
IM		 929 } else {
930 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
931 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 932 sdhci_write_block_to_card(s);
d7dfca08
IM		 933 }
934 }
935}
936
937static bool sdhci_can_issue_command(SDHCIState *s)
938{
6890a695 939 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
d7dfca08
IM		 940 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
941 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
942 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
943 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
944 return false;
945 }
946
947 return true;
948}
949
950/* The Buffer Data Port register must be accessed in sequential and
951 * continuous manner */
952static inline bool
953sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
954{
955 if ((s->data_count & 0x3) != byte_num) {
8be487d8
PMD		 956 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
957 "is prohibited\n");
d7dfca08
IM		 958 return false;
959 }
960 return true;
961}
962
45e5dc43
PMD		 963static void sdhci_resume_pending_transfer(SDHCIState *s)
964{
965 timer_del(s->transfer_timer);
966 sdhci_data_transfer(s);
967}
968
d368ba43 969static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 970{
d368ba43 971 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 972 uint32_t ret = 0;
973
45e5dc43
PMD		 974 if (timer_pending(s->transfer_timer)) {
975 sdhci_resume_pending_transfer(s);
976 }
977
d7dfca08
IM		 978 switch (offset & ~0x3) {
979 case SDHC_SYSAD:
980 ret = s->sdmasysad;
981 break;
982 case SDHC_BLKSIZE:
983 ret = s->blksize | (s->blkcnt << 16);
984 break;
985 case SDHC_ARGUMENT:
986 ret = s->argument;
987 break;
988 case SDHC_TRNMOD:
989 ret = s->trnmod | (s->cmdreg << 16);
990 break;
991 case SDHC_RSPREG0 ... SDHC_RSPREG3:
992 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
993 break;
994 case SDHC_BDATA:
995 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 996 ret = sdhci_read_dataport(s, size);
8be487d8 997 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 998 return ret;
999 }
1000 break;
1001 case SDHC_PRNSTS:
1002 ret = s->prnsts;
da346922
PMD		 1003 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
1004 sdbus_get_dat_lines(&s->sdbus));
1005 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
1006 sdbus_get_cmd_line(&s->sdbus));
d7dfca08
IM		 1007 break;
1008 case SDHC_HOSTCTL:
06c5120b 1009 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
d7dfca08
IM		 1010 (s->wakcon << 24);
1011 break;
1012 case SDHC_CLKCON:
1013 ret = s->clkcon | (s->timeoutcon << 16);
1014 break;
1015 case SDHC_NORINTSTS:
1016 ret = s->norintsts | (s->errintsts << 16);
1017 break;
1018 case SDHC_NORINTSTSEN:
1019 ret = s->norintstsen | (s->errintstsen << 16);
1020 break;
1021 case SDHC_NORINTSIGEN:
1022 ret = s->norintsigen | (s->errintsigen << 16);
1023 break;
1024 case SDHC_ACMD12ERRSTS:
ea55a221 1025 ret = s->acmd12errsts | (s->hostctl2 << 16);
d7dfca08 1026 break;
cd209421 1027 case SDHC_CAPAB:
5efc9016
PMD		 1028 ret = (uint32_t)s->capareg;
1029 break;
1030 case SDHC_CAPAB + 4:
1031 ret = (uint32_t)(s->capareg >> 32);
d7dfca08
IM		 1032 break;
1033 case SDHC_MAXCURR:
5efc9016
PMD		 1034 ret = (uint32_t)s->maxcurr;
1035 break;
1036 case SDHC_MAXCURR + 4:
1037 ret = (uint32_t)(s->maxcurr >> 32);
d7dfca08
IM		 1038 break;
1039 case SDHC_ADMAERR:
1040 ret = s->admaerr;
1041 break;
1042 case SDHC_ADMASYSADDR:
1043 ret = (uint32_t)s->admasysaddr;
1044 break;
1045 case SDHC_ADMASYSADDR + 4:
1046 ret = (uint32_t)(s->admasysaddr >> 32);
1047 break;
1048 case SDHC_SLOT_INT_STATUS:
aceb5b06 1049 ret = (s->version << 16) | sdhci_slotint(s);
d7dfca08
IM		 1050 break;
1051 default:
00b004b3
PMD		 1052 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1053 "not implemented\n", size, offset);
d7dfca08
IM		 1054 break;
1055 }
1056
1057 ret >>= (offset & 0x3) * 8;
1058 ret &= (1ULL << (size * 8)) - 1;
8be487d8 1059 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 1060 return ret;
1061}
1062
1063static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1064{
1065 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1066 return;
1067 }
1068 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1069
1070 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1071 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1072 if (s->stopped_state == sdhc_gap_read) {
1073 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 1074 sdhci_read_block_from_card(s);
d7dfca08
IM		 1075 } else {
1076 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 1077 sdhci_write_block_to_card(s);
d7dfca08
IM		 1078 }
1079 s->stopped_state = sdhc_not_stopped;
1080 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1081 if (s->prnsts & SDHC_DOING_READ) {
1082 s->stopped_state = sdhc_gap_read;
1083 } else if (s->prnsts & SDHC_DOING_WRITE) {
1084 s->stopped_state = sdhc_gap_write;
1085 }
1086 }
1087}
1088
1089static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1090{
1091 switch (value) {
1092 case SDHC_RESET_ALL:
d368ba43 1093 sdhci_reset(s);
d7dfca08
IM		 1094 break;
1095 case SDHC_RESET_CMD:
1096 s->prnsts &= ~SDHC_CMD_INHIBIT;
1097 s->norintsts &= ~SDHC_NIS_CMDCMP;
1098 break;
1099 case SDHC_RESET_DATA:
1100 s->data_count = 0;
1101 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
1102 SDHC_DOING_READ | SDHC_DOING_WRITE |
1103 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
1104 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
1105 s->stopped_state = sdhc_not_stopped;
1106 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
1107 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
1108 break;
1109 }
1110}
1111
1112static void
d368ba43 1113sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 1114{
d368ba43 1115 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 1116 unsigned shift = 8 * (offset & 0x3);
1117 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 1118 uint32_t value = val;
d7dfca08
IM		 1119 value <<= shift;
1120
45e5dc43
PMD		 1121 if (timer_pending(s->transfer_timer)) {
1122 sdhci_resume_pending_transfer(s);
1123 }
1124
d7dfca08
IM		 1125 switch (offset & ~0x3) {
1126 case SDHC_SYSAD:
8be45cc9
BM		 1127 if (!TRANSFERRING_DATA(s->prnsts)) {
1128 s->sdmasysad = (s->sdmasysad & mask) | value;
1129 MASKED_WRITE(s->sdmasysad, mask, value);
1130 /* Writing to last byte of sdmasysad might trigger transfer */
1131 if (!(mask & 0xFF000000) && s->blkcnt && s->blksize &&
1132 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
1133 if (s->trnmod & SDHC_TRNS_MULTI) {
1134 sdhci_sdma_transfer_multi_blocks(s);
1135 } else {
1136 sdhci_sdma_transfer_single_block(s);
1137 }
45ba9f76 1138 }
d7dfca08
IM		 1139 }
1140 break;
1141 case SDHC_BLKSIZE:
1142 if (!TRANSFERRING_DATA(s->prnsts)) {
dfba99f1 1143 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 12));
d7dfca08 1144 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
9201bb9a 1145
5cd7aa34
BM		 1146 /* Limit block size to the maximum buffer size */
1147 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1148 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than "
1149 "the maximum buffer 0x%x\n", __func__, s->blksize,
1150 s->buf_maxsz);
9201bb9a 1151
5cd7aa34
BM		 1152 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1153 }
9201bb9a
AF		 1154 }
1155
d7dfca08
IM		 1156 break;
1157 case SDHC_ARGUMENT:
1158 MASKED_WRITE(s->argument, mask, value);
1159 break;
1160 case SDHC_TRNMOD:
1161 /* DMA can be enabled only if it is supported as indicated by
1162 * capabilities register */
6ff37c3d 1163 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
d7dfca08
IM		 1164 value &= ~SDHC_TRNS_DMA;
1165 }
24bddf9d 1166 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
d7dfca08
IM		 1167 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1168
1169 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1170 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1171 break;
1172 }
1173
d368ba43 1174 sdhci_send_command(s);
d7dfca08
IM		 1175 break;
1176 case SDHC_BDATA:
1177 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1178 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1179 }
1180 break;
1181 case SDHC_HOSTCTL:
1182 if (!(mask & 0xFF0000)) {
1183 sdhci_blkgap_write(s, value >> 16);
1184 }
06c5120b 1185 MASKED_WRITE(s->hostctl1, mask, value);
d7dfca08
IM		 1186 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1187 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1188 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1189 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1190 s->pwrcon &= ~SDHC_POWER_ON;
1191 }
1192 break;
1193 case SDHC_CLKCON:
1194 if (!(mask & 0xFF000000)) {
1195 sdhci_reset_write(s, value >> 24);
1196 }
1197 MASKED_WRITE(s->clkcon, mask, value);
1198 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1199 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1200 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1201 } else {
1202 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1203 }
1204 break;
1205 case SDHC_NORINTSTS:
1206 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1207 value &= ~SDHC_NIS_CARDINT;
1208 }
1209 s->norintsts &= mask | ~value;
1210 s->errintsts &= (mask >> 16) | ~(value >> 16);
1211 if (s->errintsts) {
1212 s->norintsts |= SDHC_NIS_ERR;
1213 } else {
1214 s->norintsts &= ~SDHC_NIS_ERR;
1215 }
1216 sdhci_update_irq(s);
1217 break;
1218 case SDHC_NORINTSTSEN:
1219 MASKED_WRITE(s->norintstsen, mask, value);
1220 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1221 s->norintsts &= s->norintstsen;
1222 s->errintsts &= s->errintstsen;
1223 if (s->errintsts) {
1224 s->norintsts |= SDHC_NIS_ERR;
1225 } else {
1226 s->norintsts &= ~SDHC_NIS_ERR;
1227 }
0a7ac9f9
AB		 1228 /* Quirk for Raspberry Pi: pending card insert interrupt
1229 * appears when first enabled after power on */
1230 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1231 assert(s->pending_insert_quirk);
1232 s->norintsts |= SDHC_NIS_INSERT;
1233 s->pending_insert_state = false;
1234 }
d7dfca08
IM		 1235 sdhci_update_irq(s);
1236 break;
1237 case SDHC_NORINTSIGEN:
1238 MASKED_WRITE(s->norintsigen, mask, value);
1239 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1240 sdhci_update_irq(s);
1241 break;
1242 case SDHC_ADMAERR:
1243 MASKED_WRITE(s->admaerr, mask, value);
1244 break;
1245 case SDHC_ADMASYSADDR:
1246 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1247 (uint64_t)mask)) | (uint64_t)value;
1248 break;
1249 case SDHC_ADMASYSADDR + 4:
1250 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1251 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1252 break;
1253 case SDHC_FEAER:
1254 s->acmd12errsts |= value;
1255 s->errintsts |= (value >> 16) & s->errintstsen;
1256 if (s->acmd12errsts) {
1257 s->errintsts |= SDHC_EIS_CMD12ERR;
1258 }
1259 if (s->errintsts) {
1260 s->norintsts |= SDHC_NIS_ERR;
1261 }
1262 sdhci_update_irq(s);
1263 break;
5d2c0464 1264 case SDHC_ACMD12ERRSTS:
0034ebe6
PMD		 1265 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1266 if (s->uhs_mode >= UHS_I) {
1267 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1268
1269 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1270 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1271 } else {
1272 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1273 }
1274 }
5d2c0464 1275 break;
5efc9016
PMD		 1276
1277 case SDHC_CAPAB:
1278 case SDHC_CAPAB + 4:
1279 case SDHC_MAXCURR:
1280 case SDHC_MAXCURR + 4:
1281 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1282 " <- 0x%08x read-only\n", size, offset, value >> shift);
1283 break;
1284
d7dfca08 1285 default:
00b004b3
PMD		 1286 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1287 "not implemented\n", size, offset, value >> shift);
d7dfca08
IM		 1288 break;
1289 }
8be487d8
PMD		 1290 trace_sdhci_access("wr", size << 3, offset, "<-",
1291 value >> shift, value >> shift);
d7dfca08
IM		 1292}
1293
1294static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1295 .read = sdhci_read,
1296 .write = sdhci_write,
d7dfca08
IM		 1297 .valid = {
1298 .min_access_size = 1,
1299 .max_access_size = 4,
1300 .unaligned = false
1301 },
1302 .endianness = DEVICE_LITTLE_ENDIAN,
1303};
1304
aceb5b06
PMD		 1305static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
1306{
de1b3800 1307 ERRP_GUARD();
6ff37c3d 1308
4d67852d
PMD		 1309 switch (s->sd_spec_version) {
1310 case 2 ... 3:
1311 break;
1312 default:
1313 error_setg(errp, "Only Spec v2/v3 are supported");
aceb5b06
PMD		 1314 return;
1315 }
1316 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
6ff37c3d 1317
de1b3800
VSO		 1318 sdhci_check_capareg(s, errp);
1319 if (*errp) {
6ff37c3d
PMD		 1320 return;
1321 }
aceb5b06
PMD		 1322}
1323
b635d98c
PMD		 1324/* --- qdev common --- */
1325
ce864603 1326void sdhci_initfn(SDHCIState *s)
d7dfca08 1327{
40bbc194
PM		 1328 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1329 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
d7dfca08 1330
bc72ad67 1331 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1332 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
fd1e5c81
AS		 1333
1334 s->io_ops = &sdhci_mmio_ops;
d7dfca08
IM		 1335}
1336
ce864603 1337void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1338{
bc72ad67 1339 timer_free(s->insert_timer);
bc72ad67 1340 timer_free(s->transfer_timer);
d7dfca08 1341
012aef07
MA		 1342 g_free(s->fifo_buffer);
1343 s->fifo_buffer = NULL;
d7dfca08
IM		 1344}
1345
ce864603 1346void sdhci_common_realize(SDHCIState *s, Error **errp)
25367498 1347{
de1b3800 1348 ERRP_GUARD();
aceb5b06 1349
de1b3800
VSO		 1350 sdhci_init_readonly_registers(s, errp);
1351 if (*errp) {
aceb5b06
PMD		 1352 return;
1353 }
25367498
PMD		 1354 s->buf_maxsz = sdhci_get_fifolen(s);
1355 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1356
c0983085 1357 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
25367498
PMD		 1358 SDHC_REGISTERS_MAP_SIZE);
1359}
1360
b69c3c21 1361void sdhci_common_unrealize(SDHCIState *s)
8b7455c7
PMD		 1362{
1363 /* This function is expected to be called only once for each class:
1364 * - SysBus: via DeviceClass->unrealize(),
1365 * - PCI: via PCIDeviceClass->exit().
1366 * However to avoid double-free and/or use-after-free we still nullify
1367 * this variable (better safe than sorry!). */
1368 g_free(s->fifo_buffer);
1369 s->fifo_buffer = NULL;
1370}
1371
0a7ac9f9
AB		 1372static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1373{
1374 SDHCIState *s = opaque;
1375
1376 return s->pending_insert_state;
1377}
1378
1379static const VMStateDescription sdhci_pending_insert_vmstate = {
1380 .name = "sdhci/pending-insert",
1381 .version_id = 1,
1382 .minimum_version_id = 1,
1383 .needed = sdhci_pending_insert_vmstate_needed,
1384 .fields = (VMStateField[]) {
1385 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1386 VMSTATE_END_OF_LIST()
1387 },
1388};
1389
d7dfca08
IM		 1390const VMStateDescription sdhci_vmstate = {
1391 .name = "sdhci",
1392 .version_id = 1,
1393 .minimum_version_id = 1,
35d08458 1394 .fields = (VMStateField[]) {
d7dfca08
IM		 1395 VMSTATE_UINT32(sdmasysad, SDHCIState),
1396 VMSTATE_UINT16(blksize, SDHCIState),
1397 VMSTATE_UINT16(blkcnt, SDHCIState),
1398 VMSTATE_UINT32(argument, SDHCIState),
1399 VMSTATE_UINT16(trnmod, SDHCIState),
1400 VMSTATE_UINT16(cmdreg, SDHCIState),
1401 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1402 VMSTATE_UINT32(prnsts, SDHCIState),
06c5120b 1403 VMSTATE_UINT8(hostctl1, SDHCIState),
d7dfca08
IM		 1404 VMSTATE_UINT8(pwrcon, SDHCIState),
1405 VMSTATE_UINT8(blkgap, SDHCIState),
1406 VMSTATE_UINT8(wakcon, SDHCIState),
1407 VMSTATE_UINT16(clkcon, SDHCIState),
1408 VMSTATE_UINT8(timeoutcon, SDHCIState),
1409 VMSTATE_UINT8(admaerr, SDHCIState),
1410 VMSTATE_UINT16(norintsts, SDHCIState),
1411 VMSTATE_UINT16(errintsts, SDHCIState),
1412 VMSTATE_UINT16(norintstsen, SDHCIState),
1413 VMSTATE_UINT16(errintstsen, SDHCIState),
1414 VMSTATE_UINT16(norintsigen, SDHCIState),
1415 VMSTATE_UINT16(errintsigen, SDHCIState),
1416 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1417 VMSTATE_UINT16(data_count, SDHCIState),
1418 VMSTATE_UINT64(admasysaddr, SDHCIState),
1419 VMSTATE_UINT8(stopped_state, SDHCIState),
59046ec2 1420 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
e720677e
PB		 1421 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1422 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08 1423 VMSTATE_END_OF_LIST()
0a7ac9f9
AB		 1424 },
1425 .subsections = (const VMStateDescription*[]) {
1426 &sdhci_pending_insert_vmstate,
1427 NULL
1428 },
d7dfca08
IM		 1429};
1430
ce864603 1431void sdhci_common_class_init(ObjectClass *klass, void *data)
1c92c505
PMD		 1432{
1433 DeviceClass *dc = DEVICE_CLASS(klass);
1434
1435 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1436 dc->vmsd = &sdhci_vmstate;
1437 dc->reset = sdhci_poweron_reset;
1438}
1439
b635d98c
PMD		 1440/* --- qdev SysBus --- */
1441
5ec911c3 1442static Property sdhci_sysbus_properties[] = {
b635d98c 1443 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
0a7ac9f9
AB		 1444 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1445 false),
60765b6c
PMD		 1446 DEFINE_PROP_LINK("dma", SDHCIState,
1447 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
5ec911c3
KC		 1448 DEFINE_PROP_END_OF_LIST(),
1449};
1450
7302dcd6
KC		 1451static void sdhci_sysbus_init(Object *obj)
1452{
1453 SDHCIState *s = SYSBUS_SDHCI(obj);
5ec911c3 1454
40bbc194 1455 sdhci_initfn(s);
7302dcd6
KC		 1456}
1457
1458static void sdhci_sysbus_finalize(Object *obj)
1459{
1460 SDHCIState *s = SYSBUS_SDHCI(obj);
60765b6c
PMD		 1461
1462 if (s->dma_mr) {
1463 object_unparent(OBJECT(s->dma_mr));
1464 }
1465
7302dcd6
KC		 1466 sdhci_uninitfn(s);
1467}
1468
1019388c 1469static void sdhci_sysbus_realize(DeviceState *dev, Error **errp)
d7dfca08 1470{
de1b3800 1471 ERRP_GUARD();
7302dcd6 1472 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08
IM		 1473 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1474
de1b3800
VSO		 1475 sdhci_common_realize(s, errp);
1476 if (*errp) {
25367498
PMD		 1477 return;
1478 }
1479
60765b6c 1480 if (s->dma_mr) {
02e57e1c 1481 s->dma_as = &s->sysbus_dma_as;
60765b6c
PMD		 1482 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1483 } else {
1484 /* use system_memory() if property "dma" not set */
1485 s->dma_as = &address_space_memory;
1486 }
dd55c485 1487
d7dfca08 1488 sysbus_init_irq(sbd, &s->irq);
fd1e5c81 1489
d7dfca08
IM		 1490 sysbus_init_mmio(sbd, &s->iomem);
1491}
1492
b69c3c21 1493static void sdhci_sysbus_unrealize(DeviceState *dev)
8b7455c7
PMD		 1494{
1495 SDHCIState *s = SYSBUS_SDHCI(dev);
1496
b69c3c21 1497 sdhci_common_unrealize(s);
60765b6c
PMD		 1498
1499 if (s->dma_mr) {
1500 address_space_destroy(s->dma_as);
1501 }
8b7455c7
PMD		 1502}
1503
7302dcd6 1504static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1505{
1506 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08 1507
4f67d30b 1508 device_class_set_props(dc, sdhci_sysbus_properties);
7302dcd6 1509 dc->realize = sdhci_sysbus_realize;
8b7455c7 1510 dc->unrealize = sdhci_sysbus_unrealize;
1c92c505
PMD		 1511
1512 sdhci_common_class_init(klass, data);
d7dfca08
IM		 1513}
1514
7302dcd6
KC		 1515static const TypeInfo sdhci_sysbus_info = {
1516 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1517 .parent = TYPE_SYS_BUS_DEVICE,
1518 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1519 .instance_init = sdhci_sysbus_init,
1520 .instance_finalize = sdhci_sysbus_finalize,
1521 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1522};
1523
b635d98c
PMD		 1524/* --- qdev bus master --- */
1525
40bbc194
PM		 1526static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1527{
1528 SDBusClass *sbc = SD_BUS_CLASS(klass);
1529
1530 sbc->set_inserted = sdhci_set_inserted;
1531 sbc->set_readonly = sdhci_set_readonly;
1532}
1533
1534static const TypeInfo sdhci_bus_info = {
1535 .name = TYPE_SDHCI_BUS,
1536 .parent = TYPE_SD_BUS,
1537 .instance_size = sizeof(SDBus),
1538 .class_init = sdhci_bus_class_init,
1539};
1540
efadc818
PMD		 1541/* --- qdev i.MX eSDHC --- */
1542
fd1e5c81
AS		 1543static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
1544{
1545 SDHCIState *s = SYSBUS_SDHCI(opaque);
1546 uint32_t ret;
06c5120b 1547 uint16_t hostctl1;
fd1e5c81
AS		 1548
1549 switch (offset) {
1550 default:
1551 return sdhci_read(opaque, offset, size);
1552
1553 case SDHC_HOSTCTL:
1554 /*
1555 * For a detailed explanation on the following bit
1556 * manipulation code see comments in a similar part of
1557 * usdhc_write()
1558 */
06c5120b 1559 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
fd1e5c81 1560
06c5120b
PMD		 1561 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1562 hostctl1 |= ESDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1563 }
1564
06c5120b
PMD		 1565 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1566 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1567 }
1568
06c5120b 1569 ret = hostctl1;
fd1e5c81
AS		 1570 ret |= (uint32_t)s->blkgap << 16;
1571 ret |= (uint32_t)s->wakcon << 24;
1572
1573 break;
1574
6bfd06da
HEF		 1575 case SDHC_PRNSTS:
1576 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1577 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1578 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1579 ret |= ESDHC_PRNSTS_SDSTB;
1580 }
1581 break;
1582
3b2d8176
GR		 1583 case ESDHC_VENDOR_SPEC:
1584 ret = s->vendor_spec;
1585 break;
fd1e5c81
AS		 1586 case ESDHC_DLL_CTRL:
1587 case ESDHC_TUNE_CTRL_STATUS:
1588 case ESDHC_UNDOCUMENTED_REG27:
1589 case ESDHC_TUNING_CTRL:
fd1e5c81
AS		 1590 case ESDHC_MIX_CTRL:
1591 case ESDHC_WTMK_LVL:
1592 ret = 0;
1593 break;
1594 }
1595
1596 return ret;
1597}
1598
1599static void
1600usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1601{
1602 SDHCIState *s = SYSBUS_SDHCI(opaque);
06c5120b 1603 uint8_t hostctl1;
fd1e5c81
AS		 1604 uint32_t value = (uint32_t)val;
1605
1606 switch (offset) {
1607 case ESDHC_DLL_CTRL:
1608 case ESDHC_TUNE_CTRL_STATUS:
1609 case ESDHC_UNDOCUMENTED_REG27:
1610 case ESDHC_TUNING_CTRL:
1611 case ESDHC_WTMK_LVL:
3b2d8176
GR		 1612 break;
1613
fd1e5c81 1614 case ESDHC_VENDOR_SPEC:
3b2d8176
GR		 1615 s->vendor_spec = value;
1616 switch (s->vendor) {
1617 case SDHCI_VENDOR_IMX:
1618 if (value & ESDHC_IMX_FRC_SDCLK_ON) {
1619 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
1620 } else {
1621 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
1622 }
1623 break;
1624 default:
1625 break;
1626 }
fd1e5c81
AS		 1627 break;
1628
1629 case SDHC_HOSTCTL:
1630 /*
1631 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1632 *
1633 * 7 6 5 4 3 2 1 0
1634 * |-----------+--------+--------+-----------+----------+---------|
1635 * | Card | Card | Endian | DATA3 | Data | Led |
1636 * | Detect | Detect | Mode | as Card | Transfer | Control |
1637 * | Signal | Test | | Detection | Width | |
1638 * | Selection | Level | | Pin | | |
1639 * |-----------+--------+--------+-----------+----------+---------|
1640 *
1641 * and 0x29
1642 *
1643 * 15 10 9 8
1644 * |----------+------|
1645 * | Reserved | DMA |
1646 * | | Sel. |
1647 * | | |
1648 * |----------+------|
1649 *
1650 * and here's what SDCHI spec expects those offsets to be:
1651 *
1652 * 0x28 (Host Control Register)
1653 *
1654 * 7 6 5 4 3 2 1 0
1655 * |--------+--------+----------+------+--------+----------+---------|
1656 * | Card | Card | Extended | DMA | High | Data | LED |
1657 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1658 * | Signal | Test | Transfer | | Enable | Width | |
1659 * | Sel. | Level | Width | | | | |
1660 * |--------+--------+----------+------+--------+----------+---------|
1661 *
1662 * and 0x29 (Power Control Register)
1663 *
1664 * |----------------------------------|
1665 * | Power Control Register |
1666 * | |
1667 * | Description omitted, |
1668 * | since it has no analog in ESDHCI |
1669 * | |
1670 * |----------------------------------|
1671 *
1672 * Since offsets 0x2A and 0x2B should be compatible between
1673 * both IP specs we only need to reconcile least 16-bit of the
1674 * word we've been given.
1675 */
1676
1677 /*
1678 * First, save bits 7 6 and 0 since they are identical
1679 */
06c5120b
PMD		 1680 hostctl1 = value & (SDHC_CTRL_LED |
1681 SDHC_CTRL_CDTEST_INS |
1682 SDHC_CTRL_CDTEST_EN);
fd1e5c81
AS		 1683 /*
1684 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1685 * bits 5 and 1
1686 */
1687 if (value & ESDHC_CTRL_8BITBUS) {
06c5120b 1688 hostctl1 |= SDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1689 }
1690
1691 if (value & ESDHC_CTRL_4BITBUS) {
06c5120b 1692 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1693 }
1694
1695 /*
1696 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1697 */
06c5120b 1698 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
fd1e5c81
AS		 1699
1700 /*
1701 * Now place the corrected value into low 16-bit of the value
1702 * we are going to give standard SDHCI write function
1703 *
1704 * NOTE: This transformation should be the inverse of what can
1705 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1706 * kernel
1707 */
1708 value &= ~UINT16_MAX;
06c5120b 1709 value |= hostctl1;
fd1e5c81
AS		 1710 value |= (uint16_t)s->pwrcon << 8;
1711
1712 sdhci_write(opaque, offset, value, size);
1713 break;
1714
1715 case ESDHC_MIX_CTRL:
1716 /*
1717 * So, when SD/MMC stack in Linux tries to write to "Transfer
1718 * Mode Register", ESDHC i.MX quirk code will translate it
1719 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1720 * order to get where we started
1721 *
1722 * Note that Auto CMD23 Enable bit is located in a wrong place
1723 * on i.MX, but since it is not used by QEMU we do not care.
1724 *
1725 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1726 * here becuase it will result in a call to
1727 * sdhci_send_command(s) which we don't want.
1728 *
1729 */
1730 s->trnmod = value & UINT16_MAX;
1731 break;
1732 case SDHC_TRNMOD:
1733 /*
1734 * Similar to above, but this time a write to "Command
1735 * Register" will be translated into a 4-byte write to
1736 * "Transfer Mode register" where lower 16-bit of value would
1737 * be set to zero. So what we do is fill those bits with
1738 * cached value from s->trnmod and let the SDHCI
1739 * infrastructure handle the rest
1740 */
1741 sdhci_write(opaque, offset, val | s->trnmod, size);
1742 break;
1743 case SDHC_BLKSIZE:
1744 /*
1745 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1746 * Linux driver will try to zero this field out which will
1747 * break the rest of SDHCI emulation.
1748 *
1749 * Linux defaults to maximum possible setting (512K boundary)
1750 * and it seems to be the only option that i.MX IP implements,
1751 * so we artificially set it to that value.
1752 */
1753 val |= 0x7 << 12;
1754 /* FALLTHROUGH */
1755 default:
1756 sdhci_write(opaque, offset, val, size);
1757 break;
1758 }
1759}
1760
fd1e5c81
AS		 1761static const MemoryRegionOps usdhc_mmio_ops = {
1762 .read = usdhc_read,
1763 .write = usdhc_write,
1764 .valid = {
1765 .min_access_size = 1,
1766 .max_access_size = 4,
1767 .unaligned = false
1768 },
1769 .endianness = DEVICE_LITTLE_ENDIAN,
1770};
1771
1772static void imx_usdhc_init(Object *obj)
1773{
1774 SDHCIState *s = SYSBUS_SDHCI(obj);
1775
1776 s->io_ops = &usdhc_mmio_ops;
1777 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1778}
1779
1780static const TypeInfo imx_usdhc_info = {
1781 .name = TYPE_IMX_USDHC,
1782 .parent = TYPE_SYSBUS_SDHCI,
1783 .instance_init = imx_usdhc_init,
1784};
1785
c85fba50
PMD		 1786/* --- qdev Samsung s3c --- */
1787
1788#define S3C_SDHCI_CONTROL2 0x80
1789#define S3C_SDHCI_CONTROL3 0x84
1790#define S3C_SDHCI_CONTROL4 0x8c
1791
1792static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
1793{
1794 uint64_t ret;
1795
1796 switch (offset) {
1797 case S3C_SDHCI_CONTROL2:
1798 case S3C_SDHCI_CONTROL3:
1799 case S3C_SDHCI_CONTROL4:
1800 /* ignore */
1801 ret = 0;
1802 break;
1803 default:
1804 ret = sdhci_read(opaque, offset, size);
1805 break;
1806 }
1807
1808 return ret;
1809}
1810
1811static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
1812 unsigned size)
1813{
1814 switch (offset) {
1815 case S3C_SDHCI_CONTROL2:
1816 case S3C_SDHCI_CONTROL3:
1817 case S3C_SDHCI_CONTROL4:
1818 /* ignore */
1819 break;
1820 default:
1821 sdhci_write(opaque, offset, val, size);
1822 break;
1823 }
1824}
1825
1826static const MemoryRegionOps sdhci_s3c_mmio_ops = {
1827 .read = sdhci_s3c_read,
1828 .write = sdhci_s3c_write,
1829 .valid = {
1830 .min_access_size = 1,
1831 .max_access_size = 4,
1832 .unaligned = false
1833 },
1834 .endianness = DEVICE_LITTLE_ENDIAN,
1835};
1836
1837static void sdhci_s3c_init(Object *obj)
1838{
1839 SDHCIState *s = SYSBUS_SDHCI(obj);
1840
1841 s->io_ops = &sdhci_s3c_mmio_ops;
1842}
1843
1844static const TypeInfo sdhci_s3c_info = {
1845 .name = TYPE_S3C_SDHCI ,
1846 .parent = TYPE_SYSBUS_SDHCI,
1847 .instance_init = sdhci_s3c_init,
1848};
1849
d7dfca08
IM		 1850static void sdhci_register_types(void)
1851{
7302dcd6 1852 type_register_static(&sdhci_sysbus_info);
40bbc194 1853 type_register_static(&sdhci_bus_info);
fd1e5c81 1854 type_register_static(&imx_usdhc_info);
c85fba50 1855 type_register_static(&sdhci_s3c_info);
d7dfca08
IM		 1856}
1857
1858type_init(sdhci_register_types)
Mirror of https://git.qemu.org/git/qemu.git