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target-sparc: Store %asi in TB flags
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
7a3f1944
FB		 36#define DEBUG_DISAS
37
72cbca10
FB		 38#define DYNAMIC_PC 1 /* dynamic pc value */
39#define JUMP_PC 2 /* dynamic pc value which takes only two values
40 according to jump_pc[T2] */
41
1a2fb1c0 42/* global register indexes */
1bcea73e
LV		 43static TCGv_env cpu_env;
44static TCGv_ptr cpu_regwptr;
25517f99
PB		 45static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
46static TCGv_i32 cpu_cc_op;
a7812ae4 47static TCGv_i32 cpu_psr;
d2dc4069
RH		 48static TCGv cpu_fsr, cpu_pc, cpu_npc;
49static TCGv cpu_regs[32];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a6d567e5 56static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 60#else
61static TCGv cpu_wim;
dc99a3f2 62#endif
714547bb 63/* Floating point registers */
30038fd8 64static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 65
022c62cb 66#include "exec/gen-icount.h"
2e70f6ef 67
7a3f1944 68typedef struct DisasContext {
0f8a249a
BS		 69 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
70 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 71 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 72 int is_br;
e8af50a3 73 int mem_idx;
a80dde08 74 int fpu_enabled;
2cade6a3 75 int address_mask_32bit;
060718c1 76 int singlestep;
8393617c 77 uint32_t cc_op; /* current CC operation */
cf495bcf 78 struct TranslationBlock *tb;
5578ceab 79 sparc_def_t *def;
30038fd8 80 TCGv_i32 t32[3];
88023616 81 TCGv ttl[5];
30038fd8 82 int n_t32;
88023616 83 int n_ttl;
a6d567e5
RH		 84#ifdef TARGET_SPARC64
85 int asi;
86#endif
7a3f1944
FB		 87} DisasContext;
88
416fcaea
RH		 89typedef struct {
90 TCGCond cond;
91 bool is_bool;
92 bool g1, g2;
93 TCGv c1, c2;
94} DisasCompare;
95
3475187d 96// This function uses non-native bit order
dc1a6971
BS		 97#define GET_FIELD(X, FROM, TO) \
98 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 99
3475187d 100// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 101#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 102 GET_FIELD(X, 31 - (TO), 31 - (FROM))
103
104#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 105#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 106
107#ifdef TARGET_SPARC64
0387d928 108#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 109#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 110#else
c185970a 111#define DFPREG(r) (r & 0x1e)
1f587329 112#define QFPREG(r) (r & 0x1c)
3475187d
FB		 113#endif
114
b158a785
BS		 115#define UA2005_HTRAP_MASK 0xff
116#define V8_TRAP_MASK 0x7f
117
3475187d
FB		 118static int sign_extend(int x, int len)
119{
120 len = 32 - len;
121 return (x << len) >> len;
122}
123
7a3f1944
FB		 124#define IS_IMM (insn & (1<<13))
125
2ae23e17
RH		 126static inline TCGv_i32 get_temp_i32(DisasContext *dc)
127{
128 TCGv_i32 t;
129 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
130 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
131 return t;
132}
133
134static inline TCGv get_temp_tl(DisasContext *dc)
135{
136 TCGv t;
137 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
138 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
139 return t;
140}
141
141ae5c1
RH		 142static inline void gen_update_fprs_dirty(int rd)
143{
144#if defined(TARGET_SPARC64)
145 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
146#endif
147}
148
ff07ec83 149/* floating point registers moves */
208ae657
RH		 150static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
151{
30038fd8
RH		 152#if TCG_TARGET_REG_BITS == 32
153 if (src & 1) {
154 return TCGV_LOW(cpu_fpr[src / 2]);
155 } else {
156 return TCGV_HIGH(cpu_fpr[src / 2]);
157 }
158#else
159 if (src & 1) {
160 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
161 } else {
2ae23e17 162 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 163 TCGv_i64 t = tcg_temp_new_i64();
164
165 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 166 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 167 tcg_temp_free_i64(t);
168
30038fd8
RH		 169 return ret;
170 }
171#endif
208ae657
RH		 172}
173
174static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
175{
30038fd8
RH		 176#if TCG_TARGET_REG_BITS == 32
177 if (dst & 1) {
178 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
179 } else {
180 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
181 }
182#else
183 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
184 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
185 (dst & 1 ? 0 : 32), 32);
186#endif
141ae5c1 187 gen_update_fprs_dirty(dst);
208ae657
RH		 188}
189
ba5f5179 190static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 191{
ba5f5179 192 return get_temp_i32(dc);
208ae657
RH		 193}
194
96eda024
RH		 195static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
196{
96eda024 197 src = DFPREG(src);
30038fd8 198 return cpu_fpr[src / 2];
96eda024
RH		 199}
200
201static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
202{
203 dst = DFPREG(dst);
30038fd8 204 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 205 gen_update_fprs_dirty(dst);
206}
207
3886b8a3 208static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 209{
3886b8a3 210 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 211}
212
ff07ec83
BS		 213static void gen_op_load_fpr_QT0(unsigned int src)
214{
30038fd8
RH		 215 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
216 offsetof(CPU_QuadU, ll.upper));
217 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
218 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 219}
220
221static void gen_op_load_fpr_QT1(unsigned int src)
222{
30038fd8
RH		 223 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
224 offsetof(CPU_QuadU, ll.upper));
225 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
226 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 227}
228
229static void gen_op_store_QT0_fpr(unsigned int dst)
230{
30038fd8
RH		 231 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
232 offsetof(CPU_QuadU, ll.upper));
233 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
234 offsetof(CPU_QuadU, ll.lower));
ff07ec83 235}
1f587329 236
ac11f776 237#ifdef TARGET_SPARC64
30038fd8 238static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 239{
240 rd = QFPREG(rd);
241 rs = QFPREG(rs);
242
30038fd8
RH		 243 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
244 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 245 gen_update_fprs_dirty(rd);
246}
247#endif
248
81ad8ba2
BS		 249/* moves */
250#ifdef CONFIG_USER_ONLY
3475187d 251#define supervisor(dc) 0
81ad8ba2 252#ifdef TARGET_SPARC64
e9ebed4d 253#define hypervisor(dc) 0
81ad8ba2 254#endif
3475187d 255#else
2aae2b8e 256#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 257#ifdef TARGET_SPARC64
2aae2b8e 258#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 259#else
3475187d 260#endif
81ad8ba2
BS		 261#endif
262
2cade6a3
BS		 263#ifdef TARGET_SPARC64
264#ifndef TARGET_ABI32
265#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 266#else
2cade6a3
BS		 267#define AM_CHECK(dc) (1)
268#endif
1a2fb1c0 269#endif
3391c818 270
2cade6a3
BS		 271static inline void gen_address_mask(DisasContext *dc, TCGv addr)
272{
273#ifdef TARGET_SPARC64
274 if (AM_CHECK(dc))
275 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
276#endif
277}
278
88023616
RH		 279static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
280{
d2dc4069
RH		 281 if (reg > 0) {
282 assert(reg < 32);
283 return cpu_regs[reg];
284 } else {
88023616 285 TCGv t = get_temp_tl(dc);
d2dc4069 286 tcg_gen_movi_tl(t, 0);
88023616 287 return t;
88023616
RH		 288 }
289}
290
291static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
292{
293 if (reg > 0) {
d2dc4069
RH		 294 assert(reg < 32);
295 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 296 }
297}
298
299static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
300{
d2dc4069
RH		 301 if (reg > 0) {
302 assert(reg < 32);
303 return cpu_regs[reg];
88023616 304 } else {
d2dc4069 305 return get_temp_tl(dc);
88023616
RH		 306 }
307}
308
90aa39a1
SF		 309static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
310 target_ulong npc)
311{
312 if (unlikely(s->singlestep)) {
313 return false;
314 }
315
316#ifndef CONFIG_USER_ONLY
317 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
318 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
319#else
320 return true;
321#endif
322}
323
5fafdf24 324static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 325 target_ulong pc, target_ulong npc)
326{
90aa39a1 327 if (use_goto_tb(s, pc, npc)) {
6e256c93 328 /* jump to same page: we can use a direct jump */
57fec1fe 329 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 330 tcg_gen_movi_tl(cpu_pc, pc);
331 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 332 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 333 } else {
334 /* jump to another page: currently not optimized */
2f5680ee
BS		 335 tcg_gen_movi_tl(cpu_pc, pc);
336 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 337 tcg_gen_exit_tb(0);
6e256c93
FB		 338 }
339}
340
19f329ad 341// XXX suboptimal
a7812ae4 342static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 343{
8911f501 344 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 345 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 346 tcg_gen_andi_tl(reg, reg, 0x1);
347}
348
a7812ae4 349static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 350{
8911f501 351 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 352 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 353 tcg_gen_andi_tl(reg, reg, 0x1);
354}
355
a7812ae4 356static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 357{
8911f501 358 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 359 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 360 tcg_gen_andi_tl(reg, reg, 0x1);
361}
362
a7812ae4 363static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 364{
8911f501 365 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 366 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 367 tcg_gen_andi_tl(reg, reg, 0x1);
368}
369
4af984a7 370static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 371{
4af984a7 372 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 373 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 374 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 375 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 376}
377
70c48285 378static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 379{
70c48285
RH		 380 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
381
382 /* Carry is computed from a previous add: (dst < src) */
383#if TARGET_LONG_BITS == 64
384 cc_src1_32 = tcg_temp_new_i32();
385 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 386 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
387 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 388#else
389 cc_src1_32 = cpu_cc_dst;
390 cc_src2_32 = cpu_cc_src;
391#endif
392
393 carry_32 = tcg_temp_new_i32();
394 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
395
396#if TARGET_LONG_BITS == 64
397 tcg_temp_free_i32(cc_src1_32);
398 tcg_temp_free_i32(cc_src2_32);
399#endif
400
401 return carry_32;
41d72852
BS		 402}
403
70c48285 404static TCGv_i32 gen_sub32_carry32(void)
41d72852 405{
70c48285
RH		 406 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
407
408 /* Carry is computed from a previous borrow: (src1 < src2) */
409#if TARGET_LONG_BITS == 64
410 cc_src1_32 = tcg_temp_new_i32();
411 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 412 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
413 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 414#else
415 cc_src1_32 = cpu_cc_src;
416 cc_src2_32 = cpu_cc_src2;
417#endif
418
419 carry_32 = tcg_temp_new_i32();
420 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
421
422#if TARGET_LONG_BITS == 64
423 tcg_temp_free_i32(cc_src1_32);
424 tcg_temp_free_i32(cc_src2_32);
425#endif
426
427 return carry_32;
428}
429
430static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
431 TCGv src2, int update_cc)
432{
433 TCGv_i32 carry_32;
434 TCGv carry;
435
436 switch (dc->cc_op) {
437 case CC_OP_DIV:
438 case CC_OP_LOGIC:
439 /* Carry is known to be zero. Fall back to plain ADD. */
440 if (update_cc) {
441 gen_op_add_cc(dst, src1, src2);
442 } else {
443 tcg_gen_add_tl(dst, src1, src2);
444 }
445 return;
446
447 case CC_OP_ADD:
448 case CC_OP_TADD:
449 case CC_OP_TADDTV:
15fe216f
RH		 450 if (TARGET_LONG_BITS == 32) {
451 /* We can re-use the host's hardware carry generation by using
452 an ADD2 opcode. We discard the low part of the output.
453 Ideally we'd combine this operation with the add that
454 generated the carry in the first place. */
455 carry = tcg_temp_new();
456 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
457 tcg_temp_free(carry);
70c48285
RH		 458 goto add_done;
459 }
70c48285
RH		 460 carry_32 = gen_add32_carry32();
461 break;
462
463 case CC_OP_SUB:
464 case CC_OP_TSUB:
465 case CC_OP_TSUBTV:
466 carry_32 = gen_sub32_carry32();
467 break;
468
469 default:
470 /* We need external help to produce the carry. */
471 carry_32 = tcg_temp_new_i32();
2ffd9176 472 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 473 break;
474 }
475
476#if TARGET_LONG_BITS == 64
477 carry = tcg_temp_new();
478 tcg_gen_extu_i32_i64(carry, carry_32);
479#else
480 carry = carry_32;
481#endif
482
483 tcg_gen_add_tl(dst, src1, src2);
484 tcg_gen_add_tl(dst, dst, carry);
485
486 tcg_temp_free_i32(carry_32);
487#if TARGET_LONG_BITS == 64
488 tcg_temp_free(carry);
489#endif
490
70c48285 491 add_done:
70c48285
RH		 492 if (update_cc) {
493 tcg_gen_mov_tl(cpu_cc_src, src1);
494 tcg_gen_mov_tl(cpu_cc_src2, src2);
495 tcg_gen_mov_tl(cpu_cc_dst, dst);
496 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
497 dc->cc_op = CC_OP_ADDX;
498 }
dc99a3f2
BS		 499}
500
41d72852 501static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 502{
4af984a7 503 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 504 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 505 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 506 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 507}
508
70c48285
RH		 509static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
510 TCGv src2, int update_cc)
41d72852 511{
70c48285
RH		 512 TCGv_i32 carry_32;
513 TCGv carry;
41d72852 514
70c48285
RH		 515 switch (dc->cc_op) {
516 case CC_OP_DIV:
517 case CC_OP_LOGIC:
518 /* Carry is known to be zero. Fall back to plain SUB. */
519 if (update_cc) {
520 gen_op_sub_cc(dst, src1, src2);
521 } else {
522 tcg_gen_sub_tl(dst, src1, src2);
523 }
524 return;
525
526 case CC_OP_ADD:
527 case CC_OP_TADD:
528 case CC_OP_TADDTV:
529 carry_32 = gen_add32_carry32();
530 break;
531
532 case CC_OP_SUB:
533 case CC_OP_TSUB:
534 case CC_OP_TSUBTV:
15fe216f
RH		 535 if (TARGET_LONG_BITS == 32) {
536 /* We can re-use the host's hardware carry generation by using
537 a SUB2 opcode. We discard the low part of the output.
538 Ideally we'd combine this operation with the add that
539 generated the carry in the first place. */
540 carry = tcg_temp_new();
541 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
542 tcg_temp_free(carry);
70c48285
RH		 543 goto sub_done;
544 }
70c48285
RH		 545 carry_32 = gen_sub32_carry32();
546 break;
547
548 default:
549 /* We need external help to produce the carry. */
550 carry_32 = tcg_temp_new_i32();
2ffd9176 551 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 552 break;
553 }
554
555#if TARGET_LONG_BITS == 64
556 carry = tcg_temp_new();
557 tcg_gen_extu_i32_i64(carry, carry_32);
558#else
559 carry = carry_32;
560#endif
561
562 tcg_gen_sub_tl(dst, src1, src2);
563 tcg_gen_sub_tl(dst, dst, carry);
564
565 tcg_temp_free_i32(carry_32);
566#if TARGET_LONG_BITS == 64
567 tcg_temp_free(carry);
568#endif
569
70c48285 570 sub_done:
70c48285
RH		 571 if (update_cc) {
572 tcg_gen_mov_tl(cpu_cc_src, src1);
573 tcg_gen_mov_tl(cpu_cc_src2, src2);
574 tcg_gen_mov_tl(cpu_cc_dst, dst);
575 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
576 dc->cc_op = CC_OP_SUBX;
577 }
dc99a3f2
BS		 578}
579
4af984a7 580static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 581{
de9e9d9f 582 TCGv r_temp, zero, t0;
d9bdab86 583
a7812ae4 584 r_temp = tcg_temp_new();
de9e9d9f 585 t0 = tcg_temp_new();
d9bdab86
BS		 586
587 /* old op:
588 if (!(env->y & 1))
589 T1 = 0;
590 */
6cb675b0 591 zero = tcg_const_tl(0);
72ccba79 592 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 593 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 594 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 595 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
596 zero, cpu_cc_src2);
597 tcg_temp_free(zero);
d9bdab86
BS		 598
599 // b2 = T0 & 1;
600 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 601 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
602 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 603 tcg_gen_shri_tl(t0, cpu_y, 1);
604 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
605 tcg_gen_or_tl(t0, t0, r_temp);
606 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 607
608 // b1 = N ^ V;
de9e9d9f 609 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 610 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 611 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 612 tcg_temp_free(r_temp);
d9bdab86
BS		 613
614 // T0 = (b1 << 31) | (T0 >> 1);
615 // src1 = T0;
de9e9d9f 616 tcg_gen_shli_tl(t0, t0, 31);
6f551262 617 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 618 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
619 tcg_temp_free(t0);
d9bdab86 620
5c6a0628 621 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 622
5c6a0628 623 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 624}
625
fb170183 626static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 627{
528692a8 628#if TARGET_LONG_BITS == 32
fb170183 629 if (sign_ext) {
528692a8 630 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 631 } else {
528692a8 632 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 633 }
528692a8
RH		 634#else
635 TCGv t0 = tcg_temp_new_i64();
636 TCGv t1 = tcg_temp_new_i64();
fb170183 637
528692a8
RH		 638 if (sign_ext) {
639 tcg_gen_ext32s_i64(t0, src1);
640 tcg_gen_ext32s_i64(t1, src2);
641 } else {
642 tcg_gen_ext32u_i64(t0, src1);
643 tcg_gen_ext32u_i64(t1, src2);
644 }
fb170183 645
528692a8
RH		 646 tcg_gen_mul_i64(dst, t0, t1);
647 tcg_temp_free(t0);
648 tcg_temp_free(t1);
fb170183 649
528692a8
RH		 650 tcg_gen_shri_i64(cpu_y, dst, 32);
651#endif
8879d139
BS		 652}
653
fb170183 654static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 655{
fb170183
IK		 656 /* zero-extend truncated operands before multiplication */
657 gen_op_multiply(dst, src1, src2, 0);
658}
8879d139 659
fb170183
IK		 660static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
661{
662 /* sign-extend truncated operands before multiplication */
663 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 664}
665
19f329ad
BS		 666// 1
667static inline void gen_op_eval_ba(TCGv dst)
668{
669 tcg_gen_movi_tl(dst, 1);
670}
671
672// Z
a7812ae4 673static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 674{
675 gen_mov_reg_Z(dst, src);
676}
677
678// Z | (N ^ V)
a7812ae4 679static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 680{
de9e9d9f
RH		 681 TCGv t0 = tcg_temp_new();
682 gen_mov_reg_N(t0, src);
19f329ad 683 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 684 tcg_gen_xor_tl(dst, dst, t0);
685 gen_mov_reg_Z(t0, src);
686 tcg_gen_or_tl(dst, dst, t0);
687 tcg_temp_free(t0);
19f329ad
BS		 688}
689
690// N ^ V
a7812ae4 691static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 692{
de9e9d9f
RH		 693 TCGv t0 = tcg_temp_new();
694 gen_mov_reg_V(t0, src);
19f329ad 695 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 696 tcg_gen_xor_tl(dst, dst, t0);
697 tcg_temp_free(t0);
19f329ad
BS		 698}
699
700// C | Z
a7812ae4 701static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 702{
de9e9d9f
RH		 703 TCGv t0 = tcg_temp_new();
704 gen_mov_reg_Z(t0, src);
19f329ad 705 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 706 tcg_gen_or_tl(dst, dst, t0);
707 tcg_temp_free(t0);
19f329ad
BS		 708}
709
710// C
a7812ae4 711static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 712{
713 gen_mov_reg_C(dst, src);
714}
715
716// V
a7812ae4 717static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 718{
719 gen_mov_reg_V(dst, src);
720}
721
722// 0
723static inline void gen_op_eval_bn(TCGv dst)
724{
725 tcg_gen_movi_tl(dst, 0);
726}
727
728// N
a7812ae4 729static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 730{
731 gen_mov_reg_N(dst, src);
732}
733
734// !Z
a7812ae4 735static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 736{
737 gen_mov_reg_Z(dst, src);
738 tcg_gen_xori_tl(dst, dst, 0x1);
739}
740
741// !(Z | (N ^ V))
a7812ae4 742static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 743{
de9e9d9f 744 gen_op_eval_ble(dst, src);
19f329ad
BS		 745 tcg_gen_xori_tl(dst, dst, 0x1);
746}
747
748// !(N ^ V)
a7812ae4 749static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 750{
de9e9d9f 751 gen_op_eval_bl(dst, src);
19f329ad
BS		 752 tcg_gen_xori_tl(dst, dst, 0x1);
753}
754
755// !(C | Z)
a7812ae4 756static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 757{
de9e9d9f 758 gen_op_eval_bleu(dst, src);
19f329ad
BS		 759 tcg_gen_xori_tl(dst, dst, 0x1);
760}
761
762// !C
a7812ae4 763static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 764{
765 gen_mov_reg_C(dst, src);
766 tcg_gen_xori_tl(dst, dst, 0x1);
767}
768
769// !N
a7812ae4 770static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 771{
772 gen_mov_reg_N(dst, src);
773 tcg_gen_xori_tl(dst, dst, 0x1);
774}
775
776// !V
a7812ae4 777static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 778{
779 gen_mov_reg_V(dst, src);
780 tcg_gen_xori_tl(dst, dst, 0x1);
781}
782
783/*
784 FPSR bit field FCC1 | FCC0:
785 0 =
786 1 <
787 2 >
788 3 unordered
789*/
790static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
791 unsigned int fcc_offset)
792{
ba6a9d8c 793 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 794 tcg_gen_andi_tl(reg, reg, 0x1);
795}
796
797static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
798 unsigned int fcc_offset)
799{
ba6a9d8c 800 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 801 tcg_gen_andi_tl(reg, reg, 0x1);
802}
803
804// !0: FCC0 | FCC1
805static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
806 unsigned int fcc_offset)
807{
de9e9d9f 808 TCGv t0 = tcg_temp_new();
19f329ad 809 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 810 gen_mov_reg_FCC1(t0, src, fcc_offset);
811 tcg_gen_or_tl(dst, dst, t0);
812 tcg_temp_free(t0);
19f329ad
BS		 813}
814
815// 1 or 2: FCC0 ^ FCC1
816static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
817 unsigned int fcc_offset)
818{
de9e9d9f 819 TCGv t0 = tcg_temp_new();
19f329ad 820 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 821 gen_mov_reg_FCC1(t0, src, fcc_offset);
822 tcg_gen_xor_tl(dst, dst, t0);
823 tcg_temp_free(t0);
19f329ad
BS		 824}
825
826// 1 or 3: FCC0
827static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
828 unsigned int fcc_offset)
829{
830 gen_mov_reg_FCC0(dst, src, fcc_offset);
831}
832
833// 1: FCC0 & !FCC1
834static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
835 unsigned int fcc_offset)
836{
de9e9d9f 837 TCGv t0 = tcg_temp_new();
19f329ad 838 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 839 gen_mov_reg_FCC1(t0, src, fcc_offset);
840 tcg_gen_andc_tl(dst, dst, t0);
841 tcg_temp_free(t0);
19f329ad
BS		 842}
843
844// 2 or 3: FCC1
845static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
846 unsigned int fcc_offset)
847{
848 gen_mov_reg_FCC1(dst, src, fcc_offset);
849}
850
851// 2: !FCC0 & FCC1
852static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
853 unsigned int fcc_offset)
854{
de9e9d9f 855 TCGv t0 = tcg_temp_new();
19f329ad 856 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 857 gen_mov_reg_FCC1(t0, src, fcc_offset);
858 tcg_gen_andc_tl(dst, t0, dst);
859 tcg_temp_free(t0);
19f329ad
BS		 860}
861
862// 3: FCC0 & FCC1
863static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
864 unsigned int fcc_offset)
865{
de9e9d9f 866 TCGv t0 = tcg_temp_new();
19f329ad 867 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 868 gen_mov_reg_FCC1(t0, src, fcc_offset);
869 tcg_gen_and_tl(dst, dst, t0);
870 tcg_temp_free(t0);
19f329ad
BS		 871}
872
873// 0: !(FCC0 | FCC1)
874static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
875 unsigned int fcc_offset)
876{
de9e9d9f 877 TCGv t0 = tcg_temp_new();
19f329ad 878 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 879 gen_mov_reg_FCC1(t0, src, fcc_offset);
880 tcg_gen_or_tl(dst, dst, t0);
19f329ad 881 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 882 tcg_temp_free(t0);
19f329ad
BS		 883}
884
885// 0 or 3: !(FCC0 ^ FCC1)
886static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
887 unsigned int fcc_offset)
888{
de9e9d9f 889 TCGv t0 = tcg_temp_new();
19f329ad 890 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 891 gen_mov_reg_FCC1(t0, src, fcc_offset);
892 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 893 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 894 tcg_temp_free(t0);
19f329ad
BS		 895}
896
897// 0 or 2: !FCC0
898static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
899 unsigned int fcc_offset)
900{
901 gen_mov_reg_FCC0(dst, src, fcc_offset);
902 tcg_gen_xori_tl(dst, dst, 0x1);
903}
904
905// !1: !(FCC0 & !FCC1)
906static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
907 unsigned int fcc_offset)
908{
de9e9d9f 909 TCGv t0 = tcg_temp_new();
19f329ad 910 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 911 gen_mov_reg_FCC1(t0, src, fcc_offset);
912 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 913 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 914 tcg_temp_free(t0);
19f329ad
BS		 915}
916
917// 0 or 1: !FCC1
918static inline void gen_op_eval_fble(TCGv dst, TCGv src,
919 unsigned int fcc_offset)
920{
921 gen_mov_reg_FCC1(dst, src, fcc_offset);
922 tcg_gen_xori_tl(dst, dst, 0x1);
923}
924
925// !2: !(!FCC0 & FCC1)
926static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
927 unsigned int fcc_offset)
928{
de9e9d9f 929 TCGv t0 = tcg_temp_new();
19f329ad 930 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 931 gen_mov_reg_FCC1(t0, src, fcc_offset);
932 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 933 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 934 tcg_temp_free(t0);
19f329ad
BS		 935}
936
937// !3: !(FCC0 & FCC1)
938static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
939 unsigned int fcc_offset)
940{
de9e9d9f 941 TCGv t0 = tcg_temp_new();
19f329ad 942 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 943 gen_mov_reg_FCC1(t0, src, fcc_offset);
944 tcg_gen_and_tl(dst, dst, t0);
19f329ad 945 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 946 tcg_temp_free(t0);
19f329ad
BS		 947}
948
46525e1f 949static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 950 target_ulong pc2, TCGv r_cond)
83469015 951{
42a268c2 952 TCGLabel *l1 = gen_new_label();
83469015 953
cb63669a 954 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 955
6e256c93 956 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 957
958 gen_set_label(l1);
6e256c93 959 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 960}
961
bfa31b76 962static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 963{
42a268c2 964 TCGLabel *l1 = gen_new_label();
bfa31b76 965 target_ulong npc = dc->npc;
83469015 966
bfa31b76 967 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 968
bfa31b76 969 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 970
971 gen_set_label(l1);
bfa31b76
RH		 972 gen_goto_tb(dc, 1, npc + 4, npc + 8);
973
974 dc->is_br = 1;
83469015
FB		 975}
976
2bf2e019
RH		 977static void gen_branch_n(DisasContext *dc, target_ulong pc1)
978{
979 target_ulong npc = dc->npc;
980
981 if (likely(npc != DYNAMIC_PC)) {
982 dc->pc = npc;
983 dc->jump_pc[0] = pc1;
984 dc->jump_pc[1] = npc + 4;
985 dc->npc = JUMP_PC;
986 } else {
987 TCGv t, z;
988
989 tcg_gen_mov_tl(cpu_pc, cpu_npc);
990
991 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
992 t = tcg_const_tl(pc1);
993 z = tcg_const_tl(0);
994 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
995 tcg_temp_free(t);
996 tcg_temp_free(z);
997
998 dc->pc = DYNAMIC_PC;
999 }
1000}
1001
2e655fe7 1002static inline void gen_generic_branch(DisasContext *dc)
83469015 1003{
61316742
RH		 1004 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1005 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1006 TCGv zero = tcg_const_tl(0);
19f329ad 1007
61316742 1008 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1009
61316742
RH		 1010 tcg_temp_free(npc0);
1011 tcg_temp_free(npc1);
1012 tcg_temp_free(zero);
83469015
FB		 1013}
1014
4af984a7
BS		 1015/* call this function before using the condition register as it may
1016 have been set for a jump */
dee8913c 1017static inline void flush_cond(DisasContext *dc)
83469015
FB		 1018{
1019 if (dc->npc == JUMP_PC) {
2e655fe7 1020 gen_generic_branch(dc);
83469015
FB		 1021 dc->npc = DYNAMIC_PC;
1022 }
1023}
1024
934da7ee 1025static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1026{
1027 if (dc->npc == JUMP_PC) {
2e655fe7 1028 gen_generic_branch(dc);
72cbca10
FB		 1029 dc->npc = DYNAMIC_PC;
1030 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1031 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1032 }
1033}
1034
20132b96 1035static inline void update_psr(DisasContext *dc)
72cbca10 1036{
cfa90513
BS		 1037 if (dc->cc_op != CC_OP_FLAGS) {
1038 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1039 gen_helper_compute_psr(cpu_env);
cfa90513 1040 }
20132b96
RH		 1041}
1042
1043static inline void save_state(DisasContext *dc)
1044{
1045 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1046 save_npc(dc);
72cbca10
FB		 1047}
1048
4fbe0067
RH		 1049static void gen_exception(DisasContext *dc, int which)
1050{
1051 TCGv_i32 t;
1052
1053 save_state(dc);
1054 t = tcg_const_i32(which);
1055 gen_helper_raise_exception(cpu_env, t);
1056 tcg_temp_free_i32(t);
1057 dc->is_br = 1;
1058}
1059
13a6dd00 1060static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1061{
1062 if (dc->npc == JUMP_PC) {
2e655fe7 1063 gen_generic_branch(dc);
48d5c82b 1064 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1065 dc->pc = DYNAMIC_PC;
1066 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1067 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1068 dc->pc = DYNAMIC_PC;
1069 } else {
1070 dc->pc = dc->npc;
1071 }
1072}
1073
38bc628b
BS		 1074static inline void gen_op_next_insn(void)
1075{
48d5c82b
BS		 1076 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1077 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1078}
1079
416fcaea
RH		 1080static void free_compare(DisasCompare *cmp)
1081{
1082 if (!cmp->g1) {
1083 tcg_temp_free(cmp->c1);
1084 }
1085 if (!cmp->g2) {
1086 tcg_temp_free(cmp->c2);
1087 }
1088}
1089
2a484ecf 1090static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1091 DisasContext *dc)
19f329ad 1092{
2a484ecf 1093 static int subcc_cond[16] = {
96b5a3d3 1094 TCG_COND_NEVER,
2a484ecf
RH		 1095 TCG_COND_EQ,
1096 TCG_COND_LE,
1097 TCG_COND_LT,
1098 TCG_COND_LEU,
1099 TCG_COND_LTU,
1100 -1, /* neg */
1101 -1, /* overflow */
96b5a3d3 1102 TCG_COND_ALWAYS,
2a484ecf
RH		 1103 TCG_COND_NE,
1104 TCG_COND_GT,
1105 TCG_COND_GE,
1106 TCG_COND_GTU,
1107 TCG_COND_GEU,
1108 -1, /* pos */
1109 -1, /* no overflow */
1110 };
1111
96b5a3d3
RH		 1112 static int logic_cond[16] = {
1113 TCG_COND_NEVER,
1114 TCG_COND_EQ, /* eq: Z */
1115 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1116 TCG_COND_LT, /* lt: N ^ V -> N */
1117 TCG_COND_EQ, /* leu: C | Z -> Z */
1118 TCG_COND_NEVER, /* ltu: C -> 0 */
1119 TCG_COND_LT, /* neg: N */
1120 TCG_COND_NEVER, /* vs: V -> 0 */
1121 TCG_COND_ALWAYS,
1122 TCG_COND_NE, /* ne: !Z */
1123 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1124 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1125 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1126 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1127 TCG_COND_GE, /* pos: !N */
1128 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1129 };
1130
a7812ae4 1131 TCGv_i32 r_src;
416fcaea
RH		 1132 TCGv r_dst;
1133
3475187d 1134#ifdef TARGET_SPARC64
2a484ecf 1135 if (xcc) {
dc99a3f2 1136 r_src = cpu_xcc;
2a484ecf 1137 } else {
dc99a3f2 1138 r_src = cpu_psr;
2a484ecf 1139 }
3475187d 1140#else
dc99a3f2 1141 r_src = cpu_psr;
3475187d 1142#endif
2a484ecf 1143
8393617c 1144 switch (dc->cc_op) {
96b5a3d3
RH		 1145 case CC_OP_LOGIC:
1146 cmp->cond = logic_cond[cond];
1147 do_compare_dst_0:
1148 cmp->is_bool = false;
1149 cmp->g2 = false;
1150 cmp->c2 = tcg_const_tl(0);
1151#ifdef TARGET_SPARC64
1152 if (!xcc) {
1153 cmp->g1 = false;
1154 cmp->c1 = tcg_temp_new();
1155 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1156 break;
1157 }
1158#endif
1159 cmp->g1 = true;
1160 cmp->c1 = cpu_cc_dst;
1161 break;
1162
2a484ecf
RH		 1163 case CC_OP_SUB:
1164 switch (cond) {
1165 case 6: /* neg */
1166 case 14: /* pos */
1167 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1168 goto do_compare_dst_0;
2a484ecf 1169
2a484ecf
RH		 1170 case 7: /* overflow */
1171 case 15: /* !overflow */
1172 goto do_dynamic;
1173
1174 default:
1175 cmp->cond = subcc_cond[cond];
1176 cmp->is_bool = false;
1177#ifdef TARGET_SPARC64
1178 if (!xcc) {
1179 /* Note that sign-extension works for unsigned compares as
1180 long as both operands are sign-extended. */
1181 cmp->g1 = cmp->g2 = false;
1182 cmp->c1 = tcg_temp_new();
1183 cmp->c2 = tcg_temp_new();
1184 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1185 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1186 break;
2a484ecf
RH		 1187 }
1188#endif
1189 cmp->g1 = cmp->g2 = true;
1190 cmp->c1 = cpu_cc_src;
1191 cmp->c2 = cpu_cc_src2;
1192 break;
1193 }
8393617c 1194 break;
2a484ecf 1195
8393617c 1196 default:
2a484ecf 1197 do_dynamic:
2ffd9176 1198 gen_helper_compute_psr(cpu_env);
8393617c 1199 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1200 /* FALLTHRU */
1201
1202 case CC_OP_FLAGS:
1203 /* We're going to generate a boolean result. */
1204 cmp->cond = TCG_COND_NE;
1205 cmp->is_bool = true;
1206 cmp->g1 = cmp->g2 = false;
1207 cmp->c1 = r_dst = tcg_temp_new();
1208 cmp->c2 = tcg_const_tl(0);
1209
1210 switch (cond) {
1211 case 0x0:
1212 gen_op_eval_bn(r_dst);
1213 break;
1214 case 0x1:
1215 gen_op_eval_be(r_dst, r_src);
1216 break;
1217 case 0x2:
1218 gen_op_eval_ble(r_dst, r_src);
1219 break;
1220 case 0x3:
1221 gen_op_eval_bl(r_dst, r_src);
1222 break;
1223 case 0x4:
1224 gen_op_eval_bleu(r_dst, r_src);
1225 break;
1226 case 0x5:
1227 gen_op_eval_bcs(r_dst, r_src);
1228 break;
1229 case 0x6:
1230 gen_op_eval_bneg(r_dst, r_src);
1231 break;
1232 case 0x7:
1233 gen_op_eval_bvs(r_dst, r_src);
1234 break;
1235 case 0x8:
1236 gen_op_eval_ba(r_dst);
1237 break;
1238 case 0x9:
1239 gen_op_eval_bne(r_dst, r_src);
1240 break;
1241 case 0xa:
1242 gen_op_eval_bg(r_dst, r_src);
1243 break;
1244 case 0xb:
1245 gen_op_eval_bge(r_dst, r_src);
1246 break;
1247 case 0xc:
1248 gen_op_eval_bgu(r_dst, r_src);
1249 break;
1250 case 0xd:
1251 gen_op_eval_bcc(r_dst, r_src);
1252 break;
1253 case 0xe:
1254 gen_op_eval_bpos(r_dst, r_src);
1255 break;
1256 case 0xf:
1257 gen_op_eval_bvc(r_dst, r_src);
1258 break;
1259 }
19f329ad
BS		 1260 break;
1261 }
1262}
7a3f1944 1263
416fcaea 1264static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1265{
19f329ad 1266 unsigned int offset;
416fcaea
RH		 1267 TCGv r_dst;
1268
1269 /* For now we still generate a straight boolean result. */
1270 cmp->cond = TCG_COND_NE;
1271 cmp->is_bool = true;
1272 cmp->g1 = cmp->g2 = false;
1273 cmp->c1 = r_dst = tcg_temp_new();
1274 cmp->c2 = tcg_const_tl(0);
19f329ad 1275
19f329ad
BS		 1276 switch (cc) {
1277 default:
1278 case 0x0:
1279 offset = 0;
1280 break;
1281 case 0x1:
1282 offset = 32 - 10;
1283 break;
1284 case 0x2:
1285 offset = 34 - 10;
1286 break;
1287 case 0x3:
1288 offset = 36 - 10;
1289 break;
1290 }
1291
1292 switch (cond) {
1293 case 0x0:
1294 gen_op_eval_bn(r_dst);
1295 break;
1296 case 0x1:
87e92502 1297 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 case 0x2:
87e92502 1300 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1301 break;
1302 case 0x3:
87e92502 1303 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0x4:
87e92502 1306 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0x5:
87e92502 1309 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1310 break;
1311 case 0x6:
87e92502 1312 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0x7:
87e92502 1315 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0x8:
1318 gen_op_eval_ba(r_dst);
1319 break;
1320 case 0x9:
87e92502 1321 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1322 break;
1323 case 0xa:
87e92502 1324 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1325 break;
1326 case 0xb:
87e92502 1327 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1328 break;
1329 case 0xc:
87e92502 1330 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1331 break;
1332 case 0xd:
87e92502 1333 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1334 break;
1335 case 0xe:
87e92502 1336 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1337 break;
1338 case 0xf:
87e92502 1339 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1340 break;
1341 }
e8af50a3 1342}
00f219bf 1343
416fcaea
RH		 1344static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1345 DisasContext *dc)
1346{
1347 DisasCompare cmp;
1348 gen_compare(&cmp, cc, cond, dc);
1349
1350 /* The interface is to return a boolean in r_dst. */
1351 if (cmp.is_bool) {
1352 tcg_gen_mov_tl(r_dst, cmp.c1);
1353 } else {
1354 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1355 }
1356
1357 free_compare(&cmp);
1358}
1359
1360static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1361{
1362 DisasCompare cmp;
1363 gen_fcompare(&cmp, cc, cond);
1364
1365 /* The interface is to return a boolean in r_dst. */
1366 if (cmp.is_bool) {
1367 tcg_gen_mov_tl(r_dst, cmp.c1);
1368 } else {
1369 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1370 }
1371
1372 free_compare(&cmp);
1373}
1374
19f329ad 1375#ifdef TARGET_SPARC64
00f219bf
BS		 1376// Inverted logic
1377static const int gen_tcg_cond_reg[8] = {
1378 -1,
1379 TCG_COND_NE,
1380 TCG_COND_GT,
1381 TCG_COND_GE,
1382 -1,
1383 TCG_COND_EQ,
1384 TCG_COND_LE,
1385 TCG_COND_LT,
1386};
19f329ad 1387
416fcaea
RH		 1388static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1389{
1390 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1391 cmp->is_bool = false;
1392 cmp->g1 = true;
1393 cmp->g2 = false;
1394 cmp->c1 = r_src;
1395 cmp->c2 = tcg_const_tl(0);
1396}
1397
4af984a7 1398static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1399{
416fcaea
RH		 1400 DisasCompare cmp;
1401 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1402
416fcaea
RH		 1403 /* The interface is to return a boolean in r_dst. */
1404 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1405
1406 free_compare(&cmp);
19f329ad 1407}
3475187d 1408#endif
cf495bcf 1409
d4a288ef 1410static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1411{
cf495bcf 1412 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1413 target_ulong target = dc->pc + offset;
5fafdf24 1414
22036a49
AT		 1415#ifdef TARGET_SPARC64
1416 if (unlikely(AM_CHECK(dc))) {
1417 target &= 0xffffffffULL;
1418 }
1419#endif
cf495bcf 1420 if (cond == 0x0) {
0f8a249a
BS		 1421 /* unconditional not taken */
1422 if (a) {
1423 dc->pc = dc->npc + 4;
1424 dc->npc = dc->pc + 4;
1425 } else {
1426 dc->pc = dc->npc;
1427 dc->npc = dc->pc + 4;
1428 }
cf495bcf 1429 } else if (cond == 0x8) {
0f8a249a
BS		 1430 /* unconditional taken */
1431 if (a) {
1432 dc->pc = target;
1433 dc->npc = dc->pc + 4;
1434 } else {
1435 dc->pc = dc->npc;
1436 dc->npc = target;
c27e2752 1437 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1438 }
cf495bcf 1439 } else {
dee8913c 1440 flush_cond(dc);
d4a288ef 1441 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1442 if (a) {
bfa31b76 1443 gen_branch_a(dc, target);
0f8a249a 1444 } else {
2bf2e019 1445 gen_branch_n(dc, target);
0f8a249a 1446 }
cf495bcf 1447 }
7a3f1944
FB		 1448}
1449
d4a288ef 1450static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1451{
1452 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1453 target_ulong target = dc->pc + offset;
1454
22036a49
AT		 1455#ifdef TARGET_SPARC64
1456 if (unlikely(AM_CHECK(dc))) {
1457 target &= 0xffffffffULL;
1458 }
1459#endif
e8af50a3 1460 if (cond == 0x0) {
0f8a249a
BS		 1461 /* unconditional not taken */
1462 if (a) {
1463 dc->pc = dc->npc + 4;
1464 dc->npc = dc->pc + 4;
1465 } else {
1466 dc->pc = dc->npc;
1467 dc->npc = dc->pc + 4;
1468 }
e8af50a3 1469 } else if (cond == 0x8) {
0f8a249a
BS		 1470 /* unconditional taken */
1471 if (a) {
1472 dc->pc = target;
1473 dc->npc = dc->pc + 4;
1474 } else {
1475 dc->pc = dc->npc;
1476 dc->npc = target;
c27e2752 1477 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1478 }
e8af50a3 1479 } else {
dee8913c 1480 flush_cond(dc);
d4a288ef 1481 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1482 if (a) {
bfa31b76 1483 gen_branch_a(dc, target);
0f8a249a 1484 } else {
2bf2e019 1485 gen_branch_n(dc, target);
0f8a249a 1486 }
e8af50a3
FB		 1487 }
1488}
1489
3475187d 1490#ifdef TARGET_SPARC64
4af984a7 1491static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1492 TCGv r_reg)
7a3f1944 1493{
3475187d
FB		 1494 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1495 target_ulong target = dc->pc + offset;
1496
22036a49
AT		 1497 if (unlikely(AM_CHECK(dc))) {
1498 target &= 0xffffffffULL;
1499 }
dee8913c 1500 flush_cond(dc);
d4a288ef 1501 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1502 if (a) {
bfa31b76 1503 gen_branch_a(dc, target);
3475187d 1504 } else {
2bf2e019 1505 gen_branch_n(dc, target);
3475187d 1506 }
7a3f1944
FB		 1507}
1508
a7812ae4 1509static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1510{
714547bb
BS		 1511 switch (fccno) {
1512 case 0:
2e2f4ade 1513 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1514 break;
1515 case 1:
2e2f4ade 1516 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1517 break;
1518 case 2:
2e2f4ade 1519 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1520 break;
1521 case 3:
2e2f4ade 1522 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1523 break;
1524 }
7e8c2b6c
BS		 1525}
1526
03fb8cfc 1527static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1528{
a7812ae4
PB		 1529 switch (fccno) {
1530 case 0:
03fb8cfc 1531 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1532 break;
1533 case 1:
03fb8cfc 1534 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1535 break;
1536 case 2:
03fb8cfc 1537 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1538 break;
1539 case 3:
03fb8cfc 1540 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1541 break;
1542 }
7e8c2b6c
BS		 1543}
1544
7e8c2b6c
BS		 1545static inline void gen_op_fcmpq(int fccno)
1546{
a7812ae4
PB		 1547 switch (fccno) {
1548 case 0:
2e2f4ade 1549 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1550 break;
1551 case 1:
2e2f4ade 1552 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1553 break;
1554 case 2:
2e2f4ade 1555 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1556 break;
1557 case 3:
2e2f4ade 1558 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1559 break;
1560 }
7e8c2b6c 1561}
7e8c2b6c 1562
a7812ae4 1563static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1564{
714547bb
BS		 1565 switch (fccno) {
1566 case 0:
2e2f4ade 1567 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1568 break;
1569 case 1:
2e2f4ade 1570 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1571 break;
1572 case 2:
2e2f4ade 1573 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1574 break;
1575 case 3:
2e2f4ade 1576 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1577 break;
1578 }
7e8c2b6c
BS		 1579}
1580
03fb8cfc 1581static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1582{
a7812ae4
PB		 1583 switch (fccno) {
1584 case 0:
03fb8cfc 1585 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1586 break;
1587 case 1:
03fb8cfc 1588 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1589 break;
1590 case 2:
03fb8cfc 1591 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1592 break;
1593 case 3:
03fb8cfc 1594 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1595 break;
1596 }
7e8c2b6c
BS		 1597}
1598
7e8c2b6c
BS		 1599static inline void gen_op_fcmpeq(int fccno)
1600{
a7812ae4
PB		 1601 switch (fccno) {
1602 case 0:
2e2f4ade 1603 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1604 break;
1605 case 1:
2e2f4ade 1606 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1607 break;
1608 case 2:
2e2f4ade 1609 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1610 break;
1611 case 3:
2e2f4ade 1612 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1613 break;
1614 }
7e8c2b6c 1615}
7e8c2b6c
BS		 1616
1617#else
1618
714547bb 1619static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1620{
2e2f4ade 1621 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1622}
1623
03fb8cfc 1624static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1625{
03fb8cfc 1626 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1627}
1628
7e8c2b6c
BS		 1629static inline void gen_op_fcmpq(int fccno)
1630{
2e2f4ade 1631 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1632}
7e8c2b6c 1633
714547bb 1634static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1635{
2e2f4ade 1636 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1637}
1638
03fb8cfc 1639static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1640{
03fb8cfc 1641 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1642}
1643
7e8c2b6c
BS		 1644static inline void gen_op_fcmpeq(int fccno)
1645{
2e2f4ade 1646 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1647}
1648#endif
1649
4fbe0067 1650static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1651{
47ad35f1 1652 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1653 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1654 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1655}
1656
5b12f1e8 1657static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1658{
1659#if !defined(CONFIG_USER_ONLY)
1660 if (!dc->fpu_enabled) {
4fbe0067 1661 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1662 return 1;
1663 }
1664#endif
1665 return 0;
1666}
1667
7e8c2b6c
BS		 1668static inline void gen_op_clear_ieee_excp_and_FTT(void)
1669{
47ad35f1 1670 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1671}
1672
61f17f6e
RH		 1673static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1674 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1675{
1676 TCGv_i32 dst, src;
1677
61f17f6e 1678 src = gen_load_fpr_F(dc, rs);
ba5f5179 1679 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1680
1681 gen(dst, cpu_env, src);
1682
61f17f6e
RH		 1683 gen_store_fpr_F(dc, rd, dst);
1684}
1685
1686static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1687 void (*gen)(TCGv_i32, TCGv_i32))
1688{
1689 TCGv_i32 dst, src;
1690
1691 src = gen_load_fpr_F(dc, rs);
ba5f5179 1692 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1693
1694 gen(dst, src);
1695
1696 gen_store_fpr_F(dc, rd, dst);
1697}
1698
1699static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1700 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1701{
1702 TCGv_i32 dst, src1, src2;
1703
61f17f6e
RH		 1704 src1 = gen_load_fpr_F(dc, rs1);
1705 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1706 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1707
1708 gen(dst, cpu_env, src1, src2);
1709
61f17f6e
RH		 1710 gen_store_fpr_F(dc, rd, dst);
1711}
1712
1713#ifdef TARGET_SPARC64
1714static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1715 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1716{
1717 TCGv_i32 dst, src1, src2;
1718
1719 src1 = gen_load_fpr_F(dc, rs1);
1720 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1721 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1722
1723 gen(dst, src1, src2);
1724
1725 gen_store_fpr_F(dc, rd, dst);
1726}
1727#endif
1728
1729static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1730 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1731{
1732 TCGv_i64 dst, src;
1733
61f17f6e 1734 src = gen_load_fpr_D(dc, rs);
3886b8a3 1735 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1736
1737 gen(dst, cpu_env, src);
1738
61f17f6e
RH		 1739 gen_store_fpr_D(dc, rd, dst);
1740}
1741
1742#ifdef TARGET_SPARC64
1743static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1744 void (*gen)(TCGv_i64, TCGv_i64))
1745{
1746 TCGv_i64 dst, src;
1747
1748 src = gen_load_fpr_D(dc, rs);
3886b8a3 1749 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1750
1751 gen(dst, src);
1752
1753 gen_store_fpr_D(dc, rd, dst);
1754}
1755#endif
1756
1757static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1758 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1759{
1760 TCGv_i64 dst, src1, src2;
1761
61f17f6e
RH		 1762 src1 = gen_load_fpr_D(dc, rs1);
1763 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1764 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1765
1766 gen(dst, cpu_env, src1, src2);
1767
61f17f6e
RH		 1768 gen_store_fpr_D(dc, rd, dst);
1769}
1770
1771#ifdef TARGET_SPARC64
1772static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1773 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1774{
1775 TCGv_i64 dst, src1, src2;
1776
1777 src1 = gen_load_fpr_D(dc, rs1);
1778 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1779 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1780
1781 gen(dst, src1, src2);
1782
1783 gen_store_fpr_D(dc, rd, dst);
1784}
f888300b 1785
2dedf314
RH		 1786static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1787 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1788{
1789 TCGv_i64 dst, src1, src2;
1790
1791 src1 = gen_load_fpr_D(dc, rs1);
1792 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1793 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1794
1795 gen(dst, cpu_gsr, src1, src2);
1796
1797 gen_store_fpr_D(dc, rd, dst);
1798}
1799
f888300b
RH		 1800static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1801 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1802{
1803 TCGv_i64 dst, src0, src1, src2;
1804
1805 src1 = gen_load_fpr_D(dc, rs1);
1806 src2 = gen_load_fpr_D(dc, rs2);
1807 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1808 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1809
1810 gen(dst, src0, src1, src2);
1811
1812 gen_store_fpr_D(dc, rd, dst);
1813}
61f17f6e
RH		 1814#endif
1815
1816static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1817 void (*gen)(TCGv_ptr))
1818{
61f17f6e
RH		 1819 gen_op_load_fpr_QT1(QFPREG(rs));
1820
1821 gen(cpu_env);
1822
61f17f6e
RH		 1823 gen_op_store_QT0_fpr(QFPREG(rd));
1824 gen_update_fprs_dirty(QFPREG(rd));
1825}
1826
1827#ifdef TARGET_SPARC64
1828static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1829 void (*gen)(TCGv_ptr))
1830{
1831 gen_op_load_fpr_QT1(QFPREG(rs));
1832
1833 gen(cpu_env);
1834
1835 gen_op_store_QT0_fpr(QFPREG(rd));
1836 gen_update_fprs_dirty(QFPREG(rd));
1837}
1838#endif
1839
1840static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1841 void (*gen)(TCGv_ptr))
1842{
61f17f6e
RH		 1843 gen_op_load_fpr_QT0(QFPREG(rs1));
1844 gen_op_load_fpr_QT1(QFPREG(rs2));
1845
1846 gen(cpu_env);
1847
61f17f6e
RH		 1848 gen_op_store_QT0_fpr(QFPREG(rd));
1849 gen_update_fprs_dirty(QFPREG(rd));
1850}
1851
1852static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1853 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1854{
1855 TCGv_i64 dst;
1856 TCGv_i32 src1, src2;
1857
61f17f6e
RH		 1858 src1 = gen_load_fpr_F(dc, rs1);
1859 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1860 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1861
1862 gen(dst, cpu_env, src1, src2);
1863
61f17f6e
RH		 1864 gen_store_fpr_D(dc, rd, dst);
1865}
1866
1867static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1868 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1869{
1870 TCGv_i64 src1, src2;
1871
61f17f6e
RH		 1872 src1 = gen_load_fpr_D(dc, rs1);
1873 src2 = gen_load_fpr_D(dc, rs2);
1874
1875 gen(cpu_env, src1, src2);
1876
61f17f6e
RH		 1877 gen_op_store_QT0_fpr(QFPREG(rd));
1878 gen_update_fprs_dirty(QFPREG(rd));
1879}
1880
1881#ifdef TARGET_SPARC64
1882static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1883 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1884{
1885 TCGv_i64 dst;
1886 TCGv_i32 src;
1887
61f17f6e 1888 src = gen_load_fpr_F(dc, rs);
3886b8a3 1889 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1890
1891 gen(dst, cpu_env, src);
1892
61f17f6e
RH		 1893 gen_store_fpr_D(dc, rd, dst);
1894}
1895#endif
1896
1897static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1898 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1899{
1900 TCGv_i64 dst;
1901 TCGv_i32 src;
1902
1903 src = gen_load_fpr_F(dc, rs);
3886b8a3 1904 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1905
1906 gen(dst, cpu_env, src);
1907
1908 gen_store_fpr_D(dc, rd, dst);
1909}
1910
1911static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1912 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1913{
1914 TCGv_i32 dst;
1915 TCGv_i64 src;
1916
61f17f6e 1917 src = gen_load_fpr_D(dc, rs);
ba5f5179 1918 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1919
1920 gen(dst, cpu_env, src);
1921
61f17f6e
RH		 1922 gen_store_fpr_F(dc, rd, dst);
1923}
1924
1925static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1926 void (*gen)(TCGv_i32, TCGv_ptr))
1927{
1928 TCGv_i32 dst;
1929
61f17f6e 1930 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1931 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1932
1933 gen(dst, cpu_env);
1934
61f17f6e
RH		 1935 gen_store_fpr_F(dc, rd, dst);
1936}
1937
1938static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1939 void (*gen)(TCGv_i64, TCGv_ptr))
1940{
1941 TCGv_i64 dst;
1942
61f17f6e 1943 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1944 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1945
1946 gen(dst, cpu_env);
1947
61f17f6e
RH		 1948 gen_store_fpr_D(dc, rd, dst);
1949}
1950
1951static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1952 void (*gen)(TCGv_ptr, TCGv_i32))
1953{
1954 TCGv_i32 src;
1955
1956 src = gen_load_fpr_F(dc, rs);
1957
1958 gen(cpu_env, src);
1959
1960 gen_op_store_QT0_fpr(QFPREG(rd));
1961 gen_update_fprs_dirty(QFPREG(rd));
1962}
1963
1964static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1965 void (*gen)(TCGv_ptr, TCGv_i64))
1966{
1967 TCGv_i64 src;
1968
1969 src = gen_load_fpr_D(dc, rs);
1970
1971 gen(cpu_env, src);
1972
1973 gen_op_store_QT0_fpr(QFPREG(rd));
1974 gen_update_fprs_dirty(QFPREG(rd));
1975}
1976
1a2fb1c0 1977/* asi moves */
22e70060
RH		 1978#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1979static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
1a2fb1c0 1980{
a6d567e5 1981 int asi;
1a2fb1c0 1982
1a2fb1c0 1983 if (IS_IMM) {
22e70060 1984#ifdef TARGET_SPARC64
a6d567e5 1985 asi = dc->asi;
22e70060
RH		 1986#else
1987 gen_exception(dc, TT_ILL_INSN);
a6d567e5 1988 asi = 0;
22e70060 1989#endif
1a2fb1c0 1990 } else {
a6d567e5 1991 asi = GET_FIELD(insn, 19, 26);
1a2fb1c0 1992 }
a6d567e5 1993 return tcg_const_i32(asi);
0425bee5
BS		 1994}
1995
22e70060
RH		 1996static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
1997 int insn, int size, int sign)
0425bee5 1998{
a7812ae4 1999 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 2000
22e70060 2001 r_asi = gen_get_asi(dc, insn);
2ea815ca
BS		 2002 r_size = tcg_const_i32(size);
2003 r_sign = tcg_const_i32(sign);
22e70060 2004#ifdef TARGET_SPARC64
fe8d8f0f 2005 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
22e70060
RH		 2006#else
2007 {
2008 TCGv_i64 t64 = tcg_temp_new_i64();
2009 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2010 tcg_gen_trunc_i64_tl(dst, t64);
2011 tcg_temp_free_i64(t64);
2012 }
2013#endif
a7812ae4
PB		 2014 tcg_temp_free_i32(r_sign);
2015 tcg_temp_free_i32(r_size);
2016 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2017}
2018
22e70060
RH		 2019static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
2020 int insn, int size)
1a2fb1c0 2021{
a7812ae4 2022 TCGv_i32 r_asi, r_size;
1a2fb1c0 2023
22e70060 2024 r_asi = gen_get_asi(dc, insn);
2ea815ca 2025 r_size = tcg_const_i32(size);
22e70060 2026#ifdef TARGET_SPARC64
fe8d8f0f 2027 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
22e70060
RH		 2028#else
2029 {
2030 TCGv_i64 t64 = tcg_temp_new_i64();
2031 tcg_gen_extu_tl_i64(t64, src);
2032 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2033 tcg_temp_free_i64(t64);
2034 }
2035#endif
a7812ae4
PB		 2036 tcg_temp_free_i32(r_size);
2037 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2038}
2039
22e70060
RH		 2040static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2041 TCGv addr, int insn)
1a2fb1c0 2042{
22e70060
RH		 2043 TCGv_i32 r_asi, r_size, r_sign;
2044 TCGv_i64 s64, t64 = tcg_temp_new_i64();
1a2fb1c0 2045
22e70060
RH		 2046 r_asi = gen_get_asi(dc, insn);
2047 r_size = tcg_const_i32(4);
2048 r_sign = tcg_const_i32(0);
2049 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2050 tcg_temp_free_i32(r_sign);
2051
2052 s64 = tcg_temp_new_i64();
2053 tcg_gen_extu_tl_i64(s64, src);
2054 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
2055 tcg_temp_free_i64(s64);
a7812ae4
PB		 2056 tcg_temp_free_i32(r_size);
2057 tcg_temp_free_i32(r_asi);
22e70060
RH		 2058
2059 tcg_gen_trunc_i64_tl(dst, t64);
2060 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2061}
2062
22e70060
RH		 2063static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
2064 int insn, int rd)
2065{
2066 TCGv val1 = gen_load_gpr(dc, rd);
2067 TCGv dst = gen_dest_gpr(dc, rd);
2068 TCGv_i32 r_asi = gen_get_asi(dc, insn);
2069
2070 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2071 tcg_temp_free_i32(r_asi);
2072 gen_store_gpr(dc, rd, dst);
2073}
2074
2075static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2076{
2077 TCGv_i32 r_asi, r_size, r_sign;
2078 TCGv_i64 s64, d64 = tcg_temp_new_i64();
2079
2080 r_asi = gen_get_asi(dc, insn);
2081 r_size = tcg_const_i32(1);
2082 r_sign = tcg_const_i32(0);
2083 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_size, r_sign);
2084 tcg_temp_free_i32(r_sign);
2085
2086 s64 = tcg_const_i64(0xff);
2087 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
2088 tcg_temp_free_i64(s64);
2089 tcg_temp_free_i32(r_size);
2090 tcg_temp_free_i32(r_asi);
2091
2092 tcg_gen_trunc_i64_tl(dst, d64);
2093 tcg_temp_free_i64(d64);
2094}
2095#endif
2096
2097#ifdef TARGET_SPARC64
2098static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2099 int insn, int size, int rd)
1a2fb1c0 2100{
a7812ae4 2101 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2102
22e70060 2103 r_asi = gen_get_asi(dc, insn);
2ea815ca
BS		 2104 r_size = tcg_const_i32(size);
2105 r_rd = tcg_const_i32(rd);
22e70060 2106 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2107 tcg_temp_free_i32(r_rd);
2108 tcg_temp_free_i32(r_size);
2109 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2110}
2111
22e70060
RH		 2112static void gen_stf_asi(DisasContext *dc, TCGv addr,
2113 int insn, int size, int rd)
1a2fb1c0 2114{
22e70060 2115 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2116
22e70060
RH		 2117 r_asi = gen_get_asi(dc, insn);
2118 r_size = tcg_const_i32(size);
2119 r_rd = tcg_const_i32(rd);
2120 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
2121 tcg_temp_free_i32(r_rd);
a7812ae4
PB		 2122 tcg_temp_free_i32(r_size);
2123 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2124}
2125
22e70060
RH		 2126static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2127 int insn, int rd)
1a2fb1c0 2128{
a7812ae4 2129 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2130
22e70060 2131 r_asi = gen_get_asi(dc, insn);
db166940 2132 r_rd = tcg_const_i32(rd);
fe8d8f0f 2133 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2134 tcg_temp_free_i32(r_rd);
2135 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2136}
2137
22e70060
RH		 2138static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2139 int insn, int rd)
0425bee5 2140{
a7812ae4 2141 TCGv_i32 r_asi, r_size;
c7785e16 2142 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2143 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2144
1ec789ab 2145 tcg_gen_concat_tl_i64(t64, lo, hi);
22e70060 2146 r_asi = gen_get_asi(dc, insn);
2ea815ca 2147 r_size = tcg_const_i32(8);
1ec789ab 2148 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2149 tcg_temp_free_i32(r_size);
2150 tcg_temp_free_i32(r_asi);
1ec789ab 2151 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2152}
2153
22e70060
RH		 2154static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
2155 int insn, int rd)
1a2fb1c0 2156{
81634eea
RH		 2157 TCGv val1 = gen_load_gpr(dc, rd);
2158 TCGv dst = gen_dest_gpr(dc, rd);
22e70060 2159 TCGv_i32 r_asi = gen_get_asi(dc, insn);
1a2fb1c0 2160
81634eea 2161 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2162 tcg_temp_free_i32(r_asi);
81634eea 2163 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2164}
2165
2166#elif !defined(CONFIG_USER_ONLY)
22e70060
RH		 2167static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2168 int insn, int rd)
1a2fb1c0 2169{
a7812ae4 2170 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2171 TCGv t;
1ec789ab 2172 TCGv_i64 t64;
1a2fb1c0 2173
22e70060 2174 r_asi = gen_get_asi(dc, insn);
2ea815ca
BS		 2175 r_size = tcg_const_i32(8);
2176 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2177 t64 = tcg_temp_new_i64();
2178 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2179 tcg_temp_free_i32(r_sign);
2180 tcg_temp_free_i32(r_size);
2181 tcg_temp_free_i32(r_asi);
c7785e16 2182
d2dc4069
RH		 2183 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2184 whereby "rd + 1" elicits "error: array subscript is above array".
2185 Since we have already asserted that rd is even, the semantics
2186 are unchanged. */
2187 t = gen_dest_gpr(dc, rd | 1);
1ec789ab 2188 tcg_gen_trunc_i64_tl(t, t64);
d2dc4069 2189 gen_store_gpr(dc, rd | 1, t);
c7785e16 2190
1ec789ab
RH		 2191 tcg_gen_shri_i64(t64, t64, 32);
2192 tcg_gen_trunc_i64_tl(hi, t64);
2193 tcg_temp_free_i64(t64);
c7785e16 2194 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2195}
2196
22e70060
RH		 2197static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2198 int insn, int rd)
0425bee5 2199{
a7812ae4 2200 TCGv_i32 r_asi, r_size;
c7785e16 2201 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2202 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2203
1ec789ab 2204 tcg_gen_concat_tl_i64(t64, lo, hi);
22e70060 2205 r_asi = gen_get_asi(dc, insn);
2ea815ca 2206 r_size = tcg_const_i32(8);
1ec789ab
RH		 2207 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2208 tcg_temp_free_i32(r_size);
2209 tcg_temp_free_i32(r_asi);
2210 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2211}
2212#endif
2213
9d1d4e34 2214static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2215{
9d1d4e34
RH		 2216 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2217 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2218}
2219
9d1d4e34 2220static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2221{
a49d9390 2222 if (IS_IMM) { /* immediate */
42a8aa83 2223 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2224 TCGv t = get_temp_tl(dc);
2225 tcg_gen_movi_tl(t, simm);
2226 return t;
2227 } else { /* register */
42a8aa83 2228 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2229 return gen_load_gpr(dc, rs2);
a49d9390 2230 }
a49d9390
BS		 2231}
2232
8194f35a 2233#ifdef TARGET_SPARC64
7e480893
RH		 2234static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2235{
2236 TCGv_i32 c32, zero, dst, s1, s2;
2237
2238 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2239 or fold the comparison down to 32 bits and use movcond_i32. Choose
2240 the later. */
2241 c32 = tcg_temp_new_i32();
2242 if (cmp->is_bool) {
ecc7b3aa 2243 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2244 } else {
2245 TCGv_i64 c64 = tcg_temp_new_i64();
2246 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2247 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2248 tcg_temp_free_i64(c64);
2249 }
2250
2251 s1 = gen_load_fpr_F(dc, rs);
2252 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2253 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2254 zero = tcg_const_i32(0);
2255
2256 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2257
2258 tcg_temp_free_i32(c32);
2259 tcg_temp_free_i32(zero);
2260 gen_store_fpr_F(dc, rd, dst);
2261}
2262
2263static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2264{
3886b8a3 2265 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2266 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2267 gen_load_fpr_D(dc, rs),
2268 gen_load_fpr_D(dc, rd));
2269 gen_store_fpr_D(dc, rd, dst);
2270}
2271
2272static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2273{
2274 int qd = QFPREG(rd);
2275 int qs = QFPREG(rs);
2276
2277 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2278 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2279 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2280 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2281
2282 gen_update_fprs_dirty(qd);
2283}
2284
a2035e83 2285#ifndef CONFIG_USER_ONLY
1bcea73e 2286static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2287{
b551ec04 2288 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2289
2290 /* load env->tl into r_tl */
b551ec04 2291 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2292
2293 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2294 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2295
2296 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2297 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2298 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2299
2300 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2301 {
2302 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2303 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2304 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2305 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2306 }
8194f35a 2307
b551ec04 2308 tcg_temp_free_i32(r_tl);
8194f35a 2309}
a2035e83 2310#endif
6c073553
RH		 2311
2312static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2313 int width, bool cc, bool left)
2314{
2315 TCGv lo1, lo2, t1, t2;
2316 uint64_t amask, tabl, tabr;
2317 int shift, imask, omask;
2318
2319 if (cc) {
2320 tcg_gen_mov_tl(cpu_cc_src, s1);
2321 tcg_gen_mov_tl(cpu_cc_src2, s2);
2322 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2323 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2324 dc->cc_op = CC_OP_SUB;
2325 }
2326
2327 /* Theory of operation: there are two tables, left and right (not to
2328 be confused with the left and right versions of the opcode). These
2329 are indexed by the low 3 bits of the inputs. To make things "easy",
2330 these tables are loaded into two constants, TABL and TABR below.
2331 The operation index = (input & imask) << shift calculates the index
2332 into the constant, while val = (table >> index) & omask calculates
2333 the value we're looking for. */
2334 switch (width) {
2335 case 8:
2336 imask = 0x7;
2337 shift = 3;
2338 omask = 0xff;
2339 if (left) {
2340 tabl = 0x80c0e0f0f8fcfeffULL;
2341 tabr = 0xff7f3f1f0f070301ULL;
2342 } else {
2343 tabl = 0x0103070f1f3f7fffULL;
2344 tabr = 0xfffefcf8f0e0c080ULL;
2345 }
2346 break;
2347 case 16:
2348 imask = 0x6;
2349 shift = 1;
2350 omask = 0xf;
2351 if (left) {
2352 tabl = 0x8cef;
2353 tabr = 0xf731;
2354 } else {
2355 tabl = 0x137f;
2356 tabr = 0xfec8;
2357 }
2358 break;
2359 case 32:
2360 imask = 0x4;
2361 shift = 0;
2362 omask = 0x3;
2363 if (left) {
2364 tabl = (2 << 2) | 3;
2365 tabr = (3 << 2) | 1;
2366 } else {
2367 tabl = (1 << 2) | 3;
2368 tabr = (3 << 2) | 2;
2369 }
2370 break;
2371 default:
2372 abort();
2373 }
2374
2375 lo1 = tcg_temp_new();
2376 lo2 = tcg_temp_new();
2377 tcg_gen_andi_tl(lo1, s1, imask);
2378 tcg_gen_andi_tl(lo2, s2, imask);
2379 tcg_gen_shli_tl(lo1, lo1, shift);
2380 tcg_gen_shli_tl(lo2, lo2, shift);
2381
2382 t1 = tcg_const_tl(tabl);
2383 t2 = tcg_const_tl(tabr);
2384 tcg_gen_shr_tl(lo1, t1, lo1);
2385 tcg_gen_shr_tl(lo2, t2, lo2);
2386 tcg_gen_andi_tl(dst, lo1, omask);
2387 tcg_gen_andi_tl(lo2, lo2, omask);
2388
2389 amask = -8;
2390 if (AM_CHECK(dc)) {
2391 amask &= 0xffffffffULL;
2392 }
2393 tcg_gen_andi_tl(s1, s1, amask);
2394 tcg_gen_andi_tl(s2, s2, amask);
2395
2396 /* We want to compute
2397 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2398 We've already done dst = lo1, so this reduces to
2399 dst &= (s1 == s2 ? -1 : lo2)
2400 Which we perform by
2401 lo2 |= -(s1 == s2)
2402 dst &= lo2
2403 */
2404 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2405 tcg_gen_neg_tl(t1, t1);
2406 tcg_gen_or_tl(lo2, lo2, t1);
2407 tcg_gen_and_tl(dst, dst, lo2);
2408
2409 tcg_temp_free(lo1);
2410 tcg_temp_free(lo2);
2411 tcg_temp_free(t1);
2412 tcg_temp_free(t2);
2413}
add545ab
RH		 2414
2415static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2416{
2417 TCGv tmp = tcg_temp_new();
2418
2419 tcg_gen_add_tl(tmp, s1, s2);
2420 tcg_gen_andi_tl(dst, tmp, -8);
2421 if (left) {
2422 tcg_gen_neg_tl(tmp, tmp);
2423 }
2424 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2425
2426 tcg_temp_free(tmp);
2427}
50c796f9
RH		 2428
2429static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2430{
2431 TCGv t1, t2, shift;
2432
2433 t1 = tcg_temp_new();
2434 t2 = tcg_temp_new();
2435 shift = tcg_temp_new();
2436
2437 tcg_gen_andi_tl(shift, gsr, 7);
2438 tcg_gen_shli_tl(shift, shift, 3);
2439 tcg_gen_shl_tl(t1, s1, shift);
2440
2441 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2442 shift of (up to 63) followed by a constant shift of 1. */
2443 tcg_gen_xori_tl(shift, shift, 63);
2444 tcg_gen_shr_tl(t2, s2, shift);
2445 tcg_gen_shri_tl(t2, t2, 1);
2446
2447 tcg_gen_or_tl(dst, t1, t2);
2448
2449 tcg_temp_free(t1);
2450 tcg_temp_free(t2);
2451 tcg_temp_free(shift);
2452}
8194f35a
IK		 2453#endif
2454
64a88d5d 2455#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2456 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2457 goto illegal_insn;
2458#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2459 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2460 goto nfpu_insn;
2461
0bee699e 2462/* before an instruction, dc->pc must be static */
0184e266 2463static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2464{
0184e266 2465 unsigned int opc, rs1, rs2, rd;
a4273524 2466 TCGv cpu_src1, cpu_src2;
208ae657 2467 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2468 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2469 target_long simm;
7a3f1944 2470
cf495bcf 2471 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2472 rd = GET_FIELD(insn, 2, 6);
6ae20372 2473
cf495bcf 2474 switch (opc) {
0f8a249a
BS		 2475 case 0: /* branches/sethi */
2476 {
2477 unsigned int xop = GET_FIELD(insn, 7, 9);
2478 int32_t target;
2479 switch (xop) {
3475187d 2480#ifdef TARGET_SPARC64
0f8a249a
BS		 2481 case 0x1: /* V9 BPcc */
2482 {
2483 int cc;
2484
2485 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2486 target = sign_extend(target, 19);
0f8a249a
BS		 2487 target <<= 2;
2488 cc = GET_FIELD_SP(insn, 20, 21);
2489 if (cc == 0)
d4a288ef 2490 do_branch(dc, target, insn, 0);
0f8a249a 2491 else if (cc == 2)
d4a288ef 2492 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2493 else
2494 goto illegal_insn;
2495 goto jmp_insn;
2496 }
2497 case 0x3: /* V9 BPr */
2498 {
2499 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2500 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2501 target = sign_extend(target, 16);
2502 target <<= 2;
9d1d4e34 2503 cpu_src1 = get_src1(dc, insn);
d4a288ef 2504 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2505 goto jmp_insn;
2506 }
2507 case 0x5: /* V9 FBPcc */
2508 {
2509 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2510 if (gen_trap_ifnofpu(dc)) {
a80dde08 2511 goto jmp_insn;
5b12f1e8 2512 }
0f8a249a
BS		 2513 target = GET_FIELD_SP(insn, 0, 18);
2514 target = sign_extend(target, 19);
2515 target <<= 2;
d4a288ef 2516 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2517 goto jmp_insn;
2518 }
a4d17f19 2519#else
0f8a249a
BS		 2520 case 0x7: /* CBN+x */
2521 {
2522 goto ncp_insn;
2523 }
2524#endif
2525 case 0x2: /* BN+x */
2526 {
2527 target = GET_FIELD(insn, 10, 31);
2528 target = sign_extend(target, 22);
2529 target <<= 2;
d4a288ef 2530 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2531 goto jmp_insn;
2532 }
2533 case 0x6: /* FBN+x */
2534 {
5b12f1e8 2535 if (gen_trap_ifnofpu(dc)) {
a80dde08 2536 goto jmp_insn;
5b12f1e8 2537 }
0f8a249a
BS		 2538 target = GET_FIELD(insn, 10, 31);
2539 target = sign_extend(target, 22);
2540 target <<= 2;
d4a288ef 2541 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2542 goto jmp_insn;
2543 }
2544 case 0x4: /* SETHI */
97ea2859
RH		 2545 /* Special-case %g0 because that's the canonical nop. */
2546 if (rd) {
0f8a249a 2547 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2548 TCGv t = gen_dest_gpr(dc, rd);
2549 tcg_gen_movi_tl(t, value << 10);
2550 gen_store_gpr(dc, rd, t);
0f8a249a 2551 }
0f8a249a
BS		 2552 break;
2553 case 0x0: /* UNIMPL */
2554 default:
3475187d 2555 goto illegal_insn;
0f8a249a
BS		 2556 }
2557 break;
2558 }
2559 break;
dc1a6971
BS		 2560 case 1: /*CALL*/
2561 {
0f8a249a 2562 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2563 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2564
97ea2859
RH		 2565 tcg_gen_movi_tl(o7, dc->pc);
2566 gen_store_gpr(dc, 15, o7);
0f8a249a 2567 target += dc->pc;
13a6dd00 2568 gen_mov_pc_npc(dc);
22036a49
AT		 2569#ifdef TARGET_SPARC64
2570 if (unlikely(AM_CHECK(dc))) {
2571 target &= 0xffffffffULL;
2572 }
2573#endif
0f8a249a
BS		 2574 dc->npc = target;
2575 }
2576 goto jmp_insn;
2577 case 2: /* FPU & Logical Operations */
2578 {
2579 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2580 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2581 TCGv cpu_tmp0;
5793f2a4 2582
0f8a249a 2583 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2584 int cond = GET_FIELD(insn, 3, 6);
2585 TCGv_i32 trap;
42a268c2
RH		 2586 TCGLabel *l1 = NULL;
2587 int mask;
3475187d 2588
bd49ed41
RH		 2589 if (cond == 0) {
2590 /* Trap never. */
2591 break;
cf495bcf 2592 }
b04d9890 2593
bd49ed41 2594 save_state(dc);
b04d9890 2595
bd49ed41
RH		 2596 if (cond != 8) {
2597 /* Conditional trap. */
3a49e759 2598 DisasCompare cmp;
3475187d 2599#ifdef TARGET_SPARC64
0f8a249a
BS		 2600 /* V9 icc/xcc */
2601 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2602 if (cc == 0) {
2603 gen_compare(&cmp, 0, cond, dc);
2604 } else if (cc == 2) {
2605 gen_compare(&cmp, 1, cond, dc);
2606 } else {
0f8a249a 2607 goto illegal_insn;
3a49e759 2608 }
3475187d 2609#else
3a49e759 2610 gen_compare(&cmp, 0, cond, dc);
3475187d 2611#endif
b158a785 2612 l1 = gen_new_label();
3a49e759
RH		 2613 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2614 cmp.c1, cmp.c2, l1);
2615 free_compare(&cmp);
bd49ed41 2616 }
b158a785 2617
bd49ed41
RH		 2618 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2619 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2620
2621 /* Don't use the normal temporaries, as they may well have
2622 gone out of scope with the branch above. While we're
2623 doing that we might as well pre-truncate to 32-bit. */
2624 trap = tcg_temp_new_i32();
2625
2626 rs1 = GET_FIELD_SP(insn, 14, 18);
2627 if (IS_IMM) {
2628 rs2 = GET_FIELD_SP(insn, 0, 6);
2629 if (rs1 == 0) {
2630 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2631 /* Signal that the trap value is fully constant. */
2632 mask = 0;
2633 } else {
97ea2859 2634 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2635 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2636 tcg_gen_addi_i32(trap, trap, rs2);
2637 }
2638 } else {
97ea2859 2639 TCGv t1, t2;
bd49ed41 2640 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2641 t1 = gen_load_gpr(dc, rs1);
2642 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2643 tcg_gen_add_tl(t1, t1, t2);
2644 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2645 }
2646 if (mask != 0) {
2647 tcg_gen_andi_i32(trap, trap, mask);
2648 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2649 }
2650
2651 gen_helper_raise_exception(cpu_env, trap);
2652 tcg_temp_free_i32(trap);
b158a785 2653
fe1755cb
RH		 2654 if (cond == 8) {
2655 /* An unconditional trap ends the TB. */
2656 dc->is_br = 1;
2657 goto jmp_insn;
2658 } else {
2659 /* A conditional trap falls through to the next insn. */
b158a785 2660 gen_set_label(l1);
fe1755cb 2661 break;
cf495bcf
FB		 2662 }
2663 } else if (xop == 0x28) {
2664 rs1 = GET_FIELD(insn, 13, 17);
2665 switch(rs1) {
2666 case 0: /* rdy */
65fe7b09
BS		 2667#ifndef TARGET_SPARC64
2668 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2669 manual, rdy on the microSPARC
2670 II */
2671 case 0x0f: /* stbar in the SPARCv8 manual,
2672 rdy on the microSPARC II */
2673 case 0x10 ... 0x1f: /* implementation-dependent in the
2674 SPARCv8 manual, rdy on the
2675 microSPARC II */
4a2ba232
FC		 2676 /* Read Asr17 */
2677 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2678 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2679 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2680 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2681 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2682 break;
2683 }
65fe7b09 2684#endif
97ea2859 2685 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2686 break;
3475187d 2687#ifdef TARGET_SPARC64
0f8a249a 2688 case 0x2: /* V9 rdccr */
20132b96 2689 update_psr(dc);
063c3675 2690 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2691 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2692 break;
0f8a249a 2693 case 0x3: /* V9 rdasi */
a6d567e5 2694 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 2695 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2696 break;
0f8a249a 2697 case 0x4: /* V9 rdtick */
ccd4a219 2698 {
a7812ae4 2699 TCGv_ptr r_tickptr;
c9a46442 2700 TCGv_i32 r_const;
ccd4a219 2701
a7812ae4 2702 r_tickptr = tcg_temp_new_ptr();
c9a46442 2703 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2704 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2705 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2706 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2707 r_const);
a7812ae4 2708 tcg_temp_free_ptr(r_tickptr);
c9a46442 2709 tcg_temp_free_i32(r_const);
97ea2859 2710 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2711 }
3475187d 2712 break;
0f8a249a 2713 case 0x5: /* V9 rdpc */
2ea815ca 2714 {
97ea2859 2715 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2716 if (unlikely(AM_CHECK(dc))) {
97ea2859 2717 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2718 } else {
97ea2859 2719 tcg_gen_movi_tl(t, dc->pc);
22036a49 2720 }
97ea2859 2721 gen_store_gpr(dc, rd, t);
2ea815ca 2722 }
0f8a249a
BS		 2723 break;
2724 case 0x6: /* V9 rdfprs */
255e1fcb 2725 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2726 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2727 break;
65fe7b09
BS		 2728 case 0xf: /* V9 membar */
2729 break; /* no effect */
0f8a249a 2730 case 0x13: /* Graphics Status */
5b12f1e8 2731 if (gen_trap_ifnofpu(dc)) {
725cb90b 2732 goto jmp_insn;
5b12f1e8 2733 }
97ea2859 2734 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2735 break;
9d926598 2736 case 0x16: /* Softint */
e86ceb0d
RH		 2737 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
2738 offsetof(CPUSPARCState, softint));
97ea2859 2739 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2740 break;
0f8a249a 2741 case 0x17: /* Tick compare */
97ea2859 2742 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2743 break;
0f8a249a 2744 case 0x18: /* System tick */
ccd4a219 2745 {
a7812ae4 2746 TCGv_ptr r_tickptr;
c9a46442 2747 TCGv_i32 r_const;
ccd4a219 2748
a7812ae4 2749 r_tickptr = tcg_temp_new_ptr();
c9a46442 2750 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2751 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2752 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 2753 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2754 r_const);
a7812ae4 2755 tcg_temp_free_ptr(r_tickptr);
c9a46442 2756 tcg_temp_free_i32(r_const);
97ea2859 2757 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2758 }
83469015 2759 break;
0f8a249a 2760 case 0x19: /* System tick compare */
97ea2859 2761 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2762 break;
0f8a249a
BS		 2763 case 0x10: /* Performance Control */
2764 case 0x11: /* Performance Instrumentation Counter */
2765 case 0x12: /* Dispatch Control */
2766 case 0x14: /* Softint set, WO */
2767 case 0x15: /* Softint clear, WO */
3475187d
FB		 2768#endif
2769 default:
cf495bcf
FB		 2770 goto illegal_insn;
2771 }
e8af50a3 2772#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2773 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2774#ifndef TARGET_SPARC64
20132b96 2775 if (!supervisor(dc)) {
0f8a249a 2776 goto priv_insn;
20132b96
RH		 2777 }
2778 update_psr(dc);
063c3675 2779 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2780#else
fb79ceb9 2781 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2782 if (!hypervisor(dc))
2783 goto priv_insn;
2784 rs1 = GET_FIELD(insn, 13, 17);
2785 switch (rs1) {
2786 case 0: // hpstate
2787 // gen_op_rdhpstate();
2788 break;
2789 case 1: // htstate
2790 // gen_op_rdhtstate();
2791 break;
2792 case 3: // hintp
255e1fcb 2793 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2794 break;
2795 case 5: // htba
255e1fcb 2796 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2797 break;
2798 case 6: // hver
255e1fcb 2799 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2800 break;
2801 case 31: // hstick_cmpr
255e1fcb 2802 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2803 break;
2804 default:
2805 goto illegal_insn;
2806 }
2807#endif
97ea2859 2808 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2809 break;
3475187d 2810 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2811 if (!supervisor(dc)) {
0f8a249a 2812 goto priv_insn;
de9e9d9f
RH		 2813 }
2814 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2815#ifdef TARGET_SPARC64
2816 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2817 switch (rs1) {
2818 case 0: // tpc
375ee38b 2819 {
a7812ae4 2820 TCGv_ptr r_tsptr;
375ee38b 2821
a7812ae4 2822 r_tsptr = tcg_temp_new_ptr();
8194f35a 2823 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2824 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2825 offsetof(trap_state, tpc));
a7812ae4 2826 tcg_temp_free_ptr(r_tsptr);
375ee38b 2827 }
0f8a249a
BS		 2828 break;
2829 case 1: // tnpc
375ee38b 2830 {
a7812ae4 2831 TCGv_ptr r_tsptr;
375ee38b 2832
a7812ae4 2833 r_tsptr = tcg_temp_new_ptr();
8194f35a 2834 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2835 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2836 offsetof(trap_state, tnpc));
a7812ae4 2837 tcg_temp_free_ptr(r_tsptr);
375ee38b 2838 }
0f8a249a
BS		 2839 break;
2840 case 2: // tstate
375ee38b 2841 {
a7812ae4 2842 TCGv_ptr r_tsptr;
375ee38b 2843
a7812ae4 2844 r_tsptr = tcg_temp_new_ptr();
8194f35a 2845 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2846 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2847 offsetof(trap_state, tstate));
a7812ae4 2848 tcg_temp_free_ptr(r_tsptr);
375ee38b 2849 }
0f8a249a
BS		 2850 break;
2851 case 3: // tt
375ee38b 2852 {
45778f99 2853 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2854
8194f35a 2855 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2856 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2857 offsetof(trap_state, tt));
a7812ae4 2858 tcg_temp_free_ptr(r_tsptr);
375ee38b 2859 }
0f8a249a
BS		 2860 break;
2861 case 4: // tick
ccd4a219 2862 {
a7812ae4 2863 TCGv_ptr r_tickptr;
c9a46442 2864 TCGv_i32 r_const;
ccd4a219 2865
a7812ae4 2866 r_tickptr = tcg_temp_new_ptr();
c9a46442 2867 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2868 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2869 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2870 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
2871 r_tickptr, r_const);
a7812ae4 2872 tcg_temp_free_ptr(r_tickptr);
c9a46442 2873 tcg_temp_free_i32(r_const);
ccd4a219 2874 }
0f8a249a
BS		 2875 break;
2876 case 5: // tba
255e1fcb 2877 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2878 break;
2879 case 6: // pstate
45778f99
RH		 2880 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2881 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2882 break;
2883 case 7: // tl
45778f99
RH		 2884 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2885 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2886 break;
2887 case 8: // pil
45778f99
RH		 2888 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2889 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2890 break;
2891 case 9: // cwp
063c3675 2892 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2893 break;
2894 case 10: // cansave
45778f99
RH		 2895 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2896 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2897 break;
2898 case 11: // canrestore
45778f99
RH		 2899 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2900 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2901 break;
2902 case 12: // cleanwin
45778f99
RH		 2903 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2904 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2905 break;
2906 case 13: // otherwin
45778f99
RH		 2907 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2908 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2909 break;
2910 case 14: // wstate
45778f99
RH		 2911 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2912 offsetof(CPUSPARCState, wstate));
0f8a249a 2913 break;
e9ebed4d 2914 case 16: // UA2005 gl
fb79ceb9 2915 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2916 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2917 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2918 break;
2919 case 26: // UA2005 strand status
fb79ceb9 2920 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2921 if (!hypervisor(dc))
2922 goto priv_insn;
527067d8 2923 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2924 break;
0f8a249a 2925 case 31: // ver
255e1fcb 2926 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2927 break;
2928 case 15: // fq
2929 default:
2930 goto illegal_insn;
2931 }
3475187d 2932#else
255e1fcb 2933 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2934#endif
97ea2859 2935 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2936 break;
3475187d
FB		 2937 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2938#ifdef TARGET_SPARC64
66442b07 2939 save_state(dc);
063c3675 2940 gen_helper_flushw(cpu_env);
3475187d 2941#else
0f8a249a
BS		 2942 if (!supervisor(dc))
2943 goto priv_insn;
97ea2859 2944 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2945#endif
e8af50a3
FB		 2946 break;
2947#endif
0f8a249a 2948 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2949 if (gen_trap_ifnofpu(dc)) {
a80dde08 2950 goto jmp_insn;
5b12f1e8 2951 }
0f8a249a 2952 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2953 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2954 rs2 = GET_FIELD(insn, 27, 31);
2955 xop = GET_FIELD(insn, 18, 26);
66442b07 2956 save_state(dc);
0f8a249a 2957 switch (xop) {
dc1a6971 2958 case 0x1: /* fmovs */
208ae657
RH		 2959 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2960 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2961 break;
2962 case 0x5: /* fnegs */
61f17f6e 2963 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2964 break;
2965 case 0x9: /* fabss */
61f17f6e 2966 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2967 break;
2968 case 0x29: /* fsqrts */
2969 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2970 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2971 break;
2972 case 0x2a: /* fsqrtd */
2973 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2974 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2975 break;
2976 case 0x2b: /* fsqrtq */
2977 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2978 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2979 break;
2980 case 0x41: /* fadds */
61f17f6e 2981 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2982 break;
2983 case 0x42: /* faddd */
61f17f6e 2984 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2985 break;
2986 case 0x43: /* faddq */
2987 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2988 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2989 break;
2990 case 0x45: /* fsubs */
61f17f6e 2991 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2992 break;
2993 case 0x46: /* fsubd */
61f17f6e 2994 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 2995 break;
2996 case 0x47: /* fsubq */
2997 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2998 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 2999 break;
3000 case 0x49: /* fmuls */
3001 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3002 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3003 break;
3004 case 0x4a: /* fmuld */
3005 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3006 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3007 break;
3008 case 0x4b: /* fmulq */
3009 CHECK_FPU_FEATURE(dc, FLOAT128);
3010 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3011 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3012 break;
3013 case 0x4d: /* fdivs */
61f17f6e 3014 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3015 break;
3016 case 0x4e: /* fdivd */
61f17f6e 3017 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3018 break;
3019 case 0x4f: /* fdivq */
3020 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3021 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3022 break;
3023 case 0x69: /* fsmuld */
3024 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3025 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3026 break;
3027 case 0x6e: /* fdmulq */
3028 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3029 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3030 break;
3031 case 0xc4: /* fitos */
61f17f6e 3032 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3033 break;
3034 case 0xc6: /* fdtos */
61f17f6e 3035 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3036 break;
3037 case 0xc7: /* fqtos */
3038 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3039 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3040 break;
3041 case 0xc8: /* fitod */
61f17f6e 3042 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3043 break;
3044 case 0xc9: /* fstod */
61f17f6e 3045 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3046 break;
3047 case 0xcb: /* fqtod */
3048 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3049 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3050 break;
3051 case 0xcc: /* fitoq */
3052 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3053 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3054 break;
3055 case 0xcd: /* fstoq */
3056 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3057 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3058 break;
3059 case 0xce: /* fdtoq */
3060 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3061 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3062 break;
3063 case 0xd1: /* fstoi */
61f17f6e 3064 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3065 break;
3066 case 0xd2: /* fdtoi */
61f17f6e 3067 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3068 break;
3069 case 0xd3: /* fqtoi */
3070 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3071 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3072 break;
3475187d 3073#ifdef TARGET_SPARC64
dc1a6971 3074 case 0x2: /* V9 fmovd */
96eda024
RH		 3075 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3076 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3077 break;
3078 case 0x3: /* V9 fmovq */
3079 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3080 gen_move_Q(rd, rs2);
dc1a6971
BS		 3081 break;
3082 case 0x6: /* V9 fnegd */
61f17f6e 3083 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3084 break;
3085 case 0x7: /* V9 fnegq */
3086 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3087 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3088 break;
3089 case 0xa: /* V9 fabsd */
61f17f6e 3090 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3091 break;
3092 case 0xb: /* V9 fabsq */
3093 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3094 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3095 break;
3096 case 0x81: /* V9 fstox */
61f17f6e 3097 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3098 break;
3099 case 0x82: /* V9 fdtox */
61f17f6e 3100 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3101 break;
3102 case 0x83: /* V9 fqtox */
3103 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3104 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3105 break;
3106 case 0x84: /* V9 fxtos */
61f17f6e 3107 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3108 break;
3109 case 0x88: /* V9 fxtod */
61f17f6e 3110 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3111 break;
3112 case 0x8c: /* V9 fxtoq */
3113 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3114 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3115 break;
0f8a249a 3116#endif
dc1a6971
BS		 3117 default:
3118 goto illegal_insn;
0f8a249a
BS		 3119 }
3120 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3121#ifdef TARGET_SPARC64
0f8a249a 3122 int cond;
3475187d 3123#endif
5b12f1e8 3124 if (gen_trap_ifnofpu(dc)) {
a80dde08 3125 goto jmp_insn;
5b12f1e8 3126 }
0f8a249a 3127 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3128 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3129 rs2 = GET_FIELD(insn, 27, 31);
3130 xop = GET_FIELD(insn, 18, 26);
66442b07 3131 save_state(dc);
dcf24905 3132
690995a6
RH		 3133#ifdef TARGET_SPARC64
3134#define FMOVR(sz) \
3135 do { \
3136 DisasCompare cmp; \
e7c8afb9 3137 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3138 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3139 gen_compare_reg(&cmp, cond, cpu_src1); \
3140 gen_fmov##sz(dc, &cmp, rd, rs2); \
3141 free_compare(&cmp); \
3142 } while (0)
3143
3144 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3145 FMOVR(s);
0f8a249a
BS		 3146 break;
3147 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3148 FMOVR(d);
0f8a249a
BS		 3149 break;
3150 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3151 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3152 FMOVR(q);
1f587329 3153 break;
0f8a249a 3154 }
690995a6 3155#undef FMOVR
0f8a249a
BS		 3156#endif
3157 switch (xop) {
3475187d 3158#ifdef TARGET_SPARC64
7e480893
RH		 3159#define FMOVCC(fcc, sz) \
3160 do { \
3161 DisasCompare cmp; \
714547bb 3162 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3163 gen_fcompare(&cmp, fcc, cond); \
3164 gen_fmov##sz(dc, &cmp, rd, rs2); \
3165 free_compare(&cmp); \
3166 } while (0)
3167
0f8a249a 3168 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3169 FMOVCC(0, s);
0f8a249a
BS		 3170 break;
3171 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3172 FMOVCC(0, d);
0f8a249a
BS		 3173 break;
3174 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3175 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3176 FMOVCC(0, q);
1f587329 3177 break;
0f8a249a 3178 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3179 FMOVCC(1, s);
0f8a249a
BS		 3180 break;
3181 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3182 FMOVCC(1, d);
0f8a249a
BS		 3183 break;
3184 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3185 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3186 FMOVCC(1, q);
1f587329 3187 break;
0f8a249a 3188 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3189 FMOVCC(2, s);
0f8a249a
BS		 3190 break;
3191 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3192 FMOVCC(2, d);
0f8a249a
BS		 3193 break;
3194 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3195 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3196 FMOVCC(2, q);
1f587329 3197 break;
0f8a249a 3198 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3199 FMOVCC(3, s);
0f8a249a
BS		 3200 break;
3201 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3202 FMOVCC(3, d);
0f8a249a
BS		 3203 break;
3204 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3205 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3206 FMOVCC(3, q);
1f587329 3207 break;
7e480893
RH		 3208#undef FMOVCC
3209#define FMOVCC(xcc, sz) \
3210 do { \
3211 DisasCompare cmp; \
714547bb 3212 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3213 gen_compare(&cmp, xcc, cond, dc); \
3214 gen_fmov##sz(dc, &cmp, rd, rs2); \
3215 free_compare(&cmp); \
3216 } while (0)
19f329ad 3217
0f8a249a 3218 case 0x101: /* V9 fmovscc %icc */
7e480893 3219 FMOVCC(0, s);
0f8a249a
BS		 3220 break;
3221 case 0x102: /* V9 fmovdcc %icc */
7e480893 3222 FMOVCC(0, d);
b7d69dc2 3223 break;
0f8a249a 3224 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3225 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3226 FMOVCC(0, q);
1f587329 3227 break;
0f8a249a 3228 case 0x181: /* V9 fmovscc %xcc */
7e480893 3229 FMOVCC(1, s);
0f8a249a
BS		 3230 break;
3231 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3232 FMOVCC(1, d);
0f8a249a
BS		 3233 break;
3234 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3235 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3236 FMOVCC(1, q);
1f587329 3237 break;
7e480893 3238#undef FMOVCC
1f587329
BS		 3239#endif
3240 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3241 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3242 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3243 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3244 break;
1f587329 3245 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3246 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3247 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3248 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3249 break;
1f587329 3250 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3251 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3252 gen_op_load_fpr_QT0(QFPREG(rs1));
3253 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3254 gen_op_fcmpq(rd & 3);
1f587329 3255 break;
0f8a249a 3256 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3257 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3258 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3259 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3260 break;
3261 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3262 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3263 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3264 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3265 break;
1f587329 3266 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3267 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3268 gen_op_load_fpr_QT0(QFPREG(rs1));
3269 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3270 gen_op_fcmpeq(rd & 3);
1f587329 3271 break;
0f8a249a
BS		 3272 default:
3273 goto illegal_insn;
3274 }
0f8a249a 3275 } else if (xop == 0x2) {
97ea2859 3276 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3277 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3278 if (rs1 == 0) {
97ea2859 3279 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3280 if (IS_IMM) { /* immediate */
67526b20 3281 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3282 tcg_gen_movi_tl(dst, simm);
3283 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3284 } else { /* register */
3285 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3286 if (rs2 == 0) {
3287 tcg_gen_movi_tl(dst, 0);
3288 gen_store_gpr(dc, rd, dst);
3289 } else {
3290 cpu_src2 = gen_load_gpr(dc, rs2);
3291 gen_store_gpr(dc, rd, cpu_src2);
3292 }
0f8a249a 3293 }
0f8a249a 3294 } else {
9d1d4e34 3295 cpu_src1 = get_src1(dc, insn);
0f8a249a 3296 if (IS_IMM) { /* immediate */
67526b20 3297 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3298 tcg_gen_ori_tl(dst, cpu_src1, simm);
3299 gen_store_gpr(dc, rd, dst);
0f8a249a 3300 } else { /* register */
0f8a249a 3301 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3302 if (rs2 == 0) {
3303 /* mov shortcut: or x, %g0, y -> mov x, y */
3304 gen_store_gpr(dc, rd, cpu_src1);
3305 } else {
3306 cpu_src2 = gen_load_gpr(dc, rs2);
3307 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3308 gen_store_gpr(dc, rd, dst);
3309 }
0f8a249a 3310 }
0f8a249a 3311 }
83469015 3312#ifdef TARGET_SPARC64
0f8a249a 3313 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3314 cpu_src1 = get_src1(dc, insn);
0f8a249a 3315 if (IS_IMM) { /* immediate */
67526b20 3316 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3317 if (insn & (1 << 12)) {
67526b20 3318 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3319 } else {
67526b20 3320 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3321 }
0f8a249a 3322 } else { /* register */
83469015 3323 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3324 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3325 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3326 if (insn & (1 << 12)) {
6ae20372 3327 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3328 } else {
6ae20372 3329 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3330 }
01b1fa6d 3331 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3332 }
97ea2859 3333 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3334 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3335 cpu_src1 = get_src1(dc, insn);
0f8a249a 3336 if (IS_IMM) { /* immediate */
67526b20 3337 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3338 if (insn & (1 << 12)) {
67526b20 3339 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3340 } else {
6ae20372 3341 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3342 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3343 }
0f8a249a 3344 } else { /* register */
83469015 3345 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3346 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3347 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3348 if (insn & (1 << 12)) {
6ae20372
BS		 3349 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3350 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3351 } else {
6ae20372
BS		 3352 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3353 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3354 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3355 }
83469015 3356 }
97ea2859 3357 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3358 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3359 cpu_src1 = get_src1(dc, insn);
0f8a249a 3360 if (IS_IMM) { /* immediate */
67526b20 3361 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3362 if (insn & (1 << 12)) {
67526b20 3363 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3364 } else {
97ea2859 3365 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3366 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3367 }
0f8a249a 3368 } else { /* register */
83469015 3369 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3370 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3371 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3372 if (insn & (1 << 12)) {
6ae20372
BS		 3373 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3374 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3375 } else {
6ae20372 3376 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3377 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3378 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3379 }
83469015 3380 }
97ea2859 3381 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3382#endif
fcc72045 3383 } else if (xop < 0x36) {
cf495bcf 3384 if (xop < 0x20) {
9d1d4e34
RH		 3385 cpu_src1 = get_src1(dc, insn);
3386 cpu_src2 = get_src2(dc, insn);
cf495bcf 3387 switch (xop & ~0x10) {
b89e94af 3388 case 0x0: /* add */
97ea2859
RH		 3389 if (xop & 0x10) {
3390 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3391 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3392 dc->cc_op = CC_OP_ADD;
41d72852 3393 } else {
97ea2859 3394 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3395 }
cf495bcf 3396 break;
b89e94af 3397 case 0x1: /* and */
97ea2859 3398 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3399 if (xop & 0x10) {
38482a77
BS		 3400 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3401 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3402 dc->cc_op = CC_OP_LOGIC;
41d72852 3403 }
cf495bcf 3404 break;
b89e94af 3405 case 0x2: /* or */
97ea2859 3406 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3407 if (xop & 0x10) {
38482a77
BS		 3408 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3409 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3410 dc->cc_op = CC_OP_LOGIC;
8393617c 3411 }
0f8a249a 3412 break;
b89e94af 3413 case 0x3: /* xor */
97ea2859 3414 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3415 if (xop & 0x10) {
38482a77
BS		 3416 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3417 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3418 dc->cc_op = CC_OP_LOGIC;
8393617c 3419 }
cf495bcf 3420 break;
b89e94af 3421 case 0x4: /* sub */
97ea2859
RH		 3422 if (xop & 0x10) {
3423 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3424 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3425 dc->cc_op = CC_OP_SUB;
41d72852 3426 } else {
97ea2859 3427 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3428 }
cf495bcf 3429 break;
b89e94af 3430 case 0x5: /* andn */
97ea2859 3431 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3432 if (xop & 0x10) {
38482a77
BS		 3433 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3434 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3435 dc->cc_op = CC_OP_LOGIC;
8393617c 3436 }
cf495bcf 3437 break;
b89e94af 3438 case 0x6: /* orn */
97ea2859 3439 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3440 if (xop & 0x10) {
38482a77
BS		 3441 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3442 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3443 dc->cc_op = CC_OP_LOGIC;
8393617c 3444 }
cf495bcf 3445 break;
b89e94af 3446 case 0x7: /* xorn */
97ea2859 3447 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3448 if (xop & 0x10) {
38482a77
BS		 3449 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3450 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3451 dc->cc_op = CC_OP_LOGIC;
8393617c 3452 }
cf495bcf 3453 break;
b89e94af 3454 case 0x8: /* addx, V9 addc */
70c48285
RH		 3455 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3456 (xop & 0x10));
cf495bcf 3457 break;
ded3ab80 3458#ifdef TARGET_SPARC64
0f8a249a 3459 case 0x9: /* V9 mulx */
97ea2859 3460 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3461 break;
3462#endif
b89e94af 3463 case 0xa: /* umul */
64a88d5d 3464 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3465 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3466 if (xop & 0x10) {
38482a77
BS		 3467 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3468 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3469 dc->cc_op = CC_OP_LOGIC;
8393617c 3470 }
cf495bcf 3471 break;
b89e94af 3472 case 0xb: /* smul */
64a88d5d 3473 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3474 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3475 if (xop & 0x10) {
38482a77
BS		 3476 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3477 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3478 dc->cc_op = CC_OP_LOGIC;
8393617c 3479 }
cf495bcf 3480 break;
b89e94af 3481 case 0xc: /* subx, V9 subc */
70c48285
RH		 3482 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3483 (xop & 0x10));
cf495bcf 3484 break;
ded3ab80 3485#ifdef TARGET_SPARC64
0f8a249a 3486 case 0xd: /* V9 udivx */
c28ae41e 3487 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3488 break;
3489#endif
b89e94af 3490 case 0xe: /* udiv */
64a88d5d 3491 CHECK_IU_FEATURE(dc, DIV);
8393617c 3492 if (xop & 0x10) {
7a5e4488
BS		 3493 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3494 cpu_src2);
6c78ea32 3495 dc->cc_op = CC_OP_DIV;
0fcec41e 3496 } else {
7a5e4488
BS		 3497 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3498 cpu_src2);
8393617c 3499 }
cf495bcf 3500 break;
b89e94af 3501 case 0xf: /* sdiv */
64a88d5d 3502 CHECK_IU_FEATURE(dc, DIV);
8393617c 3503 if (xop & 0x10) {
7a5e4488
BS		 3504 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3505 cpu_src2);
6c78ea32 3506 dc->cc_op = CC_OP_DIV;
0fcec41e 3507 } else {
7a5e4488
BS		 3508 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3509 cpu_src2);
8393617c 3510 }
cf495bcf
FB		 3511 break;
3512 default:
3513 goto illegal_insn;
3514 }
97ea2859 3515 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3516 } else {
9d1d4e34
RH		 3517 cpu_src1 = get_src1(dc, insn);
3518 cpu_src2 = get_src2(dc, insn);
cf495bcf 3519 switch (xop) {
0f8a249a 3520 case 0x20: /* taddcc */
a2ea4aa9 3521 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3522 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3523 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3524 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3525 break;
3526 case 0x21: /* tsubcc */
a2ea4aa9 3527 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3528 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3529 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3530 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3531 break;
3532 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3533 gen_helper_taddcctv(cpu_dst, cpu_env,
3534 cpu_src1, cpu_src2);
97ea2859 3535 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3536 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3537 break;
3538 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3539 gen_helper_tsubcctv(cpu_dst, cpu_env,
3540 cpu_src1, cpu_src2);
97ea2859 3541 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3542 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3543 break;
cf495bcf 3544 case 0x24: /* mulscc */
20132b96 3545 update_psr(dc);
6ae20372 3546 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3547 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3548 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3549 dc->cc_op = CC_OP_ADD;
cf495bcf 3550 break;
83469015 3551#ifndef TARGET_SPARC64
0f8a249a 3552 case 0x25: /* sll */
e35298cd 3553 if (IS_IMM) { /* immediate */
67526b20
BS		 3554 simm = GET_FIELDs(insn, 20, 31);
3555 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3556 } else { /* register */
de9e9d9f 3557 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3558 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3559 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3560 }
97ea2859 3561 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3562 break;
83469015 3563 case 0x26: /* srl */
e35298cd 3564 if (IS_IMM) { /* immediate */
67526b20
BS		 3565 simm = GET_FIELDs(insn, 20, 31);
3566 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3567 } else { /* register */
de9e9d9f 3568 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3569 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3570 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3571 }
97ea2859 3572 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3573 break;
83469015 3574 case 0x27: /* sra */
e35298cd 3575 if (IS_IMM) { /* immediate */
67526b20
BS		 3576 simm = GET_FIELDs(insn, 20, 31);
3577 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3578 } else { /* register */
de9e9d9f 3579 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3580 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3581 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3582 }
97ea2859 3583 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3584 break;
83469015 3585#endif
cf495bcf
FB		 3586 case 0x30:
3587 {
de9e9d9f 3588 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3589 switch(rd) {
3475187d 3590 case 0: /* wry */
5068cbd9
BS		 3591 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3592 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3593 break;
65fe7b09
BS		 3594#ifndef TARGET_SPARC64
3595 case 0x01 ... 0x0f: /* undefined in the
3596 SPARCv8 manual, nop
3597 on the microSPARC
3598 II */
3599 case 0x10 ... 0x1f: /* implementation-dependent
3600 in the SPARCv8
3601 manual, nop on the
3602 microSPARC II */
d1c36ba7
RH		 3603 if ((rd == 0x13) && (dc->def->features &
3604 CPU_FEATURE_POWERDOWN)) {
3605 /* LEON3 power-down */
1cf892ca 3606 save_state(dc);
d1c36ba7
RH		 3607 gen_helper_power_down(cpu_env);
3608 }
65fe7b09
BS		 3609 break;
3610#else
0f8a249a 3611 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3612 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3613 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3614 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3615 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3616 break;
3617 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3618 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3619 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 3620 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3621 offsetof(CPUSPARCState, asi));
3622 /* End TB to notice changed ASI. */
3623 save_state(dc);
3624 gen_op_next_insn();
3625 tcg_gen_exit_tb(0);
3626 dc->is_br = 1;
0f8a249a
BS		 3627 break;
3628 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3629 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3630 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3631 save_state(dc);
3299908c 3632 gen_op_next_insn();
57fec1fe 3633 tcg_gen_exit_tb(0);
3299908c 3634 dc->is_br = 1;
0f8a249a
BS		 3635 break;
3636 case 0xf: /* V9 sir, nop if user */
3475187d 3637#if !defined(CONFIG_USER_ONLY)
6ad6135d 3638 if (supervisor(dc)) {
1a2fb1c0 3639 ; // XXX
6ad6135d 3640 }
3475187d 3641#endif
0f8a249a
BS		 3642 break;
3643 case 0x13: /* Graphics Status */
5b12f1e8 3644 if (gen_trap_ifnofpu(dc)) {
725cb90b 3645 goto jmp_insn;
5b12f1e8 3646 }
255e1fcb 3647 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3648 break;
9d926598
BS		 3649 case 0x14: /* Softint set */
3650 if (!supervisor(dc))
3651 goto illegal_insn;
aeff993c
RH		 3652 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3653 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3654 break;
3655 case 0x15: /* Softint clear */
3656 if (!supervisor(dc))
3657 goto illegal_insn;
aeff993c
RH		 3658 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3659 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3660 break;
3661 case 0x16: /* Softint write */
3662 if (!supervisor(dc))
3663 goto illegal_insn;
aeff993c
RH		 3664 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3665 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3666 break;
0f8a249a 3667 case 0x17: /* Tick compare */
83469015 3668#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3669 if (!supervisor(dc))
3670 goto illegal_insn;
83469015 3671#endif
ccd4a219 3672 {
a7812ae4 3673 TCGv_ptr r_tickptr;
ccd4a219 3674
255e1fcb 3675 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3676 cpu_src2);
a7812ae4 3677 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3678 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3679 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3680 gen_helper_tick_set_limit(r_tickptr,
3681 cpu_tick_cmpr);
3682 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3683 }
0f8a249a
BS		 3684 break;
3685 case 0x18: /* System tick */
83469015 3686#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3687 if (!supervisor(dc))
3688 goto illegal_insn;
83469015 3689#endif
ccd4a219 3690 {
a7812ae4 3691 TCGv_ptr r_tickptr;
ccd4a219 3692
7b04bd5c 3693 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3694 cpu_src2);
a7812ae4 3695 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3696 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3697 offsetof(CPUSPARCState, stick));
a7812ae4 3698 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3699 cpu_tmp0);
a7812ae4 3700 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3701 }
0f8a249a
BS		 3702 break;
3703 case 0x19: /* System tick compare */
83469015 3704#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3705 if (!supervisor(dc))
3706 goto illegal_insn;
3475187d 3707#endif
ccd4a219 3708 {
a7812ae4 3709 TCGv_ptr r_tickptr;
ccd4a219 3710
255e1fcb 3711 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3712 cpu_src2);
a7812ae4 3713 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3714 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3715 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3716 gen_helper_tick_set_limit(r_tickptr,
3717 cpu_stick_cmpr);
3718 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3719 }
0f8a249a 3720 break;
83469015 3721
0f8a249a 3722 case 0x10: /* Performance Control */
77f193da
BS		 3723 case 0x11: /* Performance Instrumentation
3724 Counter */
0f8a249a 3725 case 0x12: /* Dispatch Control */
83469015 3726#endif
3475187d 3727 default:
cf495bcf
FB		 3728 goto illegal_insn;
3729 }
3730 }
3731 break;
e8af50a3 3732#if !defined(CONFIG_USER_ONLY)
af7bf89b 3733 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3734 {
0f8a249a
BS		 3735 if (!supervisor(dc))
3736 goto priv_insn;
3475187d 3737#ifdef TARGET_SPARC64
0f8a249a
BS		 3738 switch (rd) {
3739 case 0:
063c3675 3740 gen_helper_saved(cpu_env);
0f8a249a
BS		 3741 break;
3742 case 1:
063c3675 3743 gen_helper_restored(cpu_env);
0f8a249a 3744 break;
e9ebed4d
BS		 3745 case 2: /* UA2005 allclean */
3746 case 3: /* UA2005 otherw */
3747 case 4: /* UA2005 normalw */
3748 case 5: /* UA2005 invalw */
3749 // XXX
0f8a249a 3750 default:
3475187d
FB		 3751 goto illegal_insn;
3752 }
3753#else
de9e9d9f 3754 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3755 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3756 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3757 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3758 dc->cc_op = CC_OP_FLAGS;
66442b07 3759 save_state(dc);
9e61bde5 3760 gen_op_next_insn();
57fec1fe 3761 tcg_gen_exit_tb(0);
0f8a249a 3762 dc->is_br = 1;
3475187d 3763#endif
e8af50a3
FB		 3764 }
3765 break;
af7bf89b 3766 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3767 {
0f8a249a
BS		 3768 if (!supervisor(dc))
3769 goto priv_insn;
de9e9d9f 3770 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3771 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3772#ifdef TARGET_SPARC64
0f8a249a
BS		 3773 switch (rd) {
3774 case 0: // tpc
375ee38b 3775 {
a7812ae4 3776 TCGv_ptr r_tsptr;
375ee38b 3777
a7812ae4 3778 r_tsptr = tcg_temp_new_ptr();
8194f35a 3779 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3780 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3781 offsetof(trap_state, tpc));
a7812ae4 3782 tcg_temp_free_ptr(r_tsptr);
375ee38b 3783 }
0f8a249a
BS		 3784 break;
3785 case 1: // tnpc
375ee38b 3786 {
a7812ae4 3787 TCGv_ptr r_tsptr;
375ee38b 3788
a7812ae4 3789 r_tsptr = tcg_temp_new_ptr();
8194f35a 3790 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3791 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3792 offsetof(trap_state, tnpc));
a7812ae4 3793 tcg_temp_free_ptr(r_tsptr);
375ee38b 3794 }
0f8a249a
BS		 3795 break;
3796 case 2: // tstate
375ee38b 3797 {
a7812ae4 3798 TCGv_ptr r_tsptr;
375ee38b 3799
a7812ae4 3800 r_tsptr = tcg_temp_new_ptr();
8194f35a 3801 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3802 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3803 offsetof(trap_state,
3804 tstate));
a7812ae4 3805 tcg_temp_free_ptr(r_tsptr);
375ee38b 3806 }
0f8a249a
BS		 3807 break;
3808 case 3: // tt
375ee38b 3809 {
a7812ae4 3810 TCGv_ptr r_tsptr;
375ee38b 3811
a7812ae4 3812 r_tsptr = tcg_temp_new_ptr();
8194f35a 3813 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3814 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3815 offsetof(trap_state, tt));
a7812ae4 3816 tcg_temp_free_ptr(r_tsptr);
375ee38b 3817 }
0f8a249a
BS		 3818 break;
3819 case 4: // tick
ccd4a219 3820 {
a7812ae4 3821 TCGv_ptr r_tickptr;
ccd4a219 3822
a7812ae4 3823 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3824 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3825 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3826 gen_helper_tick_set_count(r_tickptr,
3827 cpu_tmp0);
3828 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3829 }
0f8a249a
BS		 3830 break;
3831 case 5: // tba
255e1fcb 3832 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3833 break;
3834 case 6: // pstate
6234ac09
RH		 3835 save_state(dc);
3836 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3837 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3838 break;
3839 case 7: // tl
6234ac09 3840 save_state(dc);
7b9e066b 3841 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3842 offsetof(CPUSPARCState, tl));
3843 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3844 break;
3845 case 8: // pil
063c3675 3846 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3847 break;
3848 case 9: // cwp
063c3675 3849 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3850 break;
3851 case 10: // cansave
7b9e066b
RH		 3852 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3853 offsetof(CPUSPARCState,
3854 cansave));
0f8a249a
BS		 3855 break;
3856 case 11: // canrestore
7b9e066b
RH		 3857 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3858 offsetof(CPUSPARCState,
3859 canrestore));
0f8a249a
BS		 3860 break;
3861 case 12: // cleanwin
7b9e066b
RH		 3862 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3863 offsetof(CPUSPARCState,
3864 cleanwin));
0f8a249a
BS		 3865 break;
3866 case 13: // otherwin
7b9e066b
RH		 3867 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3868 offsetof(CPUSPARCState,
3869 otherwin));
0f8a249a
BS		 3870 break;
3871 case 14: // wstate
7b9e066b
RH		 3872 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3873 offsetof(CPUSPARCState,
3874 wstate));
0f8a249a 3875 break;
e9ebed4d 3876 case 16: // UA2005 gl
fb79ceb9 3877 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3878 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3879 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3880 break;
3881 case 26: // UA2005 strand status
fb79ceb9 3882 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3883 if (!hypervisor(dc))
3884 goto priv_insn;
527067d8 3885 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3886 break;
0f8a249a
BS		 3887 default:
3888 goto illegal_insn;
3889 }
3475187d 3890#else
7b9e066b
RH		 3891 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3892 if (dc->def->nwindows != 32) {
3893 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3894 (1 << dc->def->nwindows) - 1);
7b9e066b 3895 }
3475187d 3896#endif
e8af50a3
FB		 3897 }
3898 break;
e9ebed4d 3899 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3900 {
e9ebed4d 3901#ifndef TARGET_SPARC64
0f8a249a
BS		 3902 if (!supervisor(dc))
3903 goto priv_insn;
255e1fcb 3904 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3905#else
fb79ceb9 3906 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3907 if (!hypervisor(dc))
3908 goto priv_insn;
de9e9d9f 3909 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3910 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3911 switch (rd) {
3912 case 0: // hpstate
3913 // XXX gen_op_wrhpstate();
66442b07 3914 save_state(dc);
e9ebed4d 3915 gen_op_next_insn();
57fec1fe 3916 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3917 dc->is_br = 1;
3918 break;
3919 case 1: // htstate
3920 // XXX gen_op_wrhtstate();
3921 break;
3922 case 3: // hintp
255e1fcb 3923 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3924 break;
3925 case 5: // htba
255e1fcb 3926 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3927 break;
3928 case 31: // hstick_cmpr
ccd4a219 3929 {
a7812ae4 3930 TCGv_ptr r_tickptr;
ccd4a219 3931
255e1fcb 3932 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3933 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3934 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3935 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3936 gen_helper_tick_set_limit(r_tickptr,
3937 cpu_hstick_cmpr);
3938 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3939 }
e9ebed4d
BS		 3940 break;
3941 case 6: // hver readonly
3942 default:
3943 goto illegal_insn;
3944 }
3945#endif
e8af50a3
FB		 3946 }
3947 break;
3948#endif
3475187d 3949#ifdef TARGET_SPARC64
0f8a249a
BS		 3950 case 0x2c: /* V9 movcc */
3951 {
3952 int cc = GET_FIELD_SP(insn, 11, 12);
3953 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3954 DisasCompare cmp;
97ea2859 3955 TCGv dst;
00f219bf 3956
0f8a249a 3957 if (insn & (1 << 18)) {
f52879b4
RH		 3958 if (cc == 0) {
3959 gen_compare(&cmp, 0, cond, dc);
3960 } else if (cc == 2) {
3961 gen_compare(&cmp, 1, cond, dc);
3962 } else {
0f8a249a 3963 goto illegal_insn;
f52879b4 3964 }
0f8a249a 3965 } else {
f52879b4 3966 gen_fcompare(&cmp, cc, cond);
0f8a249a 3967 }
00f219bf 3968
f52879b4
RH		 3969 /* The get_src2 above loaded the normal 13-bit
3970 immediate field, not the 11-bit field we have
3971 in movcc. But it did handle the reg case. */
3972 if (IS_IMM) {
67526b20 3973 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3974 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3975 }
f52879b4 3976
97ea2859
RH		 3977 dst = gen_load_gpr(dc, rd);
3978 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3979 cmp.c1, cmp.c2,
97ea2859 3980 cpu_src2, dst);
f52879b4 3981 free_compare(&cmp);
97ea2859 3982 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3983 break;
3984 }
3985 case 0x2d: /* V9 sdivx */
c28ae41e 3986 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3987 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3988 break;
3989 case 0x2e: /* V9 popc */
97ea2859
RH		 3990 gen_helper_popc(cpu_dst, cpu_src2);
3991 gen_store_gpr(dc, rd, cpu_dst);
3992 break;
0f8a249a
BS		 3993 case 0x2f: /* V9 movr */
3994 {
3995 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3996 DisasCompare cmp;
97ea2859 3997 TCGv dst;
00f219bf 3998
c33f80f5 3999 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4000
c33f80f5
RH		 4001 /* The get_src2 above loaded the normal 13-bit
4002 immediate field, not the 10-bit field we have
4003 in movr. But it did handle the reg case. */
4004 if (IS_IMM) {
67526b20 4005 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4006 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4007 }
c33f80f5 4008
97ea2859
RH		 4009 dst = gen_load_gpr(dc, rd);
4010 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4011 cmp.c1, cmp.c2,
97ea2859 4012 cpu_src2, dst);
c33f80f5 4013 free_compare(&cmp);
97ea2859 4014 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4015 break;
4016 }
4017#endif
4018 default:
4019 goto illegal_insn;
4020 }
4021 }
3299908c
BS		 4022 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4023#ifdef TARGET_SPARC64
4024 int opf = GET_FIELD_SP(insn, 5, 13);
4025 rs1 = GET_FIELD(insn, 13, 17);
4026 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4027 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4028 goto jmp_insn;
5b12f1e8 4029 }
3299908c
BS		 4030
4031 switch (opf) {
e9ebed4d 4032 case 0x000: /* VIS I edge8cc */
6c073553 4033 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4034 cpu_src1 = gen_load_gpr(dc, rs1);
4035 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4036 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4037 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4038 break;
e9ebed4d 4039 case 0x001: /* VIS II edge8n */
6c073553 4040 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4041 cpu_src1 = gen_load_gpr(dc, rs1);
4042 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4043 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4044 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4045 break;
e9ebed4d 4046 case 0x002: /* VIS I edge8lcc */
6c073553 4047 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4048 cpu_src1 = gen_load_gpr(dc, rs1);
4049 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4050 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4051 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4052 break;
e9ebed4d 4053 case 0x003: /* VIS II edge8ln */
6c073553 4054 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4055 cpu_src1 = gen_load_gpr(dc, rs1);
4056 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4057 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4058 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4059 break;
e9ebed4d 4060 case 0x004: /* VIS I edge16cc */
6c073553 4061 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4062 cpu_src1 = gen_load_gpr(dc, rs1);
4063 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4064 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4065 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4066 break;
e9ebed4d 4067 case 0x005: /* VIS II edge16n */
6c073553 4068 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4069 cpu_src1 = gen_load_gpr(dc, rs1);
4070 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4071 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4072 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4073 break;
e9ebed4d 4074 case 0x006: /* VIS I edge16lcc */
6c073553 4075 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4076 cpu_src1 = gen_load_gpr(dc, rs1);
4077 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4078 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4079 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4080 break;
e9ebed4d 4081 case 0x007: /* VIS II edge16ln */
6c073553 4082 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4083 cpu_src1 = gen_load_gpr(dc, rs1);
4084 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4085 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4086 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4087 break;
e9ebed4d 4088 case 0x008: /* VIS I edge32cc */
6c073553 4089 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4090 cpu_src1 = gen_load_gpr(dc, rs1);
4091 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4092 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4093 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4094 break;
e9ebed4d 4095 case 0x009: /* VIS II edge32n */
6c073553 4096 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4097 cpu_src1 = gen_load_gpr(dc, rs1);
4098 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4099 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4100 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4101 break;
e9ebed4d 4102 case 0x00a: /* VIS I edge32lcc */
6c073553 4103 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4104 cpu_src1 = gen_load_gpr(dc, rs1);
4105 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4106 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4107 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4108 break;
e9ebed4d 4109 case 0x00b: /* VIS II edge32ln */
6c073553 4110 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4111 cpu_src1 = gen_load_gpr(dc, rs1);
4112 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4113 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4114 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4115 break;
e9ebed4d 4116 case 0x010: /* VIS I array8 */
64a88d5d 4117 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4118 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4119 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4120 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4121 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4122 break;
4123 case 0x012: /* VIS I array16 */
64a88d5d 4124 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4125 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4126 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4127 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4128 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4129 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4130 break;
4131 case 0x014: /* VIS I array32 */
64a88d5d 4132 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4133 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4134 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4135 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4136 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4137 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4138 break;
3299908c 4139 case 0x018: /* VIS I alignaddr */
64a88d5d 4140 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4141 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4142 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4143 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4144 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4145 break;
4146 case 0x01a: /* VIS I alignaddrl */
add545ab 4147 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4148 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4149 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4150 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4151 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4152 break;
4153 case 0x019: /* VIS II bmask */
793a137a 4154 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4155 cpu_src1 = gen_load_gpr(dc, rs1);
4156 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4157 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4158 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4159 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4160 break;
e9ebed4d 4161 case 0x020: /* VIS I fcmple16 */
64a88d5d 4162 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4163 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4164 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4165 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4166 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4167 break;
4168 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4169 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4170 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4171 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4172 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4173 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4174 break;
e9ebed4d 4175 case 0x024: /* VIS I fcmple32 */
64a88d5d 4176 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4177 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4178 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4179 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4180 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4181 break;
4182 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4183 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4184 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4185 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4186 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4187 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4188 break;
4189 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4190 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4191 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4192 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4193 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4194 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4195 break;
4196 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4197 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4198 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4199 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4200 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4201 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4202 break;
4203 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4204 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4205 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4206 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4207 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4208 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4209 break;
4210 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4211 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4212 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4213 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4214 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4215 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4216 break;
4217 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4218 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4219 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4220 break;
4221 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4222 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4223 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4224 break;
4225 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4226 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4227 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4228 break;
4229 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4230 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4231 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4232 break;
4233 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4234 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4235 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4236 break;
4237 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4238 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4239 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4240 break;
4241 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4242 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4243 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4244 break;
4245 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4246 CHECK_FPU_FEATURE(dc, VIS1);
4247 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4248 break;
e9ebed4d 4249 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4250 CHECK_FPU_FEATURE(dc, VIS1);
4251 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4252 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4253 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4254 gen_store_fpr_F(dc, rd, cpu_dst_32);
4255 break;
e9ebed4d 4256 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4257 CHECK_FPU_FEATURE(dc, VIS1);
4258 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4259 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4260 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4261 gen_store_fpr_F(dc, rd, cpu_dst_32);
4262 break;
f888300b
RH		 4263 case 0x03e: /* VIS I pdist */
4264 CHECK_FPU_FEATURE(dc, VIS1);
4265 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4266 break;
3299908c 4267 case 0x048: /* VIS I faligndata */
64a88d5d 4268 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4269 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4270 break;
e9ebed4d 4271 case 0x04b: /* VIS I fpmerge */
64a88d5d 4272 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4273 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4274 break;
4275 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4276 CHECK_FPU_FEATURE(dc, VIS2);
4277 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4278 break;
e9ebed4d 4279 case 0x04d: /* VIS I fexpand */
64a88d5d 4280 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4281 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4282 break;
4283 case 0x050: /* VIS I fpadd16 */
64a88d5d 4284 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4285 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4286 break;
4287 case 0x051: /* VIS I fpadd16s */
64a88d5d 4288 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4289 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4290 break;
4291 case 0x052: /* VIS I fpadd32 */
64a88d5d 4292 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4293 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4294 break;
4295 case 0x053: /* VIS I fpadd32s */
64a88d5d 4296 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4297 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4298 break;
4299 case 0x054: /* VIS I fpsub16 */
64a88d5d 4300 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4301 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4302 break;
4303 case 0x055: /* VIS I fpsub16s */
64a88d5d 4304 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4305 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4306 break;
4307 case 0x056: /* VIS I fpsub32 */
64a88d5d 4308 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4309 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4310 break;
4311 case 0x057: /* VIS I fpsub32s */
64a88d5d 4312 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4313 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4314 break;
3299908c 4315 case 0x060: /* VIS I fzero */
64a88d5d 4316 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4317 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4318 tcg_gen_movi_i64(cpu_dst_64, 0);
4319 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4320 break;
4321 case 0x061: /* VIS I fzeros */
64a88d5d 4322 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4323 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4324 tcg_gen_movi_i32(cpu_dst_32, 0);
4325 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4326 break;
e9ebed4d 4327 case 0x062: /* VIS I fnor */
64a88d5d 4328 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4329 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4330 break;
4331 case 0x063: /* VIS I fnors */
64a88d5d 4332 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4333 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4334 break;
4335 case 0x064: /* VIS I fandnot2 */
64a88d5d 4336 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4337 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4338 break;
4339 case 0x065: /* VIS I fandnot2s */
64a88d5d 4340 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4341 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4342 break;
4343 case 0x066: /* VIS I fnot2 */
64a88d5d 4344 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4345 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4346 break;
4347 case 0x067: /* VIS I fnot2s */
64a88d5d 4348 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4349 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4350 break;
4351 case 0x068: /* VIS I fandnot1 */
64a88d5d 4352 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4353 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4354 break;
4355 case 0x069: /* VIS I fandnot1s */
64a88d5d 4356 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4357 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4358 break;
4359 case 0x06a: /* VIS I fnot1 */
64a88d5d 4360 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4361 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4362 break;
4363 case 0x06b: /* VIS I fnot1s */
64a88d5d 4364 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4365 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4366 break;
4367 case 0x06c: /* VIS I fxor */
64a88d5d 4368 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4369 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4370 break;
4371 case 0x06d: /* VIS I fxors */
64a88d5d 4372 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4373 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4374 break;
4375 case 0x06e: /* VIS I fnand */
64a88d5d 4376 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4377 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4378 break;
4379 case 0x06f: /* VIS I fnands */
64a88d5d 4380 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4381 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4382 break;
4383 case 0x070: /* VIS I fand */
64a88d5d 4384 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4385 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4386 break;
4387 case 0x071: /* VIS I fands */
64a88d5d 4388 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4389 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4390 break;
4391 case 0x072: /* VIS I fxnor */
64a88d5d 4392 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4393 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4394 break;
4395 case 0x073: /* VIS I fxnors */
64a88d5d 4396 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4397 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4398 break;
3299908c 4399 case 0x074: /* VIS I fsrc1 */
64a88d5d 4400 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4401 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4402 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4403 break;
4404 case 0x075: /* VIS I fsrc1s */
64a88d5d 4405 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4406 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4407 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4408 break;
e9ebed4d 4409 case 0x076: /* VIS I fornot2 */
64a88d5d 4410 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4411 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4412 break;
4413 case 0x077: /* VIS I fornot2s */
64a88d5d 4414 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4415 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4416 break;
3299908c 4417 case 0x078: /* VIS I fsrc2 */
64a88d5d 4418 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4419 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4420 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4421 break;
4422 case 0x079: /* VIS I fsrc2s */
64a88d5d 4423 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4424 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4425 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4426 break;
e9ebed4d 4427 case 0x07a: /* VIS I fornot1 */
64a88d5d 4428 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4429 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4430 break;
4431 case 0x07b: /* VIS I fornot1s */
64a88d5d 4432 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4433 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4434 break;
4435 case 0x07c: /* VIS I for */
64a88d5d 4436 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4437 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4438 break;
4439 case 0x07d: /* VIS I fors */
64a88d5d 4440 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4441 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4442 break;
3299908c 4443 case 0x07e: /* VIS I fone */
64a88d5d 4444 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4445 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4446 tcg_gen_movi_i64(cpu_dst_64, -1);
4447 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4448 break;
4449 case 0x07f: /* VIS I fones */
64a88d5d 4450 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4451 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4452 tcg_gen_movi_i32(cpu_dst_32, -1);
4453 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4454 break;
e9ebed4d
BS		 4455 case 0x080: /* VIS I shutdown */
4456 case 0x081: /* VIS II siam */
4457 // XXX
4458 goto illegal_insn;
3299908c
BS		 4459 default:
4460 goto illegal_insn;
4461 }
4462#else
0f8a249a 4463 goto ncp_insn;
3299908c
BS		 4464#endif
4465 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4466#ifdef TARGET_SPARC64
0f8a249a 4467 goto illegal_insn;
fcc72045 4468#else
0f8a249a 4469 goto ncp_insn;
fcc72045 4470#endif
3475187d 4471#ifdef TARGET_SPARC64
0f8a249a 4472 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4473 TCGv_i32 r_const;
2ea815ca 4474
66442b07 4475 save_state(dc);
9d1d4e34 4476 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4477 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4478 if (IS_IMM) { /* immediate */
67526b20 4479 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4480 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4481 } else { /* register */
3475187d 4482 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4483 if (rs2) {
97ea2859 4484 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4485 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4486 } else {
7b04bd5c 4487 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4488 }
3475187d 4489 }
063c3675 4490 gen_helper_restore(cpu_env);
13a6dd00 4491 gen_mov_pc_npc(dc);
2ea815ca 4492 r_const = tcg_const_i32(3);
7b04bd5c 4493 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4494 tcg_temp_free_i32(r_const);
7b04bd5c 4495 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4496 dc->npc = DYNAMIC_PC;
4497 goto jmp_insn;
3475187d 4498#endif
0f8a249a 4499 } else {
9d1d4e34 4500 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4501 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4502 if (IS_IMM) { /* immediate */
67526b20 4503 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4504 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4505 } else { /* register */
e80cfcfc 4506 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4507 if (rs2) {
97ea2859 4508 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4509 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4510 } else {
7b04bd5c 4511 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4512 }
cf495bcf 4513 }
0f8a249a
BS		 4514 switch (xop) {
4515 case 0x38: /* jmpl */
4516 {
97ea2859 4517 TCGv t;
a7812ae4 4518 TCGv_i32 r_const;
2ea815ca 4519
97ea2859
RH		 4520 t = gen_dest_gpr(dc, rd);
4521 tcg_gen_movi_tl(t, dc->pc);
4522 gen_store_gpr(dc, rd, t);
13a6dd00 4523 gen_mov_pc_npc(dc);
2ea815ca 4524 r_const = tcg_const_i32(3);
7b04bd5c 4525 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4526 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4527 gen_address_mask(dc, cpu_tmp0);
4528 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4529 dc->npc = DYNAMIC_PC;
4530 }
4531 goto jmp_insn;
3475187d 4532#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4533 case 0x39: /* rett, V9 return */
4534 {
a7812ae4 4535 TCGv_i32 r_const;
2ea815ca 4536
0f8a249a
BS		 4537 if (!supervisor(dc))
4538 goto priv_insn;
13a6dd00 4539 gen_mov_pc_npc(dc);
2ea815ca 4540 r_const = tcg_const_i32(3);
7b04bd5c 4541 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4542 tcg_temp_free_i32(r_const);
7b04bd5c 4543 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4544 dc->npc = DYNAMIC_PC;
063c3675 4545 gen_helper_rett(cpu_env);
0f8a249a
BS		 4546 }
4547 goto jmp_insn;
4548#endif
4549 case 0x3b: /* flush */
5578ceab 4550 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4551 goto unimp_flush;
dcfd14b3 4552 /* nop */
0f8a249a
BS		 4553 break;
4554 case 0x3c: /* save */
66442b07 4555 save_state(dc);
063c3675 4556 gen_helper_save(cpu_env);
7b04bd5c 4557 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4558 break;
4559 case 0x3d: /* restore */
66442b07 4560 save_state(dc);
063c3675 4561 gen_helper_restore(cpu_env);
7b04bd5c 4562 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4563 break;
3475187d 4564#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4565 case 0x3e: /* V9 done/retry */
4566 {
4567 switch (rd) {
4568 case 0:
4569 if (!supervisor(dc))
4570 goto priv_insn;
4571 dc->npc = DYNAMIC_PC;
4572 dc->pc = DYNAMIC_PC;
063c3675 4573 gen_helper_done(cpu_env);
0f8a249a
BS		 4574 goto jmp_insn;
4575 case 1:
4576 if (!supervisor(dc))
4577 goto priv_insn;
4578 dc->npc = DYNAMIC_PC;
4579 dc->pc = DYNAMIC_PC;
063c3675 4580 gen_helper_retry(cpu_env);
0f8a249a
BS		 4581 goto jmp_insn;
4582 default:
4583 goto illegal_insn;
4584 }
4585 }
4586 break;
4587#endif
4588 default:
4589 goto illegal_insn;
4590 }
cf495bcf 4591 }
0f8a249a
BS		 4592 break;
4593 }
4594 break;
4595 case 3: /* load/store instructions */
4596 {
4597 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4598 /* ??? gen_address_mask prevents us from using a source
4599 register directly. Always generate a temporary. */
4600 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4601
5e6ed439
RH		 4602 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4603 if (xop == 0x3c || xop == 0x3e) {
4604 /* V9 casa/casxa : no offset */
71817e48 4605 } else if (IS_IMM) { /* immediate */
67526b20 4606 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4607 if (simm != 0) {
4608 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4609 }
0f8a249a
BS		 4610 } else { /* register */
4611 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4612 if (rs2 != 0) {
5e6ed439 4613 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4614 }
0f8a249a 4615 }
2f2ecb83
BS		 4616 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4617 (xop > 0x17 && xop <= 0x1d ) ||
4618 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4619 TCGv cpu_val = gen_dest_gpr(dc, rd);
4620
0f8a249a 4621 switch (xop) {
b89e94af 4622 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4623 gen_address_mask(dc, cpu_addr);
6ae20372 4624 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4625 break;
b89e94af 4626 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4627 gen_address_mask(dc, cpu_addr);
6ae20372 4628 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4629 break;
b89e94af 4630 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4631 gen_address_mask(dc, cpu_addr);
6ae20372 4632 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4633 break;
b89e94af 4634 case 0x3: /* ldd, load double word */
0f8a249a 4635 if (rd & 1)
d4218d99 4636 goto illegal_insn;
1a2fb1c0 4637 else {
a7812ae4 4638 TCGv_i32 r_const;
abcc7191 4639 TCGv_i64 t64;
2ea815ca 4640
66442b07 4641 save_state(dc);
2ea815ca 4642 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4643 /* XXX remove alignment check */
4644 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4645 tcg_temp_free_i32(r_const);
2cade6a3 4646 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4647 t64 = tcg_temp_new_i64();
4648 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4649 tcg_gen_trunc_i64_tl(cpu_val, t64);
4650 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4651 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4652 tcg_gen_shri_i64(t64, t64, 32);
4653 tcg_gen_trunc_i64_tl(cpu_val, t64);
4654 tcg_temp_free_i64(t64);
de9e9d9f 4655 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4656 }
0f8a249a 4657 break;
b89e94af 4658 case 0x9: /* ldsb, load signed byte */
2cade6a3 4659 gen_address_mask(dc, cpu_addr);
6ae20372 4660 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4661 break;
b89e94af 4662 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4663 gen_address_mask(dc, cpu_addr);
6ae20372 4664 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4665 break;
4666 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4667 {
4668 TCGv r_const;
b64d2e57 4669 TCGv tmp = tcg_temp_new();
2ea815ca 4670
2cade6a3 4671 gen_address_mask(dc, cpu_addr);
b64d2e57 4672 tcg_gen_qemu_ld8u(tmp, cpu_addr, dc->mem_idx);
2ea815ca
BS		 4673 r_const = tcg_const_tl(0xff);
4674 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
b64d2e57 4675 tcg_gen_mov_tl(cpu_val, tmp);
2ea815ca 4676 tcg_temp_free(r_const);
b64d2e57 4677 tcg_temp_free(tmp);
2ea815ca 4678 }
0f8a249a 4679 break;
de9e9d9f
RH		 4680 case 0x0f:
4681 /* swap, swap register with memory. Also atomically */
4682 {
4683 TCGv t0 = get_temp_tl(dc);
4684 CHECK_IU_FEATURE(dc, SWAP);
4685 cpu_src1 = gen_load_gpr(dc, rd);
4686 gen_address_mask(dc, cpu_addr);
4687 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4688 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4689 tcg_gen_mov_tl(cpu_val, t0);
4690 }
0f8a249a 4691 break;
3475187d 4692#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4693 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4694#ifndef TARGET_SPARC64
0f8a249a
BS		 4695 if (IS_IMM)
4696 goto illegal_insn;
4697 if (!supervisor(dc))
4698 goto priv_insn;
6ea4a6c8 4699#endif
66442b07 4700 save_state(dc);
22e70060 4701 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4702 break;
b89e94af 4703 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4704#ifndef TARGET_SPARC64
0f8a249a
BS		 4705 if (IS_IMM)
4706 goto illegal_insn;
4707 if (!supervisor(dc))
4708 goto priv_insn;
4709#endif
66442b07 4710 save_state(dc);
22e70060 4711 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4712 break;
b89e94af 4713 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4714#ifndef TARGET_SPARC64
0f8a249a
BS		 4715 if (IS_IMM)
4716 goto illegal_insn;
4717 if (!supervisor(dc))
4718 goto priv_insn;
3475187d 4719#endif
66442b07 4720 save_state(dc);
22e70060 4721 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4722 break;
b89e94af 4723 case 0x13: /* ldda, load double word alternate */
3475187d 4724#ifndef TARGET_SPARC64
0f8a249a
BS		 4725 if (IS_IMM)
4726 goto illegal_insn;
4727 if (!supervisor(dc))
4728 goto priv_insn;
3475187d 4729#endif
0f8a249a 4730 if (rd & 1)
d4218d99 4731 goto illegal_insn;
66442b07 4732 save_state(dc);
c7785e16 4733 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4734 goto skip_move;
b89e94af 4735 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4736#ifndef TARGET_SPARC64
0f8a249a
BS		 4737 if (IS_IMM)
4738 goto illegal_insn;
4739 if (!supervisor(dc))
4740 goto priv_insn;
4741#endif
66442b07 4742 save_state(dc);
22e70060 4743 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4744 break;
b89e94af 4745 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4746#ifndef TARGET_SPARC64
0f8a249a
BS		 4747 if (IS_IMM)
4748 goto illegal_insn;
4749 if (!supervisor(dc))
4750 goto priv_insn;
3475187d 4751#endif
66442b07 4752 save_state(dc);
22e70060 4753 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4754 break;
4755 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4756#ifndef TARGET_SPARC64
0f8a249a
BS		 4757 if (IS_IMM)
4758 goto illegal_insn;
4759 if (!supervisor(dc))
4760 goto priv_insn;
4761#endif
66442b07 4762 save_state(dc);
22e70060 4763 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 4764 break;
b89e94af 4765 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4766 atomically */
64a88d5d 4767 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4768#ifndef TARGET_SPARC64
0f8a249a
BS		 4769 if (IS_IMM)
4770 goto illegal_insn;
4771 if (!supervisor(dc))
4772 goto priv_insn;
6ea4a6c8 4773#endif
66442b07 4774 save_state(dc);
06828032 4775 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 4776 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4777 break;
3475187d
FB		 4778
4779#ifndef TARGET_SPARC64
0f8a249a
BS		 4780 case 0x30: /* ldc */
4781 case 0x31: /* ldcsr */
4782 case 0x33: /* lddc */
4783 goto ncp_insn;
3475187d
FB		 4784#endif
4785#endif
4786#ifdef TARGET_SPARC64
0f8a249a 4787 case 0x08: /* V9 ldsw */
2cade6a3 4788 gen_address_mask(dc, cpu_addr);
6ae20372 4789 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4790 break;
4791 case 0x0b: /* V9 ldx */
2cade6a3 4792 gen_address_mask(dc, cpu_addr);
6ae20372 4793 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4794 break;
4795 case 0x18: /* V9 ldswa */
66442b07 4796 save_state(dc);
22e70060 4797 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4798 break;
4799 case 0x1b: /* V9 ldxa */
66442b07 4800 save_state(dc);
22e70060 4801 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4802 break;
4803 case 0x2d: /* V9 prefetch, no effect */
4804 goto skip_move;
4805 case 0x30: /* V9 ldfa */
5b12f1e8 4806 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4807 goto jmp_insn;
4808 }
66442b07 4809 save_state(dc);
22e70060 4810 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
638737ad 4811 gen_update_fprs_dirty(rd);
81ad8ba2 4812 goto skip_move;
0f8a249a 4813 case 0x33: /* V9 lddfa */
5b12f1e8 4814 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4815 goto jmp_insn;
4816 }
66442b07 4817 save_state(dc);
22e70060 4818 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
638737ad 4819 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4820 goto skip_move;
0f8a249a
BS		 4821 case 0x3d: /* V9 prefetcha, no effect */
4822 goto skip_move;
4823 case 0x32: /* V9 ldqfa */
64a88d5d 4824 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4825 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4826 goto jmp_insn;
4827 }
66442b07 4828 save_state(dc);
22e70060 4829 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
638737ad 4830 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4831 goto skip_move;
0f8a249a
BS		 4832#endif
4833 default:
4834 goto illegal_insn;
4835 }
97ea2859 4836 gen_store_gpr(dc, rd, cpu_val);
db166940 4837#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4838 skip_move: ;
3475187d 4839#endif
0f8a249a 4840 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4841 TCGv t0;
4842
5b12f1e8 4843 if (gen_trap_ifnofpu(dc)) {
a80dde08 4844 goto jmp_insn;
5b12f1e8 4845 }
66442b07 4846 save_state(dc);
0f8a249a 4847 switch (xop) {
b89e94af 4848 case 0x20: /* ldf, load fpreg */
2cade6a3 4849 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4850 t0 = get_temp_tl(dc);
4851 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4852 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4853 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4854 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4855 break;
3a3b925d
BS		 4856 case 0x21: /* ldfsr, V9 ldxfsr */
4857#ifdef TARGET_SPARC64
2cade6a3 4858 gen_address_mask(dc, cpu_addr);
3a3b925d 4859 if (rd == 1) {
abcc7191
RH		 4860 TCGv_i64 t64 = tcg_temp_new_i64();
4861 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4862 gen_helper_ldxfsr(cpu_env, t64);
4863 tcg_temp_free_i64(t64);
f8641947 4864 break;
fe987e23 4865 }
f8641947 4866#endif
de9e9d9f
RH		 4867 cpu_dst_32 = get_temp_i32(dc);
4868 t0 = get_temp_tl(dc);
4869 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4870 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4871 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4872 break;
b89e94af 4873 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4874 {
a7812ae4 4875 TCGv_i32 r_const;
2ea815ca
BS		 4876
4877 CHECK_FPU_FEATURE(dc, FLOAT128);
4878 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4879 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4880 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4881 tcg_temp_free_i32(r_const);
2ea815ca 4882 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4883 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4884 }
1f587329 4885 break;
b89e94af 4886 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4887 gen_address_mask(dc, cpu_addr);
3886b8a3 4888 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4889 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4890 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4891 break;
4892 default:
4893 goto illegal_insn;
4894 }
dc1a6971 4895 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4896 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4897 TCGv cpu_val = gen_load_gpr(dc, rd);
4898
0f8a249a 4899 switch (xop) {
b89e94af 4900 case 0x4: /* st, store word */
2cade6a3 4901 gen_address_mask(dc, cpu_addr);
6ae20372 4902 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4903 break;
b89e94af 4904 case 0x5: /* stb, store byte */
2cade6a3 4905 gen_address_mask(dc, cpu_addr);
6ae20372 4906 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4907 break;
b89e94af 4908 case 0x6: /* sth, store halfword */
2cade6a3 4909 gen_address_mask(dc, cpu_addr);
6ae20372 4910 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4911 break;
b89e94af 4912 case 0x7: /* std, store double word */
0f8a249a 4913 if (rd & 1)
d4218d99 4914 goto illegal_insn;
1a2fb1c0 4915 else {
a7812ae4 4916 TCGv_i32 r_const;
abcc7191 4917 TCGv_i64 t64;
81634eea 4918 TCGv lo;
1a2fb1c0 4919
66442b07 4920 save_state(dc);
2cade6a3 4921 gen_address_mask(dc, cpu_addr);
2ea815ca 4922 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4923 /* XXX remove alignment check */
4924 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4925 tcg_temp_free_i32(r_const);
81634eea 4926 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4927
4928 t64 = tcg_temp_new_i64();
4929 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4930 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4931 tcg_temp_free_i64(t64);
7fa76c0b 4932 }
0f8a249a 4933 break;
3475187d 4934#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4935 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4936#ifndef TARGET_SPARC64
0f8a249a
BS		 4937 if (IS_IMM)
4938 goto illegal_insn;
4939 if (!supervisor(dc))
4940 goto priv_insn;
6ea4a6c8 4941#endif
66442b07 4942 save_state(dc);
22e70060 4943 gen_st_asi(dc, cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4944 dc->npc = DYNAMIC_PC;
d39c0b99 4945 break;
b89e94af 4946 case 0x15: /* stba, store byte alternate */
3475187d 4947#ifndef TARGET_SPARC64
0f8a249a
BS		 4948 if (IS_IMM)
4949 goto illegal_insn;
4950 if (!supervisor(dc))
4951 goto priv_insn;
3475187d 4952#endif
66442b07 4953 save_state(dc);
22e70060 4954 gen_st_asi(dc, cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4955 dc->npc = DYNAMIC_PC;
d39c0b99 4956 break;
b89e94af 4957 case 0x16: /* stha, store halfword alternate */
3475187d 4958#ifndef TARGET_SPARC64
0f8a249a
BS		 4959 if (IS_IMM)
4960 goto illegal_insn;
4961 if (!supervisor(dc))
4962 goto priv_insn;
6ea4a6c8 4963#endif
66442b07 4964 save_state(dc);
22e70060 4965 gen_st_asi(dc, cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4966 dc->npc = DYNAMIC_PC;
d39c0b99 4967 break;
b89e94af 4968 case 0x17: /* stda, store double word alternate */
3475187d 4969#ifndef TARGET_SPARC64
0f8a249a
BS		 4970 if (IS_IMM)
4971 goto illegal_insn;
4972 if (!supervisor(dc))
4973 goto priv_insn;
3475187d 4974#endif
0f8a249a 4975 if (rd & 1)
d4218d99 4976 goto illegal_insn;
1a2fb1c0 4977 else {
66442b07 4978 save_state(dc);
c7785e16 4979 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4980 }
d39c0b99 4981 break;
e80cfcfc 4982#endif
3475187d 4983#ifdef TARGET_SPARC64
0f8a249a 4984 case 0x0e: /* V9 stx */
2cade6a3 4985 gen_address_mask(dc, cpu_addr);
6ae20372 4986 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4987 break;
4988 case 0x1e: /* V9 stxa */
66442b07 4989 save_state(dc);
22e70060 4990 gen_st_asi(dc, cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4991 dc->npc = DYNAMIC_PC;
0f8a249a 4992 break;
3475187d 4993#endif
0f8a249a
BS		 4994 default:
4995 goto illegal_insn;
4996 }
4997 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4998 if (gen_trap_ifnofpu(dc)) {
a80dde08 4999 goto jmp_insn;
5b12f1e8 5000 }
66442b07 5001 save_state(dc);
0f8a249a 5002 switch (xop) {
b89e94af 5003 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 5004 {
5005 TCGv t = get_temp_tl(dc);
5006 gen_address_mask(dc, cpu_addr);
5007 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5008 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5009 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5010 }
0f8a249a
BS		 5011 break;
5012 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5013 {
5014 TCGv t = get_temp_tl(dc);
5015
5016 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5017#ifdef TARGET_SPARC64
f8641947
RH		 5018 gen_address_mask(dc, cpu_addr);
5019 if (rd == 1) {
5020 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5021 break;
5022 }
3a3b925d 5023#endif
f8641947
RH		 5024 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5025 }
0f8a249a 5026 break;
1f587329
BS		 5027 case 0x26:
5028#ifdef TARGET_SPARC64
1f587329 5029 /* V9 stqf, store quad fpreg */
2ea815ca 5030 {
a7812ae4 5031 TCGv_i32 r_const;
2ea815ca
BS		 5032
5033 CHECK_FPU_FEATURE(dc, FLOAT128);
5034 gen_op_load_fpr_QT0(QFPREG(rd));
5035 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5036 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5037 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5038 tcg_temp_free_i32(r_const);
2ea815ca 5039 }
1f587329 5040 break;
1f587329
BS		 5041#else /* !TARGET_SPARC64 */
5042 /* stdfq, store floating point queue */
5043#if defined(CONFIG_USER_ONLY)
5044 goto illegal_insn;
5045#else
0f8a249a
BS		 5046 if (!supervisor(dc))
5047 goto priv_insn;
5b12f1e8 5048 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5049 goto jmp_insn;
5b12f1e8 5050 }
0f8a249a 5051 goto nfq_insn;
1f587329 5052#endif
0f8a249a 5053#endif
b89e94af 5054 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5055 gen_address_mask(dc, cpu_addr);
5056 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5057 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5058 break;
5059 default:
5060 goto illegal_insn;
5061 }
5062 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5063 save_state(dc);
0f8a249a 5064 switch (xop) {
a4d17f19 5065#ifdef TARGET_SPARC64
0f8a249a 5066 case 0x34: /* V9 stfa */
5b12f1e8 5067 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5068 goto jmp_insn;
5069 }
22e70060 5070 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5071 break;
1f587329 5072 case 0x36: /* V9 stqfa */
2ea815ca 5073 {
a7812ae4 5074 TCGv_i32 r_const;
2ea815ca
BS		 5075
5076 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5077 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5078 goto jmp_insn;
5079 }
2ea815ca 5080 r_const = tcg_const_i32(7);
fe8d8f0f 5081 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5082 tcg_temp_free_i32(r_const);
22e70060 5083 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5084 }
1f587329 5085 break;
0f8a249a 5086 case 0x37: /* V9 stdfa */
5b12f1e8 5087 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5088 goto jmp_insn;
5089 }
22e70060 5090 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5091 break;
0f8a249a 5092 case 0x3e: /* V9 casxa */
a4273524
RH		 5093 rs2 = GET_FIELD(insn, 27, 31);
5094 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5095 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5096 break;
a4d17f19 5097#else
0f8a249a
BS		 5098 case 0x34: /* stc */
5099 case 0x35: /* stcsr */
5100 case 0x36: /* stdcq */
5101 case 0x37: /* stdc */
5102 goto ncp_insn;
16c358e9
SH		 5103#endif
5104#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5105 case 0x3c: /* V9 or LEON3 casa */
5106#ifndef TARGET_SPARC64
5107 CHECK_IU_FEATURE(dc, CASA);
5108 if (IS_IMM) {
5109 goto illegal_insn;
5110 }
bd4e097a
AZ		 5111 /* LEON3 allows CASA from user space with ASI 0xa */
5112 if ((GET_FIELD(insn, 19, 26) != 0xa) && !supervisor(dc)) {
16c358e9
SH		 5113 goto priv_insn;
5114 }
5115#endif
5116 rs2 = GET_FIELD(insn, 27, 31);
5117 cpu_src2 = gen_load_gpr(dc, rs2);
5118 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5119 break;
0f8a249a
BS		 5120#endif
5121 default:
5122 goto illegal_insn;
5123 }
a4273524 5124 } else {
0f8a249a 5125 goto illegal_insn;
a4273524 5126 }
0f8a249a
BS		 5127 }
5128 break;
cf495bcf
FB		 5129 }
5130 /* default case for non jump instructions */
72cbca10 5131 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5132 dc->pc = DYNAMIC_PC;
5133 gen_op_next_insn();
72cbca10
FB		 5134 } else if (dc->npc == JUMP_PC) {
5135 /* we can do a static jump */
6ae20372 5136 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5137 dc->is_br = 1;
5138 } else {
0f8a249a
BS		 5139 dc->pc = dc->npc;
5140 dc->npc = dc->npc + 4;
cf495bcf 5141 }
e80cfcfc 5142 jmp_insn:
42a8aa83 5143 goto egress;
cf495bcf 5144 illegal_insn:
4fbe0067 5145 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5146 goto egress;
64a88d5d 5147 unimp_flush:
4fbe0067 5148 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5149 goto egress;
e80cfcfc 5150#if !defined(CONFIG_USER_ONLY)
e8af50a3 5151 priv_insn:
4fbe0067 5152 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5153 goto egress;
64a88d5d 5154#endif
e80cfcfc 5155 nfpu_insn:
4fbe0067 5156 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5157 goto egress;
64a88d5d 5158#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5159 nfq_insn:
4fbe0067 5160 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5161 goto egress;
9143e598 5162#endif
fcc72045
BS		 5163#ifndef TARGET_SPARC64
5164 ncp_insn:
4fbe0067 5165 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5166 goto egress;
fcc72045 5167#endif
42a8aa83 5168 egress:
30038fd8
RH		 5169 if (dc->n_t32 != 0) {
5170 int i;
5171 for (i = dc->n_t32 - 1; i >= 0; --i) {
5172 tcg_temp_free_i32(dc->t32[i]);
5173 }
5174 dc->n_t32 = 0;
5175 }
88023616
RH		 5176 if (dc->n_ttl != 0) {
5177 int i;
5178 for (i = dc->n_ttl - 1; i >= 0; --i) {
5179 tcg_temp_free(dc->ttl[i]);
5180 }
5181 dc->n_ttl = 0;
5182 }
7a3f1944
FB		 5183}
5184
4e5e1215 5185void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5186{
4e5e1215 5187 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5188 CPUState *cs = CPU(cpu);
72cbca10 5189 target_ulong pc_start, last_pc;
cf495bcf 5190 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5191 int num_insns;
5192 int max_insns;
0184e266 5193 unsigned int insn;
cf495bcf
FB		 5194
5195 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5196 dc->tb = tb;
72cbca10 5197 pc_start = tb->pc;
cf495bcf 5198 dc->pc = pc_start;
e80cfcfc 5199 last_pc = dc->pc;
72cbca10 5200 dc->npc = (target_ulong) tb->cs_base;
8393617c 5201 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5202 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
5578ceab 5203 dc->def = env->def;
f838e2c5
BS		 5204 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5205 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5206 dc->singlestep = (cs->singlestep_enabled || singlestep);
a6d567e5
RH		 5207#ifdef TARGET_SPARC64
5208 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
5209#endif
cf495bcf 5210
2e70f6ef
PB		 5211 num_insns = 0;
5212 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5213 if (max_insns == 0) {
2e70f6ef 5214 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5215 }
5216 if (max_insns > TCG_MAX_INSNS) {
5217 max_insns = TCG_MAX_INSNS;
5218 }
5219
cd42d5b2 5220 gen_tb_start(tb);
cf495bcf 5221 do {
a3d5ad76
RH		 5222 if (dc->npc & JUMP_PC) {
5223 assert(dc->jump_pc[1] == dc->pc + 4);
5224 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5225 } else {
5226 tcg_gen_insn_start(dc->pc, dc->npc);
5227 }
959082fc 5228 num_insns++;
522a0d4e 5229 last_pc = dc->pc;
667b8e29 5230
b933066a
RH		 5231 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5232 if (dc->pc != pc_start) {
5233 save_state(dc);
5234 }
5235 gen_helper_debug(cpu_env);
5236 tcg_gen_exit_tb(0);
5237 dc->is_br = 1;
5238 goto exit_gen_loop;
5239 }
5240
959082fc 5241 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5242 gen_io_start();
667b8e29
RH		 5243 }
5244
0184e266 5245 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5246
0184e266 5247 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5248
5249 if (dc->is_br)
5250 break;
5251 /* if the next PC is different, we abort now */
5252 if (dc->pc != (last_pc + 4))
5253 break;
d39c0b99
FB		 5254 /* if we reach a page boundary, we stop generation so that the
5255 PC of a TT_TFAULT exception is always in the right page */
5256 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5257 break;
e80cfcfc
FB		 5258 /* if single step mode, we generate only one instruction and
5259 generate an exception */
060718c1 5260 if (dc->singlestep) {
e80cfcfc
FB		 5261 break;
5262 }
fe700adb 5263 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5264 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5265 num_insns < max_insns);
e80cfcfc
FB		 5266
5267 exit_gen_loop:
b09b2fd3 5268 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5269 gen_io_end();
b09b2fd3 5270 }
72cbca10 5271 if (!dc->is_br) {
5fafdf24 5272 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5273 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5274 /* static PC and NPC: we can use direct chaining */
2f5680ee 5275 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5276 } else {
b09b2fd3 5277 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5278 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5279 }
934da7ee 5280 save_npc(dc);
57fec1fe 5281 tcg_gen_exit_tb(0);
72cbca10
FB		 5282 }
5283 }
806f352d 5284 gen_tb_end(tb, num_insns);
0a7df5da 5285
4e5e1215
RH		 5286 tb->size = last_pc + 4 - pc_start;
5287 tb->icount = num_insns;
5288
7a3f1944 5289#ifdef DEBUG_DISAS
4910e6e4
RH		 5290 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5291 && qemu_log_in_addr_range(pc_start)) {
93fcfe39
AL		 5292 qemu_log("--------------\n");
5293 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5294 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5295 qemu_log("\n");
cf495bcf 5296 }
7a3f1944 5297#endif
7a3f1944
FB		 5298}
5299
c48fcb47 5300void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5301{
c48fcb47 5302 static int inited;
d2dc4069 5303 static const char gregnames[32][4] = {
0ea63844 5304 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5305 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5306 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5307 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5308 };
0ea63844 5309 static const char fregnames[32][4] = {
30038fd8
RH		 5310 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5311 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5312 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5313 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5314 };
aaed909a 5315
0ea63844 5316 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5317#ifdef TARGET_SPARC64
0ea63844 5318 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5319 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5320#else
0ea63844
RH		 5321 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5322#endif
5323 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5324 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5325 };
5326
5327 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5328#ifdef TARGET_SPARC64
5329 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5330 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5331 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5332 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5333 "hstick_cmpr" },
5334 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5335 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5336 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5337 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5338 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5339#endif
0ea63844
RH		 5340 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5341 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5342 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5343 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5344 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5345 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5346 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5347 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5348#ifndef CONFIG_USER_ONLY
0ea63844 5349 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5350#endif
0ea63844
RH		 5351 };
5352
5353 unsigned int i;
5354
5355 /* init various static tables */
5356 if (inited) {
5357 return;
5358 }
5359 inited = 1;
5360
5361 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 5362 tcg_ctx.tcg_env = cpu_env;
0ea63844
RH		 5363
5364 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5365 offsetof(CPUSPARCState, regwptr),
5366 "regwptr");
5367
5368 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5369 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5370 }
5371
5372 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5373 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5374 }
5375
d2dc4069 5376 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5377 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5378 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5379 offsetof(CPUSPARCState, gregs[i]),
5380 gregnames[i]);
5381 }
5382
5383 for (i = 8; i < 32; ++i) {
5384 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5385 (i - 8) * sizeof(target_ulong),
5386 gregnames[i]);
0ea63844
RH		 5387 }
5388
5389 for (i = 0; i < TARGET_DPREGS; i++) {
5390 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5391 offsetof(CPUSPARCState, fpr[i]),
5392 fregnames[i]);
1a2fb1c0 5393 }
658138bc 5394}
d2856f1a 5395
bad729e2
RH		 5396void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5397 target_ulong *data)
d2856f1a 5398{
bad729e2
RH		 5399 target_ulong pc = data[0];
5400 target_ulong npc = data[1];
5401
5402 env->pc = pc;
6c42444f 5403 if (npc == DYNAMIC_PC) {
d2856f1a 5404 /* dynamic NPC: already stored */
6c42444f 5405 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5406 /* jump PC: use 'cond' and the jump targets of the translation */
5407 if (env->cond) {
6c42444f 5408 env->npc = npc & ~3;
d7da2a10 5409 } else {
6c42444f 5410 env->npc = pc + 4;
d7da2a10 5411 }
d2856f1a
AJ		 5412 } else {
5413 env->npc = npc;
5414 }
5415}
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