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KVM: x86: decode_modrm does not regard modrm correctly
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
8b3c3104 232int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 236 int err;
18863bdd 237
2bf78fa7 238 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 239 return 0;
2bf78fa7 240 smsr->values[slot].curr = value;
8b3c3104
AH		 241 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
242 if (err)
243 return 1;
244
18863bdd
AK		 245 if (!smsr->registered) {
246 smsr->urn.on_user_return = kvm_on_user_return;
247 user_return_notifier_register(&smsr->urn);
248 smsr->registered = true;
249 }
8b3c3104 250 return 0;
18863bdd
AK		 251}
252EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
253
13a34e06 254static void drop_user_return_notifiers(void)
3548bab5 255{
013f6a5d
MT		 256 unsigned int cpu = smp_processor_id();
257 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 258
259 if (smsr->registered)
260 kvm_on_user_return(&smsr->urn);
261}
262
6866b83e
CO		 263u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
264{
8a5a87d9 265 return vcpu->arch.apic_base;
6866b83e
CO		 266}
267EXPORT_SYMBOL_GPL(kvm_get_apic_base);
268
58cb628d
JK		 269int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
270{
271 u64 old_state = vcpu->arch.apic_base &
272 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
273 u64 new_state = msr_info->data &
274 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
275 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
276 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
277
278 if (!msr_info->host_initiated &&
279 ((msr_info->data & reserved_bits) != 0 ||
280 new_state == X2APIC_ENABLE ||
281 (new_state == MSR_IA32_APICBASE_ENABLE &&
282 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
283 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
284 old_state == 0)))
285 return 1;
286
287 kvm_lapic_set_base(vcpu, msr_info->data);
288 return 0;
6866b83e
CO		 289}
290EXPORT_SYMBOL_GPL(kvm_set_apic_base);
291
2605fc21 292asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 293{
294 /* Fault while not rebooting. We want the trace. */
295 BUG();
296}
297EXPORT_SYMBOL_GPL(kvm_spurious_fault);
298
3fd28fce
ED		 299#define EXCPT_BENIGN 0
300#define EXCPT_CONTRIBUTORY 1
301#define EXCPT_PF 2
302
303static int exception_class(int vector)
304{
305 switch (vector) {
306 case PF_VECTOR:
307 return EXCPT_PF;
308 case DE_VECTOR:
309 case TS_VECTOR:
310 case NP_VECTOR:
311 case SS_VECTOR:
312 case GP_VECTOR:
313 return EXCPT_CONTRIBUTORY;
314 default:
315 break;
316 }
317 return EXCPT_BENIGN;
318}
319
d6e8c854
NA		 320#define EXCPT_FAULT 0
321#define EXCPT_TRAP 1
322#define EXCPT_ABORT 2
323#define EXCPT_INTERRUPT 3
324
325static int exception_type(int vector)
326{
327 unsigned int mask;
328
329 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
330 return EXCPT_INTERRUPT;
331
332 mask = 1 << vector;
333
334 /* #DB is trap, as instruction watchpoints are handled elsewhere */
335 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
336 return EXCPT_TRAP;
337
338 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
339 return EXCPT_ABORT;
340
341 /* Reserved exceptions will result in fault */
342 return EXCPT_FAULT;
343}
344
3fd28fce 345static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 346 unsigned nr, bool has_error, u32 error_code,
347 bool reinject)
3fd28fce
ED		 348{
349 u32 prev_nr;
350 int class1, class2;
351
3842d135
AK		 352 kvm_make_request(KVM_REQ_EVENT, vcpu);
353
3fd28fce
ED		 354 if (!vcpu->arch.exception.pending) {
355 queue:
356 vcpu->arch.exception.pending = true;
357 vcpu->arch.exception.has_error_code = has_error;
358 vcpu->arch.exception.nr = nr;
359 vcpu->arch.exception.error_code = error_code;
3f0fd292 360 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 361 return;
362 }
363
364 /* to check exception */
365 prev_nr = vcpu->arch.exception.nr;
366 if (prev_nr == DF_VECTOR) {
367 /* triple fault -> shutdown */
a8eeb04a 368 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 369 return;
370 }
371 class1 = exception_class(prev_nr);
372 class2 = exception_class(nr);
373 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
374 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
375 /* generate double fault per SDM Table 5-5 */
376 vcpu->arch.exception.pending = true;
377 vcpu->arch.exception.has_error_code = true;
378 vcpu->arch.exception.nr = DF_VECTOR;
379 vcpu->arch.exception.error_code = 0;
380 } else
381 /* replace previous exception with a new one in a hope
382 that instruction re-execution will regenerate lost
383 exception */
384 goto queue;
385}
386
298101da
AK		 387void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
388{
ce7ddec4 389 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 390}
391EXPORT_SYMBOL_GPL(kvm_queue_exception);
392
ce7ddec4
JR		 393void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
394{
395 kvm_multiple_exception(vcpu, nr, false, 0, true);
396}
397EXPORT_SYMBOL_GPL(kvm_requeue_exception);
398
db8fcefa 399void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 400{
db8fcefa
AP		 401 if (err)
402 kvm_inject_gp(vcpu, 0);
403 else
404 kvm_x86_ops->skip_emulated_instruction(vcpu);
405}
406EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 407
6389ee94 408void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 409{
410 ++vcpu->stat.pf_guest;
6389ee94
AK		 411 vcpu->arch.cr2 = fault->address;
412 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 413}
27d6c865 414EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 415
ef54bcfe 416static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 417{
6389ee94
AK		 418 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
419 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 420 else
6389ee94 421 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 422
423 return fault->nested_page_fault;
d4f8cf66
JR		 424}
425
3419ffc8
SY		 426void kvm_inject_nmi(struct kvm_vcpu *vcpu)
427{
7460fb4a
AK		 428 atomic_inc(&vcpu->arch.nmi_queued);
429 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 430}
431EXPORT_SYMBOL_GPL(kvm_inject_nmi);
432
298101da
AK		 433void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
434{
ce7ddec4 435 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 436}
437EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
438
ce7ddec4
JR		 439void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
440{
441 kvm_multiple_exception(vcpu, nr, true, error_code, true);
442}
443EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
444
0a79b009
AK		 445/*
446 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
447 * a #GP and return false.
448 */
449bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 450{
0a79b009
AK		 451 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
452 return true;
453 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
454 return false;
298101da 455}
0a79b009 456EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 457
16f8a6f9
NA		 458bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
459{
460 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
461 return true;
462
463 kvm_queue_exception(vcpu, UD_VECTOR);
464 return false;
465}
466EXPORT_SYMBOL_GPL(kvm_require_dr);
467
ec92fe44
JR		 468/*
469 * This function will be used to read from the physical memory of the currently
470 * running guest. The difference to kvm_read_guest_page is that this function
471 * can read from guest physical or from the guest's guest physical memory.
472 */
473int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
474 gfn_t ngfn, void *data, int offset, int len,
475 u32 access)
476{
54987b7a 477 struct x86_exception exception;
ec92fe44
JR		 478 gfn_t real_gfn;
479 gpa_t ngpa;
480
481 ngpa = gfn_to_gpa(ngfn);
54987b7a 482 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 483 if (real_gfn == UNMAPPED_GVA)
484 return -EFAULT;
485
486 real_gfn = gpa_to_gfn(real_gfn);
487
488 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
489}
490EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
491
3d06b8bf
JR		 492int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
493 void *data, int offset, int len, u32 access)
494{
495 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
496 data, offset, len, access);
497}
498
a03490ed
CO		 499/*
500 * Load the pae pdptrs. Return true is they are all valid.
501 */
ff03a073 502int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 503{
504 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
505 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
506 int i;
507 int ret;
ff03a073 508 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 509
ff03a073
JR		 510 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
511 offset * sizeof(u64), sizeof(pdpte),
512 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 513 if (ret < 0) {
514 ret = 0;
515 goto out;
516 }
517 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 518 if (is_present_gpte(pdpte[i]) &&
20c466b5 519 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 520 ret = 0;
521 goto out;
522 }
523 }
524 ret = 1;
525
ff03a073 526 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 527 __set_bit(VCPU_EXREG_PDPTR,
528 (unsigned long *)&vcpu->arch.regs_avail);
529 __set_bit(VCPU_EXREG_PDPTR,
530 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 531out:
a03490ed
CO		 532
533 return ret;
534}
cc4b6871 535EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 536
d835dfec
AK		 537static bool pdptrs_changed(struct kvm_vcpu *vcpu)
538{
ff03a073 539 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 540 bool changed = true;
3d06b8bf
JR		 541 int offset;
542 gfn_t gfn;
d835dfec
AK		 543 int r;
544
545 if (is_long_mode(vcpu) || !is_pae(vcpu))
546 return false;
547
6de4f3ad
AK		 548 if (!test_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_avail))
550 return true;
551
9f8fe504
AK		 552 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
553 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 554 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
555 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 556 if (r < 0)
557 goto out;
ff03a073 558 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 559out:
d835dfec
AK		 560
561 return changed;
562}
563
49a9b07e 564int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 565{
aad82703
SY		 566 unsigned long old_cr0 = kvm_read_cr0(vcpu);
567 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
568 X86_CR0_CD | X86_CR0_NW;
569
f9a48e6a
AK		 570 cr0 |= X86_CR0_ET;
571
ab344828 572#ifdef CONFIG_X86_64
0f12244f
GN		 573 if (cr0 & 0xffffffff00000000UL)
574 return 1;
ab344828
GN		 575#endif
576
577 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 578
0f12244f
GN		 579 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
580 return 1;
a03490ed 581
0f12244f
GN		 582 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
583 return 1;
a03490ed
CO		 584
585 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
586#ifdef CONFIG_X86_64
f6801dff 587 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 588 int cs_db, cs_l;
589
0f12244f
GN		 590 if (!is_pae(vcpu))
591 return 1;
a03490ed 592 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 593 if (cs_l)
594 return 1;
a03490ed
CO		 595 } else
596#endif
ff03a073 597 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 598 kvm_read_cr3(vcpu)))
0f12244f 599 return 1;
a03490ed
CO		 600 }
601
ad756a16
MJ		 602 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
603 return 1;
604
a03490ed 605 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 606
d170c419 607 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 608 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 609 kvm_async_pf_hash_reset(vcpu);
610 }
e5f3f027 611
aad82703
SY		 612 if ((cr0 ^ old_cr0) & update_bits)
613 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 614 return 0;
615}
2d3ad1f4 616EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 617
2d3ad1f4 618void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 619{
49a9b07e 620 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 621}
2d3ad1f4 622EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 623
42bdf991
MT		 624static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
625{
626 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
627 !vcpu->guest_xcr0_loaded) {
628 /* kvm_set_xcr() also depends on this */
629 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
630 vcpu->guest_xcr0_loaded = 1;
631 }
632}
633
634static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (vcpu->guest_xcr0_loaded) {
637 if (vcpu->arch.xcr0 != host_xcr0)
638 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
639 vcpu->guest_xcr0_loaded = 0;
640 }
641}
642
2acf923e
DC		 643int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
644{
56c103ec
LJ		 645 u64 xcr0 = xcr;
646 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 647 u64 valid_bits;
2acf923e
DC		 648
649 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
650 if (index != XCR_XFEATURE_ENABLED_MASK)
651 return 1;
2acf923e
DC		 652 if (!(xcr0 & XSTATE_FP))
653 return 1;
654 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
655 return 1;
46c34cb0
PB		 656
657 /*
658 * Do not allow the guest to set bits that we do not support
659 * saving. However, xcr0 bit 0 is always set, even if the
660 * emulated CPU does not support XSAVE (see fx_init).
661 */
662 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
663 if (xcr0 & ~valid_bits)
2acf923e 664 return 1;
46c34cb0 665
390bd528
LJ		 666 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
667 return 1;
668
612263b3
CP		 669 if (xcr0 & XSTATE_AVX512) {
670 if (!(xcr0 & XSTATE_YMM))
671 return 1;
672 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
673 return 1;
674 }
42bdf991 675 kvm_put_guest_xcr0(vcpu);
2acf923e 676 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 677
678 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
679 kvm_update_cpuid(vcpu);
2acf923e
DC		 680 return 0;
681}
682
683int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
684{
764bcbc5
Z		 685 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
686 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 687 kvm_inject_gp(vcpu, 0);
688 return 1;
689 }
690 return 0;
691}
692EXPORT_SYMBOL_GPL(kvm_set_xcr);
693
a83b29c6 694int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 695{
fc78f519 696 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 697 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
698 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 699 if (cr4 & CR4_RESERVED_BITS)
700 return 1;
a03490ed 701
2acf923e
DC		 702 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
703 return 1;
704
c68b734f
YW		 705 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
706 return 1;
707
97ec8c06
FW		 708 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
709 return 1;
710
afcbf13f 711 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 712 return 1;
713
a03490ed 714 if (is_long_mode(vcpu)) {
0f12244f
GN		 715 if (!(cr4 & X86_CR4_PAE))
716 return 1;
a2edf57f
AK		 717 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
718 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 719 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
720 kvm_read_cr3(vcpu)))
0f12244f
GN		 721 return 1;
722
ad756a16
MJ		 723 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
724 if (!guest_cpuid_has_pcid(vcpu))
725 return 1;
726
727 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
728 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
729 return 1;
730 }
731
5e1746d6 732 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 733 return 1;
a03490ed 734
ad756a16
MJ		 735 if (((cr4 ^ old_cr4) & pdptr_bits) ||
736 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 737 kvm_mmu_reset_context(vcpu);
0f12244f 738
97ec8c06
FW		 739 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
740 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
741
2acf923e 742 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 743 kvm_update_cpuid(vcpu);
2acf923e 744
0f12244f
GN		 745 return 0;
746}
2d3ad1f4 747EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 748
2390218b 749int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 750{
9f8fe504 751 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 752 kvm_mmu_sync_roots(vcpu);
77c3913b 753 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 754 return 0;
d835dfec
AK		 755 }
756
a03490ed 757 if (is_long_mode(vcpu)) {
d9f89b88
JK		 758 if (cr3 & CR3_L_MODE_RESERVED_BITS)
759 return 1;
760 } else if (is_pae(vcpu) && is_paging(vcpu) &&
761 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 762 return 1;
a03490ed 763
0f12244f 764 vcpu->arch.cr3 = cr3;
aff48baa 765 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 766 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 767 return 0;
768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 770
eea1cff9 771int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 772{
0f12244f
GN		 773 if (cr8 & CR8_RESERVED_BITS)
774 return 1;
a03490ed
CO		 775 if (irqchip_in_kernel(vcpu->kvm))
776 kvm_lapic_set_tpr(vcpu, cr8);
777 else
ad312c7c 778 vcpu->arch.cr8 = cr8;
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 782
2d3ad1f4 783unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 784{
785 if (irqchip_in_kernel(vcpu->kvm))
786 return kvm_lapic_get_cr8(vcpu);
787 else
ad312c7c 788 return vcpu->arch.cr8;
a03490ed 789}
2d3ad1f4 790EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 791
73aaf249
JK		 792static void kvm_update_dr6(struct kvm_vcpu *vcpu)
793{
794 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
795 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
796}
797
c8639010
JK		 798static void kvm_update_dr7(struct kvm_vcpu *vcpu)
799{
800 unsigned long dr7;
801
802 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
803 dr7 = vcpu->arch.guest_debug_dr7;
804 else
805 dr7 = vcpu->arch.dr7;
806 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 807 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
808 if (dr7 & DR7_BP_EN_MASK)
809 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 810}
811
6f43ed01
NA		 812static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
813{
814 u64 fixed = DR6_FIXED_1;
815
816 if (!guest_cpuid_has_rtm(vcpu))
817 fixed |= DR6_RTM;
818 return fixed;
819}
820
338dbc97 821static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 822{
823 switch (dr) {
824 case 0 ... 3:
825 vcpu->arch.db[dr] = val;
826 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
827 vcpu->arch.eff_db[dr] = val;
828 break;
829 case 4:
020df079
GN		 830 /* fall through */
831 case 6:
338dbc97
GN		 832 if (val & 0xffffffff00000000ULL)
833 return -1; /* #GP */
6f43ed01 834 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 835 kvm_update_dr6(vcpu);
020df079
GN		 836 break;
837 case 5:
020df079
GN		 838 /* fall through */
839 default: /* 7 */
338dbc97
GN		 840 if (val & 0xffffffff00000000ULL)
841 return -1; /* #GP */
020df079 842 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 843 kvm_update_dr7(vcpu);
020df079
GN		 844 break;
845 }
846
847 return 0;
848}
338dbc97
GN		 849
850int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
851{
16f8a6f9 852 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 853 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 854 return 1;
855 }
856 return 0;
338dbc97 857}
020df079
GN		 858EXPORT_SYMBOL_GPL(kvm_set_dr);
859
16f8a6f9 860int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 861{
862 switch (dr) {
863 case 0 ... 3:
864 *val = vcpu->arch.db[dr];
865 break;
866 case 4:
020df079
GN		 867 /* fall through */
868 case 6:
73aaf249
JK		 869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 *val = vcpu->arch.dr6;
871 else
872 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 873 break;
874 case 5:
020df079
GN		 875 /* fall through */
876 default: /* 7 */
877 *val = vcpu->arch.dr7;
878 break;
879 }
338dbc97
GN		 880 return 0;
881}
020df079
GN		 882EXPORT_SYMBOL_GPL(kvm_get_dr);
883
022cd0e8
AK		 884bool kvm_rdpmc(struct kvm_vcpu *vcpu)
885{
886 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
887 u64 data;
888 int err;
889
890 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
891 if (err)
892 return err;
893 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
894 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
895 return err;
896}
897EXPORT_SYMBOL_GPL(kvm_rdpmc);
898
043405e1
CO		 899/*
900 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
901 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
902 *
903 * This list is modified at module load time to reflect the
e3267cbb
GC		 904 * capabilities of the host cpu. This capabilities test skips MSRs that are
905 * kvm-specific. Those are put in the beginning of the list.
043405e1 906 */
e3267cbb 907
e984097b 908#define KVM_SAVE_MSRS_BEGIN 12
043405e1 909static u32 msrs_to_save[] = {
e3267cbb 910 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 911 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 912 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 913 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 914 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 915 MSR_KVM_PV_EOI_EN,
043405e1 916 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 917 MSR_STAR,
043405e1
CO		 918#ifdef CONFIG_X86_64
919 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
920#endif
b3897a49 921 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 922 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 923};
924
925static unsigned num_msrs_to_save;
926
f1d24831 927static const u32 emulated_msrs[] = {
ba904635 928 MSR_IA32_TSC_ADJUST,
a3e06bbe 929 MSR_IA32_TSCDEADLINE,
043405e1 930 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 931 MSR_IA32_MCG_STATUS,
932 MSR_IA32_MCG_CTL,
043405e1
CO		 933};
934
384bb783 935bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 936{
b69e8cae 937 if (efer & efer_reserved_bits)
384bb783 938 return false;
15c4a640 939
1b2fd70c
AG		 940 if (efer & EFER_FFXSR) {
941 struct kvm_cpuid_entry2 *feat;
942
943 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 944 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 945 return false;
1b2fd70c
AG		 946 }
947
d8017474
AG		 948 if (efer & EFER_SVME) {
949 struct kvm_cpuid_entry2 *feat;
950
951 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 952 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 953 return false;
d8017474
AG		 954 }
955
384bb783
JK		 956 return true;
957}
958EXPORT_SYMBOL_GPL(kvm_valid_efer);
959
960static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
961{
962 u64 old_efer = vcpu->arch.efer;
963
964 if (!kvm_valid_efer(vcpu, efer))
965 return 1;
966
967 if (is_paging(vcpu)
968 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
969 return 1;
970
15c4a640 971 efer &= ~EFER_LMA;
f6801dff 972 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 973
a3d204e2
SY		 974 kvm_x86_ops->set_efer(vcpu, efer);
975
aad82703
SY		 976 /* Update reserved bits */
977 if ((efer ^ old_efer) & EFER_NX)
978 kvm_mmu_reset_context(vcpu);
979
b69e8cae 980 return 0;
15c4a640
CO		 981}
982
f2b4b7dd
JR		 983void kvm_enable_efer_bits(u64 mask)
984{
985 efer_reserved_bits &= ~mask;
986}
987EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
988
15c4a640
CO		 989/*
990 * Writes msr value into into the appropriate "register".
991 * Returns 0 on success, non-0 otherwise.
992 * Assumes vcpu_load() was already called.
993 */
8fe8ab46 994int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 995{
854e8bb1
NA		 996 switch (msr->index) {
997 case MSR_FS_BASE:
998 case MSR_GS_BASE:
999 case MSR_KERNEL_GS_BASE:
1000 case MSR_CSTAR:
1001 case MSR_LSTAR:
1002 if (is_noncanonical_address(msr->data))
1003 return 1;
1004 break;
1005 case MSR_IA32_SYSENTER_EIP:
1006 case MSR_IA32_SYSENTER_ESP:
1007 /*
1008 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1009 * non-canonical address is written on Intel but not on
1010 * AMD (which ignores the top 32-bits, because it does
1011 * not implement 64-bit SYSENTER).
1012 *
1013 * 64-bit code should hence be able to write a non-canonical
1014 * value on AMD. Making the address canonical ensures that
1015 * vmentry does not fail on Intel after writing a non-canonical
1016 * value, and that something deterministic happens if the guest
1017 * invokes 64-bit SYSENTER.
1018 */
1019 msr->data = get_canonical(msr->data);
1020 }
8fe8ab46 1021 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1022}
854e8bb1 1023EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1024
313a3dc7
CO		 1025/*
1026 * Adapt set_msr() to msr_io()'s calling convention
1027 */
1028static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1029{
8fe8ab46
WA		 1030 struct msr_data msr;
1031
1032 msr.data = *data;
1033 msr.index = index;
1034 msr.host_initiated = true;
1035 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1036}
1037
16e8d74d
MT		 1038#ifdef CONFIG_X86_64
1039struct pvclock_gtod_data {
1040 seqcount_t seq;
1041
1042 struct { /* extract of a clocksource struct */
1043 int vclock_mode;
1044 cycle_t cycle_last;
1045 cycle_t mask;
1046 u32 mult;
1047 u32 shift;
1048 } clock;
1049
cbcf2dd3
TG		 1050 u64 boot_ns;
1051 u64 nsec_base;
16e8d74d
MT		 1052};
1053
1054static struct pvclock_gtod_data pvclock_gtod_data;
1055
1056static void update_pvclock_gtod(struct timekeeper *tk)
1057{
1058 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1059 u64 boot_ns;
1060
d28ede83 1061 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1062
1063 write_seqcount_begin(&vdata->seq);
1064
1065 /* copy pvclock gtod data */
d28ede83
TG		 1066 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1067 vdata->clock.cycle_last = tk->tkr.cycle_last;
1068 vdata->clock.mask = tk->tkr.mask;
1069 vdata->clock.mult = tk->tkr.mult;
1070 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1071
cbcf2dd3 1072 vdata->boot_ns = boot_ns;
d28ede83 1073 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1074
1075 write_seqcount_end(&vdata->seq);
1076}
1077#endif
1078
1079
18068523
GOC		 1080static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1081{
9ed3c444
AK		 1082 int version;
1083 int r;
50d0a0f9 1084 struct pvclock_wall_clock wc;
923de3cf 1085 struct timespec boot;
18068523
GOC		 1086
1087 if (!wall_clock)
1088 return;
1089
9ed3c444
AK		 1090 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1091 if (r)
1092 return;
1093
1094 if (version & 1)
1095 ++version; /* first time write, random junk */
1096
1097 ++version;
18068523 1098
18068523
GOC		 1099 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1100
50d0a0f9
GH		 1101 /*
1102 * The guest calculates current wall clock time by adding
34c238a1 1103 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1104 * wall clock specified here. guest system time equals host
1105 * system time for us, thus we must fill in host boot time here.
1106 */
923de3cf 1107 getboottime(&boot);
50d0a0f9 1108
4b648665
BR		 1109 if (kvm->arch.kvmclock_offset) {
1110 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1111 boot = timespec_sub(boot, ts);
1112 }
50d0a0f9
GH		 1113 wc.sec = boot.tv_sec;
1114 wc.nsec = boot.tv_nsec;
1115 wc.version = version;
18068523
GOC		 1116
1117 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1118
1119 version++;
1120 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1121}
1122
50d0a0f9
GH		 1123static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1124{
1125 uint32_t quotient, remainder;
1126
1127 /* Don't try to replace with do_div(), this one calculates
1128 * "(dividend << 32) / divisor" */
1129 __asm__ ( "divl %4"
1130 : "=a" (quotient), "=d" (remainder)
1131 : "0" (0), "1" (dividend), "r" (divisor) );
1132 return quotient;
1133}
1134
5f4e3f88
ZA		 1135static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1136 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1137{
5f4e3f88 1138 uint64_t scaled64;
50d0a0f9
GH		 1139 int32_t shift = 0;
1140 uint64_t tps64;
1141 uint32_t tps32;
1142
5f4e3f88
ZA		 1143 tps64 = base_khz * 1000LL;
1144 scaled64 = scaled_khz * 1000LL;
50933623 1145 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1146 tps64 >>= 1;
1147 shift--;
1148 }
1149
1150 tps32 = (uint32_t)tps64;
50933623
JK		 1151 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1152 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1153 scaled64 >>= 1;
1154 else
1155 tps32 <<= 1;
50d0a0f9
GH		 1156 shift++;
1157 }
1158
5f4e3f88
ZA		 1159 *pshift = shift;
1160 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1161
5f4e3f88
ZA		 1162 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1163 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1164}
1165
759379dd
ZA		 1166static inline u64 get_kernel_ns(void)
1167{
bb0b5812 1168 return ktime_get_boot_ns();
50d0a0f9
GH		 1169}
1170
d828199e 1171#ifdef CONFIG_X86_64
16e8d74d 1172static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1173#endif
16e8d74d 1174
c8076604 1175static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1176unsigned long max_tsc_khz;
c8076604 1177
cc578287 1178static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1179{
cc578287
ZA		 1180 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1181 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1182}
1183
cc578287 1184static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1185{
cc578287
ZA		 1186 u64 v = (u64)khz * (1000000 + ppm);
1187 do_div(v, 1000000);
1188 return v;
1e993611
JR		 1189}
1190
cc578287 1191static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1192{
cc578287
ZA		 1193 u32 thresh_lo, thresh_hi;
1194 int use_scaling = 0;
217fc9cf 1195
03ba32ca
MT		 1196 /* tsc_khz can be zero if TSC calibration fails */
1197 if (this_tsc_khz == 0)
1198 return;
1199
c285545f
ZA		 1200 /* Compute a scale to convert nanoseconds in TSC cycles */
1201 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1202 &vcpu->arch.virtual_tsc_shift,
1203 &vcpu->arch.virtual_tsc_mult);
1204 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1205
1206 /*
1207 * Compute the variation in TSC rate which is acceptable
1208 * within the range of tolerance and decide if the
1209 * rate being applied is within that bounds of the hardware
1210 * rate. If so, no scaling or compensation need be done.
1211 */
1212 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1213 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1214 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1215 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1216 use_scaling = 1;
1217 }
1218 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1219}
1220
1221static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1222{
e26101b1 1223 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1224 vcpu->arch.virtual_tsc_mult,
1225 vcpu->arch.virtual_tsc_shift);
e26101b1 1226 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1227 return tsc;
1228}
1229
b48aa97e
MT		 1230void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1231{
1232#ifdef CONFIG_X86_64
1233 bool vcpus_matched;
1234 bool do_request = false;
1235 struct kvm_arch *ka = &vcpu->kvm->arch;
1236 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1237
1238 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1239 atomic_read(&vcpu->kvm->online_vcpus));
1240
1241 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1242 if (!ka->use_master_clock)
1243 do_request = 1;
1244
1245 if (!vcpus_matched && ka->use_master_clock)
1246 do_request = 1;
1247
1248 if (do_request)
1249 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1250
1251 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1252 atomic_read(&vcpu->kvm->online_vcpus),
1253 ka->use_master_clock, gtod->clock.vclock_mode);
1254#endif
1255}
1256
ba904635
WA		 1257static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1258{
1259 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1260 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1261}
1262
8fe8ab46 1263void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1264{
1265 struct kvm *kvm = vcpu->kvm;
f38e098f 1266 u64 offset, ns, elapsed;
99e3e30a 1267 unsigned long flags;
02626b6a 1268 s64 usdiff;
b48aa97e 1269 bool matched;
0d3da0d2 1270 bool already_matched;
8fe8ab46 1271 u64 data = msr->data;
99e3e30a 1272
038f8c11 1273 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1274 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1275 ns = get_kernel_ns();
f38e098f 1276 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1277
03ba32ca 1278 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1279 int faulted = 0;
1280
03ba32ca
MT		 1281 /* n.b - signed multiplication and division required */
1282 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1283#ifdef CONFIG_X86_64
03ba32ca 1284 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1285#else
03ba32ca 1286 /* do_div() only does unsigned */
8915aa27
MT		 1287 asm("1: idivl %[divisor]\n"
1288 "2: xor %%edx, %%edx\n"
1289 " movl $0, %[faulted]\n"
1290 "3:\n"
1291 ".section .fixup,\"ax\"\n"
1292 "4: movl $1, %[faulted]\n"
1293 " jmp 3b\n"
1294 ".previous\n"
1295
1296 _ASM_EXTABLE(1b, 4b)
1297
1298 : "=A"(usdiff), [faulted] "=r" (faulted)
1299 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1300
5d3cb0f6 1301#endif
03ba32ca
MT		 1302 do_div(elapsed, 1000);
1303 usdiff -= elapsed;
1304 if (usdiff < 0)
1305 usdiff = -usdiff;
8915aa27
MT		 1306
1307 /* idivl overflow => difference is larger than USEC_PER_SEC */
1308 if (faulted)
1309 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1310 } else
1311 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1312
1313 /*
5d3cb0f6
ZA		 1314 * Special case: TSC write with a small delta (1 second) of virtual
1315 * cycle time against real time is interpreted as an attempt to
1316 * synchronize the CPU.
1317 *
1318 * For a reliable TSC, we can match TSC offsets, and for an unstable
1319 * TSC, we add elapsed time in this computation. We could let the
1320 * compensation code attempt to catch up if we fall behind, but
1321 * it's better to try to match offsets from the beginning.
1322 */
02626b6a 1323 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1324 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1325 if (!check_tsc_unstable()) {
e26101b1 1326 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1327 pr_debug("kvm: matched tsc offset for %llu\n", data);
1328 } else {
857e4099 1329 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1330 data += delta;
1331 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1332 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1333 }
b48aa97e 1334 matched = true;
0d3da0d2 1335 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1336 } else {
1337 /*
1338 * We split periods of matched TSC writes into generations.
1339 * For each generation, we track the original measured
1340 * nanosecond time, offset, and write, so if TSCs are in
1341 * sync, we can match exact offset, and if not, we can match
4a969980 1342 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1343 *
1344 * These values are tracked in kvm->arch.cur_xxx variables.
1345 */
1346 kvm->arch.cur_tsc_generation++;
1347 kvm->arch.cur_tsc_nsec = ns;
1348 kvm->arch.cur_tsc_write = data;
1349 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1350 matched = false;
0d3da0d2 1351 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1352 kvm->arch.cur_tsc_generation, data);
f38e098f 1353 }
e26101b1
ZA		 1354
1355 /*
1356 * We also track th most recent recorded KHZ, write and time to
1357 * allow the matching interval to be extended at each write.
1358 */
f38e098f
ZA		 1359 kvm->arch.last_tsc_nsec = ns;
1360 kvm->arch.last_tsc_write = data;
5d3cb0f6 1361 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1362
b183aa58 1363 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1364
1365 /* Keep track of which generation this VCPU has synchronized to */
1366 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1367 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1368 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1369
ba904635
WA		 1370 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1371 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1372 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1373 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1374
1375 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1376 if (!matched) {
b48aa97e 1377 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1378 } else if (!already_matched) {
1379 kvm->arch.nr_vcpus_matched_tsc++;
1380 }
b48aa97e
MT		 1381
1382 kvm_track_tsc_matching(vcpu);
1383 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1384}
e26101b1 1385
99e3e30a
ZA		 1386EXPORT_SYMBOL_GPL(kvm_write_tsc);
1387
d828199e
MT		 1388#ifdef CONFIG_X86_64
1389
1390static cycle_t read_tsc(void)
1391{
1392 cycle_t ret;
1393 u64 last;
1394
1395 /*
1396 * Empirically, a fence (of type that depends on the CPU)
1397 * before rdtsc is enough to ensure that rdtsc is ordered
1398 * with respect to loads. The various CPU manuals are unclear
1399 * as to whether rdtsc can be reordered with later loads,
1400 * but no one has ever seen it happen.
1401 */
1402 rdtsc_barrier();
1403 ret = (cycle_t)vget_cycles();
1404
1405 last = pvclock_gtod_data.clock.cycle_last;
1406
1407 if (likely(ret >= last))
1408 return ret;
1409
1410 /*
1411 * GCC likes to generate cmov here, but this branch is extremely
1412 * predictable (it's just a funciton of time and the likely is
1413 * very likely) and there's a data dependence, so force GCC
1414 * to generate a branch instead. I don't barrier() because
1415 * we don't actually need a barrier, and if this function
1416 * ever gets inlined it will generate worse code.
1417 */
1418 asm volatile ("");
1419 return last;
1420}
1421
1422static inline u64 vgettsc(cycle_t *cycle_now)
1423{
1424 long v;
1425 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1426
1427 *cycle_now = read_tsc();
1428
1429 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1430 return v * gtod->clock.mult;
1431}
1432
cbcf2dd3 1433static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1434{
cbcf2dd3 1435 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1436 unsigned long seq;
d828199e 1437 int mode;
cbcf2dd3 1438 u64 ns;
d828199e 1439
d828199e
MT		 1440 do {
1441 seq = read_seqcount_begin(&gtod->seq);
1442 mode = gtod->clock.vclock_mode;
cbcf2dd3 1443 ns = gtod->nsec_base;
d828199e
MT		 1444 ns += vgettsc(cycle_now);
1445 ns >>= gtod->clock.shift;
cbcf2dd3 1446 ns += gtod->boot_ns;
d828199e 1447 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1448 *t = ns;
d828199e
MT		 1449
1450 return mode;
1451}
1452
1453/* returns true if host is using tsc clocksource */
1454static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1455{
d828199e
MT		 1456 /* checked again under seqlock below */
1457 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1458 return false;
1459
cbcf2dd3 1460 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1461}
1462#endif
1463
1464/*
1465 *
b48aa97e
MT		 1466 * Assuming a stable TSC across physical CPUS, and a stable TSC
1467 * across virtual CPUs, the following condition is possible.
1468 * Each numbered line represents an event visible to both
d828199e
MT		 1469 * CPUs at the next numbered event.
1470 *
1471 * "timespecX" represents host monotonic time. "tscX" represents
1472 * RDTSC value.
1473 *
1474 * VCPU0 on CPU0 | VCPU1 on CPU1
1475 *
1476 * 1. read timespec0,tsc0
1477 * 2. | timespec1 = timespec0 + N
1478 * | tsc1 = tsc0 + M
1479 * 3. transition to guest | transition to guest
1480 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1481 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1482 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1483 *
1484 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1485 *
1486 * - ret0 < ret1
1487 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1488 * ...
1489 * - 0 < N - M => M < N
1490 *
1491 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1492 * always the case (the difference between two distinct xtime instances
1493 * might be smaller then the difference between corresponding TSC reads,
1494 * when updating guest vcpus pvclock areas).
1495 *
1496 * To avoid that problem, do not allow visibility of distinct
1497 * system_timestamp/tsc_timestamp values simultaneously: use a master
1498 * copy of host monotonic time values. Update that master copy
1499 * in lockstep.
1500 *
b48aa97e 1501 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1502 *
1503 */
1504
1505static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1506{
1507#ifdef CONFIG_X86_64
1508 struct kvm_arch *ka = &kvm->arch;
1509 int vclock_mode;
b48aa97e
MT		 1510 bool host_tsc_clocksource, vcpus_matched;
1511
1512 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1513 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1514
1515 /*
1516 * If the host uses TSC clock, then passthrough TSC as stable
1517 * to the guest.
1518 */
b48aa97e 1519 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1520 &ka->master_kernel_ns,
1521 &ka->master_cycle_now);
1522
16a96021
MT		 1523 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1524 && !backwards_tsc_observed;
b48aa97e 1525
d828199e
MT		 1526 if (ka->use_master_clock)
1527 atomic_set(&kvm_guest_has_master_clock, 1);
1528
1529 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1530 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1531 vcpus_matched);
d828199e
MT		 1532#endif
1533}
1534
2e762ff7
MT		 1535static void kvm_gen_update_masterclock(struct kvm *kvm)
1536{
1537#ifdef CONFIG_X86_64
1538 int i;
1539 struct kvm_vcpu *vcpu;
1540 struct kvm_arch *ka = &kvm->arch;
1541
1542 spin_lock(&ka->pvclock_gtod_sync_lock);
1543 kvm_make_mclock_inprogress_request(kvm);
1544 /* no guest entries from this point */
1545 pvclock_update_vm_gtod_copy(kvm);
1546
1547 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1548 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1549
1550 /* guest entries allowed */
1551 kvm_for_each_vcpu(i, vcpu, kvm)
1552 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1553
1554 spin_unlock(&ka->pvclock_gtod_sync_lock);
1555#endif
1556}
1557
34c238a1 1558static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1559{
d828199e 1560 unsigned long flags, this_tsc_khz;
18068523 1561 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1562 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1563 s64 kernel_ns;
d828199e 1564 u64 tsc_timestamp, host_tsc;
0b79459b 1565 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1566 u8 pvclock_flags;
d828199e
MT		 1567 bool use_master_clock;
1568
1569 kernel_ns = 0;
1570 host_tsc = 0;
18068523 1571
d828199e
MT		 1572 /*
1573 * If the host uses TSC clock, then passthrough TSC as stable
1574 * to the guest.
1575 */
1576 spin_lock(&ka->pvclock_gtod_sync_lock);
1577 use_master_clock = ka->use_master_clock;
1578 if (use_master_clock) {
1579 host_tsc = ka->master_cycle_now;
1580 kernel_ns = ka->master_kernel_ns;
1581 }
1582 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1583
1584 /* Keep irq disabled to prevent changes to the clock */
1585 local_irq_save(flags);
89cbc767 1586 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1587 if (unlikely(this_tsc_khz == 0)) {
1588 local_irq_restore(flags);
1589 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1590 return 1;
1591 }
d828199e
MT		 1592 if (!use_master_clock) {
1593 host_tsc = native_read_tsc();
1594 kernel_ns = get_kernel_ns();
1595 }
1596
1597 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1598
c285545f
ZA		 1599 /*
1600 * We may have to catch up the TSC to match elapsed wall clock
1601 * time for two reasons, even if kvmclock is used.
1602 * 1) CPU could have been running below the maximum TSC rate
1603 * 2) Broken TSC compensation resets the base at each VCPU
1604 * entry to avoid unknown leaps of TSC even when running
1605 * again on the same CPU. This may cause apparent elapsed
1606 * time to disappear, and the guest to stand still or run
1607 * very slowly.
1608 */
1609 if (vcpu->tsc_catchup) {
1610 u64 tsc = compute_guest_tsc(v, kernel_ns);
1611 if (tsc > tsc_timestamp) {
f1e2b260 1612 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1613 tsc_timestamp = tsc;
1614 }
50d0a0f9
GH		 1615 }
1616
18068523
GOC		 1617 local_irq_restore(flags);
1618
0b79459b 1619 if (!vcpu->pv_time_enabled)
c285545f 1620 return 0;
18068523 1621
e48672fa 1622 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1623 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1624 &vcpu->hv_clock.tsc_shift,
1625 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1626 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1627 }
1628
1629 /* With all the info we got, fill in the values */
1d5f066e 1630 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1631 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1632 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1633
18068523
GOC		 1634 /*
1635 * The interface expects us to write an even number signaling that the
1636 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1637 * state, we just increase by 2 at the end.
18068523 1638 */
50d0a0f9 1639 vcpu->hv_clock.version += 2;
18068523 1640
0b79459b
AH		 1641 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1642 &guest_hv_clock, sizeof(guest_hv_clock))))
1643 return 0;
78c0337a
MT		 1644
1645 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1646 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1647
1648 if (vcpu->pvclock_set_guest_stopped_request) {
1649 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1650 vcpu->pvclock_set_guest_stopped_request = false;
1651 }
1652
d828199e
MT		 1653 /* If the host uses TSC clocksource, then it is stable */
1654 if (use_master_clock)
1655 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1656
78c0337a
MT		 1657 vcpu->hv_clock.flags = pvclock_flags;
1658
0b79459b
AH		 1659 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1660 &vcpu->hv_clock,
1661 sizeof(vcpu->hv_clock));
8cfdc000 1662 return 0;
c8076604
GH		 1663}
1664
0061d53d
MT		 1665/*
1666 * kvmclock updates which are isolated to a given vcpu, such as
1667 * vcpu->cpu migration, should not allow system_timestamp from
1668 * the rest of the vcpus to remain static. Otherwise ntp frequency
1669 * correction applies to one vcpu's system_timestamp but not
1670 * the others.
1671 *
1672 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1673 * We need to rate-limit these requests though, as they can
1674 * considerably slow guests that have a large number of vcpus.
1675 * The time for a remote vcpu to update its kvmclock is bound
1676 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1677 */
1678
7e44e449
AJ		 1679#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1680
1681static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1682{
1683 int i;
7e44e449
AJ		 1684 struct delayed_work *dwork = to_delayed_work(work);
1685 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1686 kvmclock_update_work);
1687 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1688 struct kvm_vcpu *vcpu;
1689
1690 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1691 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1692 kvm_vcpu_kick(vcpu);
1693 }
1694}
1695
7e44e449
AJ		 1696static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1697{
1698 struct kvm *kvm = v->kvm;
1699
105b21bb 1700 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1701 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1702 KVMCLOCK_UPDATE_DELAY);
1703}
1704
332967a3
AJ		 1705#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1706
1707static void kvmclock_sync_fn(struct work_struct *work)
1708{
1709 struct delayed_work *dwork = to_delayed_work(work);
1710 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1711 kvmclock_sync_work);
1712 struct kvm *kvm = container_of(ka, struct kvm, arch);
1713
1714 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1715 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1716 KVMCLOCK_SYNC_PERIOD);
1717}
1718
9ba075a6
AK		 1719static bool msr_mtrr_valid(unsigned msr)
1720{
1721 switch (msr) {
1722 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1723 case MSR_MTRRfix64K_00000:
1724 case MSR_MTRRfix16K_80000:
1725 case MSR_MTRRfix16K_A0000:
1726 case MSR_MTRRfix4K_C0000:
1727 case MSR_MTRRfix4K_C8000:
1728 case MSR_MTRRfix4K_D0000:
1729 case MSR_MTRRfix4K_D8000:
1730 case MSR_MTRRfix4K_E0000:
1731 case MSR_MTRRfix4K_E8000:
1732 case MSR_MTRRfix4K_F0000:
1733 case MSR_MTRRfix4K_F8000:
1734 case MSR_MTRRdefType:
1735 case MSR_IA32_CR_PAT:
1736 return true;
1737 case 0x2f8:
1738 return true;
1739 }
1740 return false;
1741}
1742
d6289b93
MT		 1743static bool valid_pat_type(unsigned t)
1744{
1745 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1746}
1747
1748static bool valid_mtrr_type(unsigned t)
1749{
1750 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1751}
1752
4566654b 1753bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1754{
1755 int i;
fd275235 1756 u64 mask;
d6289b93
MT		 1757
1758 if (!msr_mtrr_valid(msr))
1759 return false;
1760
1761 if (msr == MSR_IA32_CR_PAT) {
1762 for (i = 0; i < 8; i++)
1763 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1764 return false;
1765 return true;
1766 } else if (msr == MSR_MTRRdefType) {
1767 if (data & ~0xcff)
1768 return false;
1769 return valid_mtrr_type(data & 0xff);
1770 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1771 for (i = 0; i < 8 ; i++)
1772 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1773 return false;
1774 return true;
1775 }
1776
1777 /* variable MTRRs */
adfb5d27
WL		 1778 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1779
fd275235 1780 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1781 if ((msr & 1) == 0) {
adfb5d27 1782 /* MTRR base */
d7a2a246
WL		 1783 if (!valid_mtrr_type(data & 0xff))
1784 return false;
1785 mask |= 0xf00;
1786 } else
1787 /* MTRR mask */
1788 mask |= 0x7ff;
1789 if (data & mask) {
1790 kvm_inject_gp(vcpu, 0);
1791 return false;
1792 }
1793
adfb5d27 1794 return true;
d6289b93 1795}
4566654b 1796EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1797
9ba075a6
AK		 1798static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1799{
0bed3b56
SY		 1800 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1801
4566654b 1802 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1803 return 1;
1804
0bed3b56
SY		 1805 if (msr == MSR_MTRRdefType) {
1806 vcpu->arch.mtrr_state.def_type = data;
1807 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1808 } else if (msr == MSR_MTRRfix64K_00000)
1809 p[0] = data;
1810 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1811 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1812 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1813 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1814 else if (msr == MSR_IA32_CR_PAT)
1815 vcpu->arch.pat = data;
1816 else { /* Variable MTRRs */
1817 int idx, is_mtrr_mask;
1818 u64 *pt;
1819
1820 idx = (msr - 0x200) / 2;
1821 is_mtrr_mask = msr - 0x200 - 2 * idx;
1822 if (!is_mtrr_mask)
1823 pt =
1824 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1825 else
1826 pt =
1827 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1828 *pt = data;
1829 }
1830
1831 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1832 return 0;
1833}
15c4a640 1834
890ca9ae 1835static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1836{
890ca9ae
HY		 1837 u64 mcg_cap = vcpu->arch.mcg_cap;
1838 unsigned bank_num = mcg_cap & 0xff;
1839
15c4a640 1840 switch (msr) {
15c4a640 1841 case MSR_IA32_MCG_STATUS:
890ca9ae 1842 vcpu->arch.mcg_status = data;
15c4a640 1843 break;
c7ac679c 1844 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1845 if (!(mcg_cap & MCG_CTL_P))
1846 return 1;
1847 if (data != 0 && data != ~(u64)0)
1848 return -1;
1849 vcpu->arch.mcg_ctl = data;
1850 break;
1851 default:
1852 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1853 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1854 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1855 /* only 0 or all 1s can be written to IA32_MCi_CTL
1856 * some Linux kernels though clear bit 10 in bank 4 to
1857 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1858 * this to avoid an uncatched #GP in the guest
1859 */
890ca9ae 1860 if ((offset & 0x3) == 0 &&
114be429 1861 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1862 return -1;
1863 vcpu->arch.mce_banks[offset] = data;
1864 break;
1865 }
1866 return 1;
1867 }
1868 return 0;
1869}
1870
ffde22ac
ES		 1871static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1872{
1873 struct kvm *kvm = vcpu->kvm;
1874 int lm = is_long_mode(vcpu);
1875 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1876 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1877 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1878 : kvm->arch.xen_hvm_config.blob_size_32;
1879 u32 page_num = data & ~PAGE_MASK;
1880 u64 page_addr = data & PAGE_MASK;
1881 u8 *page;
1882 int r;
1883
1884 r = -E2BIG;
1885 if (page_num >= blob_size)
1886 goto out;
1887 r = -ENOMEM;
ff5c2c03
SL		 1888 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1889 if (IS_ERR(page)) {
1890 r = PTR_ERR(page);
ffde22ac 1891 goto out;
ff5c2c03 1892 }
ffde22ac
ES		 1893 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1894 goto out_free;
1895 r = 0;
1896out_free:
1897 kfree(page);
1898out:
1899 return r;
1900}
1901
55cd8e5a
GN		 1902static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1903{
1904 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1905}
1906
1907static bool kvm_hv_msr_partition_wide(u32 msr)
1908{
1909 bool r = false;
1910 switch (msr) {
1911 case HV_X64_MSR_GUEST_OS_ID:
1912 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1913 case HV_X64_MSR_REFERENCE_TSC:
1914 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1915 r = true;
1916 break;
1917 }
1918
1919 return r;
1920}
1921
1922static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1923{
1924 struct kvm *kvm = vcpu->kvm;
1925
1926 switch (msr) {
1927 case HV_X64_MSR_GUEST_OS_ID:
1928 kvm->arch.hv_guest_os_id = data;
1929 /* setting guest os id to zero disables hypercall page */
1930 if (!kvm->arch.hv_guest_os_id)
1931 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1932 break;
1933 case HV_X64_MSR_HYPERCALL: {
1934 u64 gfn;
1935 unsigned long addr;
1936 u8 instructions[4];
1937
1938 /* if guest os id is not set hypercall should remain disabled */
1939 if (!kvm->arch.hv_guest_os_id)
1940 break;
1941 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1942 kvm->arch.hv_hypercall = data;
1943 break;
1944 }
1945 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1946 addr = gfn_to_hva(kvm, gfn);
1947 if (kvm_is_error_hva(addr))
1948 return 1;
1949 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1950 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1951 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1952 return 1;
1953 kvm->arch.hv_hypercall = data;
b94b64c9 1954 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1955 break;
1956 }
e984097b
VR		 1957 case HV_X64_MSR_REFERENCE_TSC: {
1958 u64 gfn;
1959 HV_REFERENCE_TSC_PAGE tsc_ref;
1960 memset(&tsc_ref, 0, sizeof(tsc_ref));
1961 kvm->arch.hv_tsc_page = data;
1962 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1963 break;
1964 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1965 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1966 &tsc_ref, sizeof(tsc_ref)))
1967 return 1;
1968 mark_page_dirty(kvm, gfn);
1969 break;
1970 }
55cd8e5a 1971 default:
a737f256
CD		 1972 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1973 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1974 return 1;
1975 }
1976 return 0;
1977}
1978
1979static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1980{
10388a07
GN		 1981 switch (msr) {
1982 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1983 u64 gfn;
10388a07 1984 unsigned long addr;
55cd8e5a 1985
10388a07
GN		 1986 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1987 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1988 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1989 return 1;
10388a07
GN		 1990 break;
1991 }
b3af1e88
VR		 1992 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1993 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1994 if (kvm_is_error_hva(addr))
1995 return 1;
8b0cedff 1996 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1997 return 1;
1998 vcpu->arch.hv_vapic = data;
b3af1e88 1999 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2000 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2001 return 1;
10388a07
GN		 2002 break;
2003 }
2004 case HV_X64_MSR_EOI:
2005 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2006 case HV_X64_MSR_ICR:
2007 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2008 case HV_X64_MSR_TPR:
2009 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2010 default:
a737f256
CD		 2011 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2012 "data 0x%llx\n", msr, data);
10388a07
GN		 2013 return 1;
2014 }
2015
2016 return 0;
55cd8e5a
GN		 2017}
2018
344d9588
GN		 2019static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2020{
2021 gpa_t gpa = data & ~0x3f;
2022
4a969980 2023 /* Bits 2:5 are reserved, Should be zero */
6adba527 2024 if (data & 0x3c)
344d9588
GN		 2025 return 1;
2026
2027 vcpu->arch.apf.msr_val = data;
2028
2029 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2030 kvm_clear_async_pf_completion_queue(vcpu);
2031 kvm_async_pf_hash_reset(vcpu);
2032 return 0;
2033 }
2034
8f964525
AH		 2035 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2036 sizeof(u32)))
344d9588
GN		 2037 return 1;
2038
6adba527 2039 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2040 kvm_async_pf_wakeup_all(vcpu);
2041 return 0;
2042}
2043
12f9a48f
GC		 2044static void kvmclock_reset(struct kvm_vcpu *vcpu)
2045{
0b79459b 2046 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2047}
2048
c9aaa895
GC		 2049static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2050{
2051 u64 delta;
2052
2053 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2054 return;
2055
2056 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2057 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2058 vcpu->arch.st.accum_steal = delta;
2059}
2060
2061static void record_steal_time(struct kvm_vcpu *vcpu)
2062{
2063 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2064 return;
2065
2066 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2067 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2068 return;
2069
2070 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2071 vcpu->arch.st.steal.version += 2;
2072 vcpu->arch.st.accum_steal = 0;
2073
2074 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2075 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2076}
2077
8fe8ab46 2078int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2079{
5753785f 2080 bool pr = false;
8fe8ab46
WA		 2081 u32 msr = msr_info->index;
2082 u64 data = msr_info->data;
5753785f 2083
15c4a640 2084 switch (msr) {
2e32b719
BP		 2085 case MSR_AMD64_NB_CFG:
2086 case MSR_IA32_UCODE_REV:
2087 case MSR_IA32_UCODE_WRITE:
2088 case MSR_VM_HSAVE_PA:
2089 case MSR_AMD64_PATCH_LOADER:
2090 case MSR_AMD64_BU_CFG2:
2091 break;
2092
15c4a640 2093 case MSR_EFER:
b69e8cae 2094 return set_efer(vcpu, data);
8f1589d9
AP		 2095 case MSR_K7_HWCR:
2096 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2097 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2098 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2099 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2100 if (data != 0) {
a737f256
CD		 2101 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2102 data);
8f1589d9
AP		 2103 return 1;
2104 }
15c4a640 2105 break;
f7c6d140
AP		 2106 case MSR_FAM10H_MMIO_CONF_BASE:
2107 if (data != 0) {
a737f256
CD		 2108 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2109 "0x%llx\n", data);
f7c6d140
AP		 2110 return 1;
2111 }
15c4a640 2112 break;
b5e2fec0
AG		 2113 case MSR_IA32_DEBUGCTLMSR:
2114 if (!data) {
2115 /* We support the non-activated case already */
2116 break;
2117 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2118 /* Values other than LBR and BTF are vendor-specific,
2119 thus reserved and should throw a #GP */
2120 return 1;
2121 }
a737f256
CD		 2122 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2123 __func__, data);
b5e2fec0 2124 break;
9ba075a6
AK		 2125 case 0x200 ... 0x2ff:
2126 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2127 case MSR_IA32_APICBASE:
58cb628d 2128 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2129 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2130 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2131 case MSR_IA32_TSCDEADLINE:
2132 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2133 break;
ba904635
WA		 2134 case MSR_IA32_TSC_ADJUST:
2135 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2136 if (!msr_info->host_initiated) {
2137 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2138 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2139 }
2140 vcpu->arch.ia32_tsc_adjust_msr = data;
2141 }
2142 break;
15c4a640 2143 case MSR_IA32_MISC_ENABLE:
ad312c7c 2144 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2145 break;
11c6bffa 2146 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2147 case MSR_KVM_WALL_CLOCK:
2148 vcpu->kvm->arch.wall_clock = data;
2149 kvm_write_wall_clock(vcpu->kvm, data);
2150 break;
11c6bffa 2151 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2152 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2153 u64 gpa_offset;
12f9a48f 2154 kvmclock_reset(vcpu);
18068523
GOC		 2155
2156 vcpu->arch.time = data;
0061d53d 2157 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2158
2159 /* we verify if the enable bit is set... */
2160 if (!(data & 1))
2161 break;
2162
0b79459b 2163 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2164
0b79459b 2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2166 &vcpu->arch.pv_time, data & ~1ULL,
2167 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2168 vcpu->arch.pv_time_enabled = false;
2169 else
2170 vcpu->arch.pv_time_enabled = true;
32cad84f 2171
18068523
GOC		 2172 break;
2173 }
344d9588
GN		 2174 case MSR_KVM_ASYNC_PF_EN:
2175 if (kvm_pv_enable_async_pf(vcpu, data))
2176 return 1;
2177 break;
c9aaa895
GC		 2178 case MSR_KVM_STEAL_TIME:
2179
2180 if (unlikely(!sched_info_on()))
2181 return 1;
2182
2183 if (data & KVM_STEAL_RESERVED_MASK)
2184 return 1;
2185
2186 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2187 data & KVM_STEAL_VALID_BITS,
2188 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2189 return 1;
2190
2191 vcpu->arch.st.msr_val = data;
2192
2193 if (!(data & KVM_MSR_ENABLED))
2194 break;
2195
2196 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2197
2198 preempt_disable();
2199 accumulate_steal_time(vcpu);
2200 preempt_enable();
2201
2202 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2203
2204 break;
ae7a2a3f
MT		 2205 case MSR_KVM_PV_EOI_EN:
2206 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2207 return 1;
2208 break;
c9aaa895 2209
890ca9ae
HY		 2210 case MSR_IA32_MCG_CTL:
2211 case MSR_IA32_MCG_STATUS:
81760dcc 2212 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2213 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2214
2215 /* Performance counters are not protected by a CPUID bit,
2216 * so we should check all of them in the generic path for the sake of
2217 * cross vendor migration.
2218 * Writing a zero into the event select MSRs disables them,
2219 * which we perfectly emulate ;-). Any other value should be at least
2220 * reported, some guests depend on them.
2221 */
71db6023
AP		 2222 case MSR_K7_EVNTSEL0:
2223 case MSR_K7_EVNTSEL1:
2224 case MSR_K7_EVNTSEL2:
2225 case MSR_K7_EVNTSEL3:
2226 if (data != 0)
a737f256
CD		 2227 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2228 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2229 break;
2230 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2231 * so we ignore writes to make it happy.
2232 */
71db6023
AP		 2233 case MSR_K7_PERFCTR0:
2234 case MSR_K7_PERFCTR1:
2235 case MSR_K7_PERFCTR2:
2236 case MSR_K7_PERFCTR3:
a737f256
CD		 2237 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2238 "0x%x data 0x%llx\n", msr, data);
71db6023 2239 break;
5753785f
GN		 2240 case MSR_P6_PERFCTR0:
2241 case MSR_P6_PERFCTR1:
2242 pr = true;
2243 case MSR_P6_EVNTSEL0:
2244 case MSR_P6_EVNTSEL1:
2245 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2246 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2247
2248 if (pr || data != 0)
a737f256
CD		 2249 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2250 "0x%x data 0x%llx\n", msr, data);
5753785f 2251 break;
84e0cefa
JS		 2252 case MSR_K7_CLK_CTL:
2253 /*
2254 * Ignore all writes to this no longer documented MSR.
2255 * Writes are only relevant for old K7 processors,
2256 * all pre-dating SVM, but a recommended workaround from
4a969980 2257 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2258 * affected processor models on the command line, hence
2259 * the need to ignore the workaround.
2260 */
2261 break;
55cd8e5a
GN		 2262 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2263 if (kvm_hv_msr_partition_wide(msr)) {
2264 int r;
2265 mutex_lock(&vcpu->kvm->lock);
2266 r = set_msr_hyperv_pw(vcpu, msr, data);
2267 mutex_unlock(&vcpu->kvm->lock);
2268 return r;
2269 } else
2270 return set_msr_hyperv(vcpu, msr, data);
2271 break;
91c9c3ed 2272 case MSR_IA32_BBL_CR_CTL3:
2273 /* Drop writes to this legacy MSR -- see rdmsr
2274 * counterpart for further detail.
2275 */
a737f256 2276 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2277 break;
2b036c6b
BO		 2278 case MSR_AMD64_OSVW_ID_LENGTH:
2279 if (!guest_cpuid_has_osvw(vcpu))
2280 return 1;
2281 vcpu->arch.osvw.length = data;
2282 break;
2283 case MSR_AMD64_OSVW_STATUS:
2284 if (!guest_cpuid_has_osvw(vcpu))
2285 return 1;
2286 vcpu->arch.osvw.status = data;
2287 break;
15c4a640 2288 default:
ffde22ac
ES		 2289 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2290 return xen_hvm_config(vcpu, data);
f5132b01 2291 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2292 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2293 if (!ignore_msrs) {
a737f256
CD		 2294 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2295 msr, data);
ed85c068
AP		 2296 return 1;
2297 } else {
a737f256
CD		 2298 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2299 msr, data);
ed85c068
AP		 2300 break;
2301 }
15c4a640
CO		 2302 }
2303 return 0;
2304}
2305EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2306
2307
2308/*
2309 * Reads an msr value (of 'msr_index') into 'pdata'.
2310 * Returns 0 on success, non-0 otherwise.
2311 * Assumes vcpu_load() was already called.
2312 */
2313int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2314{
2315 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2316}
2317
9ba075a6
AK		 2318static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2319{
0bed3b56
SY		 2320 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2321
9ba075a6
AK		 2322 if (!msr_mtrr_valid(msr))
2323 return 1;
2324
0bed3b56
SY		 2325 if (msr == MSR_MTRRdefType)
2326 *pdata = vcpu->arch.mtrr_state.def_type +
2327 (vcpu->arch.mtrr_state.enabled << 10);
2328 else if (msr == MSR_MTRRfix64K_00000)
2329 *pdata = p[0];
2330 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2331 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2332 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2333 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2334 else if (msr == MSR_IA32_CR_PAT)
2335 *pdata = vcpu->arch.pat;
2336 else { /* Variable MTRRs */
2337 int idx, is_mtrr_mask;
2338 u64 *pt;
2339
2340 idx = (msr - 0x200) / 2;
2341 is_mtrr_mask = msr - 0x200 - 2 * idx;
2342 if (!is_mtrr_mask)
2343 pt =
2344 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2345 else
2346 pt =
2347 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2348 *pdata = *pt;
2349 }
2350
9ba075a6
AK		 2351 return 0;
2352}
2353
890ca9ae 2354static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2355{
2356 u64 data;
890ca9ae
HY		 2357 u64 mcg_cap = vcpu->arch.mcg_cap;
2358 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2359
2360 switch (msr) {
15c4a640
CO		 2361 case MSR_IA32_P5_MC_ADDR:
2362 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2363 data = 0;
2364 break;
15c4a640 2365 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2366 data = vcpu->arch.mcg_cap;
2367 break;
c7ac679c 2368 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2369 if (!(mcg_cap & MCG_CTL_P))
2370 return 1;
2371 data = vcpu->arch.mcg_ctl;
2372 break;
2373 case MSR_IA32_MCG_STATUS:
2374 data = vcpu->arch.mcg_status;
2375 break;
2376 default:
2377 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2378 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2379 u32 offset = msr - MSR_IA32_MC0_CTL;
2380 data = vcpu->arch.mce_banks[offset];
2381 break;
2382 }
2383 return 1;
2384 }
2385 *pdata = data;
2386 return 0;
2387}
2388
55cd8e5a
GN		 2389static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2390{
2391 u64 data = 0;
2392 struct kvm *kvm = vcpu->kvm;
2393
2394 switch (msr) {
2395 case HV_X64_MSR_GUEST_OS_ID:
2396 data = kvm->arch.hv_guest_os_id;
2397 break;
2398 case HV_X64_MSR_HYPERCALL:
2399 data = kvm->arch.hv_hypercall;
2400 break;
e984097b
VR		 2401 case HV_X64_MSR_TIME_REF_COUNT: {
2402 data =
2403 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2404 break;
2405 }
2406 case HV_X64_MSR_REFERENCE_TSC:
2407 data = kvm->arch.hv_tsc_page;
2408 break;
55cd8e5a 2409 default:
a737f256 2410 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2411 return 1;
2412 }
2413
2414 *pdata = data;
2415 return 0;
2416}
2417
2418static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2419{
2420 u64 data = 0;
2421
2422 switch (msr) {
2423 case HV_X64_MSR_VP_INDEX: {
2424 int r;
2425 struct kvm_vcpu *v;
684851a1
TY		 2426 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2427 if (v == vcpu) {
55cd8e5a 2428 data = r;
684851a1
TY		 2429 break;
2430 }
2431 }
55cd8e5a
GN		 2432 break;
2433 }
10388a07
GN		 2434 case HV_X64_MSR_EOI:
2435 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2436 case HV_X64_MSR_ICR:
2437 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2438 case HV_X64_MSR_TPR:
2439 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2440 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2441 data = vcpu->arch.hv_vapic;
2442 break;
55cd8e5a 2443 default:
a737f256 2444 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2445 return 1;
2446 }
2447 *pdata = data;
2448 return 0;
2449}
2450
890ca9ae
HY		 2451int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2452{
2453 u64 data;
2454
2455 switch (msr) {
890ca9ae 2456 case MSR_IA32_PLATFORM_ID:
15c4a640 2457 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2458 case MSR_IA32_DEBUGCTLMSR:
2459 case MSR_IA32_LASTBRANCHFROMIP:
2460 case MSR_IA32_LASTBRANCHTOIP:
2461 case MSR_IA32_LASTINTFROMIP:
2462 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2463 case MSR_K8_SYSCFG:
2464 case MSR_K7_HWCR:
61a6bd67 2465 case MSR_VM_HSAVE_PA:
9e699624 2466 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2467 case MSR_K7_EVNTSEL1:
2468 case MSR_K7_EVNTSEL2:
2469 case MSR_K7_EVNTSEL3:
1f3ee616 2470 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2471 case MSR_K7_PERFCTR1:
2472 case MSR_K7_PERFCTR2:
2473 case MSR_K7_PERFCTR3:
1fdbd48c 2474 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2475 case MSR_AMD64_NB_CFG:
f7c6d140 2476 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2477 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2478 data = 0;
2479 break;
5753785f
GN		 2480 case MSR_P6_PERFCTR0:
2481 case MSR_P6_PERFCTR1:
2482 case MSR_P6_EVNTSEL0:
2483 case MSR_P6_EVNTSEL1:
2484 if (kvm_pmu_msr(vcpu, msr))
2485 return kvm_pmu_get_msr(vcpu, msr, pdata);
2486 data = 0;
2487 break;
742bc670
MT		 2488 case MSR_IA32_UCODE_REV:
2489 data = 0x100000000ULL;
2490 break;
9ba075a6
AK		 2491 case MSR_MTRRcap:
2492 data = 0x500 | KVM_NR_VAR_MTRR;
2493 break;
2494 case 0x200 ... 0x2ff:
2495 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2496 case 0xcd: /* fsb frequency */
2497 data = 3;
2498 break;
7b914098
JS		 2499 /*
2500 * MSR_EBC_FREQUENCY_ID
2501 * Conservative value valid for even the basic CPU models.
2502 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2503 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2504 * and 266MHz for model 3, or 4. Set Core Clock
2505 * Frequency to System Bus Frequency Ratio to 1 (bits
2506 * 31:24) even though these are only valid for CPU
2507 * models > 2, however guests may end up dividing or
2508 * multiplying by zero otherwise.
2509 */
2510 case MSR_EBC_FREQUENCY_ID:
2511 data = 1 << 24;
2512 break;
15c4a640
CO		 2513 case MSR_IA32_APICBASE:
2514 data = kvm_get_apic_base(vcpu);
2515 break;
0105d1a5
GN		 2516 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2517 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2518 break;
a3e06bbe
LJ		 2519 case MSR_IA32_TSCDEADLINE:
2520 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2521 break;
ba904635
WA		 2522 case MSR_IA32_TSC_ADJUST:
2523 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2524 break;
15c4a640 2525 case MSR_IA32_MISC_ENABLE:
ad312c7c 2526 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2527 break;
847f0ad8
AG		 2528 case MSR_IA32_PERF_STATUS:
2529 /* TSC increment by tick */
2530 data = 1000ULL;
2531 /* CPU multiplier */
2532 data |= (((uint64_t)4ULL) << 40);
2533 break;
15c4a640 2534 case MSR_EFER:
f6801dff 2535 data = vcpu->arch.efer;
15c4a640 2536 break;
18068523 2537 case MSR_KVM_WALL_CLOCK:
11c6bffa 2538 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2539 data = vcpu->kvm->arch.wall_clock;
2540 break;
2541 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2542 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2543 data = vcpu->arch.time;
2544 break;
344d9588
GN		 2545 case MSR_KVM_ASYNC_PF_EN:
2546 data = vcpu->arch.apf.msr_val;
2547 break;
c9aaa895
GC		 2548 case MSR_KVM_STEAL_TIME:
2549 data = vcpu->arch.st.msr_val;
2550 break;
1d92128f
MT		 2551 case MSR_KVM_PV_EOI_EN:
2552 data = vcpu->arch.pv_eoi.msr_val;
2553 break;
890ca9ae
HY		 2554 case MSR_IA32_P5_MC_ADDR:
2555 case MSR_IA32_P5_MC_TYPE:
2556 case MSR_IA32_MCG_CAP:
2557 case MSR_IA32_MCG_CTL:
2558 case MSR_IA32_MCG_STATUS:
81760dcc 2559 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2560 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2561 case MSR_K7_CLK_CTL:
2562 /*
2563 * Provide expected ramp-up count for K7. All other
2564 * are set to zero, indicating minimum divisors for
2565 * every field.
2566 *
2567 * This prevents guest kernels on AMD host with CPU
2568 * type 6, model 8 and higher from exploding due to
2569 * the rdmsr failing.
2570 */
2571 data = 0x20000000;
2572 break;
55cd8e5a
GN		 2573 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2574 if (kvm_hv_msr_partition_wide(msr)) {
2575 int r;
2576 mutex_lock(&vcpu->kvm->lock);
2577 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2578 mutex_unlock(&vcpu->kvm->lock);
2579 return r;
2580 } else
2581 return get_msr_hyperv(vcpu, msr, pdata);
2582 break;
91c9c3ed 2583 case MSR_IA32_BBL_CR_CTL3:
2584 /* This legacy MSR exists but isn't fully documented in current
2585 * silicon. It is however accessed by winxp in very narrow
2586 * scenarios where it sets bit #19, itself documented as
2587 * a "reserved" bit. Best effort attempt to source coherent
2588 * read data here should the balance of the register be
2589 * interpreted by the guest:
2590 *
2591 * L2 cache control register 3: 64GB range, 256KB size,
2592 * enabled, latency 0x1, configured
2593 */
2594 data = 0xbe702111;
2595 break;
2b036c6b
BO		 2596 case MSR_AMD64_OSVW_ID_LENGTH:
2597 if (!guest_cpuid_has_osvw(vcpu))
2598 return 1;
2599 data = vcpu->arch.osvw.length;
2600 break;
2601 case MSR_AMD64_OSVW_STATUS:
2602 if (!guest_cpuid_has_osvw(vcpu))
2603 return 1;
2604 data = vcpu->arch.osvw.status;
2605 break;
15c4a640 2606 default:
f5132b01
GN		 2607 if (kvm_pmu_msr(vcpu, msr))
2608 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2609 if (!ignore_msrs) {
a737f256 2610 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2611 return 1;
2612 } else {
a737f256 2613 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2614 data = 0;
2615 }
2616 break;
15c4a640
CO		 2617 }
2618 *pdata = data;
2619 return 0;
2620}
2621EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2622
313a3dc7
CO		 2623/*
2624 * Read or write a bunch of msrs. All parameters are kernel addresses.
2625 *
2626 * @return number of msrs set successfully.
2627 */
2628static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2629 struct kvm_msr_entry *entries,
2630 int (*do_msr)(struct kvm_vcpu *vcpu,
2631 unsigned index, u64 *data))
2632{
f656ce01 2633 int i, idx;
313a3dc7 2634
f656ce01 2635 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2636 for (i = 0; i < msrs->nmsrs; ++i)
2637 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2638 break;
f656ce01 2639 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2640
313a3dc7
CO		 2641 return i;
2642}
2643
2644/*
2645 * Read or write a bunch of msrs. Parameters are user addresses.
2646 *
2647 * @return number of msrs set successfully.
2648 */
2649static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2650 int (*do_msr)(struct kvm_vcpu *vcpu,
2651 unsigned index, u64 *data),
2652 int writeback)
2653{
2654 struct kvm_msrs msrs;
2655 struct kvm_msr_entry *entries;
2656 int r, n;
2657 unsigned size;
2658
2659 r = -EFAULT;
2660 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2661 goto out;
2662
2663 r = -E2BIG;
2664 if (msrs.nmsrs >= MAX_IO_MSRS)
2665 goto out;
2666
313a3dc7 2667 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2668 entries = memdup_user(user_msrs->entries, size);
2669 if (IS_ERR(entries)) {
2670 r = PTR_ERR(entries);
313a3dc7 2671 goto out;
ff5c2c03 2672 }
313a3dc7
CO		 2673
2674 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2675 if (r < 0)
2676 goto out_free;
2677
2678 r = -EFAULT;
2679 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2680 goto out_free;
2681
2682 r = n;
2683
2684out_free:
7a73c028 2685 kfree(entries);
313a3dc7
CO		 2686out:
2687 return r;
2688}
2689
784aa3d7 2690int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2691{
2692 int r;
2693
2694 switch (ext) {
2695 case KVM_CAP_IRQCHIP:
2696 case KVM_CAP_HLT:
2697 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2698 case KVM_CAP_SET_TSS_ADDR:
07716717 2699 case KVM_CAP_EXT_CPUID:
9c15bb1d 2700 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2701 case KVM_CAP_CLOCKSOURCE:
7837699f 2702 case KVM_CAP_PIT:
a28e4f5a 2703 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2704 case KVM_CAP_MP_STATE:
ed848624 2705 case KVM_CAP_SYNC_MMU:
a355c85c 2706 case KVM_CAP_USER_NMI:
52d939a0 2707 case KVM_CAP_REINJECT_CONTROL:
4925663a 2708 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2709 case KVM_CAP_IRQFD:
d34e6b17 2710 case KVM_CAP_IOEVENTFD:
f848a5a8 2711 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2712 case KVM_CAP_PIT2:
e9f42757 2713 case KVM_CAP_PIT_STATE2:
b927a3ce 2714 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2715 case KVM_CAP_XEN_HVM:
afbcf7ab 2716 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2717 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2718 case KVM_CAP_HYPERV:
10388a07 2719 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2720 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2721 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2722 case KVM_CAP_DEBUGREGS:
d2be1651 2723 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2724 case KVM_CAP_XSAVE:
344d9588 2725 case KVM_CAP_ASYNC_PF:
92a1f12d 2726 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2727 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2728 case KVM_CAP_READONLY_MEM:
5f66b620 2729 case KVM_CAP_HYPERV_TIME:
100943c5 2730 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2731#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2732 case KVM_CAP_ASSIGN_DEV_IRQ:
2733 case KVM_CAP_PCI_2_3:
2734#endif
018d00d2
ZX		 2735 r = 1;
2736 break;
542472b5
LV		 2737 case KVM_CAP_COALESCED_MMIO:
2738 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2739 break;
774ead3a
AK		 2740 case KVM_CAP_VAPIC:
2741 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2742 break;
f725230a 2743 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2744 r = KVM_SOFT_MAX_VCPUS;
2745 break;
2746 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2747 r = KVM_MAX_VCPUS;
2748 break;
a988b910 2749 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2750 r = KVM_USER_MEM_SLOTS;
a988b910 2751 break;
a68a6a72
MT		 2752 case KVM_CAP_PV_MMU: /* obsolete */
2753 r = 0;
2f333bcb 2754 break;
4cee4b72 2755#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2756 case KVM_CAP_IOMMU:
a1b60c1c 2757 r = iommu_present(&pci_bus_type);
62c476c7 2758 break;
4cee4b72 2759#endif
890ca9ae
HY		 2760 case KVM_CAP_MCE:
2761 r = KVM_MAX_MCE_BANKS;
2762 break;
2d5b5a66
SY		 2763 case KVM_CAP_XCRS:
2764 r = cpu_has_xsave;
2765 break;
92a1f12d
JR		 2766 case KVM_CAP_TSC_CONTROL:
2767 r = kvm_has_tsc_control;
2768 break;
4d25a066
JK		 2769 case KVM_CAP_TSC_DEADLINE_TIMER:
2770 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2771 break;
018d00d2
ZX		 2772 default:
2773 r = 0;
2774 break;
2775 }
2776 return r;
2777
2778}
2779
043405e1
CO		 2780long kvm_arch_dev_ioctl(struct file *filp,
2781 unsigned int ioctl, unsigned long arg)
2782{
2783 void __user *argp = (void __user *)arg;
2784 long r;
2785
2786 switch (ioctl) {
2787 case KVM_GET_MSR_INDEX_LIST: {
2788 struct kvm_msr_list __user *user_msr_list = argp;
2789 struct kvm_msr_list msr_list;
2790 unsigned n;
2791
2792 r = -EFAULT;
2793 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2794 goto out;
2795 n = msr_list.nmsrs;
2796 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2797 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2798 goto out;
2799 r = -E2BIG;
e125e7b6 2800 if (n < msr_list.nmsrs)
043405e1
CO		 2801 goto out;
2802 r = -EFAULT;
2803 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2804 num_msrs_to_save * sizeof(u32)))
2805 goto out;
e125e7b6 2806 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2807 &emulated_msrs,
2808 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2809 goto out;
2810 r = 0;
2811 break;
2812 }
9c15bb1d
BP		 2813 case KVM_GET_SUPPORTED_CPUID:
2814 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2815 struct kvm_cpuid2 __user *cpuid_arg = argp;
2816 struct kvm_cpuid2 cpuid;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2820 goto out;
9c15bb1d
BP		 2821
2822 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2823 ioctl);
674eea0f
AK		 2824 if (r)
2825 goto out;
2826
2827 r = -EFAULT;
2828 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2829 goto out;
2830 r = 0;
2831 break;
2832 }
890ca9ae
HY		 2833 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2834 u64 mce_cap;
2835
2836 mce_cap = KVM_MCE_CAP_SUPPORTED;
2837 r = -EFAULT;
2838 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2839 goto out;
2840 r = 0;
2841 break;
2842 }
043405e1
CO		 2843 default:
2844 r = -EINVAL;
2845 }
2846out:
2847 return r;
2848}
2849
f5f48ee1
SY		 2850static void wbinvd_ipi(void *garbage)
2851{
2852 wbinvd();
2853}
2854
2855static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2856{
e0f0bbc5 2857 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2858}
2859
313a3dc7
CO		 2860void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2861{
f5f48ee1
SY		 2862 /* Address WBINVD may be executed by guest */
2863 if (need_emulate_wbinvd(vcpu)) {
2864 if (kvm_x86_ops->has_wbinvd_exit())
2865 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2866 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2867 smp_call_function_single(vcpu->cpu,
2868 wbinvd_ipi, NULL, 1);
2869 }
2870
313a3dc7 2871 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2872
0dd6a6ed
ZA		 2873 /* Apply any externally detected TSC adjustments (due to suspend) */
2874 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2875 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2876 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2878 }
8f6055cb 2879
48434c20 2880 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2881 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2882 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2883 if (tsc_delta < 0)
2884 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2885 if (check_tsc_unstable()) {
b183aa58
ZA		 2886 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2887 vcpu->arch.last_guest_tsc);
2888 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2889 vcpu->arch.tsc_catchup = 1;
c285545f 2890 }
d98d07ca
MT		 2891 /*
2892 * On a host with synchronized TSC, there is no need to update
2893 * kvmclock on vcpu->cpu migration
2894 */
2895 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2896 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2897 if (vcpu->cpu != cpu)
2898 kvm_migrate_timers(vcpu);
e48672fa 2899 vcpu->cpu = cpu;
6b7d7e76 2900 }
c9aaa895
GC		 2901
2902 accumulate_steal_time(vcpu);
2903 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2904}
2905
2906void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2907{
02daab21 2908 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2909 kvm_put_guest_fpu(vcpu);
6f526ec5 2910 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2911}
2912
313a3dc7
CO		 2913static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2914 struct kvm_lapic_state *s)
2915{
5a71785d 2916 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2917 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2918
2919 return 0;
2920}
2921
2922static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2923 struct kvm_lapic_state *s)
2924{
64eb0620 2925 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2926 update_cr8_intercept(vcpu);
313a3dc7
CO		 2927
2928 return 0;
2929}
2930
f77bc6a4
ZX		 2931static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2932 struct kvm_interrupt *irq)
2933{
02cdb50f 2934 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2935 return -EINVAL;
2936 if (irqchip_in_kernel(vcpu->kvm))
2937 return -ENXIO;
f77bc6a4 2938
66fd3f7f 2939 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2940 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2941
f77bc6a4
ZX		 2942 return 0;
2943}
2944
c4abb7c9
JK		 2945static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2946{
c4abb7c9 2947 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2948
2949 return 0;
2950}
2951
b209749f
AK		 2952static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2953 struct kvm_tpr_access_ctl *tac)
2954{
2955 if (tac->flags)
2956 return -EINVAL;
2957 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2958 return 0;
2959}
2960
890ca9ae
HY		 2961static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2962 u64 mcg_cap)
2963{
2964 int r;
2965 unsigned bank_num = mcg_cap & 0xff, bank;
2966
2967 r = -EINVAL;
a9e38c3e 2968 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2969 goto out;
2970 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2971 goto out;
2972 r = 0;
2973 vcpu->arch.mcg_cap = mcg_cap;
2974 /* Init IA32_MCG_CTL to all 1s */
2975 if (mcg_cap & MCG_CTL_P)
2976 vcpu->arch.mcg_ctl = ~(u64)0;
2977 /* Init IA32_MCi_CTL to all 1s */
2978 for (bank = 0; bank < bank_num; bank++)
2979 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2980out:
2981 return r;
2982}
2983
2984static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2985 struct kvm_x86_mce *mce)
2986{
2987 u64 mcg_cap = vcpu->arch.mcg_cap;
2988 unsigned bank_num = mcg_cap & 0xff;
2989 u64 *banks = vcpu->arch.mce_banks;
2990
2991 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2992 return -EINVAL;
2993 /*
2994 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2995 * reporting is disabled
2996 */
2997 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2998 vcpu->arch.mcg_ctl != ~(u64)0)
2999 return 0;
3000 banks += 4 * mce->bank;
3001 /*
3002 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3003 * reporting is disabled for the bank
3004 */
3005 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3006 return 0;
3007 if (mce->status & MCI_STATUS_UC) {
3008 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3009 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3010 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3011 return 0;
3012 }
3013 if (banks[1] & MCI_STATUS_VAL)
3014 mce->status |= MCI_STATUS_OVER;
3015 banks[2] = mce->addr;
3016 banks[3] = mce->misc;
3017 vcpu->arch.mcg_status = mce->mcg_status;
3018 banks[1] = mce->status;
3019 kvm_queue_exception(vcpu, MC_VECTOR);
3020 } else if (!(banks[1] & MCI_STATUS_VAL)
3021 || !(banks[1] & MCI_STATUS_UC)) {
3022 if (banks[1] & MCI_STATUS_VAL)
3023 mce->status |= MCI_STATUS_OVER;
3024 banks[2] = mce->addr;
3025 banks[3] = mce->misc;
3026 banks[1] = mce->status;
3027 } else
3028 banks[1] |= MCI_STATUS_OVER;
3029 return 0;
3030}
3031
3cfc3092
JK		 3032static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3033 struct kvm_vcpu_events *events)
3034{
7460fb4a 3035 process_nmi(vcpu);
03b82a30
JK		 3036 events->exception.injected =
3037 vcpu->arch.exception.pending &&
3038 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3039 events->exception.nr = vcpu->arch.exception.nr;
3040 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3041 events->exception.pad = 0;
3cfc3092
JK		 3042 events->exception.error_code = vcpu->arch.exception.error_code;
3043
03b82a30
JK		 3044 events->interrupt.injected =
3045 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3046 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3047 events->interrupt.soft = 0;
37ccdcbe 3048 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3049
3050 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3051 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3052 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3053 events->nmi.pad = 0;
3cfc3092 3054
66450a21 3055 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3056
dab4b911 3057 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3058 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3059 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3060}
3061
3062static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3063 struct kvm_vcpu_events *events)
3064{
dab4b911 3065 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3066 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3067 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3068 return -EINVAL;
3069
7460fb4a 3070 process_nmi(vcpu);
3cfc3092
JK		 3071 vcpu->arch.exception.pending = events->exception.injected;
3072 vcpu->arch.exception.nr = events->exception.nr;
3073 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3074 vcpu->arch.exception.error_code = events->exception.error_code;
3075
3076 vcpu->arch.interrupt.pending = events->interrupt.injected;
3077 vcpu->arch.interrupt.nr = events->interrupt.nr;
3078 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3079 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3080 kvm_x86_ops->set_interrupt_shadow(vcpu,
3081 events->interrupt.shadow);
3cfc3092
JK		 3082
3083 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3084 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3085 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3086 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3087
66450a21
JK		 3088 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3089 kvm_vcpu_has_lapic(vcpu))
3090 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3091
3842d135
AK		 3092 kvm_make_request(KVM_REQ_EVENT, vcpu);
3093
3cfc3092
JK		 3094 return 0;
3095}
3096
a1efbe77
JK		 3097static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3098 struct kvm_debugregs *dbgregs)
3099{
73aaf249
JK		 3100 unsigned long val;
3101
a1efbe77 3102 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3103 kvm_get_dr(vcpu, 6, &val);
73aaf249 3104 dbgregs->dr6 = val;
a1efbe77
JK		 3105 dbgregs->dr7 = vcpu->arch.dr7;
3106 dbgregs->flags = 0;
97e69aa6 3107 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3108}
3109
3110static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3111 struct kvm_debugregs *dbgregs)
3112{
3113 if (dbgregs->flags)
3114 return -EINVAL;
3115
a1efbe77
JK		 3116 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3117 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3118 kvm_update_dr6(vcpu);
a1efbe77 3119 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3120 kvm_update_dr7(vcpu);
a1efbe77 3121
a1efbe77
JK		 3122 return 0;
3123}
3124
2d5b5a66
SY		 3125static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3126 struct kvm_xsave *guest_xsave)
3127{
4344ee98 3128 if (cpu_has_xsave) {
2d5b5a66
SY		 3129 memcpy(guest_xsave->region,
3130 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3131 vcpu->arch.guest_xstate_size);
3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3133 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3134 } else {
2d5b5a66
SY		 3135 memcpy(guest_xsave->region,
3136 &vcpu->arch.guest_fpu.state->fxsave,
3137 sizeof(struct i387_fxsave_struct));
3138 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3139 XSTATE_FPSSE;
3140 }
3141}
3142
3143static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3144 struct kvm_xsave *guest_xsave)
3145{
3146 u64 xstate_bv =
3147 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3148
d7876f1b
PB		 3149 if (cpu_has_xsave) {
3150 /*
3151 * Here we allow setting states that are not present in
3152 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3153 * with old userspace.
3154 */
4ff41732 3155 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3156 return -EINVAL;
2d5b5a66 3157 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3158 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3159 } else {
2d5b5a66
SY		 3160 if (xstate_bv & ~XSTATE_FPSSE)
3161 return -EINVAL;
3162 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3163 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3164 }
3165 return 0;
3166}
3167
3168static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3169 struct kvm_xcrs *guest_xcrs)
3170{
3171 if (!cpu_has_xsave) {
3172 guest_xcrs->nr_xcrs = 0;
3173 return;
3174 }
3175
3176 guest_xcrs->nr_xcrs = 1;
3177 guest_xcrs->flags = 0;
3178 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3179 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3180}
3181
3182static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3183 struct kvm_xcrs *guest_xcrs)
3184{
3185 int i, r = 0;
3186
3187 if (!cpu_has_xsave)
3188 return -EINVAL;
3189
3190 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3191 return -EINVAL;
3192
3193 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3194 /* Only support XCR0 currently */
c67a04cb 3195 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3196 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3197 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3198 break;
3199 }
3200 if (r)
3201 r = -EINVAL;
3202 return r;
3203}
3204
1c0b28c2
EM		 3205/*
3206 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3207 * stopped by the hypervisor. This function will be called from the host only.
3208 * EINVAL is returned when the host attempts to set the flag for a guest that
3209 * does not support pv clocks.
3210 */
3211static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3212{
0b79459b 3213 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3214 return -EINVAL;
51d59c6b 3215 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3216 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3217 return 0;
3218}
3219
313a3dc7
CO		 3220long kvm_arch_vcpu_ioctl(struct file *filp,
3221 unsigned int ioctl, unsigned long arg)
3222{
3223 struct kvm_vcpu *vcpu = filp->private_data;
3224 void __user *argp = (void __user *)arg;
3225 int r;
d1ac91d8
AK		 3226 union {
3227 struct kvm_lapic_state *lapic;
3228 struct kvm_xsave *xsave;
3229 struct kvm_xcrs *xcrs;
3230 void *buffer;
3231 } u;
3232
3233 u.buffer = NULL;
313a3dc7
CO		 3234 switch (ioctl) {
3235 case KVM_GET_LAPIC: {
2204ae3c
MT		 3236 r = -EINVAL;
3237 if (!vcpu->arch.apic)
3238 goto out;
d1ac91d8 3239 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3240
b772ff36 3241 r = -ENOMEM;
d1ac91d8 3242 if (!u.lapic)
b772ff36 3243 goto out;
d1ac91d8 3244 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3245 if (r)
3246 goto out;
3247 r = -EFAULT;
d1ac91d8 3248 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3249 goto out;
3250 r = 0;
3251 break;
3252 }
3253 case KVM_SET_LAPIC: {
2204ae3c
MT		 3254 r = -EINVAL;
3255 if (!vcpu->arch.apic)
3256 goto out;
ff5c2c03 3257 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3258 if (IS_ERR(u.lapic))
3259 return PTR_ERR(u.lapic);
ff5c2c03 3260
d1ac91d8 3261 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3262 break;
3263 }
f77bc6a4
ZX		 3264 case KVM_INTERRUPT: {
3265 struct kvm_interrupt irq;
3266
3267 r = -EFAULT;
3268 if (copy_from_user(&irq, argp, sizeof irq))
3269 goto out;
3270 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3271 break;
3272 }
c4abb7c9
JK		 3273 case KVM_NMI: {
3274 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3275 break;
3276 }
313a3dc7
CO		 3277 case KVM_SET_CPUID: {
3278 struct kvm_cpuid __user *cpuid_arg = argp;
3279 struct kvm_cpuid cpuid;
3280
3281 r = -EFAULT;
3282 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3283 goto out;
3284 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3285 break;
3286 }
07716717
DK		 3287 case KVM_SET_CPUID2: {
3288 struct kvm_cpuid2 __user *cpuid_arg = argp;
3289 struct kvm_cpuid2 cpuid;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3293 goto out;
3294 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3295 cpuid_arg->entries);
07716717
DK		 3296 break;
3297 }
3298 case KVM_GET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3304 goto out;
3305 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3306 cpuid_arg->entries);
07716717
DK		 3307 if (r)
3308 goto out;
3309 r = -EFAULT;
3310 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3311 goto out;
3312 r = 0;
3313 break;
3314 }
313a3dc7
CO		 3315 case KVM_GET_MSRS:
3316 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3317 break;
3318 case KVM_SET_MSRS:
3319 r = msr_io(vcpu, argp, do_set_msr, 0);
3320 break;
b209749f
AK		 3321 case KVM_TPR_ACCESS_REPORTING: {
3322 struct kvm_tpr_access_ctl tac;
3323
3324 r = -EFAULT;
3325 if (copy_from_user(&tac, argp, sizeof tac))
3326 goto out;
3327 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3328 if (r)
3329 goto out;
3330 r = -EFAULT;
3331 if (copy_to_user(argp, &tac, sizeof tac))
3332 goto out;
3333 r = 0;
3334 break;
3335 };
b93463aa
AK		 3336 case KVM_SET_VAPIC_ADDR: {
3337 struct kvm_vapic_addr va;
3338
3339 r = -EINVAL;
3340 if (!irqchip_in_kernel(vcpu->kvm))
3341 goto out;
3342 r = -EFAULT;
3343 if (copy_from_user(&va, argp, sizeof va))
3344 goto out;
fda4e2e8 3345 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3346 break;
3347 }
890ca9ae
HY		 3348 case KVM_X86_SETUP_MCE: {
3349 u64 mcg_cap;
3350
3351 r = -EFAULT;
3352 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3353 goto out;
3354 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3355 break;
3356 }
3357 case KVM_X86_SET_MCE: {
3358 struct kvm_x86_mce mce;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&mce, argp, sizeof mce))
3362 goto out;
3363 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3364 break;
3365 }
3cfc3092
JK		 3366 case KVM_GET_VCPU_EVENTS: {
3367 struct kvm_vcpu_events events;
3368
3369 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3370
3371 r = -EFAULT;
3372 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3373 break;
3374 r = 0;
3375 break;
3376 }
3377 case KVM_SET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3379
3380 r = -EFAULT;
3381 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3382 break;
3383
3384 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3385 break;
3386 }
a1efbe77
JK		 3387 case KVM_GET_DEBUGREGS: {
3388 struct kvm_debugregs dbgregs;
3389
3390 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3391
3392 r = -EFAULT;
3393 if (copy_to_user(argp, &dbgregs,
3394 sizeof(struct kvm_debugregs)))
3395 break;
3396 r = 0;
3397 break;
3398 }
3399 case KVM_SET_DEBUGREGS: {
3400 struct kvm_debugregs dbgregs;
3401
3402 r = -EFAULT;
3403 if (copy_from_user(&dbgregs, argp,
3404 sizeof(struct kvm_debugregs)))
3405 break;
3406
3407 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3408 break;
3409 }
2d5b5a66 3410 case KVM_GET_XSAVE: {
d1ac91d8 3411 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3412 r = -ENOMEM;
d1ac91d8 3413 if (!u.xsave)
2d5b5a66
SY		 3414 break;
3415
d1ac91d8 3416 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3417
3418 r = -EFAULT;
d1ac91d8 3419 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3420 break;
3421 r = 0;
3422 break;
3423 }
3424 case KVM_SET_XSAVE: {
ff5c2c03 3425 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3426 if (IS_ERR(u.xsave))
3427 return PTR_ERR(u.xsave);
2d5b5a66 3428
d1ac91d8 3429 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3430 break;
3431 }
3432 case KVM_GET_XCRS: {
d1ac91d8 3433 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3434 r = -ENOMEM;
d1ac91d8 3435 if (!u.xcrs)
2d5b5a66
SY		 3436 break;
3437
d1ac91d8 3438 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3439
3440 r = -EFAULT;
d1ac91d8 3441 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3442 sizeof(struct kvm_xcrs)))
3443 break;
3444 r = 0;
3445 break;
3446 }
3447 case KVM_SET_XCRS: {
ff5c2c03 3448 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3449 if (IS_ERR(u.xcrs))
3450 return PTR_ERR(u.xcrs);
2d5b5a66 3451
d1ac91d8 3452 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3453 break;
3454 }
92a1f12d
JR		 3455 case KVM_SET_TSC_KHZ: {
3456 u32 user_tsc_khz;
3457
3458 r = -EINVAL;
92a1f12d
JR		 3459 user_tsc_khz = (u32)arg;
3460
3461 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3462 goto out;
3463
cc578287
ZA		 3464 if (user_tsc_khz == 0)
3465 user_tsc_khz = tsc_khz;
3466
3467 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3468
3469 r = 0;
3470 goto out;
3471 }
3472 case KVM_GET_TSC_KHZ: {
cc578287 3473 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3474 goto out;
3475 }
1c0b28c2
EM		 3476 case KVM_KVMCLOCK_CTRL: {
3477 r = kvm_set_guest_paused(vcpu);
3478 goto out;
3479 }
313a3dc7
CO		 3480 default:
3481 r = -EINVAL;
3482 }
3483out:
d1ac91d8 3484 kfree(u.buffer);
313a3dc7
CO		 3485 return r;
3486}
3487
5b1c1493
CO		 3488int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3489{
3490 return VM_FAULT_SIGBUS;
3491}
3492
1fe779f8
CO		 3493static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3494{
3495 int ret;
3496
3497 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3498 return -EINVAL;
1fe779f8
CO		 3499 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3500 return ret;
3501}
3502
b927a3ce
SY		 3503static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3504 u64 ident_addr)
3505{
3506 kvm->arch.ept_identity_map_addr = ident_addr;
3507 return 0;
3508}
3509
1fe779f8
CO		 3510static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3511 u32 kvm_nr_mmu_pages)
3512{
3513 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3514 return -EINVAL;
3515
79fac95e 3516 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3517
3518 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3519 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3520
79fac95e 3521 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3522 return 0;
3523}
3524
3525static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3526{
39de71ec 3527 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3528}
3529
1fe779f8
CO		 3530static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3531{
3532 int r;
3533
3534 r = 0;
3535 switch (chip->chip_id) {
3536 case KVM_IRQCHIP_PIC_MASTER:
3537 memcpy(&chip->chip.pic,
3538 &pic_irqchip(kvm)->pics[0],
3539 sizeof(struct kvm_pic_state));
3540 break;
3541 case KVM_IRQCHIP_PIC_SLAVE:
3542 memcpy(&chip->chip.pic,
3543 &pic_irqchip(kvm)->pics[1],
3544 sizeof(struct kvm_pic_state));
3545 break;
3546 case KVM_IRQCHIP_IOAPIC:
eba0226b 3547 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3548 break;
3549 default:
3550 r = -EINVAL;
3551 break;
3552 }
3553 return r;
3554}
3555
3556static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3557{
3558 int r;
3559
3560 r = 0;
3561 switch (chip->chip_id) {
3562 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3563 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3564 memcpy(&pic_irqchip(kvm)->pics[0],
3565 &chip->chip.pic,
3566 sizeof(struct kvm_pic_state));
f4f51050 3567 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3568 break;
3569 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3570 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3571 memcpy(&pic_irqchip(kvm)->pics[1],
3572 &chip->chip.pic,
3573 sizeof(struct kvm_pic_state));
f4f51050 3574 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3575 break;
3576 case KVM_IRQCHIP_IOAPIC:
eba0226b 3577 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3578 break;
3579 default:
3580 r = -EINVAL;
3581 break;
3582 }
3583 kvm_pic_update_irq(pic_irqchip(kvm));
3584 return r;
3585}
3586
e0f63cb9
SY		 3587static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3588{
3589 int r = 0;
3590
894a9c55 3591 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3592 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3593 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3594 return r;
3595}
3596
3597static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3598{
3599 int r = 0;
3600
894a9c55 3601 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3602 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3603 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3604 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3605 return r;
3606}
3607
3608static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3609{
3610 int r = 0;
3611
3612 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3613 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3614 sizeof(ps->channels));
3615 ps->flags = kvm->arch.vpit->pit_state.flags;
3616 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3617 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3618 return r;
3619}
3620
3621static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3622{
3623 int r = 0, start = 0;
3624 u32 prev_legacy, cur_legacy;
3625 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3626 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3627 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3628 if (!prev_legacy && cur_legacy)
3629 start = 1;
3630 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3631 sizeof(kvm->arch.vpit->pit_state.channels));
3632 kvm->arch.vpit->pit_state.flags = ps->flags;
3633 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3634 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3635 return r;
3636}
3637
52d939a0
MT		 3638static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3639 struct kvm_reinject_control *control)
3640{
3641 if (!kvm->arch.vpit)
3642 return -ENXIO;
894a9c55 3643 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3644 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3645 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3646 return 0;
3647}
3648
95d4c16c 3649/**
60c34612
TY		 3650 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3651 * @kvm: kvm instance
3652 * @log: slot id and address to which we copy the log
95d4c16c 3653 *
60c34612
TY		 3654 * We need to keep it in mind that VCPU threads can write to the bitmap
3655 * concurrently. So, to avoid losing data, we keep the following order for
3656 * each bit:
95d4c16c 3657 *
60c34612
TY		 3658 * 1. Take a snapshot of the bit and clear it if needed.
3659 * 2. Write protect the corresponding page.
3660 * 3. Flush TLB's if needed.
3661 * 4. Copy the snapshot to the userspace.
95d4c16c 3662 *
60c34612
TY		 3663 * Between 2 and 3, the guest may write to the page using the remaining TLB
3664 * entry. This is not a problem because the page will be reported dirty at
3665 * step 4 using the snapshot taken before and step 3 ensures that successive
3666 * writes will be logged for the next call.
5bb064dc 3667 */
60c34612 3668int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3669{
7850ac54 3670 int r;
5bb064dc 3671 struct kvm_memory_slot *memslot;
60c34612
TY		 3672 unsigned long n, i;
3673 unsigned long *dirty_bitmap;
3674 unsigned long *dirty_bitmap_buffer;
3675 bool is_dirty = false;
5bb064dc 3676
79fac95e 3677 mutex_lock(&kvm->slots_lock);
5bb064dc 3678
b050b015 3679 r = -EINVAL;
bbacc0c1 3680 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3681 goto out;
3682
28a37544 3683 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3684
3685 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3686 r = -ENOENT;
60c34612 3687 if (!dirty_bitmap)
b050b015
MT		 3688 goto out;
3689
87bf6e7d 3690 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3691
60c34612
TY		 3692 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3693 memset(dirty_bitmap_buffer, 0, n);
b050b015 3694
60c34612 3695 spin_lock(&kvm->mmu_lock);
b050b015 3696
60c34612
TY		 3697 for (i = 0; i < n / sizeof(long); i++) {
3698 unsigned long mask;
3699 gfn_t offset;
cdfca7b3 3700
60c34612
TY		 3701 if (!dirty_bitmap[i])
3702 continue;
b050b015 3703
60c34612 3704 is_dirty = true;
914ebccd 3705
60c34612
TY		 3706 mask = xchg(&dirty_bitmap[i], 0);
3707 dirty_bitmap_buffer[i] = mask;
edde99ce 3708
60c34612
TY		 3709 offset = i * BITS_PER_LONG;
3710 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3711 }
60c34612
TY		 3712
3713 spin_unlock(&kvm->mmu_lock);
3714
198c74f4
XG		 3715 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3716 lockdep_assert_held(&kvm->slots_lock);
3717
3718 /*
3719 * All the TLBs can be flushed out of mmu lock, see the comments in
3720 * kvm_mmu_slot_remove_write_access().
3721 */
3722 if (is_dirty)
3723 kvm_flush_remote_tlbs(kvm);
3724
60c34612
TY		 3725 r = -EFAULT;
3726 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3727 goto out;
b050b015 3728
5bb064dc
ZX		 3729 r = 0;
3730out:
79fac95e 3731 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3732 return r;
3733}
3734
aa2fbe6d
YZ		 3735int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3736 bool line_status)
23d43cf9
CD		 3737{
3738 if (!irqchip_in_kernel(kvm))
3739 return -ENXIO;
3740
3741 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3742 irq_event->irq, irq_event->level,
3743 line_status);
23d43cf9
CD		 3744 return 0;
3745}
3746
1fe779f8
CO		 3747long kvm_arch_vm_ioctl(struct file *filp,
3748 unsigned int ioctl, unsigned long arg)
3749{
3750 struct kvm *kvm = filp->private_data;
3751 void __user *argp = (void __user *)arg;
367e1319 3752 int r = -ENOTTY;
f0d66275
DH		 3753 /*
3754 * This union makes it completely explicit to gcc-3.x
3755 * that these two variables' stack usage should be
3756 * combined, not added together.
3757 */
3758 union {
3759 struct kvm_pit_state ps;
e9f42757 3760 struct kvm_pit_state2 ps2;
c5ff41ce 3761 struct kvm_pit_config pit_config;
f0d66275 3762 } u;
1fe779f8
CO		 3763
3764 switch (ioctl) {
3765 case KVM_SET_TSS_ADDR:
3766 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3767 break;
b927a3ce
SY		 3768 case KVM_SET_IDENTITY_MAP_ADDR: {
3769 u64 ident_addr;
3770
3771 r = -EFAULT;
3772 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3773 goto out;
3774 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3775 break;
3776 }
1fe779f8
CO		 3777 case KVM_SET_NR_MMU_PAGES:
3778 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3779 break;
3780 case KVM_GET_NR_MMU_PAGES:
3781 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3782 break;
3ddea128
MT		 3783 case KVM_CREATE_IRQCHIP: {
3784 struct kvm_pic *vpic;
3785
3786 mutex_lock(&kvm->lock);
3787 r = -EEXIST;
3788 if (kvm->arch.vpic)
3789 goto create_irqchip_unlock;
3e515705
AK		 3790 r = -EINVAL;
3791 if (atomic_read(&kvm->online_vcpus))
3792 goto create_irqchip_unlock;
1fe779f8 3793 r = -ENOMEM;
3ddea128
MT		 3794 vpic = kvm_create_pic(kvm);
3795 if (vpic) {
1fe779f8
CO		 3796 r = kvm_ioapic_init(kvm);
3797 if (r) {
175504cd 3798 mutex_lock(&kvm->slots_lock);
72bb2fcd 3799 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3800 &vpic->dev_master);
3801 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3802 &vpic->dev_slave);
3803 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3804 &vpic->dev_eclr);
175504cd 3805 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3806 kfree(vpic);
3807 goto create_irqchip_unlock;
1fe779f8
CO		 3808 }
3809 } else
3ddea128
MT		 3810 goto create_irqchip_unlock;
3811 smp_wmb();
3812 kvm->arch.vpic = vpic;
3813 smp_wmb();
399ec807
AK		 3814 r = kvm_setup_default_irq_routing(kvm);
3815 if (r) {
175504cd 3816 mutex_lock(&kvm->slots_lock);
3ddea128 3817 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3818 kvm_ioapic_destroy(kvm);
3819 kvm_destroy_pic(kvm);
3ddea128 3820 mutex_unlock(&kvm->irq_lock);
175504cd 3821 mutex_unlock(&kvm->slots_lock);
399ec807 3822 }
3ddea128
MT		 3823 create_irqchip_unlock:
3824 mutex_unlock(&kvm->lock);
1fe779f8 3825 break;
3ddea128 3826 }
7837699f 3827 case KVM_CREATE_PIT:
c5ff41ce
JK		 3828 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3829 goto create_pit;
3830 case KVM_CREATE_PIT2:
3831 r = -EFAULT;
3832 if (copy_from_user(&u.pit_config, argp,
3833 sizeof(struct kvm_pit_config)))
3834 goto out;
3835 create_pit:
79fac95e 3836 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3837 r = -EEXIST;
3838 if (kvm->arch.vpit)
3839 goto create_pit_unlock;
7837699f 3840 r = -ENOMEM;
c5ff41ce 3841 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3842 if (kvm->arch.vpit)
3843 r = 0;
269e05e4 3844 create_pit_unlock:
79fac95e 3845 mutex_unlock(&kvm->slots_lock);
7837699f 3846 break;
1fe779f8
CO		 3847 case KVM_GET_IRQCHIP: {
3848 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3849 struct kvm_irqchip *chip;
1fe779f8 3850
ff5c2c03
SL		 3851 chip = memdup_user(argp, sizeof(*chip));
3852 if (IS_ERR(chip)) {
3853 r = PTR_ERR(chip);
1fe779f8 3854 goto out;
ff5c2c03
SL		 3855 }
3856
1fe779f8
CO		 3857 r = -ENXIO;
3858 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3859 goto get_irqchip_out;
3860 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3861 if (r)
f0d66275 3862 goto get_irqchip_out;
1fe779f8 3863 r = -EFAULT;
f0d66275
DH		 3864 if (copy_to_user(argp, chip, sizeof *chip))
3865 goto get_irqchip_out;
1fe779f8 3866 r = 0;
f0d66275
DH		 3867 get_irqchip_out:
3868 kfree(chip);
1fe779f8
CO		 3869 break;
3870 }
3871 case KVM_SET_IRQCHIP: {
3872 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3873 struct kvm_irqchip *chip;
1fe779f8 3874
ff5c2c03
SL		 3875 chip = memdup_user(argp, sizeof(*chip));
3876 if (IS_ERR(chip)) {
3877 r = PTR_ERR(chip);
1fe779f8 3878 goto out;
ff5c2c03
SL		 3879 }
3880
1fe779f8
CO		 3881 r = -ENXIO;
3882 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3883 goto set_irqchip_out;
3884 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3885 if (r)
f0d66275 3886 goto set_irqchip_out;
1fe779f8 3887 r = 0;
f0d66275
DH		 3888 set_irqchip_out:
3889 kfree(chip);
1fe779f8
CO		 3890 break;
3891 }
e0f63cb9 3892 case KVM_GET_PIT: {
e0f63cb9 3893 r = -EFAULT;
f0d66275 3894 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3895 goto out;
3896 r = -ENXIO;
3897 if (!kvm->arch.vpit)
3898 goto out;
f0d66275 3899 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3900 if (r)
3901 goto out;
3902 r = -EFAULT;
f0d66275 3903 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3904 goto out;
3905 r = 0;
3906 break;
3907 }
3908 case KVM_SET_PIT: {
e0f63cb9 3909 r = -EFAULT;
f0d66275 3910 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3911 goto out;
3912 r = -ENXIO;
3913 if (!kvm->arch.vpit)
3914 goto out;
f0d66275 3915 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3916 break;
3917 }
e9f42757
BK		 3918 case KVM_GET_PIT2: {
3919 r = -ENXIO;
3920 if (!kvm->arch.vpit)
3921 goto out;
3922 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3923 if (r)
3924 goto out;
3925 r = -EFAULT;
3926 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3927 goto out;
3928 r = 0;
3929 break;
3930 }
3931 case KVM_SET_PIT2: {
3932 r = -EFAULT;
3933 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3934 goto out;
3935 r = -ENXIO;
3936 if (!kvm->arch.vpit)
3937 goto out;
3938 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3939 break;
3940 }
52d939a0
MT		 3941 case KVM_REINJECT_CONTROL: {
3942 struct kvm_reinject_control control;
3943 r = -EFAULT;
3944 if (copy_from_user(&control, argp, sizeof(control)))
3945 goto out;
3946 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3947 break;
3948 }
ffde22ac
ES		 3949 case KVM_XEN_HVM_CONFIG: {
3950 r = -EFAULT;
3951 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3952 sizeof(struct kvm_xen_hvm_config)))
3953 goto out;
3954 r = -EINVAL;
3955 if (kvm->arch.xen_hvm_config.flags)
3956 goto out;
3957 r = 0;
3958 break;
3959 }
afbcf7ab 3960 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3961 struct kvm_clock_data user_ns;
3962 u64 now_ns;
3963 s64 delta;
3964
3965 r = -EFAULT;
3966 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3967 goto out;
3968
3969 r = -EINVAL;
3970 if (user_ns.flags)
3971 goto out;
3972
3973 r = 0;
395c6b0a 3974 local_irq_disable();
759379dd 3975 now_ns = get_kernel_ns();
afbcf7ab 3976 delta = user_ns.clock - now_ns;
395c6b0a 3977 local_irq_enable();
afbcf7ab 3978 kvm->arch.kvmclock_offset = delta;
2e762ff7 3979 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3980 break;
3981 }
3982 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3983 struct kvm_clock_data user_ns;
3984 u64 now_ns;
3985
395c6b0a 3986 local_irq_disable();
759379dd 3987 now_ns = get_kernel_ns();
afbcf7ab 3988 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3989 local_irq_enable();
afbcf7ab 3990 user_ns.flags = 0;
97e69aa6 3991 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3992
3993 r = -EFAULT;
3994 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3995 goto out;
3996 r = 0;
3997 break;
3998 }
3999
1fe779f8
CO		 4000 default:
4001 ;
4002 }
4003out:
4004 return r;
4005}
4006
a16b043c 4007static void kvm_init_msr_list(void)
043405e1
CO		 4008{
4009 u32 dummy[2];
4010 unsigned i, j;
4011
e3267cbb
GC		 4012 /* skip the first msrs in the list. KVM-specific */
4013 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4014 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4015 continue;
93c4adc7
PB		 4016
4017 /*
4018 * Even MSRs that are valid in the host may not be exposed
4019 * to the guests in some cases. We could work around this
4020 * in VMX with the generic MSR save/load machinery, but it
4021 * is not really worthwhile since it will really only
4022 * happen with nested virtualization.
4023 */
4024 switch (msrs_to_save[i]) {
4025 case MSR_IA32_BNDCFGS:
4026 if (!kvm_x86_ops->mpx_supported())
4027 continue;
4028 break;
4029 default:
4030 break;
4031 }
4032
043405e1
CO		 4033 if (j < i)
4034 msrs_to_save[j] = msrs_to_save[i];
4035 j++;
4036 }
4037 num_msrs_to_save = j;
4038}
4039
bda9020e
MT		 4040static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4041 const void *v)
bbd9b64e 4042{
70252a10
AK		 4043 int handled = 0;
4044 int n;
4045
4046 do {
4047 n = min(len, 8);
4048 if (!(vcpu->arch.apic &&
4049 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4050 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4051 break;
4052 handled += n;
4053 addr += n;
4054 len -= n;
4055 v += n;
4056 } while (len);
bbd9b64e 4057
70252a10 4058 return handled;
bbd9b64e
CO		 4059}
4060
bda9020e 4061static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4062{
70252a10
AK		 4063 int handled = 0;
4064 int n;
4065
4066 do {
4067 n = min(len, 8);
4068 if (!(vcpu->arch.apic &&
4069 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4070 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4071 break;
4072 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4073 handled += n;
4074 addr += n;
4075 len -= n;
4076 v += n;
4077 } while (len);
bbd9b64e 4078
70252a10 4079 return handled;
bbd9b64e
CO		 4080}
4081
2dafc6c2
GN		 4082static void kvm_set_segment(struct kvm_vcpu *vcpu,
4083 struct kvm_segment *var, int seg)
4084{
4085 kvm_x86_ops->set_segment(vcpu, var, seg);
4086}
4087
4088void kvm_get_segment(struct kvm_vcpu *vcpu,
4089 struct kvm_segment *var, int seg)
4090{
4091 kvm_x86_ops->get_segment(vcpu, var, seg);
4092}
4093
54987b7a
PB		 4094gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4095 struct x86_exception *exception)
02f59dc9
JR		 4096{
4097 gpa_t t_gpa;
02f59dc9
JR		 4098
4099 BUG_ON(!mmu_is_nested(vcpu));
4100
4101 /* NPT walks are always user-walks */
4102 access |= PFERR_USER_MASK;
54987b7a 4103 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4104
4105 return t_gpa;
4106}
4107
ab9ae313
AK		 4108gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4109 struct x86_exception *exception)
1871c602
GN		 4110{
4111 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4112 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4113}
4114
ab9ae313
AK		 4115 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4116 struct x86_exception *exception)
1871c602
GN		 4117{
4118 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4119 access |= PFERR_FETCH_MASK;
ab9ae313 4120 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4121}
4122
ab9ae313
AK		 4123gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4124 struct x86_exception *exception)
1871c602
GN		 4125{
4126 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4127 access |= PFERR_WRITE_MASK;
ab9ae313 4128 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4129}
4130
4131/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4132gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4133 struct x86_exception *exception)
1871c602 4134{
ab9ae313 4135 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4136}
4137
4138static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4139 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4140 struct x86_exception *exception)
bbd9b64e
CO		 4141{
4142 void *data = val;
10589a46 4143 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4144
4145 while (bytes) {
14dfe855 4146 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4147 exception);
bbd9b64e 4148 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4149 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4150 int ret;
4151
bcc55cba 4152 if (gpa == UNMAPPED_GVA)
ab9ae313 4153 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4154 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4155 offset, toread);
10589a46 4156 if (ret < 0) {
c3cd7ffa 4157 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4158 goto out;
4159 }
bbd9b64e 4160
77c2002e
IE		 4161 bytes -= toread;
4162 data += toread;
4163 addr += toread;
bbd9b64e 4164 }
10589a46 4165out:
10589a46 4166 return r;
bbd9b64e 4167}
77c2002e 4168
1871c602 4169/* used for instruction fetching */
0f65dd70
AK		 4170static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4171 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4172 struct x86_exception *exception)
1871c602 4173{
0f65dd70 4174 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4175 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4176 unsigned offset;
4177 int ret;
0f65dd70 4178
44583cba
PB		 4179 /* Inline kvm_read_guest_virt_helper for speed. */
4180 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4181 exception);
4182 if (unlikely(gpa == UNMAPPED_GVA))
4183 return X86EMUL_PROPAGATE_FAULT;
4184
4185 offset = addr & (PAGE_SIZE-1);
4186 if (WARN_ON(offset + bytes > PAGE_SIZE))
4187 bytes = (unsigned)PAGE_SIZE - offset;
4188 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4189 offset, bytes);
4190 if (unlikely(ret < 0))
4191 return X86EMUL_IO_NEEDED;
4192
4193 return X86EMUL_CONTINUE;
1871c602
GN		 4194}
4195
064aea77 4196int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4197 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4198 struct x86_exception *exception)
1871c602 4199{
0f65dd70 4200 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4201 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4202
1871c602 4203 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4204 exception);
1871c602 4205}
064aea77 4206EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4207
0f65dd70
AK		 4208static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4209 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4210 struct x86_exception *exception)
1871c602 4211{
0f65dd70 4212 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4213 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4214}
4215
6a4d7550 4216int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4217 gva_t addr, void *val,
2dafc6c2 4218 unsigned int bytes,
bcc55cba 4219 struct x86_exception *exception)
77c2002e 4220{
0f65dd70 4221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4222 void *data = val;
4223 int r = X86EMUL_CONTINUE;
4224
4225 while (bytes) {
14dfe855
JR		 4226 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4227 PFERR_WRITE_MASK,
ab9ae313 4228 exception);
77c2002e
IE		 4229 unsigned offset = addr & (PAGE_SIZE-1);
4230 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4231 int ret;
4232
bcc55cba 4233 if (gpa == UNMAPPED_GVA)
ab9ae313 4234 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4235 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4236 if (ret < 0) {
c3cd7ffa 4237 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4238 goto out;
4239 }
4240
4241 bytes -= towrite;
4242 data += towrite;
4243 addr += towrite;
4244 }
4245out:
4246 return r;
4247}
6a4d7550 4248EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4249
af7cc7d1
XG		 4250static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4251 gpa_t *gpa, struct x86_exception *exception,
4252 bool write)
4253{
97d64b78
AK		 4254 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4255 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4256
97d64b78 4257 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4258 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4259 vcpu->arch.access, access)) {
bebb106a
XG		 4260 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4261 (gva & (PAGE_SIZE - 1));
4f022648 4262 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4263 return 1;
4264 }
4265
af7cc7d1
XG		 4266 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4267
4268 if (*gpa == UNMAPPED_GVA)
4269 return -1;
4270
4271 /* For APIC access vmexit */
4272 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4273 return 1;
4274
4f022648
XG		 4275 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4276 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4277 return 1;
4f022648 4278 }
bebb106a 4279
af7cc7d1
XG		 4280 return 0;
4281}
4282
3200f405 4283int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4284 const void *val, int bytes)
bbd9b64e
CO		 4285{
4286 int ret;
4287
4288 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4289 if (ret < 0)
bbd9b64e 4290 return 0;
f57f2ef5 4291 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4292 return 1;
4293}
4294
77d197b2
XG		 4295struct read_write_emulator_ops {
4296 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4297 int bytes);
4298 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4299 void *val, int bytes);
4300 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4301 int bytes, void *val);
4302 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4303 void *val, int bytes);
4304 bool write;
4305};
4306
4307static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4308{
4309 if (vcpu->mmio_read_completed) {
77d197b2 4310 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4311 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4312 vcpu->mmio_read_completed = 0;
4313 return 1;
4314 }
4315
4316 return 0;
4317}
4318
4319static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4320 void *val, int bytes)
4321{
4322 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4323}
4324
4325static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4326 void *val, int bytes)
4327{
4328 return emulator_write_phys(vcpu, gpa, val, bytes);
4329}
4330
4331static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4332{
4333 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4334 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4335}
4336
4337static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4338 void *val, int bytes)
4339{
4340 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4341 return X86EMUL_IO_NEEDED;
4342}
4343
4344static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4345 void *val, int bytes)
4346{
f78146b0
AK		 4347 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4348
87da7e66 4349 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4350 return X86EMUL_CONTINUE;
4351}
4352
0fbe9b0b 4353static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4354 .read_write_prepare = read_prepare,
4355 .read_write_emulate = read_emulate,
4356 .read_write_mmio = vcpu_mmio_read,
4357 .read_write_exit_mmio = read_exit_mmio,
4358};
4359
0fbe9b0b 4360static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4361 .read_write_emulate = write_emulate,
4362 .read_write_mmio = write_mmio,
4363 .read_write_exit_mmio = write_exit_mmio,
4364 .write = true,
4365};
4366
22388a3c
XG		 4367static int emulator_read_write_onepage(unsigned long addr, void *val,
4368 unsigned int bytes,
4369 struct x86_exception *exception,
4370 struct kvm_vcpu *vcpu,
0fbe9b0b 4371 const struct read_write_emulator_ops *ops)
bbd9b64e 4372{
af7cc7d1
XG		 4373 gpa_t gpa;
4374 int handled, ret;
22388a3c 4375 bool write = ops->write;
f78146b0 4376 struct kvm_mmio_fragment *frag;
10589a46 4377
22388a3c 4378 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4379
af7cc7d1 4380 if (ret < 0)
bbd9b64e 4381 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4382
4383 /* For APIC access vmexit */
af7cc7d1 4384 if (ret)
bbd9b64e
CO		 4385 goto mmio;
4386
22388a3c 4387 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4388 return X86EMUL_CONTINUE;
4389
4390mmio:
4391 /*
4392 * Is this MMIO handled locally?
4393 */
22388a3c 4394 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4395 if (handled == bytes)
bbd9b64e 4396 return X86EMUL_CONTINUE;
bbd9b64e 4397
70252a10
AK		 4398 gpa += handled;
4399 bytes -= handled;
4400 val += handled;
4401
87da7e66
XG		 4402 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4403 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4404 frag->gpa = gpa;
4405 frag->data = val;
4406 frag->len = bytes;
f78146b0 4407 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4408}
4409
22388a3c
XG		 4410int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4411 void *val, unsigned int bytes,
4412 struct x86_exception *exception,
0fbe9b0b 4413 const struct read_write_emulator_ops *ops)
bbd9b64e 4414{
0f65dd70 4415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4416 gpa_t gpa;
4417 int rc;
4418
4419 if (ops->read_write_prepare &&
4420 ops->read_write_prepare(vcpu, val, bytes))
4421 return X86EMUL_CONTINUE;
4422
4423 vcpu->mmio_nr_fragments = 0;
0f65dd70 4424
bbd9b64e
CO		 4425 /* Crossing a page boundary? */
4426 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4427 int now;
bbd9b64e
CO		 4428
4429 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4430 rc = emulator_read_write_onepage(addr, val, now, exception,
4431 vcpu, ops);
4432
bbd9b64e
CO		 4433 if (rc != X86EMUL_CONTINUE)
4434 return rc;
4435 addr += now;
4436 val += now;
4437 bytes -= now;
4438 }
22388a3c 4439
f78146b0
AK		 4440 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4441 vcpu, ops);
4442 if (rc != X86EMUL_CONTINUE)
4443 return rc;
4444
4445 if (!vcpu->mmio_nr_fragments)
4446 return rc;
4447
4448 gpa = vcpu->mmio_fragments[0].gpa;
4449
4450 vcpu->mmio_needed = 1;
4451 vcpu->mmio_cur_fragment = 0;
4452
87da7e66 4453 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4454 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4455 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4456 vcpu->run->mmio.phys_addr = gpa;
4457
4458 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4459}
4460
4461static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4462 unsigned long addr,
4463 void *val,
4464 unsigned int bytes,
4465 struct x86_exception *exception)
4466{
4467 return emulator_read_write(ctxt, addr, val, bytes,
4468 exception, &read_emultor);
4469}
4470
4471int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4472 unsigned long addr,
4473 const void *val,
4474 unsigned int bytes,
4475 struct x86_exception *exception)
4476{
4477 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4478 exception, &write_emultor);
bbd9b64e 4479}
bbd9b64e 4480
daea3e73
AK		 4481#define CMPXCHG_TYPE(t, ptr, old, new) \
4482 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4483
4484#ifdef CONFIG_X86_64
4485# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4486#else
4487# define CMPXCHG64(ptr, old, new) \
9749a6c0 4488 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4489#endif
4490
0f65dd70
AK		 4491static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4492 unsigned long addr,
bbd9b64e
CO		 4493 const void *old,
4494 const void *new,
4495 unsigned int bytes,
0f65dd70 4496 struct x86_exception *exception)
bbd9b64e 4497{
0f65dd70 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4499 gpa_t gpa;
4500 struct page *page;
4501 char *kaddr;
4502 bool exchanged;
2bacc55c 4503
daea3e73
AK		 4504 /* guests cmpxchg8b have to be emulated atomically */
4505 if (bytes > 8 || (bytes & (bytes - 1)))
4506 goto emul_write;
10589a46 4507
daea3e73 4508 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4509
daea3e73
AK		 4510 if (gpa == UNMAPPED_GVA ||
4511 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4512 goto emul_write;
2bacc55c 4513
daea3e73
AK		 4514 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4515 goto emul_write;
72dc67a6 4516
daea3e73 4517 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4518 if (is_error_page(page))
c19b8bd6 4519 goto emul_write;
72dc67a6 4520
8fd75e12 4521 kaddr = kmap_atomic(page);
daea3e73
AK		 4522 kaddr += offset_in_page(gpa);
4523 switch (bytes) {
4524 case 1:
4525 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4526 break;
4527 case 2:
4528 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4529 break;
4530 case 4:
4531 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4532 break;
4533 case 8:
4534 exchanged = CMPXCHG64(kaddr, old, new);
4535 break;
4536 default:
4537 BUG();
2bacc55c 4538 }
8fd75e12 4539 kunmap_atomic(kaddr);
daea3e73
AK		 4540 kvm_release_page_dirty(page);
4541
4542 if (!exchanged)
4543 return X86EMUL_CMPXCHG_FAILED;
4544
d3714010 4545 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4546 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4547
4548 return X86EMUL_CONTINUE;
4a5f48f6 4549
3200f405 4550emul_write:
daea3e73 4551 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4552
0f65dd70 4553 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4554}
4555
cf8f70bf
GN		 4556static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4557{
4558 /* TODO: String I/O for in kernel device */
4559 int r;
4560
4561 if (vcpu->arch.pio.in)
4562 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4563 vcpu->arch.pio.size, pd);
4564 else
4565 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4566 vcpu->arch.pio.port, vcpu->arch.pio.size,
4567 pd);
4568 return r;
4569}
4570
6f6fbe98
XG		 4571static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4572 unsigned short port, void *val,
4573 unsigned int count, bool in)
cf8f70bf 4574{
cf8f70bf 4575 vcpu->arch.pio.port = port;
6f6fbe98 4576 vcpu->arch.pio.in = in;
7972995b 4577 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4578 vcpu->arch.pio.size = size;
4579
4580 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4581 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4582 return 1;
4583 }
4584
4585 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4586 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4587 vcpu->run->io.size = size;
4588 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4589 vcpu->run->io.count = count;
4590 vcpu->run->io.port = port;
4591
4592 return 0;
4593}
4594
6f6fbe98
XG		 4595static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4596 int size, unsigned short port, void *val,
4597 unsigned int count)
cf8f70bf 4598{
ca1d4a9e 4599 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4600 int ret;
ca1d4a9e 4601
6f6fbe98
XG		 4602 if (vcpu->arch.pio.count)
4603 goto data_avail;
cf8f70bf 4604
6f6fbe98
XG		 4605 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4606 if (ret) {
4607data_avail:
4608 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4609 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4610 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4611 return 1;
4612 }
4613
cf8f70bf
GN		 4614 return 0;
4615}
4616
6f6fbe98
XG		 4617static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4618 int size, unsigned short port,
4619 const void *val, unsigned int count)
4620{
4621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4622
4623 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4624 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4625 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4626}
4627
bbd9b64e
CO		 4628static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4629{
4630 return kvm_x86_ops->get_segment_base(vcpu, seg);
4631}
4632
3cb16fe7 4633static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4634{
3cb16fe7 4635 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4636}
4637
f5f48ee1
SY		 4638int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4639{
4640 if (!need_emulate_wbinvd(vcpu))
4641 return X86EMUL_CONTINUE;
4642
4643 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4644 int cpu = get_cpu();
4645
4646 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4647 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4648 wbinvd_ipi, NULL, 1);
2eec7343 4649 put_cpu();
f5f48ee1 4650 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4651 } else
4652 wbinvd();
f5f48ee1
SY		 4653 return X86EMUL_CONTINUE;
4654}
4655EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4656
bcaf5cc5
AK		 4657static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4658{
4659 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4660}
4661
717746e3 4662int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4663{
16f8a6f9 4664 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4665}
4666
717746e3 4667int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4668{
338dbc97 4669
717746e3 4670 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4671}
4672
52a46617 4673static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4674{
52a46617 4675 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4676}
4677
717746e3 4678static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4679{
717746e3 4680 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4681 unsigned long value;
4682
4683 switch (cr) {
4684 case 0:
4685 value = kvm_read_cr0(vcpu);
4686 break;
4687 case 2:
4688 value = vcpu->arch.cr2;
4689 break;
4690 case 3:
9f8fe504 4691 value = kvm_read_cr3(vcpu);
52a46617
GN		 4692 break;
4693 case 4:
4694 value = kvm_read_cr4(vcpu);
4695 break;
4696 case 8:
4697 value = kvm_get_cr8(vcpu);
4698 break;
4699 default:
a737f256 4700 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4701 return 0;
4702 }
4703
4704 return value;
4705}
4706
717746e3 4707static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4708{
717746e3 4709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4710 int res = 0;
4711
52a46617
GN		 4712 switch (cr) {
4713 case 0:
49a9b07e 4714 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4715 break;
4716 case 2:
4717 vcpu->arch.cr2 = val;
4718 break;
4719 case 3:
2390218b 4720 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4721 break;
4722 case 4:
a83b29c6 4723 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4724 break;
4725 case 8:
eea1cff9 4726 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4727 break;
4728 default:
a737f256 4729 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4730 res = -1;
52a46617 4731 }
0f12244f
GN		 4732
4733 return res;
52a46617
GN		 4734}
4735
717746e3 4736static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4737{
717746e3 4738 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4739}
4740
4bff1e86 4741static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4742{
4bff1e86 4743 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4744}
4745
4bff1e86 4746static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4747{
4bff1e86 4748 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4749}
4750
1ac9d0cf
AK		 4751static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4752{
4753 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4754}
4755
4756static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4757{
4758 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4759}
4760
4bff1e86
AK		 4761static unsigned long emulator_get_cached_segment_base(
4762 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4763{
4bff1e86 4764 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4765}
4766
1aa36616
AK		 4767static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4768 struct desc_struct *desc, u32 *base3,
4769 int seg)
2dafc6c2
GN		 4770{
4771 struct kvm_segment var;
4772
4bff1e86 4773 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4774 *selector = var.selector;
2dafc6c2 4775
378a8b09
GN		 4776 if (var.unusable) {
4777 memset(desc, 0, sizeof(*desc));
2dafc6c2 4778 return false;
378a8b09 4779 }
2dafc6c2
GN		 4780
4781 if (var.g)
4782 var.limit >>= 12;
4783 set_desc_limit(desc, var.limit);
4784 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4785#ifdef CONFIG_X86_64
4786 if (base3)
4787 *base3 = var.base >> 32;
4788#endif
2dafc6c2
GN		 4789 desc->type = var.type;
4790 desc->s = var.s;
4791 desc->dpl = var.dpl;
4792 desc->p = var.present;
4793 desc->avl = var.avl;
4794 desc->l = var.l;
4795 desc->d = var.db;
4796 desc->g = var.g;
4797
4798 return true;
4799}
4800
1aa36616
AK		 4801static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4802 struct desc_struct *desc, u32 base3,
4803 int seg)
2dafc6c2 4804{
4bff1e86 4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4806 struct kvm_segment var;
4807
1aa36616 4808 var.selector = selector;
2dafc6c2 4809 var.base = get_desc_base(desc);
5601d05b
GN		 4810#ifdef CONFIG_X86_64
4811 var.base |= ((u64)base3) << 32;
4812#endif
2dafc6c2
GN		 4813 var.limit = get_desc_limit(desc);
4814 if (desc->g)
4815 var.limit = (var.limit << 12) | 0xfff;
4816 var.type = desc->type;
2dafc6c2
GN		 4817 var.dpl = desc->dpl;
4818 var.db = desc->d;
4819 var.s = desc->s;
4820 var.l = desc->l;
4821 var.g = desc->g;
4822 var.avl = desc->avl;
4823 var.present = desc->p;
4824 var.unusable = !var.present;
4825 var.padding = 0;
4826
4827 kvm_set_segment(vcpu, &var, seg);
4828 return;
4829}
4830
717746e3
AK		 4831static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4832 u32 msr_index, u64 *pdata)
4833{
4834 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4835}
4836
4837static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4838 u32 msr_index, u64 data)
4839{
8fe8ab46
WA		 4840 struct msr_data msr;
4841
4842 msr.data = data;
4843 msr.index = msr_index;
4844 msr.host_initiated = false;
4845 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4846}
4847
67f4d428
NA		 4848static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4849 u32 pmc)
4850{
4851 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4852}
4853
222d21aa
AK		 4854static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4855 u32 pmc, u64 *pdata)
4856{
4857 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4858}
4859
6c3287f7
AK		 4860static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4861{
4862 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4863}
4864
5037f6f3
AK		 4865static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4866{
4867 preempt_disable();
5197b808 4868 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4869 /*
4870 * CR0.TS may reference the host fpu state, not the guest fpu state,
4871 * so it may be clear at this point.
4872 */
4873 clts();
4874}
4875
4876static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4877{
4878 preempt_enable();
4879}
4880
2953538e 4881static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4882 struct x86_instruction_info *info,
c4f035c6
AK		 4883 enum x86_intercept_stage stage)
4884{
2953538e 4885 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4886}
4887
0017f93a 4888static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4889 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4890{
0017f93a 4891 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4892}
4893
dd856efa
AK		 4894static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4895{
4896 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4897}
4898
4899static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4900{
4901 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4902}
4903
0225fb50 4904static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4905 .read_gpr = emulator_read_gpr,
4906 .write_gpr = emulator_write_gpr,
1871c602 4907 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4908 .write_std = kvm_write_guest_virt_system,
1871c602 4909 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4910 .read_emulated = emulator_read_emulated,
4911 .write_emulated = emulator_write_emulated,
4912 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4913 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4914 .pio_in_emulated = emulator_pio_in_emulated,
4915 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4916 .get_segment = emulator_get_segment,
4917 .set_segment = emulator_set_segment,
5951c442 4918 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4919 .get_gdt = emulator_get_gdt,
160ce1f1 4920 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4921 .set_gdt = emulator_set_gdt,
4922 .set_idt = emulator_set_idt,
52a46617
GN		 4923 .get_cr = emulator_get_cr,
4924 .set_cr = emulator_set_cr,
9c537244 4925 .cpl = emulator_get_cpl,
35aa5375
GN		 4926 .get_dr = emulator_get_dr,
4927 .set_dr = emulator_set_dr,
717746e3
AK		 4928 .set_msr = emulator_set_msr,
4929 .get_msr = emulator_get_msr,
67f4d428 4930 .check_pmc = emulator_check_pmc,
222d21aa 4931 .read_pmc = emulator_read_pmc,
6c3287f7 4932 .halt = emulator_halt,
bcaf5cc5 4933 .wbinvd = emulator_wbinvd,
d6aa1000 4934 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4935 .get_fpu = emulator_get_fpu,
4936 .put_fpu = emulator_put_fpu,
c4f035c6 4937 .intercept = emulator_intercept,
bdb42f5a 4938 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4939};
4940
95cb2295
GN		 4941static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4942{
37ccdcbe 4943 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4944 /*
4945 * an sti; sti; sequence only disable interrupts for the first
4946 * instruction. So, if the last instruction, be it emulated or
4947 * not, left the system with the INT_STI flag enabled, it
4948 * means that the last instruction is an sti. We should not
4949 * leave the flag on in this case. The same goes for mov ss
4950 */
37ccdcbe
PB		 4951 if (int_shadow & mask)
4952 mask = 0;
6addfc42 4953 if (unlikely(int_shadow || mask)) {
95cb2295 4954 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4955 if (!mask)
4956 kvm_make_request(KVM_REQ_EVENT, vcpu);
4957 }
95cb2295
GN		 4958}
4959
ef54bcfe 4960static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4961{
4962 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4963 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4964 return kvm_propagate_fault(vcpu, &ctxt->exception);
4965
4966 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4967 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4968 ctxt->exception.error_code);
54b8486f 4969 else
da9cb575 4970 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4971 return false;
54b8486f
GN		 4972}
4973
8ec4722d
MG		 4974static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4975{
adf52235 4976 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4977 int cs_db, cs_l;
4978
8ec4722d
MG		 4979 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4980
adf52235
TY		 4981 ctxt->eflags = kvm_get_rflags(vcpu);
4982 ctxt->eip = kvm_rip_read(vcpu);
4983 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4984 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4985 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4986 cs_db ? X86EMUL_MODE_PROT32 :
4987 X86EMUL_MODE_PROT16;
4988 ctxt->guest_mode = is_guest_mode(vcpu);
4989
dd856efa 4990 init_decode_cache(ctxt);
7ae441ea 4991 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4992}
4993
71f9833b 4994int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4995{
9d74191a 4996 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4997 int ret;
4998
4999 init_emulate_ctxt(vcpu);
5000
9dac77fa
AK		 5001 ctxt->op_bytes = 2;
5002 ctxt->ad_bytes = 2;
5003 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5004 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5005
5006 if (ret != X86EMUL_CONTINUE)
5007 return EMULATE_FAIL;
5008
9dac77fa 5009 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5010 kvm_rip_write(vcpu, ctxt->eip);
5011 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5012
5013 if (irq == NMI_VECTOR)
7460fb4a 5014 vcpu->arch.nmi_pending = 0;
63995653
MG		 5015 else
5016 vcpu->arch.interrupt.pending = false;
5017
5018 return EMULATE_DONE;
5019}
5020EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5021
6d77dbfc
GN		 5022static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5023{
fc3a9157
JR		 5024 int r = EMULATE_DONE;
5025
6d77dbfc
GN		 5026 ++vcpu->stat.insn_emulation_fail;
5027 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5028 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5029 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5030 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5031 vcpu->run->internal.ndata = 0;
5032 r = EMULATE_FAIL;
5033 }
6d77dbfc 5034 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5035
5036 return r;
6d77dbfc
GN		 5037}
5038
93c05d3e 5039static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5040 bool write_fault_to_shadow_pgtable,
5041 int emulation_type)
a6f177ef 5042{
95b3cf69 5043 gpa_t gpa = cr2;
8e3d9d06 5044 pfn_t pfn;
a6f177ef 5045
991eebf9
GN		 5046 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5047 return false;
5048
95b3cf69
XG		 5049 if (!vcpu->arch.mmu.direct_map) {
5050 /*
5051 * Write permission should be allowed since only
5052 * write access need to be emulated.
5053 */
5054 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5055
95b3cf69
XG		 5056 /*
5057 * If the mapping is invalid in guest, let cpu retry
5058 * it to generate fault.
5059 */
5060 if (gpa == UNMAPPED_GVA)
5061 return true;
5062 }
a6f177ef 5063
8e3d9d06
XG		 5064 /*
5065 * Do not retry the unhandleable instruction if it faults on the
5066 * readonly host memory, otherwise it will goto a infinite loop:
5067 * retry instruction -> write #PF -> emulation fail -> retry
5068 * instruction -> ...
5069 */
5070 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5071
5072 /*
5073 * If the instruction failed on the error pfn, it can not be fixed,
5074 * report the error to userspace.
5075 */
5076 if (is_error_noslot_pfn(pfn))
5077 return false;
5078
5079 kvm_release_pfn_clean(pfn);
5080
5081 /* The instructions are well-emulated on direct mmu. */
5082 if (vcpu->arch.mmu.direct_map) {
5083 unsigned int indirect_shadow_pages;
5084
5085 spin_lock(&vcpu->kvm->mmu_lock);
5086 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5087 spin_unlock(&vcpu->kvm->mmu_lock);
5088
5089 if (indirect_shadow_pages)
5090 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5091
a6f177ef 5092 return true;
8e3d9d06 5093 }
a6f177ef 5094
95b3cf69
XG		 5095 /*
5096 * if emulation was due to access to shadowed page table
5097 * and it failed try to unshadow page and re-enter the
5098 * guest to let CPU execute the instruction.
5099 */
5100 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5101
5102 /*
5103 * If the access faults on its page table, it can not
5104 * be fixed by unprotecting shadow page and it should
5105 * be reported to userspace.
5106 */
5107 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5108}
5109
1cb3f3ae
XG		 5110static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5111 unsigned long cr2, int emulation_type)
5112{
5113 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5114 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5115
5116 last_retry_eip = vcpu->arch.last_retry_eip;
5117 last_retry_addr = vcpu->arch.last_retry_addr;
5118
5119 /*
5120 * If the emulation is caused by #PF and it is non-page_table
5121 * writing instruction, it means the VM-EXIT is caused by shadow
5122 * page protected, we can zap the shadow page and retry this
5123 * instruction directly.
5124 *
5125 * Note: if the guest uses a non-page-table modifying instruction
5126 * on the PDE that points to the instruction, then we will unmap
5127 * the instruction and go to an infinite loop. So, we cache the
5128 * last retried eip and the last fault address, if we meet the eip
5129 * and the address again, we can break out of the potential infinite
5130 * loop.
5131 */
5132 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5133
5134 if (!(emulation_type & EMULTYPE_RETRY))
5135 return false;
5136
5137 if (x86_page_table_writing_insn(ctxt))
5138 return false;
5139
5140 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5141 return false;
5142
5143 vcpu->arch.last_retry_eip = ctxt->eip;
5144 vcpu->arch.last_retry_addr = cr2;
5145
5146 if (!vcpu->arch.mmu.direct_map)
5147 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5148
22368028 5149 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5150
5151 return true;
5152}
5153
716d51ab
GN		 5154static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5155static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5156
4a1e10d5
PB		 5157static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5158 unsigned long *db)
5159{
5160 u32 dr6 = 0;
5161 int i;
5162 u32 enable, rwlen;
5163
5164 enable = dr7;
5165 rwlen = dr7 >> 16;
5166 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5167 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5168 dr6 |= (1 << i);
5169 return dr6;
5170}
5171
6addfc42 5172static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5173{
5174 struct kvm_run *kvm_run = vcpu->run;
5175
5176 /*
6addfc42
PB		 5177 * rflags is the old, "raw" value of the flags. The new value has
5178 * not been saved yet.
663f4c61
PB		 5179 *
5180 * This is correct even for TF set by the guest, because "the
5181 * processor will not generate this exception after the instruction
5182 * that sets the TF flag".
5183 */
663f4c61
PB		 5184 if (unlikely(rflags & X86_EFLAGS_TF)) {
5185 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5186 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5187 DR6_RTM;
663f4c61
PB		 5188 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5189 kvm_run->debug.arch.exception = DB_VECTOR;
5190 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5191 *r = EMULATE_USER_EXIT;
5192 } else {
5193 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5194 /*
5195 * "Certain debug exceptions may clear bit 0-3. The
5196 * remaining contents of the DR6 register are never
5197 * cleared by the processor".
5198 */
5199 vcpu->arch.dr6 &= ~15;
6f43ed01 5200 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5201 kvm_queue_exception(vcpu, DB_VECTOR);
5202 }
5203 }
5204}
5205
4a1e10d5
PB		 5206static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5207{
5208 struct kvm_run *kvm_run = vcpu->run;
5209 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5210 u32 dr6 = 0;
5211
5212 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5213 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5214 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5215 vcpu->arch.guest_debug_dr7,
5216 vcpu->arch.eff_db);
5217
5218 if (dr6 != 0) {
6f43ed01 5219 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5220 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5221 get_segment_base(vcpu, VCPU_SREG_CS);
5222
5223 kvm_run->debug.arch.exception = DB_VECTOR;
5224 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5225 *r = EMULATE_USER_EXIT;
5226 return true;
5227 }
5228 }
5229
4161a569
NA		 5230 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5231 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5232 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5233 vcpu->arch.dr7,
5234 vcpu->arch.db);
5235
5236 if (dr6 != 0) {
5237 vcpu->arch.dr6 &= ~15;
6f43ed01 5238 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5239 kvm_queue_exception(vcpu, DB_VECTOR);
5240 *r = EMULATE_DONE;
5241 return true;
5242 }
5243 }
5244
5245 return false;
5246}
5247
51d8b661
AP		 5248int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5249 unsigned long cr2,
dc25e89e
AP		 5250 int emulation_type,
5251 void *insn,
5252 int insn_len)
bbd9b64e 5253{
95cb2295 5254 int r;
9d74191a 5255 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5256 bool writeback = true;
93c05d3e 5257 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5258
93c05d3e
XG		 5259 /*
5260 * Clear write_fault_to_shadow_pgtable here to ensure it is
5261 * never reused.
5262 */
5263 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5264 kvm_clear_exception_queue(vcpu);
8d7d8102 5265
571008da 5266 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5267 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5268
5269 /*
5270 * We will reenter on the same instruction since
5271 * we do not set complete_userspace_io. This does not
5272 * handle watchpoints yet, those would be handled in
5273 * the emulate_ops.
5274 */
5275 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5276 return r;
5277
9d74191a
TY		 5278 ctxt->interruptibility = 0;
5279 ctxt->have_exception = false;
e0ad0b47 5280 ctxt->exception.vector = -1;
9d74191a 5281 ctxt->perm_ok = false;
bbd9b64e 5282
b51e974f 5283 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5284
9d74191a 5285 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5286
e46479f8 5287 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5288 ++vcpu->stat.insn_emulation;
1d2887e2 5289 if (r != EMULATION_OK) {
4005996e
AK		 5290 if (emulation_type & EMULTYPE_TRAP_UD)
5291 return EMULATE_FAIL;
991eebf9
GN		 5292 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5293 emulation_type))
bbd9b64e 5294 return EMULATE_DONE;
6d77dbfc
GN		 5295 if (emulation_type & EMULTYPE_SKIP)
5296 return EMULATE_FAIL;
5297 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5298 }
5299 }
5300
ba8afb6b 5301 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5302 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5303 if (ctxt->eflags & X86_EFLAGS_RF)
5304 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5305 return EMULATE_DONE;
5306 }
5307
1cb3f3ae
XG		 5308 if (retry_instruction(ctxt, cr2, emulation_type))
5309 return EMULATE_DONE;
5310
7ae441ea 5311 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5312 changes registers values during IO operation */
7ae441ea
GN		 5313 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5314 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5315 emulator_invalidate_register_cache(ctxt);
7ae441ea 5316 }
4d2179e1 5317
5cd21917 5318restart:
9d74191a 5319 r = x86_emulate_insn(ctxt);
bbd9b64e 5320
775fde86
JR		 5321 if (r == EMULATION_INTERCEPTED)
5322 return EMULATE_DONE;
5323
d2ddd1c4 5324 if (r == EMULATION_FAILED) {
991eebf9
GN		 5325 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5326 emulation_type))
c3cd7ffa
GN		 5327 return EMULATE_DONE;
5328
6d77dbfc 5329 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5330 }
5331
9d74191a 5332 if (ctxt->have_exception) {
d2ddd1c4 5333 r = EMULATE_DONE;
ef54bcfe
PB		 5334 if (inject_emulated_exception(vcpu))
5335 return r;
d2ddd1c4 5336 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5337 if (!vcpu->arch.pio.in) {
5338 /* FIXME: return into emulator if single-stepping. */
3457e419 5339 vcpu->arch.pio.count = 0;
0912c977 5340 } else {
7ae441ea 5341 writeback = false;
716d51ab
GN		 5342 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5343 }
ac0a48c3 5344 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5345 } else if (vcpu->mmio_needed) {
5346 if (!vcpu->mmio_is_write)
5347 writeback = false;
ac0a48c3 5348 r = EMULATE_USER_EXIT;
716d51ab 5349 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5350 } else if (r == EMULATION_RESTART)
5cd21917 5351 goto restart;
d2ddd1c4
GN		 5352 else
5353 r = EMULATE_DONE;
f850e2e6 5354
7ae441ea 5355 if (writeback) {
6addfc42 5356 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5357 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5358 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5359 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5360 if (r == EMULATE_DONE)
6addfc42
PB		 5361 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5362 __kvm_set_rflags(vcpu, ctxt->eflags);
5363
5364 /*
5365 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5366 * do nothing, and it will be requested again as soon as
5367 * the shadow expires. But we still need to check here,
5368 * because POPF has no interrupt shadow.
5369 */
5370 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5371 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5372 } else
5373 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5374
5375 return r;
de7d789a 5376}
51d8b661 5377EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5378
cf8f70bf 5379int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5380{
cf8f70bf 5381 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5382 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5383 size, port, &val, 1);
cf8f70bf 5384 /* do not return to emulator after return from userspace */
7972995b 5385 vcpu->arch.pio.count = 0;
de7d789a
CO		 5386 return ret;
5387}
cf8f70bf 5388EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5389
8cfdc000
ZA		 5390static void tsc_bad(void *info)
5391{
0a3aee0d 5392 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5393}
5394
5395static void tsc_khz_changed(void *data)
c8076604 5396{
8cfdc000
ZA		 5397 struct cpufreq_freqs *freq = data;
5398 unsigned long khz = 0;
5399
5400 if (data)
5401 khz = freq->new;
5402 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5403 khz = cpufreq_quick_get(raw_smp_processor_id());
5404 if (!khz)
5405 khz = tsc_khz;
0a3aee0d 5406 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5407}
5408
c8076604
GH		 5409static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5410 void *data)
5411{
5412 struct cpufreq_freqs *freq = data;
5413 struct kvm *kvm;
5414 struct kvm_vcpu *vcpu;
5415 int i, send_ipi = 0;
5416
8cfdc000
ZA		 5417 /*
5418 * We allow guests to temporarily run on slowing clocks,
5419 * provided we notify them after, or to run on accelerating
5420 * clocks, provided we notify them before. Thus time never
5421 * goes backwards.
5422 *
5423 * However, we have a problem. We can't atomically update
5424 * the frequency of a given CPU from this function; it is
5425 * merely a notifier, which can be called from any CPU.
5426 * Changing the TSC frequency at arbitrary points in time
5427 * requires a recomputation of local variables related to
5428 * the TSC for each VCPU. We must flag these local variables
5429 * to be updated and be sure the update takes place with the
5430 * new frequency before any guests proceed.
5431 *
5432 * Unfortunately, the combination of hotplug CPU and frequency
5433 * change creates an intractable locking scenario; the order
5434 * of when these callouts happen is undefined with respect to
5435 * CPU hotplug, and they can race with each other. As such,
5436 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5437 * undefined; you can actually have a CPU frequency change take
5438 * place in between the computation of X and the setting of the
5439 * variable. To protect against this problem, all updates of
5440 * the per_cpu tsc_khz variable are done in an interrupt
5441 * protected IPI, and all callers wishing to update the value
5442 * must wait for a synchronous IPI to complete (which is trivial
5443 * if the caller is on the CPU already). This establishes the
5444 * necessary total order on variable updates.
5445 *
5446 * Note that because a guest time update may take place
5447 * anytime after the setting of the VCPU's request bit, the
5448 * correct TSC value must be set before the request. However,
5449 * to ensure the update actually makes it to any guest which
5450 * starts running in hardware virtualization between the set
5451 * and the acquisition of the spinlock, we must also ping the
5452 * CPU after setting the request bit.
5453 *
5454 */
5455
c8076604
GH		 5456 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5457 return 0;
5458 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5459 return 0;
8cfdc000
ZA		 5460
5461 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5462
2f303b74 5463 spin_lock(&kvm_lock);
c8076604 5464 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5465 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5466 if (vcpu->cpu != freq->cpu)
5467 continue;
c285545f 5468 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5469 if (vcpu->cpu != smp_processor_id())
8cfdc000 5470 send_ipi = 1;
c8076604
GH		 5471 }
5472 }
2f303b74 5473 spin_unlock(&kvm_lock);
c8076604
GH		 5474
5475 if (freq->old < freq->new && send_ipi) {
5476 /*
5477 * We upscale the frequency. Must make the guest
5478 * doesn't see old kvmclock values while running with
5479 * the new frequency, otherwise we risk the guest sees
5480 * time go backwards.
5481 *
5482 * In case we update the frequency for another cpu
5483 * (which might be in guest context) send an interrupt
5484 * to kick the cpu out of guest context. Next time
5485 * guest context is entered kvmclock will be updated,
5486 * so the guest will not see stale values.
5487 */
8cfdc000 5488 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5489 }
5490 return 0;
5491}
5492
5493static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5494 .notifier_call = kvmclock_cpufreq_notifier
5495};
5496
5497static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5498 unsigned long action, void *hcpu)
5499{
5500 unsigned int cpu = (unsigned long)hcpu;
5501
5502 switch (action) {
5503 case CPU_ONLINE:
5504 case CPU_DOWN_FAILED:
5505 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5506 break;
5507 case CPU_DOWN_PREPARE:
5508 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5509 break;
5510 }
5511 return NOTIFY_OK;
5512}
5513
5514static struct notifier_block kvmclock_cpu_notifier_block = {
5515 .notifier_call = kvmclock_cpu_notifier,
5516 .priority = -INT_MAX
c8076604
GH		 5517};
5518
b820cc0c
ZA		 5519static void kvm_timer_init(void)
5520{
5521 int cpu;
5522
c285545f 5523 max_tsc_khz = tsc_khz;
460dd42e
SB		 5524
5525 cpu_notifier_register_begin();
b820cc0c 5526 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5527#ifdef CONFIG_CPU_FREQ
5528 struct cpufreq_policy policy;
5529 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5530 cpu = get_cpu();
5531 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5532 if (policy.cpuinfo.max_freq)
5533 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5534 put_cpu();
c285545f 5535#endif
b820cc0c
ZA		 5536 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5537 CPUFREQ_TRANSITION_NOTIFIER);
5538 }
c285545f 5539 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5540 for_each_online_cpu(cpu)
5541 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5542
5543 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5544 cpu_notifier_register_done();
5545
b820cc0c
ZA		 5546}
5547
ff9d07a0
ZY		 5548static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5549
f5132b01 5550int kvm_is_in_guest(void)
ff9d07a0 5551{
086c9855 5552 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5553}
5554
5555static int kvm_is_user_mode(void)
5556{
5557 int user_mode = 3;
dcf46b94 5558
086c9855
AS		 5559 if (__this_cpu_read(current_vcpu))
5560 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5561
ff9d07a0
ZY		 5562 return user_mode != 0;
5563}
5564
5565static unsigned long kvm_get_guest_ip(void)
5566{
5567 unsigned long ip = 0;
dcf46b94 5568
086c9855
AS		 5569 if (__this_cpu_read(current_vcpu))
5570 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5571
ff9d07a0
ZY		 5572 return ip;
5573}
5574
5575static struct perf_guest_info_callbacks kvm_guest_cbs = {
5576 .is_in_guest = kvm_is_in_guest,
5577 .is_user_mode = kvm_is_user_mode,
5578 .get_guest_ip = kvm_get_guest_ip,
5579};
5580
5581void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5582{
086c9855 5583 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5584}
5585EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5586
5587void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5588{
086c9855 5589 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5590}
5591EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5592
ce88decf
XG		 5593static void kvm_set_mmio_spte_mask(void)
5594{
5595 u64 mask;
5596 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5597
5598 /*
5599 * Set the reserved bits and the present bit of an paging-structure
5600 * entry to generate page fault with PFER.RSV = 1.
5601 */
885032b9 5602 /* Mask the reserved physical address bits. */
d1431483 5603 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5604
5605 /* Bit 62 is always reserved for 32bit host. */
5606 mask |= 0x3ull << 62;
5607
5608 /* Set the present bit. */
ce88decf
XG		 5609 mask |= 1ull;
5610
5611#ifdef CONFIG_X86_64
5612 /*
5613 * If reserved bit is not supported, clear the present bit to disable
5614 * mmio page fault.
5615 */
5616 if (maxphyaddr == 52)
5617 mask &= ~1ull;
5618#endif
5619
5620 kvm_mmu_set_mmio_spte_mask(mask);
5621}
5622
16e8d74d
MT		 5623#ifdef CONFIG_X86_64
5624static void pvclock_gtod_update_fn(struct work_struct *work)
5625{
d828199e
MT		 5626 struct kvm *kvm;
5627
5628 struct kvm_vcpu *vcpu;
5629 int i;
5630
2f303b74 5631 spin_lock(&kvm_lock);
d828199e
MT		 5632 list_for_each_entry(kvm, &vm_list, vm_list)
5633 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5634 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5635 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5636 spin_unlock(&kvm_lock);
16e8d74d
MT		 5637}
5638
5639static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5640
5641/*
5642 * Notification about pvclock gtod data update.
5643 */
5644static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5645 void *priv)
5646{
5647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5648 struct timekeeper *tk = priv;
5649
5650 update_pvclock_gtod(tk);
5651
5652 /* disable master clock if host does not trust, or does not
5653 * use, TSC clocksource
5654 */
5655 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5656 atomic_read(&kvm_guest_has_master_clock) != 0)
5657 queue_work(system_long_wq, &pvclock_gtod_work);
5658
5659 return 0;
5660}
5661
5662static struct notifier_block pvclock_gtod_notifier = {
5663 .notifier_call = pvclock_gtod_notify,
5664};
5665#endif
5666
f8c16bba 5667int kvm_arch_init(void *opaque)
043405e1 5668{
b820cc0c 5669 int r;
6b61edf7 5670 struct kvm_x86_ops *ops = opaque;
f8c16bba 5671
f8c16bba
ZX		 5672 if (kvm_x86_ops) {
5673 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5674 r = -EEXIST;
5675 goto out;
f8c16bba
ZX		 5676 }
5677
5678 if (!ops->cpu_has_kvm_support()) {
5679 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5680 r = -EOPNOTSUPP;
5681 goto out;
f8c16bba
ZX		 5682 }
5683 if (ops->disabled_by_bios()) {
5684 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5685 r = -EOPNOTSUPP;
5686 goto out;
f8c16bba
ZX		 5687 }
5688
013f6a5d
MT		 5689 r = -ENOMEM;
5690 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5691 if (!shared_msrs) {
5692 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5693 goto out;
5694 }
5695
97db56ce
AK		 5696 r = kvm_mmu_module_init();
5697 if (r)
013f6a5d 5698 goto out_free_percpu;
97db56ce 5699
ce88decf 5700 kvm_set_mmio_spte_mask();
97db56ce 5701
f8c16bba 5702 kvm_x86_ops = ops;
920c8377
PB		 5703 kvm_init_msr_list();
5704
7b52345e 5705 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5706 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5707
b820cc0c 5708 kvm_timer_init();
c8076604 5709
ff9d07a0
ZY		 5710 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5711
2acf923e
DC		 5712 if (cpu_has_xsave)
5713 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5714
c5cc421b 5715 kvm_lapic_init();
16e8d74d
MT		 5716#ifdef CONFIG_X86_64
5717 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5718#endif
5719
f8c16bba 5720 return 0;
56c6d28a 5721
013f6a5d
MT		 5722out_free_percpu:
5723 free_percpu(shared_msrs);
56c6d28a 5724out:
56c6d28a 5725 return r;
043405e1 5726}
8776e519 5727
f8c16bba
ZX		 5728void kvm_arch_exit(void)
5729{
ff9d07a0
ZY		 5730 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5731
888d256e
JK		 5732 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5733 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5734 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5735 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5736#ifdef CONFIG_X86_64
5737 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5738#endif
f8c16bba 5739 kvm_x86_ops = NULL;
56c6d28a 5740 kvm_mmu_module_exit();
013f6a5d 5741 free_percpu(shared_msrs);
56c6d28a 5742}
f8c16bba 5743
8776e519
HB		 5744int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5745{
5746 ++vcpu->stat.halt_exits;
5747 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5748 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5749 return 1;
5750 } else {
5751 vcpu->run->exit_reason = KVM_EXIT_HLT;
5752 return 0;
5753 }
5754}
5755EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5756
55cd8e5a
GN		 5757int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5758{
5759 u64 param, ingpa, outgpa, ret;
5760 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5761 bool fast, longmode;
55cd8e5a
GN		 5762
5763 /*
5764 * hypercall generates UD from non zero cpl and real mode
5765 * per HYPER-V spec
5766 */
3eeb3288 5767 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5768 kvm_queue_exception(vcpu, UD_VECTOR);
5769 return 0;
5770 }
5771
a449c7aa 5772 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5773
5774 if (!longmode) {
ccd46936
GN		 5775 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5776 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5777 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5778 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5779 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5780 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5781 }
5782#ifdef CONFIG_X86_64
5783 else {
5784 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5785 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5786 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5787 }
5788#endif
5789
5790 code = param & 0xffff;
5791 fast = (param >> 16) & 0x1;
5792 rep_cnt = (param >> 32) & 0xfff;
5793 rep_idx = (param >> 48) & 0xfff;
5794
5795 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5796
c25bc163
GN		 5797 switch (code) {
5798 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5799 kvm_vcpu_on_spin(vcpu);
5800 break;
5801 default:
5802 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5803 break;
5804 }
55cd8e5a
GN		 5805
5806 ret = res | (((u64)rep_done & 0xfff) << 32);
5807 if (longmode) {
5808 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5809 } else {
5810 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5811 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5812 }
5813
5814 return 1;
5815}
5816
6aef266c
SV		 5817/*
5818 * kvm_pv_kick_cpu_op: Kick a vcpu.
5819 *
5820 * @apicid - apicid of vcpu to be kicked.
5821 */
5822static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5823{
24d2166b 5824 struct kvm_lapic_irq lapic_irq;
6aef266c 5825
24d2166b
R		 5826 lapic_irq.shorthand = 0;
5827 lapic_irq.dest_mode = 0;
5828 lapic_irq.dest_id = apicid;
6aef266c 5829
24d2166b
R		 5830 lapic_irq.delivery_mode = APIC_DM_REMRD;
5831 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5832}
5833
8776e519
HB		 5834int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5835{
5836 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5837 int op_64_bit, r = 1;
8776e519 5838
55cd8e5a
GN		 5839 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5840 return kvm_hv_hypercall(vcpu);
5841
5fdbf976
MT		 5842 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5843 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5844 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5845 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5846 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5847
229456fc 5848 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5849
a449c7aa
NA		 5850 op_64_bit = is_64_bit_mode(vcpu);
5851 if (!op_64_bit) {
8776e519
HB		 5852 nr &= 0xFFFFFFFF;
5853 a0 &= 0xFFFFFFFF;
5854 a1 &= 0xFFFFFFFF;
5855 a2 &= 0xFFFFFFFF;
5856 a3 &= 0xFFFFFFFF;
5857 }
5858
07708c4a
JK		 5859 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5860 ret = -KVM_EPERM;
5861 goto out;
5862 }
5863
8776e519 5864 switch (nr) {
b93463aa
AK		 5865 case KVM_HC_VAPIC_POLL_IRQ:
5866 ret = 0;
5867 break;
6aef266c
SV		 5868 case KVM_HC_KICK_CPU:
5869 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5870 ret = 0;
5871 break;
8776e519
HB		 5872 default:
5873 ret = -KVM_ENOSYS;
5874 break;
5875 }
07708c4a 5876out:
a449c7aa
NA		 5877 if (!op_64_bit)
5878 ret = (u32)ret;
5fdbf976 5879 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5880 ++vcpu->stat.hypercalls;
2f333bcb 5881 return r;
8776e519
HB		 5882}
5883EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5884
b6785def 5885static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5886{
d6aa1000 5887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5888 char instruction[3];
5fdbf976 5889 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5890
8776e519 5891 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5892
9d74191a 5893 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5894}
5895
b6c7a5dc
HB		 5896/*
5897 * Check if userspace requested an interrupt window, and that the
5898 * interrupt window is open.
5899 *
5900 * No need to exit to userspace if we already have an interrupt queued.
5901 */
851ba692 5902static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5903{
8061823a 5904 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5905 vcpu->run->request_interrupt_window &&
5df56646 5906 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5907}
5908
851ba692 5909static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5910{
851ba692
AK		 5911 struct kvm_run *kvm_run = vcpu->run;
5912
91586a3b 5913 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5914 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5915 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5916 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5917 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5918 else
b6c7a5dc 5919 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5920 kvm_arch_interrupt_allowed(vcpu) &&
5921 !kvm_cpu_has_interrupt(vcpu) &&
5922 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5923}
5924
95ba8273
GN		 5925static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5926{
5927 int max_irr, tpr;
5928
5929 if (!kvm_x86_ops->update_cr8_intercept)
5930 return;
5931
88c808fd
AK		 5932 if (!vcpu->arch.apic)
5933 return;
5934
8db3baa2
GN		 5935 if (!vcpu->arch.apic->vapic_addr)
5936 max_irr = kvm_lapic_find_highest_irr(vcpu);
5937 else
5938 max_irr = -1;
95ba8273
GN		 5939
5940 if (max_irr != -1)
5941 max_irr >>= 4;
5942
5943 tpr = kvm_lapic_get_cr8(vcpu);
5944
5945 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5946}
5947
b6b8a145 5948static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5949{
b6b8a145
JK		 5950 int r;
5951
95ba8273 5952 /* try to reinject previous events if any */
b59bb7bd 5953 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5954 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5955 vcpu->arch.exception.has_error_code,
5956 vcpu->arch.exception.error_code);
d6e8c854
NA		 5957
5958 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5959 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5960 X86_EFLAGS_RF);
5961
6bdf0662
NA		 5962 if (vcpu->arch.exception.nr == DB_VECTOR &&
5963 (vcpu->arch.dr7 & DR7_GD)) {
5964 vcpu->arch.dr7 &= ~DR7_GD;
5965 kvm_update_dr7(vcpu);
5966 }
5967
b59bb7bd
GN		 5968 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5969 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5970 vcpu->arch.exception.error_code,
5971 vcpu->arch.exception.reinject);
b6b8a145 5972 return 0;
b59bb7bd
GN		 5973 }
5974
95ba8273
GN		 5975 if (vcpu->arch.nmi_injected) {
5976 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5977 return 0;
95ba8273
GN		 5978 }
5979
5980 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5981 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5982 return 0;
5983 }
5984
5985 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5986 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5987 if (r != 0)
5988 return r;
95ba8273
GN		 5989 }
5990
5991 /* try to inject new event if pending */
5992 if (vcpu->arch.nmi_pending) {
5993 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5994 --vcpu->arch.nmi_pending;
95ba8273
GN		 5995 vcpu->arch.nmi_injected = true;
5996 kvm_x86_ops->set_nmi(vcpu);
5997 }
c7c9c56c 5998 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5999 /*
6000 * Because interrupts can be injected asynchronously, we are
6001 * calling check_nested_events again here to avoid a race condition.
6002 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6003 * proposal and current concerns. Perhaps we should be setting
6004 * KVM_REQ_EVENT only on certain events and not unconditionally?
6005 */
6006 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6007 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6008 if (r != 0)
6009 return r;
6010 }
95ba8273 6011 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6012 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6013 false);
6014 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6015 }
6016 }
b6b8a145 6017 return 0;
95ba8273
GN		 6018}
6019
7460fb4a
AK		 6020static void process_nmi(struct kvm_vcpu *vcpu)
6021{
6022 unsigned limit = 2;
6023
6024 /*
6025 * x86 is limited to one NMI running, and one NMI pending after it.
6026 * If an NMI is already in progress, limit further NMIs to just one.
6027 * Otherwise, allow two (and we'll inject the first one immediately).
6028 */
6029 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6030 limit = 1;
6031
6032 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6033 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6034 kvm_make_request(KVM_REQ_EVENT, vcpu);
6035}
6036
3d81bc7e 6037static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6038{
6039 u64 eoi_exit_bitmap[4];
cf9e65b7 6040 u32 tmr[8];
c7c9c56c 6041
3d81bc7e
YZ		 6042 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6043 return;
c7c9c56c
YZ		 6044
6045 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6046 memset(tmr, 0, 32);
c7c9c56c 6047
cf9e65b7 6048 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6049 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6050 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6051}
6052
a70656b6
RK		 6053static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6054{
6055 ++vcpu->stat.tlb_flush;
6056 kvm_x86_ops->tlb_flush(vcpu);
6057}
6058
4256f43f
TC		 6059void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6060{
c24ae0dc
TC		 6061 struct page *page = NULL;
6062
f439ed27
PB		 6063 if (!irqchip_in_kernel(vcpu->kvm))
6064 return;
6065
4256f43f
TC		 6066 if (!kvm_x86_ops->set_apic_access_page_addr)
6067 return;
6068
c24ae0dc
TC		 6069 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6070 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6071
6072 /*
6073 * Do not pin apic access page in memory, the MMU notifier
6074 * will call us again if it is migrated or swapped out.
6075 */
6076 put_page(page);
4256f43f
TC		 6077}
6078EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6079
fe71557a
TC		 6080void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6081 unsigned long address)
6082{
c24ae0dc
TC		 6083 /*
6084 * The physical address of apic access page is stored in the VMCS.
6085 * Update it when it becomes invalid.
6086 */
6087 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6088 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6089}
6090
9357d939
TY		 6091/*
6092 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6093 * exiting to the userspace. Otherwise, the value will be returned to the
6094 * userspace.
6095 */
851ba692 6096static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6097{
6098 int r;
6a8b1d13 6099 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6100 vcpu->run->request_interrupt_window;
730dca42 6101 bool req_immediate_exit = false;
b6c7a5dc 6102
3e007509 6103 if (vcpu->requests) {
a8eeb04a 6104 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6105 kvm_mmu_unload(vcpu);
a8eeb04a 6106 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6107 __kvm_migrate_timers(vcpu);
d828199e
MT		 6108 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6109 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6110 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6111 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6112 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6113 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6114 if (unlikely(r))
6115 goto out;
6116 }
a8eeb04a 6117 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6118 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6119 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6120 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6121 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6122 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6123 r = 0;
6124 goto out;
6125 }
a8eeb04a 6126 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6127 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6128 r = 0;
6129 goto out;
6130 }
a8eeb04a 6131 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6132 vcpu->fpu_active = 0;
6133 kvm_x86_ops->fpu_deactivate(vcpu);
6134 }
af585b92
GN		 6135 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6136 /* Page is swapped out. Do synthetic halt */
6137 vcpu->arch.apf.halted = true;
6138 r = 1;
6139 goto out;
6140 }
c9aaa895
GC		 6141 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6142 record_steal_time(vcpu);
7460fb4a
AK		 6143 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6144 process_nmi(vcpu);
f5132b01
GN		 6145 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6146 kvm_handle_pmu_event(vcpu);
6147 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6148 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6149 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6150 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6151 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6152 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6153 }
b93463aa 6154
b463a6f7 6155 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6156 kvm_apic_accept_events(vcpu);
6157 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6158 r = 1;
6159 goto out;
6160 }
6161
b6b8a145
JK		 6162 if (inject_pending_event(vcpu, req_int_win) != 0)
6163 req_immediate_exit = true;
b463a6f7 6164 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6165 else if (vcpu->arch.nmi_pending)
c9a7953f 6166 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6167 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6168 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6169
6170 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6171 /*
6172 * Update architecture specific hints for APIC
6173 * virtual interrupt delivery.
6174 */
6175 if (kvm_x86_ops->hwapic_irr_update)
6176 kvm_x86_ops->hwapic_irr_update(vcpu,
6177 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6178 update_cr8_intercept(vcpu);
6179 kvm_lapic_sync_to_vapic(vcpu);
6180 }
6181 }
6182
d8368af8
AK		 6183 r = kvm_mmu_reload(vcpu);
6184 if (unlikely(r)) {
d905c069 6185 goto cancel_injection;
d8368af8
AK		 6186 }
6187
b6c7a5dc
HB		 6188 preempt_disable();
6189
6190 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6191 if (vcpu->fpu_active)
6192 kvm_load_guest_fpu(vcpu);
2acf923e 6193 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6194
6b7e2d09
XG		 6195 vcpu->mode = IN_GUEST_MODE;
6196
01b71917
MT		 6197 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6198
6b7e2d09
XG		 6199 /* We should set ->mode before check ->requests,
6200 * see the comment in make_all_cpus_request.
6201 */
01b71917 6202 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6203
d94e1dc9 6204 local_irq_disable();
32f88400 6205
6b7e2d09 6206 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6207 || need_resched() || signal_pending(current)) {
6b7e2d09 6208 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6209 smp_wmb();
6c142801
AK		 6210 local_irq_enable();
6211 preempt_enable();
01b71917 6212 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6213 r = 1;
d905c069 6214 goto cancel_injection;
6c142801
AK		 6215 }
6216
d6185f20
NHE		 6217 if (req_immediate_exit)
6218 smp_send_reschedule(vcpu->cpu);
6219
b6c7a5dc
HB		 6220 kvm_guest_enter();
6221
42dbaa5a 6222 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6223 set_debugreg(0, 7);
6224 set_debugreg(vcpu->arch.eff_db[0], 0);
6225 set_debugreg(vcpu->arch.eff_db[1], 1);
6226 set_debugreg(vcpu->arch.eff_db[2], 2);
6227 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6228 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6229 }
b6c7a5dc 6230
229456fc 6231 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6232 kvm_x86_ops->run(vcpu);
b6c7a5dc 6233
c77fb5fe
PB		 6234 /*
6235 * Do this here before restoring debug registers on the host. And
6236 * since we do this before handling the vmexit, a DR access vmexit
6237 * can (a) read the correct value of the debug registers, (b) set
6238 * KVM_DEBUGREG_WONT_EXIT again.
6239 */
6240 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6241 int i;
6242
6243 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6244 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6245 for (i = 0; i < KVM_NR_DB_REGS; i++)
6246 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6247 }
6248
24f1e32c
FW		 6249 /*
6250 * If the guest has used debug registers, at least dr7
6251 * will be disabled while returning to the host.
6252 * If we don't have active breakpoints in the host, we don't
6253 * care about the messed up debug address registers. But if
6254 * we have some of them active, restore the old state.
6255 */
59d8eb53 6256 if (hw_breakpoint_active())
24f1e32c 6257 hw_breakpoint_restore();
42dbaa5a 6258
886b470c
MT		 6259 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6260 native_read_tsc());
1d5f066e 6261
6b7e2d09 6262 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6263 smp_wmb();
a547c6db
YZ		 6264
6265 /* Interrupt is enabled by handle_external_intr() */
6266 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6267
6268 ++vcpu->stat.exits;
6269
6270 /*
6271 * We must have an instruction between local_irq_enable() and
6272 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6273 * the interrupt shadow. The stat.exits increment will do nicely.
6274 * But we need to prevent reordering, hence this barrier():
6275 */
6276 barrier();
6277
6278 kvm_guest_exit();
6279
6280 preempt_enable();
6281
f656ce01 6282 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6283
b6c7a5dc
HB		 6284 /*
6285 * Profile KVM exit RIPs:
6286 */
6287 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6288 unsigned long rip = kvm_rip_read(vcpu);
6289 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6290 }
6291
cc578287
ZA		 6292 if (unlikely(vcpu->arch.tsc_always_catchup))
6293 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6294
5cfb1d5a
MT		 6295 if (vcpu->arch.apic_attention)
6296 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6297
851ba692 6298 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6299 return r;
6300
6301cancel_injection:
6302 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6303 if (unlikely(vcpu->arch.apic_attention))
6304 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6305out:
6306 return r;
6307}
b6c7a5dc 6308
09cec754 6309
851ba692 6310static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6311{
6312 int r;
f656ce01 6313 struct kvm *kvm = vcpu->kvm;
d7690175 6314
f656ce01 6315 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6316
6317 r = 1;
6318 while (r > 0) {
af585b92
GN		 6319 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6320 !vcpu->arch.apf.halted)
851ba692 6321 r = vcpu_enter_guest(vcpu);
d7690175 6322 else {
f656ce01 6323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6324 kvm_vcpu_block(vcpu);
f656ce01 6325 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6326 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6327 kvm_apic_accept_events(vcpu);
09cec754
GN		 6328 switch(vcpu->arch.mp_state) {
6329 case KVM_MP_STATE_HALTED:
6aef266c 6330 vcpu->arch.pv.pv_unhalted = false;
d7690175 6331 vcpu->arch.mp_state =
09cec754
GN		 6332 KVM_MP_STATE_RUNNABLE;
6333 case KVM_MP_STATE_RUNNABLE:
af585b92 6334 vcpu->arch.apf.halted = false;
09cec754 6335 break;
66450a21
JK		 6336 case KVM_MP_STATE_INIT_RECEIVED:
6337 break;
09cec754
GN		 6338 default:
6339 r = -EINTR;
6340 break;
6341 }
6342 }
d7690175
MT		 6343 }
6344
09cec754
GN		 6345 if (r <= 0)
6346 break;
6347
6348 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6349 if (kvm_cpu_has_pending_timer(vcpu))
6350 kvm_inject_pending_timer_irqs(vcpu);
6351
851ba692 6352 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6353 r = -EINTR;
851ba692 6354 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6355 ++vcpu->stat.request_irq_exits;
6356 }
af585b92
GN		 6357
6358 kvm_check_async_pf_completion(vcpu);
6359
09cec754
GN		 6360 if (signal_pending(current)) {
6361 r = -EINTR;
851ba692 6362 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6363 ++vcpu->stat.signal_exits;
6364 }
6365 if (need_resched()) {
f656ce01 6366 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6367 cond_resched();
f656ce01 6368 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6369 }
b6c7a5dc
HB		 6370 }
6371
f656ce01 6372 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6373
6374 return r;
6375}
6376
716d51ab
GN		 6377static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6378{
6379 int r;
6380 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6381 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6382 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6383 if (r != EMULATE_DONE)
6384 return 0;
6385 return 1;
6386}
6387
6388static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6389{
6390 BUG_ON(!vcpu->arch.pio.count);
6391
6392 return complete_emulated_io(vcpu);
6393}
6394
f78146b0
AK		 6395/*
6396 * Implements the following, as a state machine:
6397 *
6398 * read:
6399 * for each fragment
87da7e66
XG		 6400 * for each mmio piece in the fragment
6401 * write gpa, len
6402 * exit
6403 * copy data
f78146b0
AK		 6404 * execute insn
6405 *
6406 * write:
6407 * for each fragment
87da7e66
XG		 6408 * for each mmio piece in the fragment
6409 * write gpa, len
6410 * copy data
6411 * exit
f78146b0 6412 */
716d51ab 6413static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6414{
6415 struct kvm_run *run = vcpu->run;
f78146b0 6416 struct kvm_mmio_fragment *frag;
87da7e66 6417 unsigned len;
5287f194 6418
716d51ab 6419 BUG_ON(!vcpu->mmio_needed);
5287f194 6420
716d51ab 6421 /* Complete previous fragment */
87da7e66
XG		 6422 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6423 len = min(8u, frag->len);
716d51ab 6424 if (!vcpu->mmio_is_write)
87da7e66
XG		 6425 memcpy(frag->data, run->mmio.data, len);
6426
6427 if (frag->len <= 8) {
6428 /* Switch to the next fragment. */
6429 frag++;
6430 vcpu->mmio_cur_fragment++;
6431 } else {
6432 /* Go forward to the next mmio piece. */
6433 frag->data += len;
6434 frag->gpa += len;
6435 frag->len -= len;
6436 }
6437
a08d3b3b 6438 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6439 vcpu->mmio_needed = 0;
0912c977
PB		 6440
6441 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6442 if (vcpu->mmio_is_write)
716d51ab
GN		 6443 return 1;
6444 vcpu->mmio_read_completed = 1;
6445 return complete_emulated_io(vcpu);
6446 }
87da7e66 6447
716d51ab
GN		 6448 run->exit_reason = KVM_EXIT_MMIO;
6449 run->mmio.phys_addr = frag->gpa;
6450 if (vcpu->mmio_is_write)
87da7e66
XG		 6451 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6452 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6453 run->mmio.is_write = vcpu->mmio_is_write;
6454 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6455 return 0;
5287f194
AK		 6456}
6457
716d51ab 6458
b6c7a5dc
HB		 6459int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6460{
6461 int r;
6462 sigset_t sigsaved;
6463
e5c30142
AK		 6464 if (!tsk_used_math(current) && init_fpu(current))
6465 return -ENOMEM;
6466
ac9f6dc0
AK		 6467 if (vcpu->sigset_active)
6468 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6469
a4535290 6470 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6471 kvm_vcpu_block(vcpu);
66450a21 6472 kvm_apic_accept_events(vcpu);
d7690175 6473 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6474 r = -EAGAIN;
6475 goto out;
b6c7a5dc
HB		 6476 }
6477
b6c7a5dc 6478 /* re-sync apic's tpr */
eea1cff9
AP		 6479 if (!irqchip_in_kernel(vcpu->kvm)) {
6480 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6481 r = -EINVAL;
6482 goto out;
6483 }
6484 }
b6c7a5dc 6485
716d51ab
GN		 6486 if (unlikely(vcpu->arch.complete_userspace_io)) {
6487 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6488 vcpu->arch.complete_userspace_io = NULL;
6489 r = cui(vcpu);
6490 if (r <= 0)
6491 goto out;
6492 } else
6493 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6494
851ba692 6495 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6496
6497out:
f1d86e46 6498 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6499 if (vcpu->sigset_active)
6500 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6501
b6c7a5dc
HB		 6502 return r;
6503}
6504
6505int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6506{
7ae441ea
GN		 6507 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6508 /*
6509 * We are here if userspace calls get_regs() in the middle of
6510 * instruction emulation. Registers state needs to be copied
4a969980 6511 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6512 * that usually, but some bad designed PV devices (vmware
6513 * backdoor interface) need this to work
6514 */
dd856efa 6515 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6516 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6517 }
5fdbf976
MT		 6518 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6519 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6520 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6521 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6522 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6523 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6524 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6525 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6526#ifdef CONFIG_X86_64
5fdbf976
MT		 6527 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6528 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6529 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6530 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6531 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6532 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6533 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6534 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6535#endif
6536
5fdbf976 6537 regs->rip = kvm_rip_read(vcpu);
91586a3b 6538 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6539
b6c7a5dc
HB		 6540 return 0;
6541}
6542
6543int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6544{
7ae441ea
GN		 6545 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6546 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6547
5fdbf976
MT		 6548 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6549 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6550 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6551 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6552 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6553 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6554 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6555 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6556#ifdef CONFIG_X86_64
5fdbf976
MT		 6557 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6558 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6559 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6560 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6561 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6562 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6563 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6564 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6565#endif
6566
5fdbf976 6567 kvm_rip_write(vcpu, regs->rip);
91586a3b 6568 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6569
b4f14abd
JK		 6570 vcpu->arch.exception.pending = false;
6571
3842d135
AK		 6572 kvm_make_request(KVM_REQ_EVENT, vcpu);
6573
b6c7a5dc
HB		 6574 return 0;
6575}
6576
b6c7a5dc
HB		 6577void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6578{
6579 struct kvm_segment cs;
6580
3e6e0aab 6581 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6582 *db = cs.db;
6583 *l = cs.l;
6584}
6585EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6586
6587int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6588 struct kvm_sregs *sregs)
6589{
89a27f4d 6590 struct desc_ptr dt;
b6c7a5dc 6591
3e6e0aab
GT		 6592 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6593 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6594 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6595 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6596 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6597 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6598
3e6e0aab
GT		 6599 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6600 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6601
6602 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6603 sregs->idt.limit = dt.size;
6604 sregs->idt.base = dt.address;
b6c7a5dc 6605 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6606 sregs->gdt.limit = dt.size;
6607 sregs->gdt.base = dt.address;
b6c7a5dc 6608
4d4ec087 6609 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6610 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6611 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6612 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6613 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6614 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6615 sregs->apic_base = kvm_get_apic_base(vcpu);
6616
923c61bb 6617 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6618
36752c9b 6619 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6620 set_bit(vcpu->arch.interrupt.nr,
6621 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6622
b6c7a5dc
HB		 6623 return 0;
6624}
6625
62d9f0db
MT		 6626int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6627 struct kvm_mp_state *mp_state)
6628{
66450a21 6629 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6630 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6631 vcpu->arch.pv.pv_unhalted)
6632 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6633 else
6634 mp_state->mp_state = vcpu->arch.mp_state;
6635
62d9f0db
MT		 6636 return 0;
6637}
6638
6639int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6640 struct kvm_mp_state *mp_state)
6641{
66450a21
JK		 6642 if (!kvm_vcpu_has_lapic(vcpu) &&
6643 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6644 return -EINVAL;
6645
6646 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6647 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6648 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6649 } else
6650 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6651 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6652 return 0;
6653}
6654
7f3d35fd
KW		 6655int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6656 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6657{
9d74191a 6658 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6659 int ret;
e01c2426 6660
8ec4722d 6661 init_emulate_ctxt(vcpu);
c697518a 6662
7f3d35fd 6663 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6664 has_error_code, error_code);
c697518a 6665
c697518a 6666 if (ret)
19d04437 6667 return EMULATE_FAIL;
37817f29 6668
9d74191a
TY		 6669 kvm_rip_write(vcpu, ctxt->eip);
6670 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6671 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6672 return EMULATE_DONE;
37817f29
IE		 6673}
6674EXPORT_SYMBOL_GPL(kvm_task_switch);
6675
b6c7a5dc
HB		 6676int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6677 struct kvm_sregs *sregs)
6678{
58cb628d 6679 struct msr_data apic_base_msr;
b6c7a5dc 6680 int mmu_reset_needed = 0;
63f42e02 6681 int pending_vec, max_bits, idx;
89a27f4d 6682 struct desc_ptr dt;
b6c7a5dc 6683
6d1068b3
PM		 6684 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6685 return -EINVAL;
6686
89a27f4d
GN		 6687 dt.size = sregs->idt.limit;
6688 dt.address = sregs->idt.base;
b6c7a5dc 6689 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6690 dt.size = sregs->gdt.limit;
6691 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6692 kvm_x86_ops->set_gdt(vcpu, &dt);
6693
ad312c7c 6694 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6695 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6696 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6697 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6698
2d3ad1f4 6699 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6700
f6801dff 6701 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6702 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6703 apic_base_msr.data = sregs->apic_base;
6704 apic_base_msr.host_initiated = true;
6705 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6706
4d4ec087 6707 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6708 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6709 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6710
fc78f519 6711 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6712 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6713 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6714 kvm_update_cpuid(vcpu);
63f42e02
XG		 6715
6716 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6717 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6718 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6719 mmu_reset_needed = 1;
6720 }
63f42e02 6721 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6722
6723 if (mmu_reset_needed)
6724 kvm_mmu_reset_context(vcpu);
6725
a50abc3b 6726 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6727 pending_vec = find_first_bit(
6728 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6729 if (pending_vec < max_bits) {
66fd3f7f 6730 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6731 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6732 }
6733
3e6e0aab
GT		 6734 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6735 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6736 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6737 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6738 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6739 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6740
3e6e0aab
GT		 6741 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6742 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6743
5f0269f5
ME		 6744 update_cr8_intercept(vcpu);
6745
9c3e4aab 6746 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6747 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6748 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6749 !is_protmode(vcpu))
9c3e4aab
MT		 6750 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6751
3842d135
AK		 6752 kvm_make_request(KVM_REQ_EVENT, vcpu);
6753
b6c7a5dc
HB		 6754 return 0;
6755}
6756
d0bfb940
JK		 6757int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6758 struct kvm_guest_debug *dbg)
b6c7a5dc 6759{
355be0b9 6760 unsigned long rflags;
ae675ef0 6761 int i, r;
b6c7a5dc 6762
4f926bf2
JK		 6763 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6764 r = -EBUSY;
6765 if (vcpu->arch.exception.pending)
2122ff5e 6766 goto out;
4f926bf2
JK		 6767 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6768 kvm_queue_exception(vcpu, DB_VECTOR);
6769 else
6770 kvm_queue_exception(vcpu, BP_VECTOR);
6771 }
6772
91586a3b
JK		 6773 /*
6774 * Read rflags as long as potentially injected trace flags are still
6775 * filtered out.
6776 */
6777 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6778
6779 vcpu->guest_debug = dbg->control;
6780 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6781 vcpu->guest_debug = 0;
6782
6783 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6784 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6785 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6786 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6787 } else {
6788 for (i = 0; i < KVM_NR_DB_REGS; i++)
6789 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6790 }
c8639010 6791 kvm_update_dr7(vcpu);
ae675ef0 6792
f92653ee
JK		 6793 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6794 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6795 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6796
91586a3b
JK		 6797 /*
6798 * Trigger an rflags update that will inject or remove the trace
6799 * flags.
6800 */
6801 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6802
c8639010 6803 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6804
4f926bf2 6805 r = 0;
d0bfb940 6806
2122ff5e 6807out:
b6c7a5dc
HB		 6808
6809 return r;
6810}
6811
8b006791
ZX		 6812/*
6813 * Translate a guest virtual address to a guest physical address.
6814 */
6815int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6816 struct kvm_translation *tr)
6817{
6818 unsigned long vaddr = tr->linear_address;
6819 gpa_t gpa;
f656ce01 6820 int idx;
8b006791 6821
f656ce01 6822 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6823 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6824 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6825 tr->physical_address = gpa;
6826 tr->valid = gpa != UNMAPPED_GVA;
6827 tr->writeable = 1;
6828 tr->usermode = 0;
8b006791
ZX		 6829
6830 return 0;
6831}
6832
d0752060
HB		 6833int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6834{
98918833
SY		 6835 struct i387_fxsave_struct *fxsave =
6836 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6837
d0752060
HB		 6838 memcpy(fpu->fpr, fxsave->st_space, 128);
6839 fpu->fcw = fxsave->cwd;
6840 fpu->fsw = fxsave->swd;
6841 fpu->ftwx = fxsave->twd;
6842 fpu->last_opcode = fxsave->fop;
6843 fpu->last_ip = fxsave->rip;
6844 fpu->last_dp = fxsave->rdp;
6845 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6846
d0752060
HB		 6847 return 0;
6848}
6849
6850int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6851{
98918833
SY		 6852 struct i387_fxsave_struct *fxsave =
6853 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6854
d0752060
HB		 6855 memcpy(fxsave->st_space, fpu->fpr, 128);
6856 fxsave->cwd = fpu->fcw;
6857 fxsave->swd = fpu->fsw;
6858 fxsave->twd = fpu->ftwx;
6859 fxsave->fop = fpu->last_opcode;
6860 fxsave->rip = fpu->last_ip;
6861 fxsave->rdp = fpu->last_dp;
6862 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6863
d0752060
HB		 6864 return 0;
6865}
6866
10ab25cd 6867int fx_init(struct kvm_vcpu *vcpu)
d0752060 6868{
10ab25cd
JK		 6869 int err;
6870
6871 err = fpu_alloc(&vcpu->arch.guest_fpu);
6872 if (err)
6873 return err;
6874
98918833 6875 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6876
2acf923e
DC		 6877 /*
6878 * Ensure guest xcr0 is valid for loading
6879 */
6880 vcpu->arch.xcr0 = XSTATE_FP;
6881
ad312c7c 6882 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6883
6884 return 0;
d0752060
HB		 6885}
6886EXPORT_SYMBOL_GPL(fx_init);
6887
98918833
SY		 6888static void fx_free(struct kvm_vcpu *vcpu)
6889{
6890 fpu_free(&vcpu->arch.guest_fpu);
6891}
6892
d0752060
HB		 6893void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6894{
2608d7a1 6895 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6896 return;
6897
2acf923e
DC		 6898 /*
6899 * Restore all possible states in the guest,
6900 * and assume host would use all available bits.
6901 * Guest xcr0 would be loaded later.
6902 */
6903 kvm_put_guest_xcr0(vcpu);
d0752060 6904 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6905 __kernel_fpu_begin();
98918833 6906 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6907 trace_kvm_fpu(1);
d0752060 6908}
d0752060
HB		 6909
6910void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6911{
2acf923e
DC		 6912 kvm_put_guest_xcr0(vcpu);
6913
d0752060
HB		 6914 if (!vcpu->guest_fpu_loaded)
6915 return;
6916
6917 vcpu->guest_fpu_loaded = 0;
98918833 6918 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6919 __kernel_fpu_end();
f096ed85 6920 ++vcpu->stat.fpu_reload;
a8eeb04a 6921 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6922 trace_kvm_fpu(0);
d0752060 6923}
e9b11c17
ZX		 6924
6925void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6926{
12f9a48f 6927 kvmclock_reset(vcpu);
7f1ea208 6928
f5f48ee1 6929 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6930 fx_free(vcpu);
e9b11c17
ZX		 6931 kvm_x86_ops->vcpu_free(vcpu);
6932}
6933
6934struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6935 unsigned int id)
6936{
6755bae8
ZA		 6937 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6938 printk_once(KERN_WARNING
6939 "kvm: SMP vm created on host with unstable TSC; "
6940 "guest TSC will not be reliable\n");
26e5215f
AK		 6941 return kvm_x86_ops->vcpu_create(kvm, id);
6942}
e9b11c17 6943
26e5215f
AK		 6944int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6945{
6946 int r;
e9b11c17 6947
0bed3b56 6948 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6949 r = vcpu_load(vcpu);
6950 if (r)
6951 return r;
57f252f2 6952 kvm_vcpu_reset(vcpu);
8a3c1a33 6953 kvm_mmu_setup(vcpu);
e9b11c17 6954 vcpu_put(vcpu);
e9b11c17 6955
26e5215f 6956 return r;
e9b11c17
ZX		 6957}
6958
42897d86
MT		 6959int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6960{
6961 int r;
8fe8ab46 6962 struct msr_data msr;
332967a3 6963 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6964
6965 r = vcpu_load(vcpu);
6966 if (r)
6967 return r;
8fe8ab46
WA		 6968 msr.data = 0x0;
6969 msr.index = MSR_IA32_TSC;
6970 msr.host_initiated = true;
6971 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6972 vcpu_put(vcpu);
6973
332967a3
AJ		 6974 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6975 KVMCLOCK_SYNC_PERIOD);
6976
42897d86
MT		 6977 return r;
6978}
6979
d40ccc62 6980void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6981{
9fc77441 6982 int r;
344d9588
GN		 6983 vcpu->arch.apf.msr_val = 0;
6984
9fc77441
MT		 6985 r = vcpu_load(vcpu);
6986 BUG_ON(r);
e9b11c17
ZX		 6987 kvm_mmu_unload(vcpu);
6988 vcpu_put(vcpu);
6989
98918833 6990 fx_free(vcpu);
e9b11c17
ZX		 6991 kvm_x86_ops->vcpu_free(vcpu);
6992}
6993
66450a21 6994void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6995{
7460fb4a
AK		 6996 atomic_set(&vcpu->arch.nmi_queued, 0);
6997 vcpu->arch.nmi_pending = 0;
448fa4a9 6998 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6999 kvm_clear_interrupt_queue(vcpu);
7000 kvm_clear_exception_queue(vcpu);
448fa4a9 7001
42dbaa5a 7002 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7003 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7004 kvm_update_dr6(vcpu);
42dbaa5a 7005 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7006 kvm_update_dr7(vcpu);
42dbaa5a 7007
3842d135 7008 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7009 vcpu->arch.apf.msr_val = 0;
c9aaa895 7010 vcpu->arch.st.msr_val = 0;
3842d135 7011
12f9a48f
GC		 7012 kvmclock_reset(vcpu);
7013
af585b92
GN		 7014 kvm_clear_async_pf_completion_queue(vcpu);
7015 kvm_async_pf_hash_reset(vcpu);
7016 vcpu->arch.apf.halted = false;
3842d135 7017
f5132b01
GN		 7018 kvm_pmu_reset(vcpu);
7019
66f7b72e
JS		 7020 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7021 vcpu->arch.regs_avail = ~0;
7022 vcpu->arch.regs_dirty = ~0;
7023
57f252f2 7024 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7025}
7026
66450a21
JK		 7027void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
7028{
7029 struct kvm_segment cs;
7030
7031 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7032 cs.selector = vector << 8;
7033 cs.base = vector << 12;
7034 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7035 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7036}
7037
13a34e06 7038int kvm_arch_hardware_enable(void)
e9b11c17 7039{
ca84d1a2
ZA		 7040 struct kvm *kvm;
7041 struct kvm_vcpu *vcpu;
7042 int i;
0dd6a6ed
ZA		 7043 int ret;
7044 u64 local_tsc;
7045 u64 max_tsc = 0;
7046 bool stable, backwards_tsc = false;
18863bdd
AK		 7047
7048 kvm_shared_msr_cpu_online();
13a34e06 7049 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7050 if (ret != 0)
7051 return ret;
7052
7053 local_tsc = native_read_tsc();
7054 stable = !check_tsc_unstable();
7055 list_for_each_entry(kvm, &vm_list, vm_list) {
7056 kvm_for_each_vcpu(i, vcpu, kvm) {
7057 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7058 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7059 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7060 backwards_tsc = true;
7061 if (vcpu->arch.last_host_tsc > max_tsc)
7062 max_tsc = vcpu->arch.last_host_tsc;
7063 }
7064 }
7065 }
7066
7067 /*
7068 * Sometimes, even reliable TSCs go backwards. This happens on
7069 * platforms that reset TSC during suspend or hibernate actions, but
7070 * maintain synchronization. We must compensate. Fortunately, we can
7071 * detect that condition here, which happens early in CPU bringup,
7072 * before any KVM threads can be running. Unfortunately, we can't
7073 * bring the TSCs fully up to date with real time, as we aren't yet far
7074 * enough into CPU bringup that we know how much real time has actually
7075 * elapsed; our helper function, get_kernel_ns() will be using boot
7076 * variables that haven't been updated yet.
7077 *
7078 * So we simply find the maximum observed TSC above, then record the
7079 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7080 * the adjustment will be applied. Note that we accumulate
7081 * adjustments, in case multiple suspend cycles happen before some VCPU
7082 * gets a chance to run again. In the event that no KVM threads get a
7083 * chance to run, we will miss the entire elapsed period, as we'll have
7084 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7085 * loose cycle time. This isn't too big a deal, since the loss will be
7086 * uniform across all VCPUs (not to mention the scenario is extremely
7087 * unlikely). It is possible that a second hibernate recovery happens
7088 * much faster than a first, causing the observed TSC here to be
7089 * smaller; this would require additional padding adjustment, which is
7090 * why we set last_host_tsc to the local tsc observed here.
7091 *
7092 * N.B. - this code below runs only on platforms with reliable TSC,
7093 * as that is the only way backwards_tsc is set above. Also note
7094 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7095 * have the same delta_cyc adjustment applied if backwards_tsc
7096 * is detected. Note further, this adjustment is only done once,
7097 * as we reset last_host_tsc on all VCPUs to stop this from being
7098 * called multiple times (one for each physical CPU bringup).
7099 *
4a969980 7100 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7101 * will be compensated by the logic in vcpu_load, which sets the TSC to
7102 * catchup mode. This will catchup all VCPUs to real time, but cannot
7103 * guarantee that they stay in perfect synchronization.
7104 */
7105 if (backwards_tsc) {
7106 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7107 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7108 list_for_each_entry(kvm, &vm_list, vm_list) {
7109 kvm_for_each_vcpu(i, vcpu, kvm) {
7110 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7111 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7112 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7113 }
7114
7115 /*
7116 * We have to disable TSC offset matching.. if you were
7117 * booting a VM while issuing an S4 host suspend....
7118 * you may have some problem. Solving this issue is
7119 * left as an exercise to the reader.
7120 */
7121 kvm->arch.last_tsc_nsec = 0;
7122 kvm->arch.last_tsc_write = 0;
7123 }
7124
7125 }
7126 return 0;
e9b11c17
ZX		 7127}
7128
13a34e06 7129void kvm_arch_hardware_disable(void)
e9b11c17 7130{
13a34e06
RK		 7131 kvm_x86_ops->hardware_disable();
7132 drop_user_return_notifiers();
e9b11c17
ZX		 7133}
7134
7135int kvm_arch_hardware_setup(void)
7136{
7137 return kvm_x86_ops->hardware_setup();
7138}
7139
7140void kvm_arch_hardware_unsetup(void)
7141{
7142 kvm_x86_ops->hardware_unsetup();
7143}
7144
7145void kvm_arch_check_processor_compat(void *rtn)
7146{
7147 kvm_x86_ops->check_processor_compatibility(rtn);
7148}
7149
3e515705
AK		 7150bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7151{
7152 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7153}
7154
54e9818f
GN		 7155struct static_key kvm_no_apic_vcpu __read_mostly;
7156
e9b11c17
ZX		 7157int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7158{
7159 struct page *page;
7160 struct kvm *kvm;
7161 int r;
7162
7163 BUG_ON(vcpu->kvm == NULL);
7164 kvm = vcpu->kvm;
7165
6aef266c 7166 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7167 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7168 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7169 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7170 else
a4535290 7171 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7172
7173 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7174 if (!page) {
7175 r = -ENOMEM;
7176 goto fail;
7177 }
ad312c7c 7178 vcpu->arch.pio_data = page_address(page);
e9b11c17 7179
cc578287 7180 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7181
e9b11c17
ZX		 7182 r = kvm_mmu_create(vcpu);
7183 if (r < 0)
7184 goto fail_free_pio_data;
7185
7186 if (irqchip_in_kernel(kvm)) {
7187 r = kvm_create_lapic(vcpu);
7188 if (r < 0)
7189 goto fail_mmu_destroy;
54e9818f
GN		 7190 } else
7191 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7192
890ca9ae
HY		 7193 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7194 GFP_KERNEL);
7195 if (!vcpu->arch.mce_banks) {
7196 r = -ENOMEM;
443c39bc 7197 goto fail_free_lapic;
890ca9ae
HY		 7198 }
7199 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7200
f1797359
WY		 7201 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7202 r = -ENOMEM;
f5f48ee1 7203 goto fail_free_mce_banks;
f1797359 7204 }
f5f48ee1 7205
66f7b72e
JS		 7206 r = fx_init(vcpu);
7207 if (r)
7208 goto fail_free_wbinvd_dirty_mask;
7209
ba904635 7210 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7211 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7212
7213 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7214 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7215
af585b92 7216 kvm_async_pf_hash_reset(vcpu);
f5132b01 7217 kvm_pmu_init(vcpu);
af585b92 7218
e9b11c17 7219 return 0;
66f7b72e
JS		 7220fail_free_wbinvd_dirty_mask:
7221 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7222fail_free_mce_banks:
7223 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7224fail_free_lapic:
7225 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7226fail_mmu_destroy:
7227 kvm_mmu_destroy(vcpu);
7228fail_free_pio_data:
ad312c7c 7229 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7230fail:
7231 return r;
7232}
7233
7234void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7235{
f656ce01
MT		 7236 int idx;
7237
f5132b01 7238 kvm_pmu_destroy(vcpu);
36cb93fd 7239 kfree(vcpu->arch.mce_banks);
e9b11c17 7240 kvm_free_lapic(vcpu);
f656ce01 7241 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7242 kvm_mmu_destroy(vcpu);
f656ce01 7243 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7244 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7245 if (!irqchip_in_kernel(vcpu->kvm))
7246 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7247}
d19a9cd2 7248
e790d9ef
RK		 7249void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7250{
ae97a3b8 7251 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7252}
7253
e08b9637 7254int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7255{
e08b9637
CO		 7256 if (type)
7257 return -EINVAL;
7258
f05e70ac 7259 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7260 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7261 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7262 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7263
5550af4d
SY		 7264 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7265 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7266 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7267 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7268 &kvm->arch.irq_sources_bitmap);
5550af4d 7269
038f8c11 7270 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7271 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7272 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7273
7274 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7275
7e44e449 7276 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7277 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7278
d89f5eff 7279 return 0;
d19a9cd2
ZX		 7280}
7281
7282static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7283{
9fc77441
MT		 7284 int r;
7285 r = vcpu_load(vcpu);
7286 BUG_ON(r);
d19a9cd2
ZX		 7287 kvm_mmu_unload(vcpu);
7288 vcpu_put(vcpu);
7289}
7290
7291static void kvm_free_vcpus(struct kvm *kvm)
7292{
7293 unsigned int i;
988a2cae 7294 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7295
7296 /*
7297 * Unpin any mmu pages first.
7298 */
af585b92
GN		 7299 kvm_for_each_vcpu(i, vcpu, kvm) {
7300 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7301 kvm_unload_vcpu_mmu(vcpu);
af585b92 7302 }
988a2cae
GN		 7303 kvm_for_each_vcpu(i, vcpu, kvm)
7304 kvm_arch_vcpu_free(vcpu);
7305
7306 mutex_lock(&kvm->lock);
7307 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7308 kvm->vcpus[i] = NULL;
d19a9cd2 7309
988a2cae
GN		 7310 atomic_set(&kvm->online_vcpus, 0);
7311 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7312}
7313
ad8ba2cd
SY		 7314void kvm_arch_sync_events(struct kvm *kvm)
7315{
332967a3 7316 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7317 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7318 kvm_free_all_assigned_devices(kvm);
aea924f6 7319 kvm_free_pit(kvm);
ad8ba2cd
SY		 7320}
7321
d19a9cd2
ZX		 7322void kvm_arch_destroy_vm(struct kvm *kvm)
7323{
27469d29
AH		 7324 if (current->mm == kvm->mm) {
7325 /*
7326 * Free memory regions allocated on behalf of userspace,
7327 * unless the the memory map has changed due to process exit
7328 * or fd copying.
7329 */
7330 struct kvm_userspace_memory_region mem;
7331 memset(&mem, 0, sizeof(mem));
7332 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7333 kvm_set_memory_region(kvm, &mem);
7334
7335 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7336 kvm_set_memory_region(kvm, &mem);
7337
7338 mem.slot = TSS_PRIVATE_MEMSLOT;
7339 kvm_set_memory_region(kvm, &mem);
7340 }
6eb55818 7341 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7342 kfree(kvm->arch.vpic);
7343 kfree(kvm->arch.vioapic);
d19a9cd2 7344 kvm_free_vcpus(kvm);
1e08ec4a 7345 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7346}
0de10343 7347
5587027c 7348void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7349 struct kvm_memory_slot *dont)
7350{
7351 int i;
7352
d89cc617
TY		 7353 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7354 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7355 kvm_kvfree(free->arch.rmap[i]);
7356 free->arch.rmap[i] = NULL;
77d11309 7357 }
d89cc617
TY		 7358 if (i == 0)
7359 continue;
7360
7361 if (!dont || free->arch.lpage_info[i - 1] !=
7362 dont->arch.lpage_info[i - 1]) {
7363 kvm_kvfree(free->arch.lpage_info[i - 1]);
7364 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7365 }
7366 }
7367}
7368
5587027c
AK		 7369int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7370 unsigned long npages)
db3fe4eb
TY		 7371{
7372 int i;
7373
d89cc617 7374 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7375 unsigned long ugfn;
7376 int lpages;
d89cc617 7377 int level = i + 1;
db3fe4eb
TY		 7378
7379 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7380 slot->base_gfn, level) + 1;
7381
d89cc617
TY		 7382 slot->arch.rmap[i] =
7383 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7384 if (!slot->arch.rmap[i])
77d11309 7385 goto out_free;
d89cc617
TY		 7386 if (i == 0)
7387 continue;
77d11309 7388
d89cc617
TY		 7389 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7390 sizeof(*slot->arch.lpage_info[i - 1]));
7391 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7392 goto out_free;
7393
7394 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7395 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7396 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7397 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7398 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7399 /*
7400 * If the gfn and userspace address are not aligned wrt each
7401 * other, or if explicitly asked to, disable large page
7402 * support for this slot
7403 */
7404 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7405 !kvm_largepages_enabled()) {
7406 unsigned long j;
7407
7408 for (j = 0; j < lpages; ++j)
d89cc617 7409 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7410 }
7411 }
7412
7413 return 0;
7414
7415out_free:
d89cc617
TY		 7416 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7417 kvm_kvfree(slot->arch.rmap[i]);
7418 slot->arch.rmap[i] = NULL;
7419 if (i == 0)
7420 continue;
7421
7422 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7423 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7424 }
7425 return -ENOMEM;
7426}
7427
e59dbe09
TY		 7428void kvm_arch_memslots_updated(struct kvm *kvm)
7429{
e6dff7d1
TY		 7430 /*
7431 * memslots->generation has been incremented.
7432 * mmio generation may have reached its maximum value.
7433 */
7434 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7435}
7436
f7784b8e
MT		 7437int kvm_arch_prepare_memory_region(struct kvm *kvm,
7438 struct kvm_memory_slot *memslot,
f7784b8e 7439 struct kvm_userspace_memory_region *mem,
7b6195a9 7440 enum kvm_mr_change change)
0de10343 7441{
7a905b14
TY		 7442 /*
7443 * Only private memory slots need to be mapped here since
7444 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7445 */
7b6195a9 7446 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7447 unsigned long userspace_addr;
604b38ac 7448
7a905b14
TY		 7449 /*
7450 * MAP_SHARED to prevent internal slot pages from being moved
7451 * by fork()/COW.
7452 */
7b6195a9 7453 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7454 PROT_READ | PROT_WRITE,
7455 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7456
7a905b14
TY		 7457 if (IS_ERR((void *)userspace_addr))
7458 return PTR_ERR((void *)userspace_addr);
604b38ac 7459
7a905b14 7460 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7461 }
7462
f7784b8e
MT		 7463 return 0;
7464}
7465
7466void kvm_arch_commit_memory_region(struct kvm *kvm,
7467 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7468 const struct kvm_memory_slot *old,
7469 enum kvm_mr_change change)
f7784b8e
MT		 7470{
7471
8482644a 7472 int nr_mmu_pages = 0;
f7784b8e 7473
8482644a 7474 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7475 int ret;
7476
8482644a
TY		 7477 ret = vm_munmap(old->userspace_addr,
7478 old->npages * PAGE_SIZE);
f7784b8e
MT		 7479 if (ret < 0)
7480 printk(KERN_WARNING
7481 "kvm_vm_ioctl_set_memory_region: "
7482 "failed to munmap memory\n");
7483 }
7484
48c0e4e9
XG		 7485 if (!kvm->arch.n_requested_mmu_pages)
7486 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7487
48c0e4e9 7488 if (nr_mmu_pages)
0de10343 7489 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7490 /*
7491 * Write protect all pages for dirty logging.
c126d94f
XG		 7492 *
7493 * All the sptes including the large sptes which point to this
7494 * slot are set to readonly. We can not create any new large
7495 * spte on this slot until the end of the logging.
7496 *
7497 * See the comments in fast_page_fault().
c972f3b1 7498 */
8482644a 7499 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7500 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7501}
1d737c8a 7502
2df72e9b 7503void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7504{
6ca18b69 7505 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7506}
7507
2df72e9b
MT		 7508void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7509 struct kvm_memory_slot *slot)
7510{
6ca18b69 7511 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7512}
7513
1d737c8a
ZX		 7514int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7515{
b6b8a145
JK		 7516 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7517 kvm_x86_ops->check_nested_events(vcpu, false);
7518
af585b92
GN		 7519 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7520 !vcpu->arch.apf.halted)
7521 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7522 || kvm_apic_has_events(vcpu)
6aef266c 7523 || vcpu->arch.pv.pv_unhalted
7460fb4a 7524 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7525 (kvm_arch_interrupt_allowed(vcpu) &&
7526 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7527}
5736199a 7528
b6d33834 7529int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7530{
b6d33834 7531 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7532}
78646121
GN		 7533
7534int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7535{
7536 return kvm_x86_ops->interrupt_allowed(vcpu);
7537}
229456fc 7538
f92653ee
JK		 7539bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7540{
7541 unsigned long current_rip = kvm_rip_read(vcpu) +
7542 get_segment_base(vcpu, VCPU_SREG_CS);
7543
7544 return current_rip == linear_rip;
7545}
7546EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7547
94fe45da
JK		 7548unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7549{
7550 unsigned long rflags;
7551
7552 rflags = kvm_x86_ops->get_rflags(vcpu);
7553 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7554 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7555 return rflags;
7556}
7557EXPORT_SYMBOL_GPL(kvm_get_rflags);
7558
6addfc42 7559static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7560{
7561 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7562 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7563 rflags |= X86_EFLAGS_TF;
94fe45da 7564 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7565}
7566
7567void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7568{
7569 __kvm_set_rflags(vcpu, rflags);
3842d135 7570 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7571}
7572EXPORT_SYMBOL_GPL(kvm_set_rflags);
7573
56028d08
GN		 7574void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7575{
7576 int r;
7577
fb67e14f 7578 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7579 work->wakeup_all)
56028d08
GN		 7580 return;
7581
7582 r = kvm_mmu_reload(vcpu);
7583 if (unlikely(r))
7584 return;
7585
fb67e14f
XG		 7586 if (!vcpu->arch.mmu.direct_map &&
7587 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7588 return;
7589
56028d08
GN		 7590 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7591}
7592
af585b92
GN		 7593static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7594{
7595 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7596}
7597
7598static inline u32 kvm_async_pf_next_probe(u32 key)
7599{
7600 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7601}
7602
7603static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7604{
7605 u32 key = kvm_async_pf_hash_fn(gfn);
7606
7607 while (vcpu->arch.apf.gfns[key] != ~0)
7608 key = kvm_async_pf_next_probe(key);
7609
7610 vcpu->arch.apf.gfns[key] = gfn;
7611}
7612
7613static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7614{
7615 int i;
7616 u32 key = kvm_async_pf_hash_fn(gfn);
7617
7618 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7619 (vcpu->arch.apf.gfns[key] != gfn &&
7620 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7621 key = kvm_async_pf_next_probe(key);
7622
7623 return key;
7624}
7625
7626bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7627{
7628 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7629}
7630
7631static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7632{
7633 u32 i, j, k;
7634
7635 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7636 while (true) {
7637 vcpu->arch.apf.gfns[i] = ~0;
7638 do {
7639 j = kvm_async_pf_next_probe(j);
7640 if (vcpu->arch.apf.gfns[j] == ~0)
7641 return;
7642 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7643 /*
7644 * k lies cyclically in ]i,j]
7645 * | i.k.j |
7646 * |....j i.k.| or |.k..j i...|
7647 */
7648 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7649 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7650 i = j;
7651 }
7652}
7653
7c90705b
GN		 7654static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7655{
7656
7657 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7658 sizeof(val));
7659}
7660
af585b92
GN		 7661void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7662 struct kvm_async_pf *work)
7663{
6389ee94
AK		 7664 struct x86_exception fault;
7665
7c90705b 7666 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7667 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7668
7669 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7670 (vcpu->arch.apf.send_user_only &&
7671 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7672 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7673 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7674 fault.vector = PF_VECTOR;
7675 fault.error_code_valid = true;
7676 fault.error_code = 0;
7677 fault.nested_page_fault = false;
7678 fault.address = work->arch.token;
7679 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7680 }
af585b92
GN		 7681}
7682
7683void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7684 struct kvm_async_pf *work)
7685{
6389ee94
AK		 7686 struct x86_exception fault;
7687
7c90705b 7688 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7689 if (work->wakeup_all)
7c90705b
GN		 7690 work->arch.token = ~0; /* broadcast wakeup */
7691 else
7692 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7693
7694 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7695 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7696 fault.vector = PF_VECTOR;
7697 fault.error_code_valid = true;
7698 fault.error_code = 0;
7699 fault.nested_page_fault = false;
7700 fault.address = work->arch.token;
7701 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7702 }
e6d53e3b 7703 vcpu->arch.apf.halted = false;
a4fa1635 7704 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7705}
7706
7707bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7708{
7709 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7710 return true;
7711 else
7712 return !kvm_event_needs_reinjection(vcpu) &&
7713 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7714}
7715
e0f0bbc5
AW		 7716void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7717{
7718 atomic_inc(&kvm->arch.noncoherent_dma_count);
7719}
7720EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7721
7722void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7723{
7724 atomic_dec(&kvm->arch.noncoherent_dma_count);
7725}
7726EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7727
7728bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7729{
7730 return atomic_read(&kvm->arch.noncoherent_dma_count);
7731}
7732EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7733
229456fc
MT		 7734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7745EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7746EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7747EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git