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KVM: add kvm_arch_sched_in
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
3548bab5
AK		 249static void drop_user_return_notifiers(void *ignore)
250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
6389ee94 411void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 417}
418
3419ffc8
SY		 419void kvm_inject_nmi(struct kvm_vcpu *vcpu)
420{
7460fb4a
AK		 421 atomic_inc(&vcpu->arch.nmi_queued);
422 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 423}
424EXPORT_SYMBOL_GPL(kvm_inject_nmi);
425
298101da
AK		 426void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
427{
ce7ddec4 428 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 429}
430EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
431
ce7ddec4
JR		 432void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
433{
434 kvm_multiple_exception(vcpu, nr, true, error_code, true);
435}
436EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
437
0a79b009
AK		 438/*
439 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
440 * a #GP and return false.
441 */
442bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 443{
0a79b009
AK		 444 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
445 return true;
446 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
447 return false;
298101da 448}
0a79b009 449EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 450
ec92fe44
JR		 451/*
452 * This function will be used to read from the physical memory of the currently
453 * running guest. The difference to kvm_read_guest_page is that this function
454 * can read from guest physical or from the guest's guest physical memory.
455 */
456int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
457 gfn_t ngfn, void *data, int offset, int len,
458 u32 access)
459{
460 gfn_t real_gfn;
461 gpa_t ngpa;
462
463 ngpa = gfn_to_gpa(ngfn);
464 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
465 if (real_gfn == UNMAPPED_GVA)
466 return -EFAULT;
467
468 real_gfn = gpa_to_gfn(real_gfn);
469
470 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
471}
472EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
473
3d06b8bf
JR		 474int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
475 void *data, int offset, int len, u32 access)
476{
477 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
478 data, offset, len, access);
479}
480
a03490ed
CO		 481/*
482 * Load the pae pdptrs. Return true is they are all valid.
483 */
ff03a073 484int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 485{
486 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
487 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
488 int i;
489 int ret;
ff03a073 490 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 491
ff03a073
JR		 492 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
493 offset * sizeof(u64), sizeof(pdpte),
494 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 495 if (ret < 0) {
496 ret = 0;
497 goto out;
498 }
499 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 500 if (is_present_gpte(pdpte[i]) &&
20c466b5 501 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 502 ret = 0;
503 goto out;
504 }
505 }
506 ret = 1;
507
ff03a073 508 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 509 __set_bit(VCPU_EXREG_PDPTR,
510 (unsigned long *)&vcpu->arch.regs_avail);
511 __set_bit(VCPU_EXREG_PDPTR,
512 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 513out:
a03490ed
CO		 514
515 return ret;
516}
cc4b6871 517EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 518
d835dfec
AK		 519static bool pdptrs_changed(struct kvm_vcpu *vcpu)
520{
ff03a073 521 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 522 bool changed = true;
3d06b8bf
JR		 523 int offset;
524 gfn_t gfn;
d835dfec
AK		 525 int r;
526
527 if (is_long_mode(vcpu) || !is_pae(vcpu))
528 return false;
529
6de4f3ad
AK		 530 if (!test_bit(VCPU_EXREG_PDPTR,
531 (unsigned long *)&vcpu->arch.regs_avail))
532 return true;
533
9f8fe504
AK		 534 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
535 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 536 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
537 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 538 if (r < 0)
539 goto out;
ff03a073 540 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 541out:
d835dfec
AK		 542
543 return changed;
544}
545
49a9b07e 546int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 547{
aad82703
SY		 548 unsigned long old_cr0 = kvm_read_cr0(vcpu);
549 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
550 X86_CR0_CD | X86_CR0_NW;
551
f9a48e6a
AK		 552 cr0 |= X86_CR0_ET;
553
ab344828 554#ifdef CONFIG_X86_64
0f12244f
GN		 555 if (cr0 & 0xffffffff00000000UL)
556 return 1;
ab344828
GN		 557#endif
558
559 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 560
0f12244f
GN		 561 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
562 return 1;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
565 return 1;
a03490ed
CO		 566
567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
568#ifdef CONFIG_X86_64
f6801dff 569 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 570 int cs_db, cs_l;
571
0f12244f
GN		 572 if (!is_pae(vcpu))
573 return 1;
a03490ed 574 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 575 if (cs_l)
576 return 1;
a03490ed
CO		 577 } else
578#endif
ff03a073 579 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 580 kvm_read_cr3(vcpu)))
0f12244f 581 return 1;
a03490ed
CO		 582 }
583
ad756a16
MJ		 584 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
585 return 1;
586
a03490ed 587 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 588
d170c419 589 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 590 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 591 kvm_async_pf_hash_reset(vcpu);
592 }
e5f3f027 593
aad82703
SY		 594 if ((cr0 ^ old_cr0) & update_bits)
595 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 596 return 0;
597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 599
2d3ad1f4 600void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 601{
49a9b07e 602 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 603}
2d3ad1f4 604EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 605
42bdf991
MT		 606static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
607{
608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
609 !vcpu->guest_xcr0_loaded) {
610 /* kvm_set_xcr() also depends on this */
611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
612 vcpu->guest_xcr0_loaded = 1;
613 }
614}
615
616static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
617{
618 if (vcpu->guest_xcr0_loaded) {
619 if (vcpu->arch.xcr0 != host_xcr0)
620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
621 vcpu->guest_xcr0_loaded = 0;
622 }
623}
624
2acf923e
DC		 625int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
626{
56c103ec
LJ		 627 u64 xcr0 = xcr;
628 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 629 u64 valid_bits;
2acf923e
DC		 630
631 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
632 if (index != XCR_XFEATURE_ENABLED_MASK)
633 return 1;
2acf923e
DC		 634 if (!(xcr0 & XSTATE_FP))
635 return 1;
636 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
637 return 1;
46c34cb0
PB		 638
639 /*
640 * Do not allow the guest to set bits that we do not support
641 * saving. However, xcr0 bit 0 is always set, even if the
642 * emulated CPU does not support XSAVE (see fx_init).
643 */
644 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
645 if (xcr0 & ~valid_bits)
2acf923e 646 return 1;
46c34cb0 647
390bd528
LJ		 648 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
649 return 1;
650
42bdf991 651 kvm_put_guest_xcr0(vcpu);
2acf923e 652 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 653
654 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
655 kvm_update_cpuid(vcpu);
2acf923e
DC		 656 return 0;
657}
658
659int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
660{
764bcbc5
Z		 661 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
662 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 663 kvm_inject_gp(vcpu, 0);
664 return 1;
665 }
666 return 0;
667}
668EXPORT_SYMBOL_GPL(kvm_set_xcr);
669
a83b29c6 670int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 671{
fc78f519 672 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 673 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
674 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 675 if (cr4 & CR4_RESERVED_BITS)
676 return 1;
a03490ed 677
2acf923e
DC		 678 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
679 return 1;
680
c68b734f
YW		 681 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
682 return 1;
683
97ec8c06
FW		 684 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
685 return 1;
686
afcbf13f 687 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 688 return 1;
689
a03490ed 690 if (is_long_mode(vcpu)) {
0f12244f
GN		 691 if (!(cr4 & X86_CR4_PAE))
692 return 1;
a2edf57f
AK		 693 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
694 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 695 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
696 kvm_read_cr3(vcpu)))
0f12244f
GN		 697 return 1;
698
ad756a16
MJ		 699 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
700 if (!guest_cpuid_has_pcid(vcpu))
701 return 1;
702
703 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
704 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
705 return 1;
706 }
707
5e1746d6 708 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 709 return 1;
a03490ed 710
ad756a16
MJ		 711 if (((cr4 ^ old_cr4) & pdptr_bits) ||
712 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 713 kvm_mmu_reset_context(vcpu);
0f12244f 714
97ec8c06
FW		 715 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
716 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
717
2acf923e 718 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 719 kvm_update_cpuid(vcpu);
2acf923e 720
0f12244f
GN		 721 return 0;
722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 724
2390218b 725int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 726{
9f8fe504 727 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 728 kvm_mmu_sync_roots(vcpu);
d835dfec 729 kvm_mmu_flush_tlb(vcpu);
0f12244f 730 return 0;
d835dfec
AK		 731 }
732
a03490ed 733 if (is_long_mode(vcpu)) {
d9f89b88
JK		 734 if (cr3 & CR3_L_MODE_RESERVED_BITS)
735 return 1;
736 } else if (is_pae(vcpu) && is_paging(vcpu) &&
737 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 738 return 1;
a03490ed 739
0f12244f 740 vcpu->arch.cr3 = cr3;
aff48baa 741 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 742 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 743 return 0;
744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 746
eea1cff9 747int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 748{
0f12244f
GN		 749 if (cr8 & CR8_RESERVED_BITS)
750 return 1;
a03490ed
CO		 751 if (irqchip_in_kernel(vcpu->kvm))
752 kvm_lapic_set_tpr(vcpu, cr8);
753 else
ad312c7c 754 vcpu->arch.cr8 = cr8;
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 758
2d3ad1f4 759unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 760{
761 if (irqchip_in_kernel(vcpu->kvm))
762 return kvm_lapic_get_cr8(vcpu);
763 else
ad312c7c 764 return vcpu->arch.cr8;
a03490ed 765}
2d3ad1f4 766EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 767
73aaf249
JK		 768static void kvm_update_dr6(struct kvm_vcpu *vcpu)
769{
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
772}
773
c8639010
JK		 774static void kvm_update_dr7(struct kvm_vcpu *vcpu)
775{
776 unsigned long dr7;
777
778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
779 dr7 = vcpu->arch.guest_debug_dr7;
780 else
781 dr7 = vcpu->arch.dr7;
782 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 783 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
784 if (dr7 & DR7_BP_EN_MASK)
785 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 786}
787
6f43ed01
NA		 788static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
789{
790 u64 fixed = DR6_FIXED_1;
791
792 if (!guest_cpuid_has_rtm(vcpu))
793 fixed |= DR6_RTM;
794 return fixed;
795}
796
338dbc97 797static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 798{
799 switch (dr) {
800 case 0 ... 3:
801 vcpu->arch.db[dr] = val;
802 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
803 vcpu->arch.eff_db[dr] = val;
804 break;
805 case 4:
338dbc97
GN		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
807 return 1; /* #UD */
020df079
GN		 808 /* fall through */
809 case 6:
338dbc97
GN		 810 if (val & 0xffffffff00000000ULL)
811 return -1; /* #GP */
6f43ed01 812 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 813 kvm_update_dr6(vcpu);
020df079
GN		 814 break;
815 case 5:
338dbc97
GN		 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
817 return 1; /* #UD */
020df079
GN		 818 /* fall through */
819 default: /* 7 */
338dbc97
GN		 820 if (val & 0xffffffff00000000ULL)
821 return -1; /* #GP */
020df079 822 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 823 kvm_update_dr7(vcpu);
020df079
GN		 824 break;
825 }
826
827 return 0;
828}
338dbc97
GN		 829
830int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
831{
832 int res;
833
834 res = __kvm_set_dr(vcpu, dr, val);
835 if (res > 0)
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 else if (res < 0)
838 kvm_inject_gp(vcpu, 0);
839
840 return res;
841}
020df079
GN		 842EXPORT_SYMBOL_GPL(kvm_set_dr);
843
338dbc97 844static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 *val = vcpu->arch.db[dr];
849 break;
850 case 4:
338dbc97 851 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 852 return 1;
020df079
GN		 853 /* fall through */
854 case 6:
73aaf249
JK		 855 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
856 *val = vcpu->arch.dr6;
857 else
858 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
338dbc97 861 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 862 return 1;
020df079
GN		 863 /* fall through */
864 default: /* 7 */
865 *val = vcpu->arch.dr7;
866 break;
867 }
868
869 return 0;
870}
338dbc97
GN		 871
872int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
873{
874 if (_kvm_get_dr(vcpu, dr, val)) {
875 kvm_queue_exception(vcpu, UD_VECTOR);
876 return 1;
877 }
878 return 0;
879}
020df079
GN		 880EXPORT_SYMBOL_GPL(kvm_get_dr);
881
022cd0e8
AK		 882bool kvm_rdpmc(struct kvm_vcpu *vcpu)
883{
884 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
885 u64 data;
886 int err;
887
888 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
889 if (err)
890 return err;
891 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
892 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
893 return err;
894}
895EXPORT_SYMBOL_GPL(kvm_rdpmc);
896
043405e1
CO		 897/*
898 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
899 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
900 *
901 * This list is modified at module load time to reflect the
e3267cbb
GC		 902 * capabilities of the host cpu. This capabilities test skips MSRs that are
903 * kvm-specific. Those are put in the beginning of the list.
043405e1 904 */
e3267cbb 905
e984097b 906#define KVM_SAVE_MSRS_BEGIN 12
043405e1 907static u32 msrs_to_save[] = {
e3267cbb 908 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 909 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 910 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 911 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 912 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 913 MSR_KVM_PV_EOI_EN,
043405e1 914 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 915 MSR_STAR,
043405e1
CO		 916#ifdef CONFIG_X86_64
917 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
918#endif
b3897a49 919 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 920 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 921};
922
923static unsigned num_msrs_to_save;
924
f1d24831 925static const u32 emulated_msrs[] = {
ba904635 926 MSR_IA32_TSC_ADJUST,
a3e06bbe 927 MSR_IA32_TSCDEADLINE,
043405e1 928 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 929 MSR_IA32_MCG_STATUS,
930 MSR_IA32_MCG_CTL,
043405e1
CO		 931};
932
384bb783 933bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 934{
b69e8cae 935 if (efer & efer_reserved_bits)
384bb783 936 return false;
15c4a640 937
1b2fd70c
AG		 938 if (efer & EFER_FFXSR) {
939 struct kvm_cpuid_entry2 *feat;
940
941 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 942 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 943 return false;
1b2fd70c
AG		 944 }
945
d8017474
AG		 946 if (efer & EFER_SVME) {
947 struct kvm_cpuid_entry2 *feat;
948
949 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 950 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 951 return false;
d8017474
AG		 952 }
953
384bb783
JK		 954 return true;
955}
956EXPORT_SYMBOL_GPL(kvm_valid_efer);
957
958static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
959{
960 u64 old_efer = vcpu->arch.efer;
961
962 if (!kvm_valid_efer(vcpu, efer))
963 return 1;
964
965 if (is_paging(vcpu)
966 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
967 return 1;
968
15c4a640 969 efer &= ~EFER_LMA;
f6801dff 970 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 971
a3d204e2
SY		 972 kvm_x86_ops->set_efer(vcpu, efer);
973
aad82703
SY		 974 /* Update reserved bits */
975 if ((efer ^ old_efer) & EFER_NX)
976 kvm_mmu_reset_context(vcpu);
977
b69e8cae 978 return 0;
15c4a640
CO		 979}
980
f2b4b7dd
JR		 981void kvm_enable_efer_bits(u64 mask)
982{
983 efer_reserved_bits &= ~mask;
984}
985EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
986
987
15c4a640
CO		 988/*
989 * Writes msr value into into the appropriate "register".
990 * Returns 0 on success, non-0 otherwise.
991 * Assumes vcpu_load() was already called.
992 */
8fe8ab46 993int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 994{
8fe8ab46 995 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 996}
997
313a3dc7
CO		 998/*
999 * Adapt set_msr() to msr_io()'s calling convention
1000 */
1001static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1002{
8fe8ab46
WA		 1003 struct msr_data msr;
1004
1005 msr.data = *data;
1006 msr.index = index;
1007 msr.host_initiated = true;
1008 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1009}
1010
16e8d74d
MT		 1011#ifdef CONFIG_X86_64
1012struct pvclock_gtod_data {
1013 seqcount_t seq;
1014
1015 struct { /* extract of a clocksource struct */
1016 int vclock_mode;
1017 cycle_t cycle_last;
1018 cycle_t mask;
1019 u32 mult;
1020 u32 shift;
1021 } clock;
1022
cbcf2dd3
TG		 1023 u64 boot_ns;
1024 u64 nsec_base;
16e8d74d
MT		 1025};
1026
1027static struct pvclock_gtod_data pvclock_gtod_data;
1028
1029static void update_pvclock_gtod(struct timekeeper *tk)
1030{
1031 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1032 u64 boot_ns;
1033
d28ede83 1034 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1035
1036 write_seqcount_begin(&vdata->seq);
1037
1038 /* copy pvclock gtod data */
d28ede83
TG		 1039 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1040 vdata->clock.cycle_last = tk->tkr.cycle_last;
1041 vdata->clock.mask = tk->tkr.mask;
1042 vdata->clock.mult = tk->tkr.mult;
1043 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1044
cbcf2dd3 1045 vdata->boot_ns = boot_ns;
d28ede83 1046 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1047
1048 write_seqcount_end(&vdata->seq);
1049}
1050#endif
1051
1052
18068523
GOC		 1053static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1054{
9ed3c444
AK		 1055 int version;
1056 int r;
50d0a0f9 1057 struct pvclock_wall_clock wc;
923de3cf 1058 struct timespec boot;
18068523
GOC		 1059
1060 if (!wall_clock)
1061 return;
1062
9ed3c444
AK		 1063 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1064 if (r)
1065 return;
1066
1067 if (version & 1)
1068 ++version; /* first time write, random junk */
1069
1070 ++version;
18068523 1071
18068523
GOC		 1072 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1073
50d0a0f9
GH		 1074 /*
1075 * The guest calculates current wall clock time by adding
34c238a1 1076 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1077 * wall clock specified here. guest system time equals host
1078 * system time for us, thus we must fill in host boot time here.
1079 */
923de3cf 1080 getboottime(&boot);
50d0a0f9 1081
4b648665
BR		 1082 if (kvm->arch.kvmclock_offset) {
1083 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1084 boot = timespec_sub(boot, ts);
1085 }
50d0a0f9
GH		 1086 wc.sec = boot.tv_sec;
1087 wc.nsec = boot.tv_nsec;
1088 wc.version = version;
18068523
GOC		 1089
1090 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1091
1092 version++;
1093 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1094}
1095
50d0a0f9
GH		 1096static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1097{
1098 uint32_t quotient, remainder;
1099
1100 /* Don't try to replace with do_div(), this one calculates
1101 * "(dividend << 32) / divisor" */
1102 __asm__ ( "divl %4"
1103 : "=a" (quotient), "=d" (remainder)
1104 : "0" (0), "1" (dividend), "r" (divisor) );
1105 return quotient;
1106}
1107
5f4e3f88
ZA		 1108static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1109 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1110{
5f4e3f88 1111 uint64_t scaled64;
50d0a0f9
GH		 1112 int32_t shift = 0;
1113 uint64_t tps64;
1114 uint32_t tps32;
1115
5f4e3f88
ZA		 1116 tps64 = base_khz * 1000LL;
1117 scaled64 = scaled_khz * 1000LL;
50933623 1118 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1119 tps64 >>= 1;
1120 shift--;
1121 }
1122
1123 tps32 = (uint32_t)tps64;
50933623
JK		 1124 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1125 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1126 scaled64 >>= 1;
1127 else
1128 tps32 <<= 1;
50d0a0f9
GH		 1129 shift++;
1130 }
1131
5f4e3f88
ZA		 1132 *pshift = shift;
1133 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1134
5f4e3f88
ZA		 1135 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1136 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1137}
1138
759379dd
ZA		 1139static inline u64 get_kernel_ns(void)
1140{
bb0b5812 1141 return ktime_get_boot_ns();
50d0a0f9
GH		 1142}
1143
d828199e 1144#ifdef CONFIG_X86_64
16e8d74d 1145static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1146#endif
16e8d74d 1147
c8076604 1148static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1149unsigned long max_tsc_khz;
c8076604 1150
cc578287 1151static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1152{
cc578287
ZA		 1153 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1154 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1155}
1156
cc578287 1157static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1158{
cc578287
ZA		 1159 u64 v = (u64)khz * (1000000 + ppm);
1160 do_div(v, 1000000);
1161 return v;
1e993611
JR		 1162}
1163
cc578287 1164static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1165{
cc578287
ZA		 1166 u32 thresh_lo, thresh_hi;
1167 int use_scaling = 0;
217fc9cf 1168
03ba32ca
MT		 1169 /* tsc_khz can be zero if TSC calibration fails */
1170 if (this_tsc_khz == 0)
1171 return;
1172
c285545f
ZA		 1173 /* Compute a scale to convert nanoseconds in TSC cycles */
1174 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1175 &vcpu->arch.virtual_tsc_shift,
1176 &vcpu->arch.virtual_tsc_mult);
1177 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1178
1179 /*
1180 * Compute the variation in TSC rate which is acceptable
1181 * within the range of tolerance and decide if the
1182 * rate being applied is within that bounds of the hardware
1183 * rate. If so, no scaling or compensation need be done.
1184 */
1185 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1186 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1187 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1188 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1189 use_scaling = 1;
1190 }
1191 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1192}
1193
1194static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1195{
e26101b1 1196 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1197 vcpu->arch.virtual_tsc_mult,
1198 vcpu->arch.virtual_tsc_shift);
e26101b1 1199 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1200 return tsc;
1201}
1202
b48aa97e
MT		 1203void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1204{
1205#ifdef CONFIG_X86_64
1206 bool vcpus_matched;
1207 bool do_request = false;
1208 struct kvm_arch *ka = &vcpu->kvm->arch;
1209 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1210
1211 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1212 atomic_read(&vcpu->kvm->online_vcpus));
1213
1214 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1215 if (!ka->use_master_clock)
1216 do_request = 1;
1217
1218 if (!vcpus_matched && ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (do_request)
1222 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1223
1224 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1225 atomic_read(&vcpu->kvm->online_vcpus),
1226 ka->use_master_clock, gtod->clock.vclock_mode);
1227#endif
1228}
1229
ba904635
WA		 1230static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1231{
1232 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1233 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1234}
1235
8fe8ab46 1236void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1237{
1238 struct kvm *kvm = vcpu->kvm;
f38e098f 1239 u64 offset, ns, elapsed;
99e3e30a 1240 unsigned long flags;
02626b6a 1241 s64 usdiff;
b48aa97e 1242 bool matched;
0d3da0d2 1243 bool already_matched;
8fe8ab46 1244 u64 data = msr->data;
99e3e30a 1245
038f8c11 1246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1247 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1248 ns = get_kernel_ns();
f38e098f 1249 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1250
03ba32ca 1251 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1252 int faulted = 0;
1253
03ba32ca
MT		 1254 /* n.b - signed multiplication and division required */
1255 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1256#ifdef CONFIG_X86_64
03ba32ca 1257 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1258#else
03ba32ca 1259 /* do_div() only does unsigned */
8915aa27
MT		 1260 asm("1: idivl %[divisor]\n"
1261 "2: xor %%edx, %%edx\n"
1262 " movl $0, %[faulted]\n"
1263 "3:\n"
1264 ".section .fixup,\"ax\"\n"
1265 "4: movl $1, %[faulted]\n"
1266 " jmp 3b\n"
1267 ".previous\n"
1268
1269 _ASM_EXTABLE(1b, 4b)
1270
1271 : "=A"(usdiff), [faulted] "=r" (faulted)
1272 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1273
5d3cb0f6 1274#endif
03ba32ca
MT		 1275 do_div(elapsed, 1000);
1276 usdiff -= elapsed;
1277 if (usdiff < 0)
1278 usdiff = -usdiff;
8915aa27
MT		 1279
1280 /* idivl overflow => difference is larger than USEC_PER_SEC */
1281 if (faulted)
1282 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1283 } else
1284 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1285
1286 /*
5d3cb0f6
ZA		 1287 * Special case: TSC write with a small delta (1 second) of virtual
1288 * cycle time against real time is interpreted as an attempt to
1289 * synchronize the CPU.
1290 *
1291 * For a reliable TSC, we can match TSC offsets, and for an unstable
1292 * TSC, we add elapsed time in this computation. We could let the
1293 * compensation code attempt to catch up if we fall behind, but
1294 * it's better to try to match offsets from the beginning.
1295 */
02626b6a 1296 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1297 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1298 if (!check_tsc_unstable()) {
e26101b1 1299 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1300 pr_debug("kvm: matched tsc offset for %llu\n", data);
1301 } else {
857e4099 1302 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1303 data += delta;
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1306 }
b48aa97e 1307 matched = true;
0d3da0d2 1308 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1309 } else {
1310 /*
1311 * We split periods of matched TSC writes into generations.
1312 * For each generation, we track the original measured
1313 * nanosecond time, offset, and write, so if TSCs are in
1314 * sync, we can match exact offset, and if not, we can match
4a969980 1315 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1316 *
1317 * These values are tracked in kvm->arch.cur_xxx variables.
1318 */
1319 kvm->arch.cur_tsc_generation++;
1320 kvm->arch.cur_tsc_nsec = ns;
1321 kvm->arch.cur_tsc_write = data;
1322 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1323 matched = false;
0d3da0d2 1324 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1325 kvm->arch.cur_tsc_generation, data);
f38e098f 1326 }
e26101b1
ZA		 1327
1328 /*
1329 * We also track th most recent recorded KHZ, write and time to
1330 * allow the matching interval to be extended at each write.
1331 */
f38e098f
ZA		 1332 kvm->arch.last_tsc_nsec = ns;
1333 kvm->arch.last_tsc_write = data;
5d3cb0f6 1334 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1335
b183aa58 1336 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1337
1338 /* Keep track of which generation this VCPU has synchronized to */
1339 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1340 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1341 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1342
ba904635
WA		 1343 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1344 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1345 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1346 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1347
1348 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1349 if (!matched) {
b48aa97e 1350 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1351 } else if (!already_matched) {
1352 kvm->arch.nr_vcpus_matched_tsc++;
1353 }
b48aa97e
MT		 1354
1355 kvm_track_tsc_matching(vcpu);
1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1357}
e26101b1 1358
99e3e30a
ZA		 1359EXPORT_SYMBOL_GPL(kvm_write_tsc);
1360
d828199e
MT		 1361#ifdef CONFIG_X86_64
1362
1363static cycle_t read_tsc(void)
1364{
1365 cycle_t ret;
1366 u64 last;
1367
1368 /*
1369 * Empirically, a fence (of type that depends on the CPU)
1370 * before rdtsc is enough to ensure that rdtsc is ordered
1371 * with respect to loads. The various CPU manuals are unclear
1372 * as to whether rdtsc can be reordered with later loads,
1373 * but no one has ever seen it happen.
1374 */
1375 rdtsc_barrier();
1376 ret = (cycle_t)vget_cycles();
1377
1378 last = pvclock_gtod_data.clock.cycle_last;
1379
1380 if (likely(ret >= last))
1381 return ret;
1382
1383 /*
1384 * GCC likes to generate cmov here, but this branch is extremely
1385 * predictable (it's just a funciton of time and the likely is
1386 * very likely) and there's a data dependence, so force GCC
1387 * to generate a branch instead. I don't barrier() because
1388 * we don't actually need a barrier, and if this function
1389 * ever gets inlined it will generate worse code.
1390 */
1391 asm volatile ("");
1392 return last;
1393}
1394
1395static inline u64 vgettsc(cycle_t *cycle_now)
1396{
1397 long v;
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1399
1400 *cycle_now = read_tsc();
1401
1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1403 return v * gtod->clock.mult;
1404}
1405
cbcf2dd3 1406static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1407{
cbcf2dd3 1408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1409 unsigned long seq;
d828199e 1410 int mode;
cbcf2dd3 1411 u64 ns;
d828199e 1412
d828199e
MT		 1413 do {
1414 seq = read_seqcount_begin(&gtod->seq);
1415 mode = gtod->clock.vclock_mode;
cbcf2dd3 1416 ns = gtod->nsec_base;
d828199e
MT		 1417 ns += vgettsc(cycle_now);
1418 ns >>= gtod->clock.shift;
cbcf2dd3 1419 ns += gtod->boot_ns;
d828199e 1420 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1421 *t = ns;
d828199e
MT		 1422
1423 return mode;
1424}
1425
1426/* returns true if host is using tsc clocksource */
1427static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1428{
d828199e
MT		 1429 /* checked again under seqlock below */
1430 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1431 return false;
1432
cbcf2dd3 1433 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1434}
1435#endif
1436
1437/*
1438 *
b48aa97e
MT		 1439 * Assuming a stable TSC across physical CPUS, and a stable TSC
1440 * across virtual CPUs, the following condition is possible.
1441 * Each numbered line represents an event visible to both
d828199e
MT		 1442 * CPUs at the next numbered event.
1443 *
1444 * "timespecX" represents host monotonic time. "tscX" represents
1445 * RDTSC value.
1446 *
1447 * VCPU0 on CPU0 | VCPU1 on CPU1
1448 *
1449 * 1. read timespec0,tsc0
1450 * 2. | timespec1 = timespec0 + N
1451 * | tsc1 = tsc0 + M
1452 * 3. transition to guest | transition to guest
1453 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1454 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1455 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1456 *
1457 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1458 *
1459 * - ret0 < ret1
1460 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1461 * ...
1462 * - 0 < N - M => M < N
1463 *
1464 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1465 * always the case (the difference between two distinct xtime instances
1466 * might be smaller then the difference between corresponding TSC reads,
1467 * when updating guest vcpus pvclock areas).
1468 *
1469 * To avoid that problem, do not allow visibility of distinct
1470 * system_timestamp/tsc_timestamp values simultaneously: use a master
1471 * copy of host monotonic time values. Update that master copy
1472 * in lockstep.
1473 *
b48aa97e 1474 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1475 *
1476 */
1477
1478static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1479{
1480#ifdef CONFIG_X86_64
1481 struct kvm_arch *ka = &kvm->arch;
1482 int vclock_mode;
b48aa97e
MT		 1483 bool host_tsc_clocksource, vcpus_matched;
1484
1485 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1486 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1487
1488 /*
1489 * If the host uses TSC clock, then passthrough TSC as stable
1490 * to the guest.
1491 */
b48aa97e 1492 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1493 &ka->master_kernel_ns,
1494 &ka->master_cycle_now);
1495
16a96021
MT		 1496 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1497 && !backwards_tsc_observed;
b48aa97e 1498
d828199e
MT		 1499 if (ka->use_master_clock)
1500 atomic_set(&kvm_guest_has_master_clock, 1);
1501
1502 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1503 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1504 vcpus_matched);
d828199e
MT		 1505#endif
1506}
1507
2e762ff7
MT		 1508static void kvm_gen_update_masterclock(struct kvm *kvm)
1509{
1510#ifdef CONFIG_X86_64
1511 int i;
1512 struct kvm_vcpu *vcpu;
1513 struct kvm_arch *ka = &kvm->arch;
1514
1515 spin_lock(&ka->pvclock_gtod_sync_lock);
1516 kvm_make_mclock_inprogress_request(kvm);
1517 /* no guest entries from this point */
1518 pvclock_update_vm_gtod_copy(kvm);
1519
1520 kvm_for_each_vcpu(i, vcpu, kvm)
1521 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1522
1523 /* guest entries allowed */
1524 kvm_for_each_vcpu(i, vcpu, kvm)
1525 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1526
1527 spin_unlock(&ka->pvclock_gtod_sync_lock);
1528#endif
1529}
1530
34c238a1 1531static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1532{
d828199e 1533 unsigned long flags, this_tsc_khz;
18068523 1534 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1535 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1536 s64 kernel_ns;
d828199e 1537 u64 tsc_timestamp, host_tsc;
0b79459b 1538 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1539 u8 pvclock_flags;
d828199e
MT		 1540 bool use_master_clock;
1541
1542 kernel_ns = 0;
1543 host_tsc = 0;
18068523 1544
d828199e
MT		 1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
1549 spin_lock(&ka->pvclock_gtod_sync_lock);
1550 use_master_clock = ka->use_master_clock;
1551 if (use_master_clock) {
1552 host_tsc = ka->master_cycle_now;
1553 kernel_ns = ka->master_kernel_ns;
1554 }
1555 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1556
1557 /* Keep irq disabled to prevent changes to the clock */
1558 local_irq_save(flags);
1559 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1560 if (unlikely(this_tsc_khz == 0)) {
1561 local_irq_restore(flags);
1562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1563 return 1;
1564 }
d828199e
MT		 1565 if (!use_master_clock) {
1566 host_tsc = native_read_tsc();
1567 kernel_ns = get_kernel_ns();
1568 }
1569
1570 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1571
c285545f
ZA		 1572 /*
1573 * We may have to catch up the TSC to match elapsed wall clock
1574 * time for two reasons, even if kvmclock is used.
1575 * 1) CPU could have been running below the maximum TSC rate
1576 * 2) Broken TSC compensation resets the base at each VCPU
1577 * entry to avoid unknown leaps of TSC even when running
1578 * again on the same CPU. This may cause apparent elapsed
1579 * time to disappear, and the guest to stand still or run
1580 * very slowly.
1581 */
1582 if (vcpu->tsc_catchup) {
1583 u64 tsc = compute_guest_tsc(v, kernel_ns);
1584 if (tsc > tsc_timestamp) {
f1e2b260 1585 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1586 tsc_timestamp = tsc;
1587 }
50d0a0f9
GH		 1588 }
1589
18068523
GOC		 1590 local_irq_restore(flags);
1591
0b79459b 1592 if (!vcpu->pv_time_enabled)
c285545f 1593 return 0;
18068523 1594
e48672fa 1595 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1596 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1597 &vcpu->hv_clock.tsc_shift,
1598 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1599 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1600 }
1601
1602 /* With all the info we got, fill in the values */
1d5f066e 1603 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1604 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1605 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1606
18068523
GOC		 1607 /*
1608 * The interface expects us to write an even number signaling that the
1609 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1610 * state, we just increase by 2 at the end.
18068523 1611 */
50d0a0f9 1612 vcpu->hv_clock.version += 2;
18068523 1613
0b79459b
AH		 1614 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1615 &guest_hv_clock, sizeof(guest_hv_clock))))
1616 return 0;
78c0337a
MT		 1617
1618 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1619 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1620
1621 if (vcpu->pvclock_set_guest_stopped_request) {
1622 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1623 vcpu->pvclock_set_guest_stopped_request = false;
1624 }
1625
d828199e
MT		 1626 /* If the host uses TSC clocksource, then it is stable */
1627 if (use_master_clock)
1628 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1629
78c0337a
MT		 1630 vcpu->hv_clock.flags = pvclock_flags;
1631
0b79459b
AH		 1632 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1633 &vcpu->hv_clock,
1634 sizeof(vcpu->hv_clock));
8cfdc000 1635 return 0;
c8076604
GH		 1636}
1637
0061d53d
MT		 1638/*
1639 * kvmclock updates which are isolated to a given vcpu, such as
1640 * vcpu->cpu migration, should not allow system_timestamp from
1641 * the rest of the vcpus to remain static. Otherwise ntp frequency
1642 * correction applies to one vcpu's system_timestamp but not
1643 * the others.
1644 *
1645 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1646 * We need to rate-limit these requests though, as they can
1647 * considerably slow guests that have a large number of vcpus.
1648 * The time for a remote vcpu to update its kvmclock is bound
1649 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1650 */
1651
7e44e449
AJ		 1652#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1653
1654static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1655{
1656 int i;
7e44e449
AJ		 1657 struct delayed_work *dwork = to_delayed_work(work);
1658 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1659 kvmclock_update_work);
1660 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1661 struct kvm_vcpu *vcpu;
1662
1663 kvm_for_each_vcpu(i, vcpu, kvm) {
1664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1665 kvm_vcpu_kick(vcpu);
1666 }
1667}
1668
7e44e449
AJ		 1669static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1670{
1671 struct kvm *kvm = v->kvm;
1672
1673 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1675 KVMCLOCK_UPDATE_DELAY);
1676}
1677
332967a3
AJ		 1678#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1679
1680static void kvmclock_sync_fn(struct work_struct *work)
1681{
1682 struct delayed_work *dwork = to_delayed_work(work);
1683 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1684 kvmclock_sync_work);
1685 struct kvm *kvm = container_of(ka, struct kvm, arch);
1686
1687 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1688 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1689 KVMCLOCK_SYNC_PERIOD);
1690}
1691
9ba075a6
AK		 1692static bool msr_mtrr_valid(unsigned msr)
1693{
1694 switch (msr) {
1695 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1696 case MSR_MTRRfix64K_00000:
1697 case MSR_MTRRfix16K_80000:
1698 case MSR_MTRRfix16K_A0000:
1699 case MSR_MTRRfix4K_C0000:
1700 case MSR_MTRRfix4K_C8000:
1701 case MSR_MTRRfix4K_D0000:
1702 case MSR_MTRRfix4K_D8000:
1703 case MSR_MTRRfix4K_E0000:
1704 case MSR_MTRRfix4K_E8000:
1705 case MSR_MTRRfix4K_F0000:
1706 case MSR_MTRRfix4K_F8000:
1707 case MSR_MTRRdefType:
1708 case MSR_IA32_CR_PAT:
1709 return true;
1710 case 0x2f8:
1711 return true;
1712 }
1713 return false;
1714}
1715
d6289b93
MT		 1716static bool valid_pat_type(unsigned t)
1717{
1718 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1719}
1720
1721static bool valid_mtrr_type(unsigned t)
1722{
1723 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1724}
1725
1726static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1727{
1728 int i;
d7a2a246 1729 u64 mask = 0;
d6289b93
MT		 1730
1731 if (!msr_mtrr_valid(msr))
1732 return false;
1733
1734 if (msr == MSR_IA32_CR_PAT) {
1735 for (i = 0; i < 8; i++)
1736 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1737 return false;
1738 return true;
1739 } else if (msr == MSR_MTRRdefType) {
1740 if (data & ~0xcff)
1741 return false;
1742 return valid_mtrr_type(data & 0xff);
1743 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1744 for (i = 0; i < 8 ; i++)
1745 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1746 return false;
1747 return true;
1748 }
1749
1750 /* variable MTRRs */
adfb5d27
WL		 1751 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1752
d7a2a246
WL		 1753 for (i = 63; i > boot_cpu_data.x86_phys_bits; i--)
1754 mask |= (1ULL << i);
1755 if ((msr & 1) == 0) {
adfb5d27 1756 /* MTRR base */
d7a2a246
WL		 1757 if (!valid_mtrr_type(data & 0xff))
1758 return false;
1759 mask |= 0xf00;
1760 } else
1761 /* MTRR mask */
1762 mask |= 0x7ff;
1763 if (data & mask) {
1764 kvm_inject_gp(vcpu, 0);
1765 return false;
1766 }
1767
adfb5d27 1768 return true;
d6289b93
MT		 1769}
1770
9ba075a6
AK		 1771static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1772{
0bed3b56
SY		 1773 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1774
d6289b93 1775 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1776 return 1;
1777
0bed3b56
SY		 1778 if (msr == MSR_MTRRdefType) {
1779 vcpu->arch.mtrr_state.def_type = data;
1780 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1781 } else if (msr == MSR_MTRRfix64K_00000)
1782 p[0] = data;
1783 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1784 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1785 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1786 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1787 else if (msr == MSR_IA32_CR_PAT)
1788 vcpu->arch.pat = data;
1789 else { /* Variable MTRRs */
1790 int idx, is_mtrr_mask;
1791 u64 *pt;
1792
1793 idx = (msr - 0x200) / 2;
1794 is_mtrr_mask = msr - 0x200 - 2 * idx;
1795 if (!is_mtrr_mask)
1796 pt =
1797 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1798 else
1799 pt =
1800 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1801 *pt = data;
1802 }
1803
1804 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1805 return 0;
1806}
15c4a640 1807
890ca9ae 1808static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1809{
890ca9ae
HY		 1810 u64 mcg_cap = vcpu->arch.mcg_cap;
1811 unsigned bank_num = mcg_cap & 0xff;
1812
15c4a640 1813 switch (msr) {
15c4a640 1814 case MSR_IA32_MCG_STATUS:
890ca9ae 1815 vcpu->arch.mcg_status = data;
15c4a640 1816 break;
c7ac679c 1817 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1818 if (!(mcg_cap & MCG_CTL_P))
1819 return 1;
1820 if (data != 0 && data != ~(u64)0)
1821 return -1;
1822 vcpu->arch.mcg_ctl = data;
1823 break;
1824 default:
1825 if (msr >= MSR_IA32_MC0_CTL &&
1826 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1827 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1828 /* only 0 or all 1s can be written to IA32_MCi_CTL
1829 * some Linux kernels though clear bit 10 in bank 4 to
1830 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1831 * this to avoid an uncatched #GP in the guest
1832 */
890ca9ae 1833 if ((offset & 0x3) == 0 &&
114be429 1834 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1835 return -1;
1836 vcpu->arch.mce_banks[offset] = data;
1837 break;
1838 }
1839 return 1;
1840 }
1841 return 0;
1842}
1843
ffde22ac
ES		 1844static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1845{
1846 struct kvm *kvm = vcpu->kvm;
1847 int lm = is_long_mode(vcpu);
1848 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1849 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1850 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1851 : kvm->arch.xen_hvm_config.blob_size_32;
1852 u32 page_num = data & ~PAGE_MASK;
1853 u64 page_addr = data & PAGE_MASK;
1854 u8 *page;
1855 int r;
1856
1857 r = -E2BIG;
1858 if (page_num >= blob_size)
1859 goto out;
1860 r = -ENOMEM;
ff5c2c03
SL		 1861 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1862 if (IS_ERR(page)) {
1863 r = PTR_ERR(page);
ffde22ac 1864 goto out;
ff5c2c03 1865 }
ffde22ac
ES		 1866 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1867 goto out_free;
1868 r = 0;
1869out_free:
1870 kfree(page);
1871out:
1872 return r;
1873}
1874
55cd8e5a
GN		 1875static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1876{
1877 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1878}
1879
1880static bool kvm_hv_msr_partition_wide(u32 msr)
1881{
1882 bool r = false;
1883 switch (msr) {
1884 case HV_X64_MSR_GUEST_OS_ID:
1885 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1886 case HV_X64_MSR_REFERENCE_TSC:
1887 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1888 r = true;
1889 break;
1890 }
1891
1892 return r;
1893}
1894
1895static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1896{
1897 struct kvm *kvm = vcpu->kvm;
1898
1899 switch (msr) {
1900 case HV_X64_MSR_GUEST_OS_ID:
1901 kvm->arch.hv_guest_os_id = data;
1902 /* setting guest os id to zero disables hypercall page */
1903 if (!kvm->arch.hv_guest_os_id)
1904 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1905 break;
1906 case HV_X64_MSR_HYPERCALL: {
1907 u64 gfn;
1908 unsigned long addr;
1909 u8 instructions[4];
1910
1911 /* if guest os id is not set hypercall should remain disabled */
1912 if (!kvm->arch.hv_guest_os_id)
1913 break;
1914 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1915 kvm->arch.hv_hypercall = data;
1916 break;
1917 }
1918 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1919 addr = gfn_to_hva(kvm, gfn);
1920 if (kvm_is_error_hva(addr))
1921 return 1;
1922 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1923 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1924 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1925 return 1;
1926 kvm->arch.hv_hypercall = data;
b94b64c9 1927 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1928 break;
1929 }
e984097b
VR		 1930 case HV_X64_MSR_REFERENCE_TSC: {
1931 u64 gfn;
1932 HV_REFERENCE_TSC_PAGE tsc_ref;
1933 memset(&tsc_ref, 0, sizeof(tsc_ref));
1934 kvm->arch.hv_tsc_page = data;
1935 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1936 break;
1937 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1938 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1939 &tsc_ref, sizeof(tsc_ref)))
1940 return 1;
1941 mark_page_dirty(kvm, gfn);
1942 break;
1943 }
55cd8e5a 1944 default:
a737f256
CD		 1945 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1946 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1947 return 1;
1948 }
1949 return 0;
1950}
1951
1952static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1953{
10388a07
GN		 1954 switch (msr) {
1955 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1956 u64 gfn;
10388a07 1957 unsigned long addr;
55cd8e5a 1958
10388a07
GN		 1959 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1960 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1961 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1962 return 1;
10388a07
GN		 1963 break;
1964 }
b3af1e88
VR		 1965 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1966 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1967 if (kvm_is_error_hva(addr))
1968 return 1;
8b0cedff 1969 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1970 return 1;
1971 vcpu->arch.hv_vapic = data;
b3af1e88 1972 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1973 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1974 return 1;
10388a07
GN		 1975 break;
1976 }
1977 case HV_X64_MSR_EOI:
1978 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1979 case HV_X64_MSR_ICR:
1980 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1981 case HV_X64_MSR_TPR:
1982 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1983 default:
a737f256
CD		 1984 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1985 "data 0x%llx\n", msr, data);
10388a07
GN		 1986 return 1;
1987 }
1988
1989 return 0;
55cd8e5a
GN		 1990}
1991
344d9588
GN		 1992static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1993{
1994 gpa_t gpa = data & ~0x3f;
1995
4a969980 1996 /* Bits 2:5 are reserved, Should be zero */
6adba527 1997 if (data & 0x3c)
344d9588
GN		 1998 return 1;
1999
2000 vcpu->arch.apf.msr_val = data;
2001
2002 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2003 kvm_clear_async_pf_completion_queue(vcpu);
2004 kvm_async_pf_hash_reset(vcpu);
2005 return 0;
2006 }
2007
8f964525
AH		 2008 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2009 sizeof(u32)))
344d9588
GN		 2010 return 1;
2011
6adba527 2012 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2013 kvm_async_pf_wakeup_all(vcpu);
2014 return 0;
2015}
2016
12f9a48f
GC		 2017static void kvmclock_reset(struct kvm_vcpu *vcpu)
2018{
0b79459b 2019 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2020}
2021
c9aaa895
GC		 2022static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2023{
2024 u64 delta;
2025
2026 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2027 return;
2028
2029 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2030 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2031 vcpu->arch.st.accum_steal = delta;
2032}
2033
2034static void record_steal_time(struct kvm_vcpu *vcpu)
2035{
2036 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2037 return;
2038
2039 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2040 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2041 return;
2042
2043 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2044 vcpu->arch.st.steal.version += 2;
2045 vcpu->arch.st.accum_steal = 0;
2046
2047 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2048 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2049}
2050
8fe8ab46 2051int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2052{
5753785f 2053 bool pr = false;
8fe8ab46
WA		 2054 u32 msr = msr_info->index;
2055 u64 data = msr_info->data;
5753785f 2056
15c4a640 2057 switch (msr) {
2e32b719
BP		 2058 case MSR_AMD64_NB_CFG:
2059 case MSR_IA32_UCODE_REV:
2060 case MSR_IA32_UCODE_WRITE:
2061 case MSR_VM_HSAVE_PA:
2062 case MSR_AMD64_PATCH_LOADER:
2063 case MSR_AMD64_BU_CFG2:
2064 break;
2065
15c4a640 2066 case MSR_EFER:
b69e8cae 2067 return set_efer(vcpu, data);
8f1589d9
AP		 2068 case MSR_K7_HWCR:
2069 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2070 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2071 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2072 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2073 if (data != 0) {
a737f256
CD		 2074 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2075 data);
8f1589d9
AP		 2076 return 1;
2077 }
15c4a640 2078 break;
f7c6d140
AP		 2079 case MSR_FAM10H_MMIO_CONF_BASE:
2080 if (data != 0) {
a737f256
CD		 2081 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2082 "0x%llx\n", data);
f7c6d140
AP		 2083 return 1;
2084 }
15c4a640 2085 break;
b5e2fec0
AG		 2086 case MSR_IA32_DEBUGCTLMSR:
2087 if (!data) {
2088 /* We support the non-activated case already */
2089 break;
2090 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2091 /* Values other than LBR and BTF are vendor-specific,
2092 thus reserved and should throw a #GP */
2093 return 1;
2094 }
a737f256
CD		 2095 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2096 __func__, data);
b5e2fec0 2097 break;
9ba075a6
AK		 2098 case 0x200 ... 0x2ff:
2099 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2100 case MSR_IA32_APICBASE:
58cb628d 2101 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2102 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2103 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2104 case MSR_IA32_TSCDEADLINE:
2105 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2106 break;
ba904635
WA		 2107 case MSR_IA32_TSC_ADJUST:
2108 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2109 if (!msr_info->host_initiated) {
2110 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2111 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2112 }
2113 vcpu->arch.ia32_tsc_adjust_msr = data;
2114 }
2115 break;
15c4a640 2116 case MSR_IA32_MISC_ENABLE:
ad312c7c 2117 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2118 break;
11c6bffa 2119 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2120 case MSR_KVM_WALL_CLOCK:
2121 vcpu->kvm->arch.wall_clock = data;
2122 kvm_write_wall_clock(vcpu->kvm, data);
2123 break;
11c6bffa 2124 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2125 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2126 u64 gpa_offset;
12f9a48f 2127 kvmclock_reset(vcpu);
18068523
GOC		 2128
2129 vcpu->arch.time = data;
0061d53d 2130 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2131
2132 /* we verify if the enable bit is set... */
2133 if (!(data & 1))
2134 break;
2135
0b79459b 2136 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2137
0b79459b 2138 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2139 &vcpu->arch.pv_time, data & ~1ULL,
2140 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2141 vcpu->arch.pv_time_enabled = false;
2142 else
2143 vcpu->arch.pv_time_enabled = true;
32cad84f 2144
18068523
GOC		 2145 break;
2146 }
344d9588
GN		 2147 case MSR_KVM_ASYNC_PF_EN:
2148 if (kvm_pv_enable_async_pf(vcpu, data))
2149 return 1;
2150 break;
c9aaa895
GC		 2151 case MSR_KVM_STEAL_TIME:
2152
2153 if (unlikely(!sched_info_on()))
2154 return 1;
2155
2156 if (data & KVM_STEAL_RESERVED_MASK)
2157 return 1;
2158
2159 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2160 data & KVM_STEAL_VALID_BITS,
2161 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2162 return 1;
2163
2164 vcpu->arch.st.msr_val = data;
2165
2166 if (!(data & KVM_MSR_ENABLED))
2167 break;
2168
2169 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2170
2171 preempt_disable();
2172 accumulate_steal_time(vcpu);
2173 preempt_enable();
2174
2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2176
2177 break;
ae7a2a3f
MT		 2178 case MSR_KVM_PV_EOI_EN:
2179 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2180 return 1;
2181 break;
c9aaa895 2182
890ca9ae
HY		 2183 case MSR_IA32_MCG_CTL:
2184 case MSR_IA32_MCG_STATUS:
2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2186 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2187
2188 /* Performance counters are not protected by a CPUID bit,
2189 * so we should check all of them in the generic path for the sake of
2190 * cross vendor migration.
2191 * Writing a zero into the event select MSRs disables them,
2192 * which we perfectly emulate ;-). Any other value should be at least
2193 * reported, some guests depend on them.
2194 */
71db6023
AP		 2195 case MSR_K7_EVNTSEL0:
2196 case MSR_K7_EVNTSEL1:
2197 case MSR_K7_EVNTSEL2:
2198 case MSR_K7_EVNTSEL3:
2199 if (data != 0)
a737f256
CD		 2200 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2201 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2202 break;
2203 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2204 * so we ignore writes to make it happy.
2205 */
71db6023
AP		 2206 case MSR_K7_PERFCTR0:
2207 case MSR_K7_PERFCTR1:
2208 case MSR_K7_PERFCTR2:
2209 case MSR_K7_PERFCTR3:
a737f256
CD		 2210 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2211 "0x%x data 0x%llx\n", msr, data);
71db6023 2212 break;
5753785f
GN		 2213 case MSR_P6_PERFCTR0:
2214 case MSR_P6_PERFCTR1:
2215 pr = true;
2216 case MSR_P6_EVNTSEL0:
2217 case MSR_P6_EVNTSEL1:
2218 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2219 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2220
2221 if (pr || data != 0)
a737f256
CD		 2222 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2223 "0x%x data 0x%llx\n", msr, data);
5753785f 2224 break;
84e0cefa
JS		 2225 case MSR_K7_CLK_CTL:
2226 /*
2227 * Ignore all writes to this no longer documented MSR.
2228 * Writes are only relevant for old K7 processors,
2229 * all pre-dating SVM, but a recommended workaround from
4a969980 2230 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2231 * affected processor models on the command line, hence
2232 * the need to ignore the workaround.
2233 */
2234 break;
55cd8e5a
GN		 2235 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2236 if (kvm_hv_msr_partition_wide(msr)) {
2237 int r;
2238 mutex_lock(&vcpu->kvm->lock);
2239 r = set_msr_hyperv_pw(vcpu, msr, data);
2240 mutex_unlock(&vcpu->kvm->lock);
2241 return r;
2242 } else
2243 return set_msr_hyperv(vcpu, msr, data);
2244 break;
91c9c3ed 2245 case MSR_IA32_BBL_CR_CTL3:
2246 /* Drop writes to this legacy MSR -- see rdmsr
2247 * counterpart for further detail.
2248 */
a737f256 2249 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2250 break;
2b036c6b
BO		 2251 case MSR_AMD64_OSVW_ID_LENGTH:
2252 if (!guest_cpuid_has_osvw(vcpu))
2253 return 1;
2254 vcpu->arch.osvw.length = data;
2255 break;
2256 case MSR_AMD64_OSVW_STATUS:
2257 if (!guest_cpuid_has_osvw(vcpu))
2258 return 1;
2259 vcpu->arch.osvw.status = data;
2260 break;
15c4a640 2261 default:
ffde22ac
ES		 2262 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2263 return xen_hvm_config(vcpu, data);
f5132b01 2264 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2265 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2266 if (!ignore_msrs) {
a737f256
CD		 2267 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2268 msr, data);
ed85c068
AP		 2269 return 1;
2270 } else {
a737f256
CD		 2271 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2272 msr, data);
ed85c068
AP		 2273 break;
2274 }
15c4a640
CO		 2275 }
2276 return 0;
2277}
2278EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2279
2280
2281/*
2282 * Reads an msr value (of 'msr_index') into 'pdata'.
2283 * Returns 0 on success, non-0 otherwise.
2284 * Assumes vcpu_load() was already called.
2285 */
2286int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2287{
2288 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2289}
2290
9ba075a6
AK		 2291static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2292{
0bed3b56
SY		 2293 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2294
9ba075a6
AK		 2295 if (!msr_mtrr_valid(msr))
2296 return 1;
2297
0bed3b56
SY		 2298 if (msr == MSR_MTRRdefType)
2299 *pdata = vcpu->arch.mtrr_state.def_type +
2300 (vcpu->arch.mtrr_state.enabled << 10);
2301 else if (msr == MSR_MTRRfix64K_00000)
2302 *pdata = p[0];
2303 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2304 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2305 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2306 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2307 else if (msr == MSR_IA32_CR_PAT)
2308 *pdata = vcpu->arch.pat;
2309 else { /* Variable MTRRs */
2310 int idx, is_mtrr_mask;
2311 u64 *pt;
2312
2313 idx = (msr - 0x200) / 2;
2314 is_mtrr_mask = msr - 0x200 - 2 * idx;
2315 if (!is_mtrr_mask)
2316 pt =
2317 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2318 else
2319 pt =
2320 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2321 *pdata = *pt;
2322 }
2323
9ba075a6
AK		 2324 return 0;
2325}
2326
890ca9ae 2327static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2328{
2329 u64 data;
890ca9ae
HY		 2330 u64 mcg_cap = vcpu->arch.mcg_cap;
2331 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2332
2333 switch (msr) {
15c4a640
CO		 2334 case MSR_IA32_P5_MC_ADDR:
2335 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2336 data = 0;
2337 break;
15c4a640 2338 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2339 data = vcpu->arch.mcg_cap;
2340 break;
c7ac679c 2341 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2342 if (!(mcg_cap & MCG_CTL_P))
2343 return 1;
2344 data = vcpu->arch.mcg_ctl;
2345 break;
2346 case MSR_IA32_MCG_STATUS:
2347 data = vcpu->arch.mcg_status;
2348 break;
2349 default:
2350 if (msr >= MSR_IA32_MC0_CTL &&
2351 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2352 u32 offset = msr - MSR_IA32_MC0_CTL;
2353 data = vcpu->arch.mce_banks[offset];
2354 break;
2355 }
2356 return 1;
2357 }
2358 *pdata = data;
2359 return 0;
2360}
2361
55cd8e5a
GN		 2362static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2363{
2364 u64 data = 0;
2365 struct kvm *kvm = vcpu->kvm;
2366
2367 switch (msr) {
2368 case HV_X64_MSR_GUEST_OS_ID:
2369 data = kvm->arch.hv_guest_os_id;
2370 break;
2371 case HV_X64_MSR_HYPERCALL:
2372 data = kvm->arch.hv_hypercall;
2373 break;
e984097b
VR		 2374 case HV_X64_MSR_TIME_REF_COUNT: {
2375 data =
2376 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2377 break;
2378 }
2379 case HV_X64_MSR_REFERENCE_TSC:
2380 data = kvm->arch.hv_tsc_page;
2381 break;
55cd8e5a 2382 default:
a737f256 2383 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2384 return 1;
2385 }
2386
2387 *pdata = data;
2388 return 0;
2389}
2390
2391static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2392{
2393 u64 data = 0;
2394
2395 switch (msr) {
2396 case HV_X64_MSR_VP_INDEX: {
2397 int r;
2398 struct kvm_vcpu *v;
684851a1
TY		 2399 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2400 if (v == vcpu) {
55cd8e5a 2401 data = r;
684851a1
TY		 2402 break;
2403 }
2404 }
55cd8e5a
GN		 2405 break;
2406 }
10388a07
GN		 2407 case HV_X64_MSR_EOI:
2408 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2409 case HV_X64_MSR_ICR:
2410 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2411 case HV_X64_MSR_TPR:
2412 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2413 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2414 data = vcpu->arch.hv_vapic;
2415 break;
55cd8e5a 2416 default:
a737f256 2417 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2418 return 1;
2419 }
2420 *pdata = data;
2421 return 0;
2422}
2423
890ca9ae
HY		 2424int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2425{
2426 u64 data;
2427
2428 switch (msr) {
890ca9ae 2429 case MSR_IA32_PLATFORM_ID:
15c4a640 2430 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2431 case MSR_IA32_DEBUGCTLMSR:
2432 case MSR_IA32_LASTBRANCHFROMIP:
2433 case MSR_IA32_LASTBRANCHTOIP:
2434 case MSR_IA32_LASTINTFROMIP:
2435 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2436 case MSR_K8_SYSCFG:
2437 case MSR_K7_HWCR:
61a6bd67 2438 case MSR_VM_HSAVE_PA:
9e699624 2439 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2440 case MSR_K7_EVNTSEL1:
2441 case MSR_K7_EVNTSEL2:
2442 case MSR_K7_EVNTSEL3:
1f3ee616 2443 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2444 case MSR_K7_PERFCTR1:
2445 case MSR_K7_PERFCTR2:
2446 case MSR_K7_PERFCTR3:
1fdbd48c 2447 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2448 case MSR_AMD64_NB_CFG:
f7c6d140 2449 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2450 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2451 data = 0;
2452 break;
5753785f
GN		 2453 case MSR_P6_PERFCTR0:
2454 case MSR_P6_PERFCTR1:
2455 case MSR_P6_EVNTSEL0:
2456 case MSR_P6_EVNTSEL1:
2457 if (kvm_pmu_msr(vcpu, msr))
2458 return kvm_pmu_get_msr(vcpu, msr, pdata);
2459 data = 0;
2460 break;
742bc670
MT		 2461 case MSR_IA32_UCODE_REV:
2462 data = 0x100000000ULL;
2463 break;
9ba075a6
AK		 2464 case MSR_MTRRcap:
2465 data = 0x500 | KVM_NR_VAR_MTRR;
2466 break;
2467 case 0x200 ... 0x2ff:
2468 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2469 case 0xcd: /* fsb frequency */
2470 data = 3;
2471 break;
7b914098
JS		 2472 /*
2473 * MSR_EBC_FREQUENCY_ID
2474 * Conservative value valid for even the basic CPU models.
2475 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2476 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2477 * and 266MHz for model 3, or 4. Set Core Clock
2478 * Frequency to System Bus Frequency Ratio to 1 (bits
2479 * 31:24) even though these are only valid for CPU
2480 * models > 2, however guests may end up dividing or
2481 * multiplying by zero otherwise.
2482 */
2483 case MSR_EBC_FREQUENCY_ID:
2484 data = 1 << 24;
2485 break;
15c4a640
CO		 2486 case MSR_IA32_APICBASE:
2487 data = kvm_get_apic_base(vcpu);
2488 break;
0105d1a5
GN		 2489 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2490 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2491 break;
a3e06bbe
LJ		 2492 case MSR_IA32_TSCDEADLINE:
2493 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2494 break;
ba904635
WA		 2495 case MSR_IA32_TSC_ADJUST:
2496 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2497 break;
15c4a640 2498 case MSR_IA32_MISC_ENABLE:
ad312c7c 2499 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2500 break;
847f0ad8
AG		 2501 case MSR_IA32_PERF_STATUS:
2502 /* TSC increment by tick */
2503 data = 1000ULL;
2504 /* CPU multiplier */
2505 data |= (((uint64_t)4ULL) << 40);
2506 break;
15c4a640 2507 case MSR_EFER:
f6801dff 2508 data = vcpu->arch.efer;
15c4a640 2509 break;
18068523 2510 case MSR_KVM_WALL_CLOCK:
11c6bffa 2511 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2512 data = vcpu->kvm->arch.wall_clock;
2513 break;
2514 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2515 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2516 data = vcpu->arch.time;
2517 break;
344d9588
GN		 2518 case MSR_KVM_ASYNC_PF_EN:
2519 data = vcpu->arch.apf.msr_val;
2520 break;
c9aaa895
GC		 2521 case MSR_KVM_STEAL_TIME:
2522 data = vcpu->arch.st.msr_val;
2523 break;
1d92128f
MT		 2524 case MSR_KVM_PV_EOI_EN:
2525 data = vcpu->arch.pv_eoi.msr_val;
2526 break;
890ca9ae
HY		 2527 case MSR_IA32_P5_MC_ADDR:
2528 case MSR_IA32_P5_MC_TYPE:
2529 case MSR_IA32_MCG_CAP:
2530 case MSR_IA32_MCG_CTL:
2531 case MSR_IA32_MCG_STATUS:
2532 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2533 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2534 case MSR_K7_CLK_CTL:
2535 /*
2536 * Provide expected ramp-up count for K7. All other
2537 * are set to zero, indicating minimum divisors for
2538 * every field.
2539 *
2540 * This prevents guest kernels on AMD host with CPU
2541 * type 6, model 8 and higher from exploding due to
2542 * the rdmsr failing.
2543 */
2544 data = 0x20000000;
2545 break;
55cd8e5a
GN		 2546 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2547 if (kvm_hv_msr_partition_wide(msr)) {
2548 int r;
2549 mutex_lock(&vcpu->kvm->lock);
2550 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2551 mutex_unlock(&vcpu->kvm->lock);
2552 return r;
2553 } else
2554 return get_msr_hyperv(vcpu, msr, pdata);
2555 break;
91c9c3ed 2556 case MSR_IA32_BBL_CR_CTL3:
2557 /* This legacy MSR exists but isn't fully documented in current
2558 * silicon. It is however accessed by winxp in very narrow
2559 * scenarios where it sets bit #19, itself documented as
2560 * a "reserved" bit. Best effort attempt to source coherent
2561 * read data here should the balance of the register be
2562 * interpreted by the guest:
2563 *
2564 * L2 cache control register 3: 64GB range, 256KB size,
2565 * enabled, latency 0x1, configured
2566 */
2567 data = 0xbe702111;
2568 break;
2b036c6b
BO		 2569 case MSR_AMD64_OSVW_ID_LENGTH:
2570 if (!guest_cpuid_has_osvw(vcpu))
2571 return 1;
2572 data = vcpu->arch.osvw.length;
2573 break;
2574 case MSR_AMD64_OSVW_STATUS:
2575 if (!guest_cpuid_has_osvw(vcpu))
2576 return 1;
2577 data = vcpu->arch.osvw.status;
2578 break;
15c4a640 2579 default:
f5132b01
GN		 2580 if (kvm_pmu_msr(vcpu, msr))
2581 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2582 if (!ignore_msrs) {
a737f256 2583 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2584 return 1;
2585 } else {
a737f256 2586 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2587 data = 0;
2588 }
2589 break;
15c4a640
CO		 2590 }
2591 *pdata = data;
2592 return 0;
2593}
2594EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2595
313a3dc7
CO		 2596/*
2597 * Read or write a bunch of msrs. All parameters are kernel addresses.
2598 *
2599 * @return number of msrs set successfully.
2600 */
2601static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2602 struct kvm_msr_entry *entries,
2603 int (*do_msr)(struct kvm_vcpu *vcpu,
2604 unsigned index, u64 *data))
2605{
f656ce01 2606 int i, idx;
313a3dc7 2607
f656ce01 2608 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2609 for (i = 0; i < msrs->nmsrs; ++i)
2610 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2611 break;
f656ce01 2612 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2613
313a3dc7
CO		 2614 return i;
2615}
2616
2617/*
2618 * Read or write a bunch of msrs. Parameters are user addresses.
2619 *
2620 * @return number of msrs set successfully.
2621 */
2622static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2623 int (*do_msr)(struct kvm_vcpu *vcpu,
2624 unsigned index, u64 *data),
2625 int writeback)
2626{
2627 struct kvm_msrs msrs;
2628 struct kvm_msr_entry *entries;
2629 int r, n;
2630 unsigned size;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2634 goto out;
2635
2636 r = -E2BIG;
2637 if (msrs.nmsrs >= MAX_IO_MSRS)
2638 goto out;
2639
313a3dc7 2640 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2641 entries = memdup_user(user_msrs->entries, size);
2642 if (IS_ERR(entries)) {
2643 r = PTR_ERR(entries);
313a3dc7 2644 goto out;
ff5c2c03 2645 }
313a3dc7
CO		 2646
2647 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2648 if (r < 0)
2649 goto out_free;
2650
2651 r = -EFAULT;
2652 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2653 goto out_free;
2654
2655 r = n;
2656
2657out_free:
7a73c028 2658 kfree(entries);
313a3dc7
CO		 2659out:
2660 return r;
2661}
2662
784aa3d7 2663int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2664{
2665 int r;
2666
2667 switch (ext) {
2668 case KVM_CAP_IRQCHIP:
2669 case KVM_CAP_HLT:
2670 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2671 case KVM_CAP_SET_TSS_ADDR:
07716717 2672 case KVM_CAP_EXT_CPUID:
9c15bb1d 2673 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2674 case KVM_CAP_CLOCKSOURCE:
7837699f 2675 case KVM_CAP_PIT:
a28e4f5a 2676 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2677 case KVM_CAP_MP_STATE:
ed848624 2678 case KVM_CAP_SYNC_MMU:
a355c85c 2679 case KVM_CAP_USER_NMI:
52d939a0 2680 case KVM_CAP_REINJECT_CONTROL:
4925663a 2681 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2682 case KVM_CAP_IRQFD:
d34e6b17 2683 case KVM_CAP_IOEVENTFD:
f848a5a8 2684 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2685 case KVM_CAP_PIT2:
e9f42757 2686 case KVM_CAP_PIT_STATE2:
b927a3ce 2687 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2688 case KVM_CAP_XEN_HVM:
afbcf7ab 2689 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2690 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2691 case KVM_CAP_HYPERV:
10388a07 2692 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2693 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2694 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2695 case KVM_CAP_DEBUGREGS:
d2be1651 2696 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2697 case KVM_CAP_XSAVE:
344d9588 2698 case KVM_CAP_ASYNC_PF:
92a1f12d 2699 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2700 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2701 case KVM_CAP_READONLY_MEM:
5f66b620 2702 case KVM_CAP_HYPERV_TIME:
100943c5 2703 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2704#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2705 case KVM_CAP_ASSIGN_DEV_IRQ:
2706 case KVM_CAP_PCI_2_3:
2707#endif
018d00d2
ZX		 2708 r = 1;
2709 break;
542472b5
LV		 2710 case KVM_CAP_COALESCED_MMIO:
2711 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2712 break;
774ead3a
AK		 2713 case KVM_CAP_VAPIC:
2714 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2715 break;
f725230a 2716 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2717 r = KVM_SOFT_MAX_VCPUS;
2718 break;
2719 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2720 r = KVM_MAX_VCPUS;
2721 break;
a988b910 2722 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2723 r = KVM_USER_MEM_SLOTS;
a988b910 2724 break;
a68a6a72
MT		 2725 case KVM_CAP_PV_MMU: /* obsolete */
2726 r = 0;
2f333bcb 2727 break;
4cee4b72 2728#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2729 case KVM_CAP_IOMMU:
a1b60c1c 2730 r = iommu_present(&pci_bus_type);
62c476c7 2731 break;
4cee4b72 2732#endif
890ca9ae
HY		 2733 case KVM_CAP_MCE:
2734 r = KVM_MAX_MCE_BANKS;
2735 break;
2d5b5a66
SY		 2736 case KVM_CAP_XCRS:
2737 r = cpu_has_xsave;
2738 break;
92a1f12d
JR		 2739 case KVM_CAP_TSC_CONTROL:
2740 r = kvm_has_tsc_control;
2741 break;
4d25a066
JK		 2742 case KVM_CAP_TSC_DEADLINE_TIMER:
2743 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2744 break;
018d00d2
ZX		 2745 default:
2746 r = 0;
2747 break;
2748 }
2749 return r;
2750
2751}
2752
043405e1
CO		 2753long kvm_arch_dev_ioctl(struct file *filp,
2754 unsigned int ioctl, unsigned long arg)
2755{
2756 void __user *argp = (void __user *)arg;
2757 long r;
2758
2759 switch (ioctl) {
2760 case KVM_GET_MSR_INDEX_LIST: {
2761 struct kvm_msr_list __user *user_msr_list = argp;
2762 struct kvm_msr_list msr_list;
2763 unsigned n;
2764
2765 r = -EFAULT;
2766 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2767 goto out;
2768 n = msr_list.nmsrs;
2769 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2770 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2771 goto out;
2772 r = -E2BIG;
e125e7b6 2773 if (n < msr_list.nmsrs)
043405e1
CO		 2774 goto out;
2775 r = -EFAULT;
2776 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2777 num_msrs_to_save * sizeof(u32)))
2778 goto out;
e125e7b6 2779 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2780 &emulated_msrs,
2781 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2782 goto out;
2783 r = 0;
2784 break;
2785 }
9c15bb1d
BP		 2786 case KVM_GET_SUPPORTED_CPUID:
2787 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2788 struct kvm_cpuid2 __user *cpuid_arg = argp;
2789 struct kvm_cpuid2 cpuid;
2790
2791 r = -EFAULT;
2792 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2793 goto out;
9c15bb1d
BP		 2794
2795 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2796 ioctl);
674eea0f
AK		 2797 if (r)
2798 goto out;
2799
2800 r = -EFAULT;
2801 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2802 goto out;
2803 r = 0;
2804 break;
2805 }
890ca9ae
HY		 2806 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2807 u64 mce_cap;
2808
2809 mce_cap = KVM_MCE_CAP_SUPPORTED;
2810 r = -EFAULT;
2811 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2812 goto out;
2813 r = 0;
2814 break;
2815 }
043405e1
CO		 2816 default:
2817 r = -EINVAL;
2818 }
2819out:
2820 return r;
2821}
2822
f5f48ee1
SY		 2823static void wbinvd_ipi(void *garbage)
2824{
2825 wbinvd();
2826}
2827
2828static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2829{
e0f0bbc5 2830 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2831}
2832
313a3dc7
CO		 2833void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2834{
f5f48ee1
SY		 2835 /* Address WBINVD may be executed by guest */
2836 if (need_emulate_wbinvd(vcpu)) {
2837 if (kvm_x86_ops->has_wbinvd_exit())
2838 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2839 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2840 smp_call_function_single(vcpu->cpu,
2841 wbinvd_ipi, NULL, 1);
2842 }
2843
313a3dc7 2844 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2845
0dd6a6ed
ZA		 2846 /* Apply any externally detected TSC adjustments (due to suspend) */
2847 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2848 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2849 vcpu->arch.tsc_offset_adjustment = 0;
2850 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2851 }
8f6055cb 2852
48434c20 2853 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2854 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2855 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2856 if (tsc_delta < 0)
2857 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2858 if (check_tsc_unstable()) {
b183aa58
ZA		 2859 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2860 vcpu->arch.last_guest_tsc);
2861 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2862 vcpu->arch.tsc_catchup = 1;
c285545f 2863 }
d98d07ca
MT		 2864 /*
2865 * On a host with synchronized TSC, there is no need to update
2866 * kvmclock on vcpu->cpu migration
2867 */
2868 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2869 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2870 if (vcpu->cpu != cpu)
2871 kvm_migrate_timers(vcpu);
e48672fa 2872 vcpu->cpu = cpu;
6b7d7e76 2873 }
c9aaa895
GC		 2874
2875 accumulate_steal_time(vcpu);
2876 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2877}
2878
2879void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2880{
02daab21 2881 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2882 kvm_put_guest_fpu(vcpu);
6f526ec5 2883 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2884}
2885
313a3dc7
CO		 2886static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2887 struct kvm_lapic_state *s)
2888{
5a71785d 2889 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2890 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2891
2892 return 0;
2893}
2894
2895static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2896 struct kvm_lapic_state *s)
2897{
64eb0620 2898 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2899 update_cr8_intercept(vcpu);
313a3dc7
CO		 2900
2901 return 0;
2902}
2903
f77bc6a4
ZX		 2904static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2905 struct kvm_interrupt *irq)
2906{
02cdb50f 2907 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2908 return -EINVAL;
2909 if (irqchip_in_kernel(vcpu->kvm))
2910 return -ENXIO;
f77bc6a4 2911
66fd3f7f 2912 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2913 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2914
f77bc6a4
ZX		 2915 return 0;
2916}
2917
c4abb7c9
JK		 2918static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2919{
c4abb7c9 2920 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2921
2922 return 0;
2923}
2924
b209749f
AK		 2925static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2926 struct kvm_tpr_access_ctl *tac)
2927{
2928 if (tac->flags)
2929 return -EINVAL;
2930 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2931 return 0;
2932}
2933
890ca9ae
HY		 2934static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2935 u64 mcg_cap)
2936{
2937 int r;
2938 unsigned bank_num = mcg_cap & 0xff, bank;
2939
2940 r = -EINVAL;
a9e38c3e 2941 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2942 goto out;
2943 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2944 goto out;
2945 r = 0;
2946 vcpu->arch.mcg_cap = mcg_cap;
2947 /* Init IA32_MCG_CTL to all 1s */
2948 if (mcg_cap & MCG_CTL_P)
2949 vcpu->arch.mcg_ctl = ~(u64)0;
2950 /* Init IA32_MCi_CTL to all 1s */
2951 for (bank = 0; bank < bank_num; bank++)
2952 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2953out:
2954 return r;
2955}
2956
2957static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2958 struct kvm_x86_mce *mce)
2959{
2960 u64 mcg_cap = vcpu->arch.mcg_cap;
2961 unsigned bank_num = mcg_cap & 0xff;
2962 u64 *banks = vcpu->arch.mce_banks;
2963
2964 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2965 return -EINVAL;
2966 /*
2967 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2968 * reporting is disabled
2969 */
2970 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2971 vcpu->arch.mcg_ctl != ~(u64)0)
2972 return 0;
2973 banks += 4 * mce->bank;
2974 /*
2975 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2976 * reporting is disabled for the bank
2977 */
2978 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2979 return 0;
2980 if (mce->status & MCI_STATUS_UC) {
2981 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2982 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2983 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2984 return 0;
2985 }
2986 if (banks[1] & MCI_STATUS_VAL)
2987 mce->status |= MCI_STATUS_OVER;
2988 banks[2] = mce->addr;
2989 banks[3] = mce->misc;
2990 vcpu->arch.mcg_status = mce->mcg_status;
2991 banks[1] = mce->status;
2992 kvm_queue_exception(vcpu, MC_VECTOR);
2993 } else if (!(banks[1] & MCI_STATUS_VAL)
2994 || !(banks[1] & MCI_STATUS_UC)) {
2995 if (banks[1] & MCI_STATUS_VAL)
2996 mce->status |= MCI_STATUS_OVER;
2997 banks[2] = mce->addr;
2998 banks[3] = mce->misc;
2999 banks[1] = mce->status;
3000 } else
3001 banks[1] |= MCI_STATUS_OVER;
3002 return 0;
3003}
3004
3cfc3092
JK		 3005static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3006 struct kvm_vcpu_events *events)
3007{
7460fb4a 3008 process_nmi(vcpu);
03b82a30
JK		 3009 events->exception.injected =
3010 vcpu->arch.exception.pending &&
3011 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3012 events->exception.nr = vcpu->arch.exception.nr;
3013 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3014 events->exception.pad = 0;
3cfc3092
JK		 3015 events->exception.error_code = vcpu->arch.exception.error_code;
3016
03b82a30
JK		 3017 events->interrupt.injected =
3018 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3019 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3020 events->interrupt.soft = 0;
37ccdcbe 3021 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3022
3023 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3024 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3025 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3026 events->nmi.pad = 0;
3cfc3092 3027
66450a21 3028 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3029
dab4b911 3030 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3031 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3032 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3033}
3034
3035static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3036 struct kvm_vcpu_events *events)
3037{
dab4b911 3038 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3039 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3040 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3041 return -EINVAL;
3042
7460fb4a 3043 process_nmi(vcpu);
3cfc3092
JK		 3044 vcpu->arch.exception.pending = events->exception.injected;
3045 vcpu->arch.exception.nr = events->exception.nr;
3046 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3047 vcpu->arch.exception.error_code = events->exception.error_code;
3048
3049 vcpu->arch.interrupt.pending = events->interrupt.injected;
3050 vcpu->arch.interrupt.nr = events->interrupt.nr;
3051 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3052 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3053 kvm_x86_ops->set_interrupt_shadow(vcpu,
3054 events->interrupt.shadow);
3cfc3092
JK		 3055
3056 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3057 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3058 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3059 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3060
66450a21
JK		 3061 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3062 kvm_vcpu_has_lapic(vcpu))
3063 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3064
3842d135
AK		 3065 kvm_make_request(KVM_REQ_EVENT, vcpu);
3066
3cfc3092
JK		 3067 return 0;
3068}
3069
a1efbe77
JK		 3070static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3071 struct kvm_debugregs *dbgregs)
3072{
73aaf249
JK		 3073 unsigned long val;
3074
a1efbe77 3075 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3076 _kvm_get_dr(vcpu, 6, &val);
3077 dbgregs->dr6 = val;
a1efbe77
JK		 3078 dbgregs->dr7 = vcpu->arch.dr7;
3079 dbgregs->flags = 0;
97e69aa6 3080 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3081}
3082
3083static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3084 struct kvm_debugregs *dbgregs)
3085{
3086 if (dbgregs->flags)
3087 return -EINVAL;
3088
a1efbe77
JK		 3089 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3090 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3091 kvm_update_dr6(vcpu);
a1efbe77 3092 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3093 kvm_update_dr7(vcpu);
a1efbe77 3094
a1efbe77
JK		 3095 return 0;
3096}
3097
2d5b5a66
SY		 3098static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3099 struct kvm_xsave *guest_xsave)
3100{
4344ee98 3101 if (cpu_has_xsave) {
2d5b5a66
SY		 3102 memcpy(guest_xsave->region,
3103 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3104 vcpu->arch.guest_xstate_size);
3105 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3106 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3107 } else {
2d5b5a66
SY		 3108 memcpy(guest_xsave->region,
3109 &vcpu->arch.guest_fpu.state->fxsave,
3110 sizeof(struct i387_fxsave_struct));
3111 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3112 XSTATE_FPSSE;
3113 }
3114}
3115
3116static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3117 struct kvm_xsave *guest_xsave)
3118{
3119 u64 xstate_bv =
3120 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3121
d7876f1b
PB		 3122 if (cpu_has_xsave) {
3123 /*
3124 * Here we allow setting states that are not present in
3125 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3126 * with old userspace.
3127 */
4ff41732 3128 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3129 return -EINVAL;
2d5b5a66 3130 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3131 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3132 } else {
2d5b5a66
SY		 3133 if (xstate_bv & ~XSTATE_FPSSE)
3134 return -EINVAL;
3135 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3136 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3137 }
3138 return 0;
3139}
3140
3141static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3142 struct kvm_xcrs *guest_xcrs)
3143{
3144 if (!cpu_has_xsave) {
3145 guest_xcrs->nr_xcrs = 0;
3146 return;
3147 }
3148
3149 guest_xcrs->nr_xcrs = 1;
3150 guest_xcrs->flags = 0;
3151 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3152 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3153}
3154
3155static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3156 struct kvm_xcrs *guest_xcrs)
3157{
3158 int i, r = 0;
3159
3160 if (!cpu_has_xsave)
3161 return -EINVAL;
3162
3163 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3164 return -EINVAL;
3165
3166 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3167 /* Only support XCR0 currently */
c67a04cb 3168 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3169 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3170 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3171 break;
3172 }
3173 if (r)
3174 r = -EINVAL;
3175 return r;
3176}
3177
1c0b28c2
EM		 3178/*
3179 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3180 * stopped by the hypervisor. This function will be called from the host only.
3181 * EINVAL is returned when the host attempts to set the flag for a guest that
3182 * does not support pv clocks.
3183 */
3184static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3185{
0b79459b 3186 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3187 return -EINVAL;
51d59c6b 3188 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3189 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3190 return 0;
3191}
3192
313a3dc7
CO		 3193long kvm_arch_vcpu_ioctl(struct file *filp,
3194 unsigned int ioctl, unsigned long arg)
3195{
3196 struct kvm_vcpu *vcpu = filp->private_data;
3197 void __user *argp = (void __user *)arg;
3198 int r;
d1ac91d8
AK		 3199 union {
3200 struct kvm_lapic_state *lapic;
3201 struct kvm_xsave *xsave;
3202 struct kvm_xcrs *xcrs;
3203 void *buffer;
3204 } u;
3205
3206 u.buffer = NULL;
313a3dc7
CO		 3207 switch (ioctl) {
3208 case KVM_GET_LAPIC: {
2204ae3c
MT		 3209 r = -EINVAL;
3210 if (!vcpu->arch.apic)
3211 goto out;
d1ac91d8 3212 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3213
b772ff36 3214 r = -ENOMEM;
d1ac91d8 3215 if (!u.lapic)
b772ff36 3216 goto out;
d1ac91d8 3217 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3218 if (r)
3219 goto out;
3220 r = -EFAULT;
d1ac91d8 3221 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3222 goto out;
3223 r = 0;
3224 break;
3225 }
3226 case KVM_SET_LAPIC: {
2204ae3c
MT		 3227 r = -EINVAL;
3228 if (!vcpu->arch.apic)
3229 goto out;
ff5c2c03 3230 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3231 if (IS_ERR(u.lapic))
3232 return PTR_ERR(u.lapic);
ff5c2c03 3233
d1ac91d8 3234 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3235 break;
3236 }
f77bc6a4
ZX		 3237 case KVM_INTERRUPT: {
3238 struct kvm_interrupt irq;
3239
3240 r = -EFAULT;
3241 if (copy_from_user(&irq, argp, sizeof irq))
3242 goto out;
3243 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3244 break;
3245 }
c4abb7c9
JK		 3246 case KVM_NMI: {
3247 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3248 break;
3249 }
313a3dc7
CO		 3250 case KVM_SET_CPUID: {
3251 struct kvm_cpuid __user *cpuid_arg = argp;
3252 struct kvm_cpuid cpuid;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3256 goto out;
3257 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3258 break;
3259 }
07716717
DK		 3260 case KVM_SET_CPUID2: {
3261 struct kvm_cpuid2 __user *cpuid_arg = argp;
3262 struct kvm_cpuid2 cpuid;
3263
3264 r = -EFAULT;
3265 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3266 goto out;
3267 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3268 cpuid_arg->entries);
07716717
DK		 3269 break;
3270 }
3271 case KVM_GET_CPUID2: {
3272 struct kvm_cpuid2 __user *cpuid_arg = argp;
3273 struct kvm_cpuid2 cpuid;
3274
3275 r = -EFAULT;
3276 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3277 goto out;
3278 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3279 cpuid_arg->entries);
07716717
DK		 3280 if (r)
3281 goto out;
3282 r = -EFAULT;
3283 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3284 goto out;
3285 r = 0;
3286 break;
3287 }
313a3dc7
CO		 3288 case KVM_GET_MSRS:
3289 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3290 break;
3291 case KVM_SET_MSRS:
3292 r = msr_io(vcpu, argp, do_set_msr, 0);
3293 break;
b209749f
AK		 3294 case KVM_TPR_ACCESS_REPORTING: {
3295 struct kvm_tpr_access_ctl tac;
3296
3297 r = -EFAULT;
3298 if (copy_from_user(&tac, argp, sizeof tac))
3299 goto out;
3300 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3301 if (r)
3302 goto out;
3303 r = -EFAULT;
3304 if (copy_to_user(argp, &tac, sizeof tac))
3305 goto out;
3306 r = 0;
3307 break;
3308 };
b93463aa
AK		 3309 case KVM_SET_VAPIC_ADDR: {
3310 struct kvm_vapic_addr va;
3311
3312 r = -EINVAL;
3313 if (!irqchip_in_kernel(vcpu->kvm))
3314 goto out;
3315 r = -EFAULT;
3316 if (copy_from_user(&va, argp, sizeof va))
3317 goto out;
fda4e2e8 3318 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3319 break;
3320 }
890ca9ae
HY		 3321 case KVM_X86_SETUP_MCE: {
3322 u64 mcg_cap;
3323
3324 r = -EFAULT;
3325 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3326 goto out;
3327 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3328 break;
3329 }
3330 case KVM_X86_SET_MCE: {
3331 struct kvm_x86_mce mce;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&mce, argp, sizeof mce))
3335 goto out;
3336 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3337 break;
3338 }
3cfc3092
JK		 3339 case KVM_GET_VCPU_EVENTS: {
3340 struct kvm_vcpu_events events;
3341
3342 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3343
3344 r = -EFAULT;
3345 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3346 break;
3347 r = 0;
3348 break;
3349 }
3350 case KVM_SET_VCPU_EVENTS: {
3351 struct kvm_vcpu_events events;
3352
3353 r = -EFAULT;
3354 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3355 break;
3356
3357 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3358 break;
3359 }
a1efbe77
JK		 3360 case KVM_GET_DEBUGREGS: {
3361 struct kvm_debugregs dbgregs;
3362
3363 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3364
3365 r = -EFAULT;
3366 if (copy_to_user(argp, &dbgregs,
3367 sizeof(struct kvm_debugregs)))
3368 break;
3369 r = 0;
3370 break;
3371 }
3372 case KVM_SET_DEBUGREGS: {
3373 struct kvm_debugregs dbgregs;
3374
3375 r = -EFAULT;
3376 if (copy_from_user(&dbgregs, argp,
3377 sizeof(struct kvm_debugregs)))
3378 break;
3379
3380 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3381 break;
3382 }
2d5b5a66 3383 case KVM_GET_XSAVE: {
d1ac91d8 3384 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3385 r = -ENOMEM;
d1ac91d8 3386 if (!u.xsave)
2d5b5a66
SY		 3387 break;
3388
d1ac91d8 3389 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3390
3391 r = -EFAULT;
d1ac91d8 3392 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3393 break;
3394 r = 0;
3395 break;
3396 }
3397 case KVM_SET_XSAVE: {
ff5c2c03 3398 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3399 if (IS_ERR(u.xsave))
3400 return PTR_ERR(u.xsave);
2d5b5a66 3401
d1ac91d8 3402 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3403 break;
3404 }
3405 case KVM_GET_XCRS: {
d1ac91d8 3406 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3407 r = -ENOMEM;
d1ac91d8 3408 if (!u.xcrs)
2d5b5a66
SY		 3409 break;
3410
d1ac91d8 3411 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3412
3413 r = -EFAULT;
d1ac91d8 3414 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3415 sizeof(struct kvm_xcrs)))
3416 break;
3417 r = 0;
3418 break;
3419 }
3420 case KVM_SET_XCRS: {
ff5c2c03 3421 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3422 if (IS_ERR(u.xcrs))
3423 return PTR_ERR(u.xcrs);
2d5b5a66 3424
d1ac91d8 3425 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3426 break;
3427 }
92a1f12d
JR		 3428 case KVM_SET_TSC_KHZ: {
3429 u32 user_tsc_khz;
3430
3431 r = -EINVAL;
92a1f12d
JR		 3432 user_tsc_khz = (u32)arg;
3433
3434 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3435 goto out;
3436
cc578287
ZA		 3437 if (user_tsc_khz == 0)
3438 user_tsc_khz = tsc_khz;
3439
3440 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3441
3442 r = 0;
3443 goto out;
3444 }
3445 case KVM_GET_TSC_KHZ: {
cc578287 3446 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3447 goto out;
3448 }
1c0b28c2
EM		 3449 case KVM_KVMCLOCK_CTRL: {
3450 r = kvm_set_guest_paused(vcpu);
3451 goto out;
3452 }
313a3dc7
CO		 3453 default:
3454 r = -EINVAL;
3455 }
3456out:
d1ac91d8 3457 kfree(u.buffer);
313a3dc7
CO		 3458 return r;
3459}
3460
5b1c1493
CO		 3461int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3462{
3463 return VM_FAULT_SIGBUS;
3464}
3465
1fe779f8
CO		 3466static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3467{
3468 int ret;
3469
3470 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3471 return -EINVAL;
1fe779f8
CO		 3472 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3473 return ret;
3474}
3475
b927a3ce
SY		 3476static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3477 u64 ident_addr)
3478{
3479 kvm->arch.ept_identity_map_addr = ident_addr;
3480 return 0;
3481}
3482
1fe779f8
CO		 3483static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3484 u32 kvm_nr_mmu_pages)
3485{
3486 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3487 return -EINVAL;
3488
79fac95e 3489 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3490
3491 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3492 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3493
79fac95e 3494 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3495 return 0;
3496}
3497
3498static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3499{
39de71ec 3500 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3501}
3502
1fe779f8
CO		 3503static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3504{
3505 int r;
3506
3507 r = 0;
3508 switch (chip->chip_id) {
3509 case KVM_IRQCHIP_PIC_MASTER:
3510 memcpy(&chip->chip.pic,
3511 &pic_irqchip(kvm)->pics[0],
3512 sizeof(struct kvm_pic_state));
3513 break;
3514 case KVM_IRQCHIP_PIC_SLAVE:
3515 memcpy(&chip->chip.pic,
3516 &pic_irqchip(kvm)->pics[1],
3517 sizeof(struct kvm_pic_state));
3518 break;
3519 case KVM_IRQCHIP_IOAPIC:
eba0226b 3520 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3521 break;
3522 default:
3523 r = -EINVAL;
3524 break;
3525 }
3526 return r;
3527}
3528
3529static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3530{
3531 int r;
3532
3533 r = 0;
3534 switch (chip->chip_id) {
3535 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3536 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3537 memcpy(&pic_irqchip(kvm)->pics[0],
3538 &chip->chip.pic,
3539 sizeof(struct kvm_pic_state));
f4f51050 3540 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3541 break;
3542 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3543 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3544 memcpy(&pic_irqchip(kvm)->pics[1],
3545 &chip->chip.pic,
3546 sizeof(struct kvm_pic_state));
f4f51050 3547 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3548 break;
3549 case KVM_IRQCHIP_IOAPIC:
eba0226b 3550 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3551 break;
3552 default:
3553 r = -EINVAL;
3554 break;
3555 }
3556 kvm_pic_update_irq(pic_irqchip(kvm));
3557 return r;
3558}
3559
e0f63cb9
SY		 3560static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3561{
3562 int r = 0;
3563
894a9c55 3564 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3565 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3566 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3567 return r;
3568}
3569
3570static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3571{
3572 int r = 0;
3573
894a9c55 3574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3575 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3576 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3578 return r;
3579}
3580
3581static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3582{
3583 int r = 0;
3584
3585 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3586 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3587 sizeof(ps->channels));
3588 ps->flags = kvm->arch.vpit->pit_state.flags;
3589 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3590 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3591 return r;
3592}
3593
3594static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3595{
3596 int r = 0, start = 0;
3597 u32 prev_legacy, cur_legacy;
3598 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3599 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3600 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3601 if (!prev_legacy && cur_legacy)
3602 start = 1;
3603 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3604 sizeof(kvm->arch.vpit->pit_state.channels));
3605 kvm->arch.vpit->pit_state.flags = ps->flags;
3606 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3607 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3608 return r;
3609}
3610
52d939a0
MT		 3611static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3612 struct kvm_reinject_control *control)
3613{
3614 if (!kvm->arch.vpit)
3615 return -ENXIO;
894a9c55 3616 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3617 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3618 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3619 return 0;
3620}
3621
95d4c16c 3622/**
60c34612
TY		 3623 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3624 * @kvm: kvm instance
3625 * @log: slot id and address to which we copy the log
95d4c16c 3626 *
60c34612
TY		 3627 * We need to keep it in mind that VCPU threads can write to the bitmap
3628 * concurrently. So, to avoid losing data, we keep the following order for
3629 * each bit:
95d4c16c 3630 *
60c34612
TY		 3631 * 1. Take a snapshot of the bit and clear it if needed.
3632 * 2. Write protect the corresponding page.
3633 * 3. Flush TLB's if needed.
3634 * 4. Copy the snapshot to the userspace.
95d4c16c 3635 *
60c34612
TY		 3636 * Between 2 and 3, the guest may write to the page using the remaining TLB
3637 * entry. This is not a problem because the page will be reported dirty at
3638 * step 4 using the snapshot taken before and step 3 ensures that successive
3639 * writes will be logged for the next call.
5bb064dc 3640 */
60c34612 3641int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3642{
7850ac54 3643 int r;
5bb064dc 3644 struct kvm_memory_slot *memslot;
60c34612
TY		 3645 unsigned long n, i;
3646 unsigned long *dirty_bitmap;
3647 unsigned long *dirty_bitmap_buffer;
3648 bool is_dirty = false;
5bb064dc 3649
79fac95e 3650 mutex_lock(&kvm->slots_lock);
5bb064dc 3651
b050b015 3652 r = -EINVAL;
bbacc0c1 3653 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3654 goto out;
3655
28a37544 3656 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3657
3658 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3659 r = -ENOENT;
60c34612 3660 if (!dirty_bitmap)
b050b015
MT		 3661 goto out;
3662
87bf6e7d 3663 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3664
60c34612
TY		 3665 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3666 memset(dirty_bitmap_buffer, 0, n);
b050b015 3667
60c34612 3668 spin_lock(&kvm->mmu_lock);
b050b015 3669
60c34612
TY		 3670 for (i = 0; i < n / sizeof(long); i++) {
3671 unsigned long mask;
3672 gfn_t offset;
cdfca7b3 3673
60c34612
TY		 3674 if (!dirty_bitmap[i])
3675 continue;
b050b015 3676
60c34612 3677 is_dirty = true;
914ebccd 3678
60c34612
TY		 3679 mask = xchg(&dirty_bitmap[i], 0);
3680 dirty_bitmap_buffer[i] = mask;
edde99ce 3681
60c34612
TY		 3682 offset = i * BITS_PER_LONG;
3683 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3684 }
60c34612
TY		 3685
3686 spin_unlock(&kvm->mmu_lock);
3687
198c74f4
XG		 3688 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3689 lockdep_assert_held(&kvm->slots_lock);
3690
3691 /*
3692 * All the TLBs can be flushed out of mmu lock, see the comments in
3693 * kvm_mmu_slot_remove_write_access().
3694 */
3695 if (is_dirty)
3696 kvm_flush_remote_tlbs(kvm);
3697
60c34612
TY		 3698 r = -EFAULT;
3699 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3700 goto out;
b050b015 3701
5bb064dc
ZX		 3702 r = 0;
3703out:
79fac95e 3704 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3705 return r;
3706}
3707
aa2fbe6d
YZ		 3708int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3709 bool line_status)
23d43cf9
CD		 3710{
3711 if (!irqchip_in_kernel(kvm))
3712 return -ENXIO;
3713
3714 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3715 irq_event->irq, irq_event->level,
3716 line_status);
23d43cf9
CD		 3717 return 0;
3718}
3719
1fe779f8
CO		 3720long kvm_arch_vm_ioctl(struct file *filp,
3721 unsigned int ioctl, unsigned long arg)
3722{
3723 struct kvm *kvm = filp->private_data;
3724 void __user *argp = (void __user *)arg;
367e1319 3725 int r = -ENOTTY;
f0d66275
DH		 3726 /*
3727 * This union makes it completely explicit to gcc-3.x
3728 * that these two variables' stack usage should be
3729 * combined, not added together.
3730 */
3731 union {
3732 struct kvm_pit_state ps;
e9f42757 3733 struct kvm_pit_state2 ps2;
c5ff41ce 3734 struct kvm_pit_config pit_config;
f0d66275 3735 } u;
1fe779f8
CO		 3736
3737 switch (ioctl) {
3738 case KVM_SET_TSS_ADDR:
3739 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3740 break;
b927a3ce
SY		 3741 case KVM_SET_IDENTITY_MAP_ADDR: {
3742 u64 ident_addr;
3743
3744 r = -EFAULT;
3745 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3746 goto out;
3747 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3748 break;
3749 }
1fe779f8
CO		 3750 case KVM_SET_NR_MMU_PAGES:
3751 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3752 break;
3753 case KVM_GET_NR_MMU_PAGES:
3754 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3755 break;
3ddea128
MT		 3756 case KVM_CREATE_IRQCHIP: {
3757 struct kvm_pic *vpic;
3758
3759 mutex_lock(&kvm->lock);
3760 r = -EEXIST;
3761 if (kvm->arch.vpic)
3762 goto create_irqchip_unlock;
3e515705
AK		 3763 r = -EINVAL;
3764 if (atomic_read(&kvm->online_vcpus))
3765 goto create_irqchip_unlock;
1fe779f8 3766 r = -ENOMEM;
3ddea128
MT		 3767 vpic = kvm_create_pic(kvm);
3768 if (vpic) {
1fe779f8
CO		 3769 r = kvm_ioapic_init(kvm);
3770 if (r) {
175504cd 3771 mutex_lock(&kvm->slots_lock);
72bb2fcd 3772 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3773 &vpic->dev_master);
3774 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3775 &vpic->dev_slave);
3776 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3777 &vpic->dev_eclr);
175504cd 3778 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3779 kfree(vpic);
3780 goto create_irqchip_unlock;
1fe779f8
CO		 3781 }
3782 } else
3ddea128
MT		 3783 goto create_irqchip_unlock;
3784 smp_wmb();
3785 kvm->arch.vpic = vpic;
3786 smp_wmb();
399ec807
AK		 3787 r = kvm_setup_default_irq_routing(kvm);
3788 if (r) {
175504cd 3789 mutex_lock(&kvm->slots_lock);
3ddea128 3790 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3791 kvm_ioapic_destroy(kvm);
3792 kvm_destroy_pic(kvm);
3ddea128 3793 mutex_unlock(&kvm->irq_lock);
175504cd 3794 mutex_unlock(&kvm->slots_lock);
399ec807 3795 }
3ddea128
MT		 3796 create_irqchip_unlock:
3797 mutex_unlock(&kvm->lock);
1fe779f8 3798 break;
3ddea128 3799 }
7837699f 3800 case KVM_CREATE_PIT:
c5ff41ce
JK		 3801 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3802 goto create_pit;
3803 case KVM_CREATE_PIT2:
3804 r = -EFAULT;
3805 if (copy_from_user(&u.pit_config, argp,
3806 sizeof(struct kvm_pit_config)))
3807 goto out;
3808 create_pit:
79fac95e 3809 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3810 r = -EEXIST;
3811 if (kvm->arch.vpit)
3812 goto create_pit_unlock;
7837699f 3813 r = -ENOMEM;
c5ff41ce 3814 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3815 if (kvm->arch.vpit)
3816 r = 0;
269e05e4 3817 create_pit_unlock:
79fac95e 3818 mutex_unlock(&kvm->slots_lock);
7837699f 3819 break;
1fe779f8
CO		 3820 case KVM_GET_IRQCHIP: {
3821 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3822 struct kvm_irqchip *chip;
1fe779f8 3823
ff5c2c03
SL		 3824 chip = memdup_user(argp, sizeof(*chip));
3825 if (IS_ERR(chip)) {
3826 r = PTR_ERR(chip);
1fe779f8 3827 goto out;
ff5c2c03
SL		 3828 }
3829
1fe779f8
CO		 3830 r = -ENXIO;
3831 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3832 goto get_irqchip_out;
3833 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3834 if (r)
f0d66275 3835 goto get_irqchip_out;
1fe779f8 3836 r = -EFAULT;
f0d66275
DH		 3837 if (copy_to_user(argp, chip, sizeof *chip))
3838 goto get_irqchip_out;
1fe779f8 3839 r = 0;
f0d66275
DH		 3840 get_irqchip_out:
3841 kfree(chip);
1fe779f8
CO		 3842 break;
3843 }
3844 case KVM_SET_IRQCHIP: {
3845 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3846 struct kvm_irqchip *chip;
1fe779f8 3847
ff5c2c03
SL		 3848 chip = memdup_user(argp, sizeof(*chip));
3849 if (IS_ERR(chip)) {
3850 r = PTR_ERR(chip);
1fe779f8 3851 goto out;
ff5c2c03
SL		 3852 }
3853
1fe779f8
CO		 3854 r = -ENXIO;
3855 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3856 goto set_irqchip_out;
3857 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3858 if (r)
f0d66275 3859 goto set_irqchip_out;
1fe779f8 3860 r = 0;
f0d66275
DH		 3861 set_irqchip_out:
3862 kfree(chip);
1fe779f8
CO		 3863 break;
3864 }
e0f63cb9 3865 case KVM_GET_PIT: {
e0f63cb9 3866 r = -EFAULT;
f0d66275 3867 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3868 goto out;
3869 r = -ENXIO;
3870 if (!kvm->arch.vpit)
3871 goto out;
f0d66275 3872 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3873 if (r)
3874 goto out;
3875 r = -EFAULT;
f0d66275 3876 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3877 goto out;
3878 r = 0;
3879 break;
3880 }
3881 case KVM_SET_PIT: {
e0f63cb9 3882 r = -EFAULT;
f0d66275 3883 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3884 goto out;
3885 r = -ENXIO;
3886 if (!kvm->arch.vpit)
3887 goto out;
f0d66275 3888 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3889 break;
3890 }
e9f42757
BK		 3891 case KVM_GET_PIT2: {
3892 r = -ENXIO;
3893 if (!kvm->arch.vpit)
3894 goto out;
3895 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3896 if (r)
3897 goto out;
3898 r = -EFAULT;
3899 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3900 goto out;
3901 r = 0;
3902 break;
3903 }
3904 case KVM_SET_PIT2: {
3905 r = -EFAULT;
3906 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3907 goto out;
3908 r = -ENXIO;
3909 if (!kvm->arch.vpit)
3910 goto out;
3911 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3912 break;
3913 }
52d939a0
MT		 3914 case KVM_REINJECT_CONTROL: {
3915 struct kvm_reinject_control control;
3916 r = -EFAULT;
3917 if (copy_from_user(&control, argp, sizeof(control)))
3918 goto out;
3919 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3920 break;
3921 }
ffde22ac
ES		 3922 case KVM_XEN_HVM_CONFIG: {
3923 r = -EFAULT;
3924 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3925 sizeof(struct kvm_xen_hvm_config)))
3926 goto out;
3927 r = -EINVAL;
3928 if (kvm->arch.xen_hvm_config.flags)
3929 goto out;
3930 r = 0;
3931 break;
3932 }
afbcf7ab 3933 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3934 struct kvm_clock_data user_ns;
3935 u64 now_ns;
3936 s64 delta;
3937
3938 r = -EFAULT;
3939 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3940 goto out;
3941
3942 r = -EINVAL;
3943 if (user_ns.flags)
3944 goto out;
3945
3946 r = 0;
395c6b0a 3947 local_irq_disable();
759379dd 3948 now_ns = get_kernel_ns();
afbcf7ab 3949 delta = user_ns.clock - now_ns;
395c6b0a 3950 local_irq_enable();
afbcf7ab 3951 kvm->arch.kvmclock_offset = delta;
2e762ff7 3952 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3953 break;
3954 }
3955 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3956 struct kvm_clock_data user_ns;
3957 u64 now_ns;
3958
395c6b0a 3959 local_irq_disable();
759379dd 3960 now_ns = get_kernel_ns();
afbcf7ab 3961 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3962 local_irq_enable();
afbcf7ab 3963 user_ns.flags = 0;
97e69aa6 3964 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3965
3966 r = -EFAULT;
3967 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3968 goto out;
3969 r = 0;
3970 break;
3971 }
3972
1fe779f8
CO		 3973 default:
3974 ;
3975 }
3976out:
3977 return r;
3978}
3979
a16b043c 3980static void kvm_init_msr_list(void)
043405e1
CO		 3981{
3982 u32 dummy[2];
3983 unsigned i, j;
3984
e3267cbb
GC		 3985 /* skip the first msrs in the list. KVM-specific */
3986 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3987 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3988 continue;
93c4adc7
PB		 3989
3990 /*
3991 * Even MSRs that are valid in the host may not be exposed
3992 * to the guests in some cases. We could work around this
3993 * in VMX with the generic MSR save/load machinery, but it
3994 * is not really worthwhile since it will really only
3995 * happen with nested virtualization.
3996 */
3997 switch (msrs_to_save[i]) {
3998 case MSR_IA32_BNDCFGS:
3999 if (!kvm_x86_ops->mpx_supported())
4000 continue;
4001 break;
4002 default:
4003 break;
4004 }
4005
043405e1
CO		 4006 if (j < i)
4007 msrs_to_save[j] = msrs_to_save[i];
4008 j++;
4009 }
4010 num_msrs_to_save = j;
4011}
4012
bda9020e
MT		 4013static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4014 const void *v)
bbd9b64e 4015{
70252a10
AK		 4016 int handled = 0;
4017 int n;
4018
4019 do {
4020 n = min(len, 8);
4021 if (!(vcpu->arch.apic &&
4022 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4023 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4024 break;
4025 handled += n;
4026 addr += n;
4027 len -= n;
4028 v += n;
4029 } while (len);
bbd9b64e 4030
70252a10 4031 return handled;
bbd9b64e
CO		 4032}
4033
bda9020e 4034static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4035{
70252a10
AK		 4036 int handled = 0;
4037 int n;
4038
4039 do {
4040 n = min(len, 8);
4041 if (!(vcpu->arch.apic &&
4042 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4043 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4044 break;
4045 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4046 handled += n;
4047 addr += n;
4048 len -= n;
4049 v += n;
4050 } while (len);
bbd9b64e 4051
70252a10 4052 return handled;
bbd9b64e
CO		 4053}
4054
2dafc6c2
GN		 4055static void kvm_set_segment(struct kvm_vcpu *vcpu,
4056 struct kvm_segment *var, int seg)
4057{
4058 kvm_x86_ops->set_segment(vcpu, var, seg);
4059}
4060
4061void kvm_get_segment(struct kvm_vcpu *vcpu,
4062 struct kvm_segment *var, int seg)
4063{
4064 kvm_x86_ops->get_segment(vcpu, var, seg);
4065}
4066
e459e322 4067gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4068{
4069 gpa_t t_gpa;
ab9ae313 4070 struct x86_exception exception;
02f59dc9
JR		 4071
4072 BUG_ON(!mmu_is_nested(vcpu));
4073
4074 /* NPT walks are always user-walks */
4075 access |= PFERR_USER_MASK;
ab9ae313 4076 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4077
4078 return t_gpa;
4079}
4080
ab9ae313
AK		 4081gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4082 struct x86_exception *exception)
1871c602
GN		 4083{
4084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4085 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4086}
4087
ab9ae313
AK		 4088 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4089 struct x86_exception *exception)
1871c602
GN		 4090{
4091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4092 access |= PFERR_FETCH_MASK;
ab9ae313 4093 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4094}
4095
ab9ae313
AK		 4096gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4097 struct x86_exception *exception)
1871c602
GN		 4098{
4099 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4100 access |= PFERR_WRITE_MASK;
ab9ae313 4101 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4102}
4103
4104/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4105gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4106 struct x86_exception *exception)
1871c602 4107{
ab9ae313 4108 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4109}
4110
4111static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4112 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4113 struct x86_exception *exception)
bbd9b64e
CO		 4114{
4115 void *data = val;
10589a46 4116 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4117
4118 while (bytes) {
14dfe855 4119 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4120 exception);
bbd9b64e 4121 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4122 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4123 int ret;
4124
bcc55cba 4125 if (gpa == UNMAPPED_GVA)
ab9ae313 4126 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4127 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4128 offset, toread);
10589a46 4129 if (ret < 0) {
c3cd7ffa 4130 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4131 goto out;
4132 }
bbd9b64e 4133
77c2002e
IE		 4134 bytes -= toread;
4135 data += toread;
4136 addr += toread;
bbd9b64e 4137 }
10589a46 4138out:
10589a46 4139 return r;
bbd9b64e 4140}
77c2002e 4141
1871c602 4142/* used for instruction fetching */
0f65dd70
AK		 4143static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4144 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4145 struct x86_exception *exception)
1871c602 4146{
0f65dd70 4147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4148 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4149 unsigned offset;
4150 int ret;
0f65dd70 4151
44583cba
PB		 4152 /* Inline kvm_read_guest_virt_helper for speed. */
4153 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4154 exception);
4155 if (unlikely(gpa == UNMAPPED_GVA))
4156 return X86EMUL_PROPAGATE_FAULT;
4157
4158 offset = addr & (PAGE_SIZE-1);
4159 if (WARN_ON(offset + bytes > PAGE_SIZE))
4160 bytes = (unsigned)PAGE_SIZE - offset;
4161 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4162 offset, bytes);
4163 if (unlikely(ret < 0))
4164 return X86EMUL_IO_NEEDED;
4165
4166 return X86EMUL_CONTINUE;
1871c602
GN		 4167}
4168
064aea77 4169int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4170 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4171 struct x86_exception *exception)
1871c602 4172{
0f65dd70 4173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4174 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4175
1871c602 4176 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4177 exception);
1871c602 4178}
064aea77 4179EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4180
0f65dd70
AK		 4181static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4182 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4183 struct x86_exception *exception)
1871c602 4184{
0f65dd70 4185 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4186 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4187}
4188
6a4d7550 4189int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4190 gva_t addr, void *val,
2dafc6c2 4191 unsigned int bytes,
bcc55cba 4192 struct x86_exception *exception)
77c2002e 4193{
0f65dd70 4194 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4195 void *data = val;
4196 int r = X86EMUL_CONTINUE;
4197
4198 while (bytes) {
14dfe855
JR		 4199 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4200 PFERR_WRITE_MASK,
ab9ae313 4201 exception);
77c2002e
IE		 4202 unsigned offset = addr & (PAGE_SIZE-1);
4203 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4204 int ret;
4205
bcc55cba 4206 if (gpa == UNMAPPED_GVA)
ab9ae313 4207 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4208 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4209 if (ret < 0) {
c3cd7ffa 4210 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4211 goto out;
4212 }
4213
4214 bytes -= towrite;
4215 data += towrite;
4216 addr += towrite;
4217 }
4218out:
4219 return r;
4220}
6a4d7550 4221EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4222
af7cc7d1
XG		 4223static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4224 gpa_t *gpa, struct x86_exception *exception,
4225 bool write)
4226{
97d64b78
AK		 4227 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4228 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4229
97d64b78 4230 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4231 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4232 vcpu->arch.access, access)) {
bebb106a
XG		 4233 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4234 (gva & (PAGE_SIZE - 1));
4f022648 4235 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4236 return 1;
4237 }
4238
af7cc7d1
XG		 4239 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4240
4241 if (*gpa == UNMAPPED_GVA)
4242 return -1;
4243
4244 /* For APIC access vmexit */
4245 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4246 return 1;
4247
4f022648
XG		 4248 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4249 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4250 return 1;
4f022648 4251 }
bebb106a 4252
af7cc7d1
XG		 4253 return 0;
4254}
4255
3200f405 4256int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4257 const void *val, int bytes)
bbd9b64e
CO		 4258{
4259 int ret;
4260
4261 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4262 if (ret < 0)
bbd9b64e 4263 return 0;
f57f2ef5 4264 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4265 return 1;
4266}
4267
77d197b2
XG		 4268struct read_write_emulator_ops {
4269 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4270 int bytes);
4271 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4272 void *val, int bytes);
4273 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4274 int bytes, void *val);
4275 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4276 void *val, int bytes);
4277 bool write;
4278};
4279
4280static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4281{
4282 if (vcpu->mmio_read_completed) {
77d197b2 4283 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4284 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4285 vcpu->mmio_read_completed = 0;
4286 return 1;
4287 }
4288
4289 return 0;
4290}
4291
4292static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4293 void *val, int bytes)
4294{
4295 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4296}
4297
4298static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4299 void *val, int bytes)
4300{
4301 return emulator_write_phys(vcpu, gpa, val, bytes);
4302}
4303
4304static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4305{
4306 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4307 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4308}
4309
4310static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4311 void *val, int bytes)
4312{
4313 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4314 return X86EMUL_IO_NEEDED;
4315}
4316
4317static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4318 void *val, int bytes)
4319{
f78146b0
AK		 4320 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4321
87da7e66 4322 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4323 return X86EMUL_CONTINUE;
4324}
4325
0fbe9b0b 4326static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4327 .read_write_prepare = read_prepare,
4328 .read_write_emulate = read_emulate,
4329 .read_write_mmio = vcpu_mmio_read,
4330 .read_write_exit_mmio = read_exit_mmio,
4331};
4332
0fbe9b0b 4333static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4334 .read_write_emulate = write_emulate,
4335 .read_write_mmio = write_mmio,
4336 .read_write_exit_mmio = write_exit_mmio,
4337 .write = true,
4338};
4339
22388a3c
XG		 4340static int emulator_read_write_onepage(unsigned long addr, void *val,
4341 unsigned int bytes,
4342 struct x86_exception *exception,
4343 struct kvm_vcpu *vcpu,
0fbe9b0b 4344 const struct read_write_emulator_ops *ops)
bbd9b64e 4345{
af7cc7d1
XG		 4346 gpa_t gpa;
4347 int handled, ret;
22388a3c 4348 bool write = ops->write;
f78146b0 4349 struct kvm_mmio_fragment *frag;
10589a46 4350
22388a3c 4351 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4352
af7cc7d1 4353 if (ret < 0)
bbd9b64e 4354 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4355
4356 /* For APIC access vmexit */
af7cc7d1 4357 if (ret)
bbd9b64e
CO		 4358 goto mmio;
4359
22388a3c 4360 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4361 return X86EMUL_CONTINUE;
4362
4363mmio:
4364 /*
4365 * Is this MMIO handled locally?
4366 */
22388a3c 4367 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4368 if (handled == bytes)
bbd9b64e 4369 return X86EMUL_CONTINUE;
bbd9b64e 4370
70252a10
AK		 4371 gpa += handled;
4372 bytes -= handled;
4373 val += handled;
4374
87da7e66
XG		 4375 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4376 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4377 frag->gpa = gpa;
4378 frag->data = val;
4379 frag->len = bytes;
f78146b0 4380 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4381}
4382
22388a3c
XG		 4383int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4384 void *val, unsigned int bytes,
4385 struct x86_exception *exception,
0fbe9b0b 4386 const struct read_write_emulator_ops *ops)
bbd9b64e 4387{
0f65dd70 4388 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4389 gpa_t gpa;
4390 int rc;
4391
4392 if (ops->read_write_prepare &&
4393 ops->read_write_prepare(vcpu, val, bytes))
4394 return X86EMUL_CONTINUE;
4395
4396 vcpu->mmio_nr_fragments = 0;
0f65dd70 4397
bbd9b64e
CO		 4398 /* Crossing a page boundary? */
4399 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4400 int now;
bbd9b64e
CO		 4401
4402 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4403 rc = emulator_read_write_onepage(addr, val, now, exception,
4404 vcpu, ops);
4405
bbd9b64e
CO		 4406 if (rc != X86EMUL_CONTINUE)
4407 return rc;
4408 addr += now;
4409 val += now;
4410 bytes -= now;
4411 }
22388a3c 4412
f78146b0
AK		 4413 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4414 vcpu, ops);
4415 if (rc != X86EMUL_CONTINUE)
4416 return rc;
4417
4418 if (!vcpu->mmio_nr_fragments)
4419 return rc;
4420
4421 gpa = vcpu->mmio_fragments[0].gpa;
4422
4423 vcpu->mmio_needed = 1;
4424 vcpu->mmio_cur_fragment = 0;
4425
87da7e66 4426 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4427 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4428 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4429 vcpu->run->mmio.phys_addr = gpa;
4430
4431 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4432}
4433
4434static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4435 unsigned long addr,
4436 void *val,
4437 unsigned int bytes,
4438 struct x86_exception *exception)
4439{
4440 return emulator_read_write(ctxt, addr, val, bytes,
4441 exception, &read_emultor);
4442}
4443
4444int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4445 unsigned long addr,
4446 const void *val,
4447 unsigned int bytes,
4448 struct x86_exception *exception)
4449{
4450 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4451 exception, &write_emultor);
bbd9b64e 4452}
bbd9b64e 4453
daea3e73
AK		 4454#define CMPXCHG_TYPE(t, ptr, old, new) \
4455 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4456
4457#ifdef CONFIG_X86_64
4458# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4459#else
4460# define CMPXCHG64(ptr, old, new) \
9749a6c0 4461 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4462#endif
4463
0f65dd70
AK		 4464static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4465 unsigned long addr,
bbd9b64e
CO		 4466 const void *old,
4467 const void *new,
4468 unsigned int bytes,
0f65dd70 4469 struct x86_exception *exception)
bbd9b64e 4470{
0f65dd70 4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4472 gpa_t gpa;
4473 struct page *page;
4474 char *kaddr;
4475 bool exchanged;
2bacc55c 4476
daea3e73
AK		 4477 /* guests cmpxchg8b have to be emulated atomically */
4478 if (bytes > 8 || (bytes & (bytes - 1)))
4479 goto emul_write;
10589a46 4480
daea3e73 4481 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4482
daea3e73
AK		 4483 if (gpa == UNMAPPED_GVA ||
4484 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4485 goto emul_write;
2bacc55c 4486
daea3e73
AK		 4487 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4488 goto emul_write;
72dc67a6 4489
daea3e73 4490 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4491 if (is_error_page(page))
c19b8bd6 4492 goto emul_write;
72dc67a6 4493
8fd75e12 4494 kaddr = kmap_atomic(page);
daea3e73
AK		 4495 kaddr += offset_in_page(gpa);
4496 switch (bytes) {
4497 case 1:
4498 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4499 break;
4500 case 2:
4501 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4502 break;
4503 case 4:
4504 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4505 break;
4506 case 8:
4507 exchanged = CMPXCHG64(kaddr, old, new);
4508 break;
4509 default:
4510 BUG();
2bacc55c 4511 }
8fd75e12 4512 kunmap_atomic(kaddr);
daea3e73
AK		 4513 kvm_release_page_dirty(page);
4514
4515 if (!exchanged)
4516 return X86EMUL_CMPXCHG_FAILED;
4517
d3714010 4518 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4519 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4520
4521 return X86EMUL_CONTINUE;
4a5f48f6 4522
3200f405 4523emul_write:
daea3e73 4524 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4525
0f65dd70 4526 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4527}
4528
cf8f70bf
GN		 4529static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4530{
4531 /* TODO: String I/O for in kernel device */
4532 int r;
4533
4534 if (vcpu->arch.pio.in)
4535 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4536 vcpu->arch.pio.size, pd);
4537 else
4538 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4539 vcpu->arch.pio.port, vcpu->arch.pio.size,
4540 pd);
4541 return r;
4542}
4543
6f6fbe98
XG		 4544static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4545 unsigned short port, void *val,
4546 unsigned int count, bool in)
cf8f70bf 4547{
cf8f70bf 4548 vcpu->arch.pio.port = port;
6f6fbe98 4549 vcpu->arch.pio.in = in;
7972995b 4550 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4551 vcpu->arch.pio.size = size;
4552
4553 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4554 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4555 return 1;
4556 }
4557
4558 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4559 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4560 vcpu->run->io.size = size;
4561 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4562 vcpu->run->io.count = count;
4563 vcpu->run->io.port = port;
4564
4565 return 0;
4566}
4567
6f6fbe98
XG		 4568static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4569 int size, unsigned short port, void *val,
4570 unsigned int count)
cf8f70bf 4571{
ca1d4a9e 4572 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4573 int ret;
ca1d4a9e 4574
6f6fbe98
XG		 4575 if (vcpu->arch.pio.count)
4576 goto data_avail;
cf8f70bf 4577
6f6fbe98
XG		 4578 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4579 if (ret) {
4580data_avail:
4581 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4582 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4583 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4584 return 1;
4585 }
4586
cf8f70bf
GN		 4587 return 0;
4588}
4589
6f6fbe98
XG		 4590static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4591 int size, unsigned short port,
4592 const void *val, unsigned int count)
4593{
4594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4595
4596 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4597 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4598 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4599}
4600
bbd9b64e
CO		 4601static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4602{
4603 return kvm_x86_ops->get_segment_base(vcpu, seg);
4604}
4605
3cb16fe7 4606static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4607{
3cb16fe7 4608 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4609}
4610
f5f48ee1
SY		 4611int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4612{
4613 if (!need_emulate_wbinvd(vcpu))
4614 return X86EMUL_CONTINUE;
4615
4616 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4617 int cpu = get_cpu();
4618
4619 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4620 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4621 wbinvd_ipi, NULL, 1);
2eec7343 4622 put_cpu();
f5f48ee1 4623 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4624 } else
4625 wbinvd();
f5f48ee1
SY		 4626 return X86EMUL_CONTINUE;
4627}
4628EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4629
bcaf5cc5
AK		 4630static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4631{
4632 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4633}
4634
717746e3 4635int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4636{
717746e3 4637 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4638}
4639
717746e3 4640int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4641{
338dbc97 4642
717746e3 4643 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4644}
4645
52a46617 4646static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4647{
52a46617 4648 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4649}
4650
717746e3 4651static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4652{
717746e3 4653 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4654 unsigned long value;
4655
4656 switch (cr) {
4657 case 0:
4658 value = kvm_read_cr0(vcpu);
4659 break;
4660 case 2:
4661 value = vcpu->arch.cr2;
4662 break;
4663 case 3:
9f8fe504 4664 value = kvm_read_cr3(vcpu);
52a46617
GN		 4665 break;
4666 case 4:
4667 value = kvm_read_cr4(vcpu);
4668 break;
4669 case 8:
4670 value = kvm_get_cr8(vcpu);
4671 break;
4672 default:
a737f256 4673 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4674 return 0;
4675 }
4676
4677 return value;
4678}
4679
717746e3 4680static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4681{
717746e3 4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4683 int res = 0;
4684
52a46617
GN		 4685 switch (cr) {
4686 case 0:
49a9b07e 4687 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4688 break;
4689 case 2:
4690 vcpu->arch.cr2 = val;
4691 break;
4692 case 3:
2390218b 4693 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4694 break;
4695 case 4:
a83b29c6 4696 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4697 break;
4698 case 8:
eea1cff9 4699 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4700 break;
4701 default:
a737f256 4702 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4703 res = -1;
52a46617 4704 }
0f12244f
GN		 4705
4706 return res;
52a46617
GN		 4707}
4708
717746e3 4709static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4710{
717746e3 4711 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4712}
4713
4bff1e86 4714static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4715{
4bff1e86 4716 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4717}
4718
4bff1e86 4719static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4720{
4bff1e86 4721 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4722}
4723
1ac9d0cf
AK		 4724static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4725{
4726 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4727}
4728
4729static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4730{
4731 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4732}
4733
4bff1e86
AK		 4734static unsigned long emulator_get_cached_segment_base(
4735 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4736{
4bff1e86 4737 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4738}
4739
1aa36616
AK		 4740static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4741 struct desc_struct *desc, u32 *base3,
4742 int seg)
2dafc6c2
GN		 4743{
4744 struct kvm_segment var;
4745
4bff1e86 4746 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4747 *selector = var.selector;
2dafc6c2 4748
378a8b09
GN		 4749 if (var.unusable) {
4750 memset(desc, 0, sizeof(*desc));
2dafc6c2 4751 return false;
378a8b09 4752 }
2dafc6c2
GN		 4753
4754 if (var.g)
4755 var.limit >>= 12;
4756 set_desc_limit(desc, var.limit);
4757 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4758#ifdef CONFIG_X86_64
4759 if (base3)
4760 *base3 = var.base >> 32;
4761#endif
2dafc6c2
GN		 4762 desc->type = var.type;
4763 desc->s = var.s;
4764 desc->dpl = var.dpl;
4765 desc->p = var.present;
4766 desc->avl = var.avl;
4767 desc->l = var.l;
4768 desc->d = var.db;
4769 desc->g = var.g;
4770
4771 return true;
4772}
4773
1aa36616
AK		 4774static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4775 struct desc_struct *desc, u32 base3,
4776 int seg)
2dafc6c2 4777{
4bff1e86 4778 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4779 struct kvm_segment var;
4780
1aa36616 4781 var.selector = selector;
2dafc6c2 4782 var.base = get_desc_base(desc);
5601d05b
GN		 4783#ifdef CONFIG_X86_64
4784 var.base |= ((u64)base3) << 32;
4785#endif
2dafc6c2
GN		 4786 var.limit = get_desc_limit(desc);
4787 if (desc->g)
4788 var.limit = (var.limit << 12) | 0xfff;
4789 var.type = desc->type;
2dafc6c2
GN		 4790 var.dpl = desc->dpl;
4791 var.db = desc->d;
4792 var.s = desc->s;
4793 var.l = desc->l;
4794 var.g = desc->g;
4795 var.avl = desc->avl;
4796 var.present = desc->p;
4797 var.unusable = !var.present;
4798 var.padding = 0;
4799
4800 kvm_set_segment(vcpu, &var, seg);
4801 return;
4802}
4803
717746e3
AK		 4804static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4805 u32 msr_index, u64 *pdata)
4806{
4807 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4808}
4809
4810static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4811 u32 msr_index, u64 data)
4812{
8fe8ab46
WA		 4813 struct msr_data msr;
4814
4815 msr.data = data;
4816 msr.index = msr_index;
4817 msr.host_initiated = false;
4818 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4819}
4820
67f4d428
NA		 4821static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4822 u32 pmc)
4823{
4824 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4825}
4826
222d21aa
AK		 4827static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4828 u32 pmc, u64 *pdata)
4829{
4830 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4831}
4832
6c3287f7
AK		 4833static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4834{
4835 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4836}
4837
5037f6f3
AK		 4838static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4839{
4840 preempt_disable();
5197b808 4841 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4842 /*
4843 * CR0.TS may reference the host fpu state, not the guest fpu state,
4844 * so it may be clear at this point.
4845 */
4846 clts();
4847}
4848
4849static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4850{
4851 preempt_enable();
4852}
4853
2953538e 4854static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4855 struct x86_instruction_info *info,
c4f035c6
AK		 4856 enum x86_intercept_stage stage)
4857{
2953538e 4858 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4859}
4860
0017f93a 4861static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4862 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4863{
0017f93a 4864 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4865}
4866
dd856efa
AK		 4867static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4868{
4869 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4870}
4871
4872static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4873{
4874 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4875}
4876
0225fb50 4877static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4878 .read_gpr = emulator_read_gpr,
4879 .write_gpr = emulator_write_gpr,
1871c602 4880 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4881 .write_std = kvm_write_guest_virt_system,
1871c602 4882 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4883 .read_emulated = emulator_read_emulated,
4884 .write_emulated = emulator_write_emulated,
4885 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4886 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4887 .pio_in_emulated = emulator_pio_in_emulated,
4888 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4889 .get_segment = emulator_get_segment,
4890 .set_segment = emulator_set_segment,
5951c442 4891 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4892 .get_gdt = emulator_get_gdt,
160ce1f1 4893 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4894 .set_gdt = emulator_set_gdt,
4895 .set_idt = emulator_set_idt,
52a46617
GN		 4896 .get_cr = emulator_get_cr,
4897 .set_cr = emulator_set_cr,
9c537244 4898 .cpl = emulator_get_cpl,
35aa5375
GN		 4899 .get_dr = emulator_get_dr,
4900 .set_dr = emulator_set_dr,
717746e3
AK		 4901 .set_msr = emulator_set_msr,
4902 .get_msr = emulator_get_msr,
67f4d428 4903 .check_pmc = emulator_check_pmc,
222d21aa 4904 .read_pmc = emulator_read_pmc,
6c3287f7 4905 .halt = emulator_halt,
bcaf5cc5 4906 .wbinvd = emulator_wbinvd,
d6aa1000 4907 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4908 .get_fpu = emulator_get_fpu,
4909 .put_fpu = emulator_put_fpu,
c4f035c6 4910 .intercept = emulator_intercept,
bdb42f5a 4911 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4912};
4913
95cb2295
GN		 4914static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4915{
37ccdcbe 4916 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4917 /*
4918 * an sti; sti; sequence only disable interrupts for the first
4919 * instruction. So, if the last instruction, be it emulated or
4920 * not, left the system with the INT_STI flag enabled, it
4921 * means that the last instruction is an sti. We should not
4922 * leave the flag on in this case. The same goes for mov ss
4923 */
37ccdcbe
PB		 4924 if (int_shadow & mask)
4925 mask = 0;
6addfc42 4926 if (unlikely(int_shadow || mask)) {
95cb2295 4927 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4928 if (!mask)
4929 kvm_make_request(KVM_REQ_EVENT, vcpu);
4930 }
95cb2295
GN		 4931}
4932
54b8486f
GN		 4933static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4934{
4935 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4936 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4937 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4938 else if (ctxt->exception.error_code_valid)
4939 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4940 ctxt->exception.error_code);
54b8486f 4941 else
da9cb575 4942 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4943}
4944
8ec4722d
MG		 4945static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4946{
adf52235 4947 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4948 int cs_db, cs_l;
4949
8ec4722d
MG		 4950 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4951
adf52235
TY		 4952 ctxt->eflags = kvm_get_rflags(vcpu);
4953 ctxt->eip = kvm_rip_read(vcpu);
4954 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4955 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4956 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4957 cs_db ? X86EMUL_MODE_PROT32 :
4958 X86EMUL_MODE_PROT16;
4959 ctxt->guest_mode = is_guest_mode(vcpu);
4960
dd856efa 4961 init_decode_cache(ctxt);
7ae441ea 4962 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4963}
4964
71f9833b 4965int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4966{
9d74191a 4967 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4968 int ret;
4969
4970 init_emulate_ctxt(vcpu);
4971
9dac77fa
AK		 4972 ctxt->op_bytes = 2;
4973 ctxt->ad_bytes = 2;
4974 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4975 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4976
4977 if (ret != X86EMUL_CONTINUE)
4978 return EMULATE_FAIL;
4979
9dac77fa 4980 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4981 kvm_rip_write(vcpu, ctxt->eip);
4982 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4983
4984 if (irq == NMI_VECTOR)
7460fb4a 4985 vcpu->arch.nmi_pending = 0;
63995653
MG		 4986 else
4987 vcpu->arch.interrupt.pending = false;
4988
4989 return EMULATE_DONE;
4990}
4991EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4992
6d77dbfc
GN		 4993static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4994{
fc3a9157
JR		 4995 int r = EMULATE_DONE;
4996
6d77dbfc
GN		 4997 ++vcpu->stat.insn_emulation_fail;
4998 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4999 if (!is_guest_mode(vcpu)) {
5000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5002 vcpu->run->internal.ndata = 0;
5003 r = EMULATE_FAIL;
5004 }
6d77dbfc 5005 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5006
5007 return r;
6d77dbfc
GN		 5008}
5009
93c05d3e 5010static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5011 bool write_fault_to_shadow_pgtable,
5012 int emulation_type)
a6f177ef 5013{
95b3cf69 5014 gpa_t gpa = cr2;
8e3d9d06 5015 pfn_t pfn;
a6f177ef 5016
991eebf9
GN		 5017 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5018 return false;
5019
95b3cf69
XG		 5020 if (!vcpu->arch.mmu.direct_map) {
5021 /*
5022 * Write permission should be allowed since only
5023 * write access need to be emulated.
5024 */
5025 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5026
95b3cf69
XG		 5027 /*
5028 * If the mapping is invalid in guest, let cpu retry
5029 * it to generate fault.
5030 */
5031 if (gpa == UNMAPPED_GVA)
5032 return true;
5033 }
a6f177ef 5034
8e3d9d06
XG		 5035 /*
5036 * Do not retry the unhandleable instruction if it faults on the
5037 * readonly host memory, otherwise it will goto a infinite loop:
5038 * retry instruction -> write #PF -> emulation fail -> retry
5039 * instruction -> ...
5040 */
5041 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5042
5043 /*
5044 * If the instruction failed on the error pfn, it can not be fixed,
5045 * report the error to userspace.
5046 */
5047 if (is_error_noslot_pfn(pfn))
5048 return false;
5049
5050 kvm_release_pfn_clean(pfn);
5051
5052 /* The instructions are well-emulated on direct mmu. */
5053 if (vcpu->arch.mmu.direct_map) {
5054 unsigned int indirect_shadow_pages;
5055
5056 spin_lock(&vcpu->kvm->mmu_lock);
5057 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5058 spin_unlock(&vcpu->kvm->mmu_lock);
5059
5060 if (indirect_shadow_pages)
5061 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5062
a6f177ef 5063 return true;
8e3d9d06 5064 }
a6f177ef 5065
95b3cf69
XG		 5066 /*
5067 * if emulation was due to access to shadowed page table
5068 * and it failed try to unshadow page and re-enter the
5069 * guest to let CPU execute the instruction.
5070 */
5071 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5072
5073 /*
5074 * If the access faults on its page table, it can not
5075 * be fixed by unprotecting shadow page and it should
5076 * be reported to userspace.
5077 */
5078 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5079}
5080
1cb3f3ae
XG		 5081static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5082 unsigned long cr2, int emulation_type)
5083{
5084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5085 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5086
5087 last_retry_eip = vcpu->arch.last_retry_eip;
5088 last_retry_addr = vcpu->arch.last_retry_addr;
5089
5090 /*
5091 * If the emulation is caused by #PF and it is non-page_table
5092 * writing instruction, it means the VM-EXIT is caused by shadow
5093 * page protected, we can zap the shadow page and retry this
5094 * instruction directly.
5095 *
5096 * Note: if the guest uses a non-page-table modifying instruction
5097 * on the PDE that points to the instruction, then we will unmap
5098 * the instruction and go to an infinite loop. So, we cache the
5099 * last retried eip and the last fault address, if we meet the eip
5100 * and the address again, we can break out of the potential infinite
5101 * loop.
5102 */
5103 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5104
5105 if (!(emulation_type & EMULTYPE_RETRY))
5106 return false;
5107
5108 if (x86_page_table_writing_insn(ctxt))
5109 return false;
5110
5111 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5112 return false;
5113
5114 vcpu->arch.last_retry_eip = ctxt->eip;
5115 vcpu->arch.last_retry_addr = cr2;
5116
5117 if (!vcpu->arch.mmu.direct_map)
5118 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5119
22368028 5120 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5121
5122 return true;
5123}
5124
716d51ab
GN		 5125static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5126static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5127
4a1e10d5
PB		 5128static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5129 unsigned long *db)
5130{
5131 u32 dr6 = 0;
5132 int i;
5133 u32 enable, rwlen;
5134
5135 enable = dr7;
5136 rwlen = dr7 >> 16;
5137 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5138 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5139 dr6 |= (1 << i);
5140 return dr6;
5141}
5142
6addfc42 5143static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5144{
5145 struct kvm_run *kvm_run = vcpu->run;
5146
5147 /*
6addfc42
PB		 5148 * rflags is the old, "raw" value of the flags. The new value has
5149 * not been saved yet.
663f4c61
PB		 5150 *
5151 * This is correct even for TF set by the guest, because "the
5152 * processor will not generate this exception after the instruction
5153 * that sets the TF flag".
5154 */
663f4c61
PB		 5155 if (unlikely(rflags & X86_EFLAGS_TF)) {
5156 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5157 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5158 DR6_RTM;
663f4c61
PB		 5159 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5160 kvm_run->debug.arch.exception = DB_VECTOR;
5161 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5162 *r = EMULATE_USER_EXIT;
5163 } else {
5164 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5165 /*
5166 * "Certain debug exceptions may clear bit 0-3. The
5167 * remaining contents of the DR6 register are never
5168 * cleared by the processor".
5169 */
5170 vcpu->arch.dr6 &= ~15;
6f43ed01 5171 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5172 kvm_queue_exception(vcpu, DB_VECTOR);
5173 }
5174 }
5175}
5176
4a1e10d5
PB		 5177static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5178{
5179 struct kvm_run *kvm_run = vcpu->run;
5180 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5181 u32 dr6 = 0;
5182
5183 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5184 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5185 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5186 vcpu->arch.guest_debug_dr7,
5187 vcpu->arch.eff_db);
5188
5189 if (dr6 != 0) {
6f43ed01 5190 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5191 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5192 get_segment_base(vcpu, VCPU_SREG_CS);
5193
5194 kvm_run->debug.arch.exception = DB_VECTOR;
5195 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5196 *r = EMULATE_USER_EXIT;
5197 return true;
5198 }
5199 }
5200
4161a569
NA		 5201 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5202 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5203 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5204 vcpu->arch.dr7,
5205 vcpu->arch.db);
5206
5207 if (dr6 != 0) {
5208 vcpu->arch.dr6 &= ~15;
6f43ed01 5209 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5210 kvm_queue_exception(vcpu, DB_VECTOR);
5211 *r = EMULATE_DONE;
5212 return true;
5213 }
5214 }
5215
5216 return false;
5217}
5218
51d8b661
AP		 5219int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5220 unsigned long cr2,
dc25e89e
AP		 5221 int emulation_type,
5222 void *insn,
5223 int insn_len)
bbd9b64e 5224{
95cb2295 5225 int r;
9d74191a 5226 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5227 bool writeback = true;
93c05d3e 5228 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5229
93c05d3e
XG		 5230 /*
5231 * Clear write_fault_to_shadow_pgtable here to ensure it is
5232 * never reused.
5233 */
5234 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5235 kvm_clear_exception_queue(vcpu);
8d7d8102 5236
571008da 5237 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5238 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5239
5240 /*
5241 * We will reenter on the same instruction since
5242 * we do not set complete_userspace_io. This does not
5243 * handle watchpoints yet, those would be handled in
5244 * the emulate_ops.
5245 */
5246 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5247 return r;
5248
9d74191a
TY		 5249 ctxt->interruptibility = 0;
5250 ctxt->have_exception = false;
e0ad0b47 5251 ctxt->exception.vector = -1;
9d74191a 5252 ctxt->perm_ok = false;
bbd9b64e 5253
b51e974f 5254 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5255
9d74191a 5256 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5257
e46479f8 5258 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5259 ++vcpu->stat.insn_emulation;
1d2887e2 5260 if (r != EMULATION_OK) {
4005996e
AK		 5261 if (emulation_type & EMULTYPE_TRAP_UD)
5262 return EMULATE_FAIL;
991eebf9
GN		 5263 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5264 emulation_type))
bbd9b64e 5265 return EMULATE_DONE;
6d77dbfc
GN		 5266 if (emulation_type & EMULTYPE_SKIP)
5267 return EMULATE_FAIL;
5268 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5269 }
5270 }
5271
ba8afb6b 5272 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5273 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5274 if (ctxt->eflags & X86_EFLAGS_RF)
5275 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5276 return EMULATE_DONE;
5277 }
5278
1cb3f3ae
XG		 5279 if (retry_instruction(ctxt, cr2, emulation_type))
5280 return EMULATE_DONE;
5281
7ae441ea 5282 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5283 changes registers values during IO operation */
7ae441ea
GN		 5284 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5285 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5286 emulator_invalidate_register_cache(ctxt);
7ae441ea 5287 }
4d2179e1 5288
5cd21917 5289restart:
9d74191a 5290 r = x86_emulate_insn(ctxt);
bbd9b64e 5291
775fde86
JR		 5292 if (r == EMULATION_INTERCEPTED)
5293 return EMULATE_DONE;
5294
d2ddd1c4 5295 if (r == EMULATION_FAILED) {
991eebf9
GN		 5296 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5297 emulation_type))
c3cd7ffa
GN		 5298 return EMULATE_DONE;
5299
6d77dbfc 5300 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5301 }
5302
9d74191a 5303 if (ctxt->have_exception) {
54b8486f 5304 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5305 r = EMULATE_DONE;
5306 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5307 if (!vcpu->arch.pio.in) {
5308 /* FIXME: return into emulator if single-stepping. */
3457e419 5309 vcpu->arch.pio.count = 0;
0912c977 5310 } else {
7ae441ea 5311 writeback = false;
716d51ab
GN		 5312 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5313 }
ac0a48c3 5314 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5315 } else if (vcpu->mmio_needed) {
5316 if (!vcpu->mmio_is_write)
5317 writeback = false;
ac0a48c3 5318 r = EMULATE_USER_EXIT;
716d51ab 5319 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5320 } else if (r == EMULATION_RESTART)
5cd21917 5321 goto restart;
d2ddd1c4
GN		 5322 else
5323 r = EMULATE_DONE;
f850e2e6 5324
7ae441ea 5325 if (writeback) {
6addfc42 5326 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5327 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5328 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5329 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5330 if (r == EMULATE_DONE)
6addfc42
PB		 5331 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5332 __kvm_set_rflags(vcpu, ctxt->eflags);
5333
5334 /*
5335 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5336 * do nothing, and it will be requested again as soon as
5337 * the shadow expires. But we still need to check here,
5338 * because POPF has no interrupt shadow.
5339 */
5340 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5341 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5342 } else
5343 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5344
5345 return r;
de7d789a 5346}
51d8b661 5347EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5348
cf8f70bf 5349int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5350{
cf8f70bf 5351 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5352 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5353 size, port, &val, 1);
cf8f70bf 5354 /* do not return to emulator after return from userspace */
7972995b 5355 vcpu->arch.pio.count = 0;
de7d789a
CO		 5356 return ret;
5357}
cf8f70bf 5358EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5359
8cfdc000
ZA		 5360static void tsc_bad(void *info)
5361{
0a3aee0d 5362 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5363}
5364
5365static void tsc_khz_changed(void *data)
c8076604 5366{
8cfdc000
ZA		 5367 struct cpufreq_freqs *freq = data;
5368 unsigned long khz = 0;
5369
5370 if (data)
5371 khz = freq->new;
5372 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5373 khz = cpufreq_quick_get(raw_smp_processor_id());
5374 if (!khz)
5375 khz = tsc_khz;
0a3aee0d 5376 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5377}
5378
c8076604
GH		 5379static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5380 void *data)
5381{
5382 struct cpufreq_freqs *freq = data;
5383 struct kvm *kvm;
5384 struct kvm_vcpu *vcpu;
5385 int i, send_ipi = 0;
5386
8cfdc000
ZA		 5387 /*
5388 * We allow guests to temporarily run on slowing clocks,
5389 * provided we notify them after, or to run on accelerating
5390 * clocks, provided we notify them before. Thus time never
5391 * goes backwards.
5392 *
5393 * However, we have a problem. We can't atomically update
5394 * the frequency of a given CPU from this function; it is
5395 * merely a notifier, which can be called from any CPU.
5396 * Changing the TSC frequency at arbitrary points in time
5397 * requires a recomputation of local variables related to
5398 * the TSC for each VCPU. We must flag these local variables
5399 * to be updated and be sure the update takes place with the
5400 * new frequency before any guests proceed.
5401 *
5402 * Unfortunately, the combination of hotplug CPU and frequency
5403 * change creates an intractable locking scenario; the order
5404 * of when these callouts happen is undefined with respect to
5405 * CPU hotplug, and they can race with each other. As such,
5406 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5407 * undefined; you can actually have a CPU frequency change take
5408 * place in between the computation of X and the setting of the
5409 * variable. To protect against this problem, all updates of
5410 * the per_cpu tsc_khz variable are done in an interrupt
5411 * protected IPI, and all callers wishing to update the value
5412 * must wait for a synchronous IPI to complete (which is trivial
5413 * if the caller is on the CPU already). This establishes the
5414 * necessary total order on variable updates.
5415 *
5416 * Note that because a guest time update may take place
5417 * anytime after the setting of the VCPU's request bit, the
5418 * correct TSC value must be set before the request. However,
5419 * to ensure the update actually makes it to any guest which
5420 * starts running in hardware virtualization between the set
5421 * and the acquisition of the spinlock, we must also ping the
5422 * CPU after setting the request bit.
5423 *
5424 */
5425
c8076604
GH		 5426 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5427 return 0;
5428 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5429 return 0;
8cfdc000
ZA		 5430
5431 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5432
2f303b74 5433 spin_lock(&kvm_lock);
c8076604 5434 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5435 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5436 if (vcpu->cpu != freq->cpu)
5437 continue;
c285545f 5438 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5439 if (vcpu->cpu != smp_processor_id())
8cfdc000 5440 send_ipi = 1;
c8076604
GH		 5441 }
5442 }
2f303b74 5443 spin_unlock(&kvm_lock);
c8076604
GH		 5444
5445 if (freq->old < freq->new && send_ipi) {
5446 /*
5447 * We upscale the frequency. Must make the guest
5448 * doesn't see old kvmclock values while running with
5449 * the new frequency, otherwise we risk the guest sees
5450 * time go backwards.
5451 *
5452 * In case we update the frequency for another cpu
5453 * (which might be in guest context) send an interrupt
5454 * to kick the cpu out of guest context. Next time
5455 * guest context is entered kvmclock will be updated,
5456 * so the guest will not see stale values.
5457 */
8cfdc000 5458 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5459 }
5460 return 0;
5461}
5462
5463static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5464 .notifier_call = kvmclock_cpufreq_notifier
5465};
5466
5467static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5468 unsigned long action, void *hcpu)
5469{
5470 unsigned int cpu = (unsigned long)hcpu;
5471
5472 switch (action) {
5473 case CPU_ONLINE:
5474 case CPU_DOWN_FAILED:
5475 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5476 break;
5477 case CPU_DOWN_PREPARE:
5478 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5479 break;
5480 }
5481 return NOTIFY_OK;
5482}
5483
5484static struct notifier_block kvmclock_cpu_notifier_block = {
5485 .notifier_call = kvmclock_cpu_notifier,
5486 .priority = -INT_MAX
c8076604
GH		 5487};
5488
b820cc0c
ZA		 5489static void kvm_timer_init(void)
5490{
5491 int cpu;
5492
c285545f 5493 max_tsc_khz = tsc_khz;
460dd42e
SB		 5494
5495 cpu_notifier_register_begin();
b820cc0c 5496 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5497#ifdef CONFIG_CPU_FREQ
5498 struct cpufreq_policy policy;
5499 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5500 cpu = get_cpu();
5501 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5502 if (policy.cpuinfo.max_freq)
5503 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5504 put_cpu();
c285545f 5505#endif
b820cc0c
ZA		 5506 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5507 CPUFREQ_TRANSITION_NOTIFIER);
5508 }
c285545f 5509 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5510 for_each_online_cpu(cpu)
5511 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5512
5513 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5514 cpu_notifier_register_done();
5515
b820cc0c
ZA		 5516}
5517
ff9d07a0
ZY		 5518static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5519
f5132b01 5520int kvm_is_in_guest(void)
ff9d07a0 5521{
086c9855 5522 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5523}
5524
5525static int kvm_is_user_mode(void)
5526{
5527 int user_mode = 3;
dcf46b94 5528
086c9855
AS		 5529 if (__this_cpu_read(current_vcpu))
5530 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5531
ff9d07a0
ZY		 5532 return user_mode != 0;
5533}
5534
5535static unsigned long kvm_get_guest_ip(void)
5536{
5537 unsigned long ip = 0;
dcf46b94 5538
086c9855
AS		 5539 if (__this_cpu_read(current_vcpu))
5540 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5541
ff9d07a0
ZY		 5542 return ip;
5543}
5544
5545static struct perf_guest_info_callbacks kvm_guest_cbs = {
5546 .is_in_guest = kvm_is_in_guest,
5547 .is_user_mode = kvm_is_user_mode,
5548 .get_guest_ip = kvm_get_guest_ip,
5549};
5550
5551void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5552{
086c9855 5553 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5554}
5555EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5556
5557void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5558{
086c9855 5559 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5560}
5561EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5562
ce88decf
XG		 5563static void kvm_set_mmio_spte_mask(void)
5564{
5565 u64 mask;
5566 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5567
5568 /*
5569 * Set the reserved bits and the present bit of an paging-structure
5570 * entry to generate page fault with PFER.RSV = 1.
5571 */
885032b9
XG		 5572 /* Mask the reserved physical address bits. */
5573 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5574
5575 /* Bit 62 is always reserved for 32bit host. */
5576 mask |= 0x3ull << 62;
5577
5578 /* Set the present bit. */
ce88decf
XG		 5579 mask |= 1ull;
5580
5581#ifdef CONFIG_X86_64
5582 /*
5583 * If reserved bit is not supported, clear the present bit to disable
5584 * mmio page fault.
5585 */
5586 if (maxphyaddr == 52)
5587 mask &= ~1ull;
5588#endif
5589
5590 kvm_mmu_set_mmio_spte_mask(mask);
5591}
5592
16e8d74d
MT		 5593#ifdef CONFIG_X86_64
5594static void pvclock_gtod_update_fn(struct work_struct *work)
5595{
d828199e
MT		 5596 struct kvm *kvm;
5597
5598 struct kvm_vcpu *vcpu;
5599 int i;
5600
2f303b74 5601 spin_lock(&kvm_lock);
d828199e
MT		 5602 list_for_each_entry(kvm, &vm_list, vm_list)
5603 kvm_for_each_vcpu(i, vcpu, kvm)
5604 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5605 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5606 spin_unlock(&kvm_lock);
16e8d74d
MT		 5607}
5608
5609static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5610
5611/*
5612 * Notification about pvclock gtod data update.
5613 */
5614static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5615 void *priv)
5616{
5617 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5618 struct timekeeper *tk = priv;
5619
5620 update_pvclock_gtod(tk);
5621
5622 /* disable master clock if host does not trust, or does not
5623 * use, TSC clocksource
5624 */
5625 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5626 atomic_read(&kvm_guest_has_master_clock) != 0)
5627 queue_work(system_long_wq, &pvclock_gtod_work);
5628
5629 return 0;
5630}
5631
5632static struct notifier_block pvclock_gtod_notifier = {
5633 .notifier_call = pvclock_gtod_notify,
5634};
5635#endif
5636
f8c16bba 5637int kvm_arch_init(void *opaque)
043405e1 5638{
b820cc0c 5639 int r;
6b61edf7 5640 struct kvm_x86_ops *ops = opaque;
f8c16bba 5641
f8c16bba
ZX		 5642 if (kvm_x86_ops) {
5643 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5644 r = -EEXIST;
5645 goto out;
f8c16bba
ZX		 5646 }
5647
5648 if (!ops->cpu_has_kvm_support()) {
5649 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5650 r = -EOPNOTSUPP;
5651 goto out;
f8c16bba
ZX		 5652 }
5653 if (ops->disabled_by_bios()) {
5654 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5655 r = -EOPNOTSUPP;
5656 goto out;
f8c16bba
ZX		 5657 }
5658
013f6a5d
MT		 5659 r = -ENOMEM;
5660 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5661 if (!shared_msrs) {
5662 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5663 goto out;
5664 }
5665
97db56ce
AK		 5666 r = kvm_mmu_module_init();
5667 if (r)
013f6a5d 5668 goto out_free_percpu;
97db56ce 5669
ce88decf 5670 kvm_set_mmio_spte_mask();
97db56ce 5671
f8c16bba 5672 kvm_x86_ops = ops;
920c8377
PB		 5673 kvm_init_msr_list();
5674
7b52345e 5675 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5676 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5677
b820cc0c 5678 kvm_timer_init();
c8076604 5679
ff9d07a0
ZY		 5680 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5681
2acf923e
DC		 5682 if (cpu_has_xsave)
5683 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5684
c5cc421b 5685 kvm_lapic_init();
16e8d74d
MT		 5686#ifdef CONFIG_X86_64
5687 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5688#endif
5689
f8c16bba 5690 return 0;
56c6d28a 5691
013f6a5d
MT		 5692out_free_percpu:
5693 free_percpu(shared_msrs);
56c6d28a 5694out:
56c6d28a 5695 return r;
043405e1 5696}
8776e519 5697
f8c16bba
ZX		 5698void kvm_arch_exit(void)
5699{
ff9d07a0
ZY		 5700 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5701
888d256e
JK		 5702 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5703 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5704 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5705 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5706#ifdef CONFIG_X86_64
5707 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5708#endif
f8c16bba 5709 kvm_x86_ops = NULL;
56c6d28a 5710 kvm_mmu_module_exit();
013f6a5d 5711 free_percpu(shared_msrs);
56c6d28a 5712}
f8c16bba 5713
8776e519
HB		 5714int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5715{
5716 ++vcpu->stat.halt_exits;
5717 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5718 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5719 return 1;
5720 } else {
5721 vcpu->run->exit_reason = KVM_EXIT_HLT;
5722 return 0;
5723 }
5724}
5725EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5726
55cd8e5a
GN		 5727int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5728{
5729 u64 param, ingpa, outgpa, ret;
5730 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5731 bool fast, longmode;
55cd8e5a
GN		 5732
5733 /*
5734 * hypercall generates UD from non zero cpl and real mode
5735 * per HYPER-V spec
5736 */
3eeb3288 5737 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5738 kvm_queue_exception(vcpu, UD_VECTOR);
5739 return 0;
5740 }
5741
a449c7aa 5742 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5743
5744 if (!longmode) {
ccd46936
GN		 5745 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5746 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5747 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5748 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5749 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5750 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5751 }
5752#ifdef CONFIG_X86_64
5753 else {
5754 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5755 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5756 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5757 }
5758#endif
5759
5760 code = param & 0xffff;
5761 fast = (param >> 16) & 0x1;
5762 rep_cnt = (param >> 32) & 0xfff;
5763 rep_idx = (param >> 48) & 0xfff;
5764
5765 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5766
c25bc163
GN		 5767 switch (code) {
5768 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5769 kvm_vcpu_on_spin(vcpu);
5770 break;
5771 default:
5772 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5773 break;
5774 }
55cd8e5a
GN		 5775
5776 ret = res | (((u64)rep_done & 0xfff) << 32);
5777 if (longmode) {
5778 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5779 } else {
5780 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5781 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5782 }
5783
5784 return 1;
5785}
5786
6aef266c
SV		 5787/*
5788 * kvm_pv_kick_cpu_op: Kick a vcpu.
5789 *
5790 * @apicid - apicid of vcpu to be kicked.
5791 */
5792static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5793{
24d2166b 5794 struct kvm_lapic_irq lapic_irq;
6aef266c 5795
24d2166b
R		 5796 lapic_irq.shorthand = 0;
5797 lapic_irq.dest_mode = 0;
5798 lapic_irq.dest_id = apicid;
6aef266c 5799
24d2166b
R		 5800 lapic_irq.delivery_mode = APIC_DM_REMRD;
5801 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5802}
5803
8776e519
HB		 5804int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5805{
5806 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5807 int op_64_bit, r = 1;
8776e519 5808
55cd8e5a
GN		 5809 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5810 return kvm_hv_hypercall(vcpu);
5811
5fdbf976
MT		 5812 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5813 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5814 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5815 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5816 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5817
229456fc 5818 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5819
a449c7aa
NA		 5820 op_64_bit = is_64_bit_mode(vcpu);
5821 if (!op_64_bit) {
8776e519
HB		 5822 nr &= 0xFFFFFFFF;
5823 a0 &= 0xFFFFFFFF;
5824 a1 &= 0xFFFFFFFF;
5825 a2 &= 0xFFFFFFFF;
5826 a3 &= 0xFFFFFFFF;
5827 }
5828
07708c4a
JK		 5829 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5830 ret = -KVM_EPERM;
5831 goto out;
5832 }
5833
8776e519 5834 switch (nr) {
b93463aa
AK		 5835 case KVM_HC_VAPIC_POLL_IRQ:
5836 ret = 0;
5837 break;
6aef266c
SV		 5838 case KVM_HC_KICK_CPU:
5839 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5840 ret = 0;
5841 break;
8776e519
HB		 5842 default:
5843 ret = -KVM_ENOSYS;
5844 break;
5845 }
07708c4a 5846out:
a449c7aa
NA		 5847 if (!op_64_bit)
5848 ret = (u32)ret;
5fdbf976 5849 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5850 ++vcpu->stat.hypercalls;
2f333bcb 5851 return r;
8776e519
HB		 5852}
5853EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5854
b6785def 5855static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5856{
d6aa1000 5857 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5858 char instruction[3];
5fdbf976 5859 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5860
8776e519 5861 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5862
9d74191a 5863 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5864}
5865
b6c7a5dc
HB		 5866/*
5867 * Check if userspace requested an interrupt window, and that the
5868 * interrupt window is open.
5869 *
5870 * No need to exit to userspace if we already have an interrupt queued.
5871 */
851ba692 5872static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5873{
8061823a 5874 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5875 vcpu->run->request_interrupt_window &&
5df56646 5876 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5877}
5878
851ba692 5879static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5880{
851ba692
AK		 5881 struct kvm_run *kvm_run = vcpu->run;
5882
91586a3b 5883 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5884 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5885 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5886 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5887 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5888 else
b6c7a5dc 5889 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5890 kvm_arch_interrupt_allowed(vcpu) &&
5891 !kvm_cpu_has_interrupt(vcpu) &&
5892 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5893}
5894
95ba8273
GN		 5895static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5896{
5897 int max_irr, tpr;
5898
5899 if (!kvm_x86_ops->update_cr8_intercept)
5900 return;
5901
88c808fd
AK		 5902 if (!vcpu->arch.apic)
5903 return;
5904
8db3baa2
GN		 5905 if (!vcpu->arch.apic->vapic_addr)
5906 max_irr = kvm_lapic_find_highest_irr(vcpu);
5907 else
5908 max_irr = -1;
95ba8273
GN		 5909
5910 if (max_irr != -1)
5911 max_irr >>= 4;
5912
5913 tpr = kvm_lapic_get_cr8(vcpu);
5914
5915 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5916}
5917
b6b8a145 5918static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5919{
b6b8a145
JK		 5920 int r;
5921
95ba8273 5922 /* try to reinject previous events if any */
b59bb7bd 5923 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5924 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5925 vcpu->arch.exception.has_error_code,
5926 vcpu->arch.exception.error_code);
d6e8c854
NA		 5927
5928 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5929 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5930 X86_EFLAGS_RF);
5931
b59bb7bd
GN		 5932 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5933 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5934 vcpu->arch.exception.error_code,
5935 vcpu->arch.exception.reinject);
b6b8a145 5936 return 0;
b59bb7bd
GN		 5937 }
5938
95ba8273
GN		 5939 if (vcpu->arch.nmi_injected) {
5940 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5941 return 0;
95ba8273
GN		 5942 }
5943
5944 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5945 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5946 return 0;
5947 }
5948
5949 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5950 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5951 if (r != 0)
5952 return r;
95ba8273
GN		 5953 }
5954
5955 /* try to inject new event if pending */
5956 if (vcpu->arch.nmi_pending) {
5957 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5958 --vcpu->arch.nmi_pending;
95ba8273
GN		 5959 vcpu->arch.nmi_injected = true;
5960 kvm_x86_ops->set_nmi(vcpu);
5961 }
c7c9c56c 5962 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5963 /*
5964 * Because interrupts can be injected asynchronously, we are
5965 * calling check_nested_events again here to avoid a race condition.
5966 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5967 * proposal and current concerns. Perhaps we should be setting
5968 * KVM_REQ_EVENT only on certain events and not unconditionally?
5969 */
5970 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5971 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5972 if (r != 0)
5973 return r;
5974 }
95ba8273 5975 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5976 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5977 false);
5978 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5979 }
5980 }
b6b8a145 5981 return 0;
95ba8273
GN		 5982}
5983
7460fb4a
AK		 5984static void process_nmi(struct kvm_vcpu *vcpu)
5985{
5986 unsigned limit = 2;
5987
5988 /*
5989 * x86 is limited to one NMI running, and one NMI pending after it.
5990 * If an NMI is already in progress, limit further NMIs to just one.
5991 * Otherwise, allow two (and we'll inject the first one immediately).
5992 */
5993 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5994 limit = 1;
5995
5996 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5997 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5998 kvm_make_request(KVM_REQ_EVENT, vcpu);
5999}
6000
3d81bc7e 6001static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6002{
6003 u64 eoi_exit_bitmap[4];
cf9e65b7 6004 u32 tmr[8];
c7c9c56c 6005
3d81bc7e
YZ		 6006 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6007 return;
c7c9c56c
YZ		 6008
6009 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6010 memset(tmr, 0, 32);
c7c9c56c 6011
cf9e65b7 6012 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6013 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6014 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6015}
6016
9357d939
TY		 6017/*
6018 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6019 * exiting to the userspace. Otherwise, the value will be returned to the
6020 * userspace.
6021 */
851ba692 6022static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6023{
6024 int r;
6a8b1d13 6025 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6026 vcpu->run->request_interrupt_window;
730dca42 6027 bool req_immediate_exit = false;
b6c7a5dc 6028
3e007509 6029 if (vcpu->requests) {
a8eeb04a 6030 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6031 kvm_mmu_unload(vcpu);
a8eeb04a 6032 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6033 __kvm_migrate_timers(vcpu);
d828199e
MT		 6034 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6035 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6036 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6037 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6038 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6039 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6040 if (unlikely(r))
6041 goto out;
6042 }
a8eeb04a 6043 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6044 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6045 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 6046 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 6047 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6048 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6049 r = 0;
6050 goto out;
6051 }
a8eeb04a 6052 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6053 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6054 r = 0;
6055 goto out;
6056 }
a8eeb04a 6057 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6058 vcpu->fpu_active = 0;
6059 kvm_x86_ops->fpu_deactivate(vcpu);
6060 }
af585b92
GN		 6061 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6062 /* Page is swapped out. Do synthetic halt */
6063 vcpu->arch.apf.halted = true;
6064 r = 1;
6065 goto out;
6066 }
c9aaa895
GC		 6067 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6068 record_steal_time(vcpu);
7460fb4a
AK		 6069 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6070 process_nmi(vcpu);
f5132b01
GN		 6071 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6072 kvm_handle_pmu_event(vcpu);
6073 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6074 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6075 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6076 vcpu_scan_ioapic(vcpu);
2f52d58c 6077 }
b93463aa 6078
b463a6f7 6079 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6080 kvm_apic_accept_events(vcpu);
6081 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6082 r = 1;
6083 goto out;
6084 }
6085
b6b8a145
JK		 6086 if (inject_pending_event(vcpu, req_int_win) != 0)
6087 req_immediate_exit = true;
b463a6f7 6088 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6089 else if (vcpu->arch.nmi_pending)
c9a7953f 6090 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6091 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6092 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6093
6094 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6095 /*
6096 * Update architecture specific hints for APIC
6097 * virtual interrupt delivery.
6098 */
6099 if (kvm_x86_ops->hwapic_irr_update)
6100 kvm_x86_ops->hwapic_irr_update(vcpu,
6101 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6102 update_cr8_intercept(vcpu);
6103 kvm_lapic_sync_to_vapic(vcpu);
6104 }
6105 }
6106
d8368af8
AK		 6107 r = kvm_mmu_reload(vcpu);
6108 if (unlikely(r)) {
d905c069 6109 goto cancel_injection;
d8368af8
AK		 6110 }
6111
b6c7a5dc
HB		 6112 preempt_disable();
6113
6114 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6115 if (vcpu->fpu_active)
6116 kvm_load_guest_fpu(vcpu);
2acf923e 6117 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6118
6b7e2d09
XG		 6119 vcpu->mode = IN_GUEST_MODE;
6120
01b71917
MT		 6121 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6122
6b7e2d09
XG		 6123 /* We should set ->mode before check ->requests,
6124 * see the comment in make_all_cpus_request.
6125 */
01b71917 6126 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6127
d94e1dc9 6128 local_irq_disable();
32f88400 6129
6b7e2d09 6130 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6131 || need_resched() || signal_pending(current)) {
6b7e2d09 6132 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6133 smp_wmb();
6c142801
AK		 6134 local_irq_enable();
6135 preempt_enable();
01b71917 6136 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6137 r = 1;
d905c069 6138 goto cancel_injection;
6c142801
AK		 6139 }
6140
d6185f20
NHE		 6141 if (req_immediate_exit)
6142 smp_send_reschedule(vcpu->cpu);
6143
b6c7a5dc
HB		 6144 kvm_guest_enter();
6145
42dbaa5a 6146 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6147 set_debugreg(0, 7);
6148 set_debugreg(vcpu->arch.eff_db[0], 0);
6149 set_debugreg(vcpu->arch.eff_db[1], 1);
6150 set_debugreg(vcpu->arch.eff_db[2], 2);
6151 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6152 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6153 }
b6c7a5dc 6154
229456fc 6155 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6156 kvm_x86_ops->run(vcpu);
b6c7a5dc 6157
c77fb5fe
PB		 6158 /*
6159 * Do this here before restoring debug registers on the host. And
6160 * since we do this before handling the vmexit, a DR access vmexit
6161 * can (a) read the correct value of the debug registers, (b) set
6162 * KVM_DEBUGREG_WONT_EXIT again.
6163 */
6164 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6165 int i;
6166
6167 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6168 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6169 for (i = 0; i < KVM_NR_DB_REGS; i++)
6170 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6171 }
6172
24f1e32c
FW		 6173 /*
6174 * If the guest has used debug registers, at least dr7
6175 * will be disabled while returning to the host.
6176 * If we don't have active breakpoints in the host, we don't
6177 * care about the messed up debug address registers. But if
6178 * we have some of them active, restore the old state.
6179 */
59d8eb53 6180 if (hw_breakpoint_active())
24f1e32c 6181 hw_breakpoint_restore();
42dbaa5a 6182
886b470c
MT		 6183 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6184 native_read_tsc());
1d5f066e 6185
6b7e2d09 6186 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6187 smp_wmb();
a547c6db
YZ		 6188
6189 /* Interrupt is enabled by handle_external_intr() */
6190 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6191
6192 ++vcpu->stat.exits;
6193
6194 /*
6195 * We must have an instruction between local_irq_enable() and
6196 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6197 * the interrupt shadow. The stat.exits increment will do nicely.
6198 * But we need to prevent reordering, hence this barrier():
6199 */
6200 barrier();
6201
6202 kvm_guest_exit();
6203
6204 preempt_enable();
6205
f656ce01 6206 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6207
b6c7a5dc
HB		 6208 /*
6209 * Profile KVM exit RIPs:
6210 */
6211 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6212 unsigned long rip = kvm_rip_read(vcpu);
6213 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6214 }
6215
cc578287
ZA		 6216 if (unlikely(vcpu->arch.tsc_always_catchup))
6217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6218
5cfb1d5a
MT		 6219 if (vcpu->arch.apic_attention)
6220 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6221
851ba692 6222 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6223 return r;
6224
6225cancel_injection:
6226 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6227 if (unlikely(vcpu->arch.apic_attention))
6228 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6229out:
6230 return r;
6231}
b6c7a5dc 6232
09cec754 6233
851ba692 6234static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6235{
6236 int r;
f656ce01 6237 struct kvm *kvm = vcpu->kvm;
d7690175 6238
f656ce01 6239 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6240
6241 r = 1;
6242 while (r > 0) {
af585b92
GN		 6243 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6244 !vcpu->arch.apf.halted)
851ba692 6245 r = vcpu_enter_guest(vcpu);
d7690175 6246 else {
f656ce01 6247 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6248 kvm_vcpu_block(vcpu);
f656ce01 6249 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6250 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6251 kvm_apic_accept_events(vcpu);
09cec754
GN		 6252 switch(vcpu->arch.mp_state) {
6253 case KVM_MP_STATE_HALTED:
6aef266c 6254 vcpu->arch.pv.pv_unhalted = false;
d7690175 6255 vcpu->arch.mp_state =
09cec754
GN		 6256 KVM_MP_STATE_RUNNABLE;
6257 case KVM_MP_STATE_RUNNABLE:
af585b92 6258 vcpu->arch.apf.halted = false;
09cec754 6259 break;
66450a21
JK		 6260 case KVM_MP_STATE_INIT_RECEIVED:
6261 break;
09cec754
GN		 6262 default:
6263 r = -EINTR;
6264 break;
6265 }
6266 }
d7690175
MT		 6267 }
6268
09cec754
GN		 6269 if (r <= 0)
6270 break;
6271
6272 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6273 if (kvm_cpu_has_pending_timer(vcpu))
6274 kvm_inject_pending_timer_irqs(vcpu);
6275
851ba692 6276 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6277 r = -EINTR;
851ba692 6278 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6279 ++vcpu->stat.request_irq_exits;
6280 }
af585b92
GN		 6281
6282 kvm_check_async_pf_completion(vcpu);
6283
09cec754
GN		 6284 if (signal_pending(current)) {
6285 r = -EINTR;
851ba692 6286 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6287 ++vcpu->stat.signal_exits;
6288 }
6289 if (need_resched()) {
f656ce01 6290 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6291 cond_resched();
f656ce01 6292 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6293 }
b6c7a5dc
HB		 6294 }
6295
f656ce01 6296 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6297
6298 return r;
6299}
6300
716d51ab
GN		 6301static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6302{
6303 int r;
6304 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6305 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6306 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6307 if (r != EMULATE_DONE)
6308 return 0;
6309 return 1;
6310}
6311
6312static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6313{
6314 BUG_ON(!vcpu->arch.pio.count);
6315
6316 return complete_emulated_io(vcpu);
6317}
6318
f78146b0
AK		 6319/*
6320 * Implements the following, as a state machine:
6321 *
6322 * read:
6323 * for each fragment
87da7e66
XG		 6324 * for each mmio piece in the fragment
6325 * write gpa, len
6326 * exit
6327 * copy data
f78146b0
AK		 6328 * execute insn
6329 *
6330 * write:
6331 * for each fragment
87da7e66
XG		 6332 * for each mmio piece in the fragment
6333 * write gpa, len
6334 * copy data
6335 * exit
f78146b0 6336 */
716d51ab 6337static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6338{
6339 struct kvm_run *run = vcpu->run;
f78146b0 6340 struct kvm_mmio_fragment *frag;
87da7e66 6341 unsigned len;
5287f194 6342
716d51ab 6343 BUG_ON(!vcpu->mmio_needed);
5287f194 6344
716d51ab 6345 /* Complete previous fragment */
87da7e66
XG		 6346 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6347 len = min(8u, frag->len);
716d51ab 6348 if (!vcpu->mmio_is_write)
87da7e66
XG		 6349 memcpy(frag->data, run->mmio.data, len);
6350
6351 if (frag->len <= 8) {
6352 /* Switch to the next fragment. */
6353 frag++;
6354 vcpu->mmio_cur_fragment++;
6355 } else {
6356 /* Go forward to the next mmio piece. */
6357 frag->data += len;
6358 frag->gpa += len;
6359 frag->len -= len;
6360 }
6361
a08d3b3b 6362 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6363 vcpu->mmio_needed = 0;
0912c977
PB		 6364
6365 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6366 if (vcpu->mmio_is_write)
716d51ab
GN		 6367 return 1;
6368 vcpu->mmio_read_completed = 1;
6369 return complete_emulated_io(vcpu);
6370 }
87da7e66 6371
716d51ab
GN		 6372 run->exit_reason = KVM_EXIT_MMIO;
6373 run->mmio.phys_addr = frag->gpa;
6374 if (vcpu->mmio_is_write)
87da7e66
XG		 6375 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6376 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6377 run->mmio.is_write = vcpu->mmio_is_write;
6378 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6379 return 0;
5287f194
AK		 6380}
6381
716d51ab 6382
b6c7a5dc
HB		 6383int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6384{
6385 int r;
6386 sigset_t sigsaved;
6387
e5c30142
AK		 6388 if (!tsk_used_math(current) && init_fpu(current))
6389 return -ENOMEM;
6390
ac9f6dc0
AK		 6391 if (vcpu->sigset_active)
6392 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6393
a4535290 6394 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6395 kvm_vcpu_block(vcpu);
66450a21 6396 kvm_apic_accept_events(vcpu);
d7690175 6397 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6398 r = -EAGAIN;
6399 goto out;
b6c7a5dc
HB		 6400 }
6401
b6c7a5dc 6402 /* re-sync apic's tpr */
eea1cff9
AP		 6403 if (!irqchip_in_kernel(vcpu->kvm)) {
6404 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6405 r = -EINVAL;
6406 goto out;
6407 }
6408 }
b6c7a5dc 6409
716d51ab
GN		 6410 if (unlikely(vcpu->arch.complete_userspace_io)) {
6411 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6412 vcpu->arch.complete_userspace_io = NULL;
6413 r = cui(vcpu);
6414 if (r <= 0)
6415 goto out;
6416 } else
6417 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6418
851ba692 6419 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6420
6421out:
f1d86e46 6422 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6423 if (vcpu->sigset_active)
6424 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6425
b6c7a5dc
HB		 6426 return r;
6427}
6428
6429int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6430{
7ae441ea
GN		 6431 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6432 /*
6433 * We are here if userspace calls get_regs() in the middle of
6434 * instruction emulation. Registers state needs to be copied
4a969980 6435 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6436 * that usually, but some bad designed PV devices (vmware
6437 * backdoor interface) need this to work
6438 */
dd856efa 6439 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6440 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6441 }
5fdbf976
MT		 6442 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6443 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6444 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6445 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6446 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6447 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6448 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6449 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6450#ifdef CONFIG_X86_64
5fdbf976
MT		 6451 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6452 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6453 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6454 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6455 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6456 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6457 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6458 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6459#endif
6460
5fdbf976 6461 regs->rip = kvm_rip_read(vcpu);
91586a3b 6462 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6463
b6c7a5dc
HB		 6464 return 0;
6465}
6466
6467int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6468{
7ae441ea
GN		 6469 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6470 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6471
5fdbf976
MT		 6472 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6473 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6474 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6475 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6476 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6477 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6478 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6479 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6480#ifdef CONFIG_X86_64
5fdbf976
MT		 6481 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6482 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6483 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6484 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6485 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6486 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6487 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6488 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6489#endif
6490
5fdbf976 6491 kvm_rip_write(vcpu, regs->rip);
91586a3b 6492 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6493
b4f14abd
JK		 6494 vcpu->arch.exception.pending = false;
6495
3842d135
AK		 6496 kvm_make_request(KVM_REQ_EVENT, vcpu);
6497
b6c7a5dc
HB		 6498 return 0;
6499}
6500
b6c7a5dc
HB		 6501void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6502{
6503 struct kvm_segment cs;
6504
3e6e0aab 6505 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6506 *db = cs.db;
6507 *l = cs.l;
6508}
6509EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6510
6511int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6512 struct kvm_sregs *sregs)
6513{
89a27f4d 6514 struct desc_ptr dt;
b6c7a5dc 6515
3e6e0aab
GT		 6516 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6517 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6518 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6519 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6520 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6521 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6522
3e6e0aab
GT		 6523 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6524 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6525
6526 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6527 sregs->idt.limit = dt.size;
6528 sregs->idt.base = dt.address;
b6c7a5dc 6529 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6530 sregs->gdt.limit = dt.size;
6531 sregs->gdt.base = dt.address;
b6c7a5dc 6532
4d4ec087 6533 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6534 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6535 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6536 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6537 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6538 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6539 sregs->apic_base = kvm_get_apic_base(vcpu);
6540
923c61bb 6541 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6542
36752c9b 6543 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6544 set_bit(vcpu->arch.interrupt.nr,
6545 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6546
b6c7a5dc
HB		 6547 return 0;
6548}
6549
62d9f0db
MT		 6550int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6551 struct kvm_mp_state *mp_state)
6552{
66450a21 6553 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6554 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6555 vcpu->arch.pv.pv_unhalted)
6556 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6557 else
6558 mp_state->mp_state = vcpu->arch.mp_state;
6559
62d9f0db
MT		 6560 return 0;
6561}
6562
6563int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6564 struct kvm_mp_state *mp_state)
6565{
66450a21
JK		 6566 if (!kvm_vcpu_has_lapic(vcpu) &&
6567 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6568 return -EINVAL;
6569
6570 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6571 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6572 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6573 } else
6574 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6575 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6576 return 0;
6577}
6578
7f3d35fd
KW		 6579int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6580 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6581{
9d74191a 6582 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6583 int ret;
e01c2426 6584
8ec4722d 6585 init_emulate_ctxt(vcpu);
c697518a 6586
7f3d35fd 6587 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6588 has_error_code, error_code);
c697518a 6589
c697518a 6590 if (ret)
19d04437 6591 return EMULATE_FAIL;
37817f29 6592
9d74191a
TY		 6593 kvm_rip_write(vcpu, ctxt->eip);
6594 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6595 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6596 return EMULATE_DONE;
37817f29
IE		 6597}
6598EXPORT_SYMBOL_GPL(kvm_task_switch);
6599
b6c7a5dc
HB		 6600int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6601 struct kvm_sregs *sregs)
6602{
58cb628d 6603 struct msr_data apic_base_msr;
b6c7a5dc 6604 int mmu_reset_needed = 0;
63f42e02 6605 int pending_vec, max_bits, idx;
89a27f4d 6606 struct desc_ptr dt;
b6c7a5dc 6607
6d1068b3
PM		 6608 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6609 return -EINVAL;
6610
89a27f4d
GN		 6611 dt.size = sregs->idt.limit;
6612 dt.address = sregs->idt.base;
b6c7a5dc 6613 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6614 dt.size = sregs->gdt.limit;
6615 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6616 kvm_x86_ops->set_gdt(vcpu, &dt);
6617
ad312c7c 6618 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6619 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6620 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6621 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6622
2d3ad1f4 6623 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6624
f6801dff 6625 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6626 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6627 apic_base_msr.data = sregs->apic_base;
6628 apic_base_msr.host_initiated = true;
6629 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6630
4d4ec087 6631 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6632 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6633 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6634
fc78f519 6635 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6636 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6637 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6638 kvm_update_cpuid(vcpu);
63f42e02
XG		 6639
6640 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6641 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6642 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6643 mmu_reset_needed = 1;
6644 }
63f42e02 6645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6646
6647 if (mmu_reset_needed)
6648 kvm_mmu_reset_context(vcpu);
6649
a50abc3b 6650 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6651 pending_vec = find_first_bit(
6652 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6653 if (pending_vec < max_bits) {
66fd3f7f 6654 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6655 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6656 }
6657
3e6e0aab
GT		 6658 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6659 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6660 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6661 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6662 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6663 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6664
3e6e0aab
GT		 6665 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6666 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6667
5f0269f5
ME		 6668 update_cr8_intercept(vcpu);
6669
9c3e4aab 6670 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6671 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6672 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6673 !is_protmode(vcpu))
9c3e4aab
MT		 6674 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6675
3842d135
AK		 6676 kvm_make_request(KVM_REQ_EVENT, vcpu);
6677
b6c7a5dc
HB		 6678 return 0;
6679}
6680
d0bfb940
JK		 6681int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6682 struct kvm_guest_debug *dbg)
b6c7a5dc 6683{
355be0b9 6684 unsigned long rflags;
ae675ef0 6685 int i, r;
b6c7a5dc 6686
4f926bf2
JK		 6687 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6688 r = -EBUSY;
6689 if (vcpu->arch.exception.pending)
2122ff5e 6690 goto out;
4f926bf2
JK		 6691 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6692 kvm_queue_exception(vcpu, DB_VECTOR);
6693 else
6694 kvm_queue_exception(vcpu, BP_VECTOR);
6695 }
6696
91586a3b
JK		 6697 /*
6698 * Read rflags as long as potentially injected trace flags are still
6699 * filtered out.
6700 */
6701 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6702
6703 vcpu->guest_debug = dbg->control;
6704 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6705 vcpu->guest_debug = 0;
6706
6707 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6708 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6709 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6710 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6711 } else {
6712 for (i = 0; i < KVM_NR_DB_REGS; i++)
6713 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6714 }
c8639010 6715 kvm_update_dr7(vcpu);
ae675ef0 6716
f92653ee
JK		 6717 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6718 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6719 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6720
91586a3b
JK		 6721 /*
6722 * Trigger an rflags update that will inject or remove the trace
6723 * flags.
6724 */
6725 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6726
c8639010 6727 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6728
4f926bf2 6729 r = 0;
d0bfb940 6730
2122ff5e 6731out:
b6c7a5dc
HB		 6732
6733 return r;
6734}
6735
8b006791
ZX		 6736/*
6737 * Translate a guest virtual address to a guest physical address.
6738 */
6739int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6740 struct kvm_translation *tr)
6741{
6742 unsigned long vaddr = tr->linear_address;
6743 gpa_t gpa;
f656ce01 6744 int idx;
8b006791 6745
f656ce01 6746 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6747 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6748 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6749 tr->physical_address = gpa;
6750 tr->valid = gpa != UNMAPPED_GVA;
6751 tr->writeable = 1;
6752 tr->usermode = 0;
8b006791
ZX		 6753
6754 return 0;
6755}
6756
d0752060
HB		 6757int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6758{
98918833
SY		 6759 struct i387_fxsave_struct *fxsave =
6760 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6761
d0752060
HB		 6762 memcpy(fpu->fpr, fxsave->st_space, 128);
6763 fpu->fcw = fxsave->cwd;
6764 fpu->fsw = fxsave->swd;
6765 fpu->ftwx = fxsave->twd;
6766 fpu->last_opcode = fxsave->fop;
6767 fpu->last_ip = fxsave->rip;
6768 fpu->last_dp = fxsave->rdp;
6769 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6770
d0752060
HB		 6771 return 0;
6772}
6773
6774int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6775{
98918833
SY		 6776 struct i387_fxsave_struct *fxsave =
6777 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6778
d0752060
HB		 6779 memcpy(fxsave->st_space, fpu->fpr, 128);
6780 fxsave->cwd = fpu->fcw;
6781 fxsave->swd = fpu->fsw;
6782 fxsave->twd = fpu->ftwx;
6783 fxsave->fop = fpu->last_opcode;
6784 fxsave->rip = fpu->last_ip;
6785 fxsave->rdp = fpu->last_dp;
6786 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6787
d0752060
HB		 6788 return 0;
6789}
6790
10ab25cd 6791int fx_init(struct kvm_vcpu *vcpu)
d0752060 6792{
10ab25cd
JK		 6793 int err;
6794
6795 err = fpu_alloc(&vcpu->arch.guest_fpu);
6796 if (err)
6797 return err;
6798
98918833 6799 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6800
2acf923e
DC		 6801 /*
6802 * Ensure guest xcr0 is valid for loading
6803 */
6804 vcpu->arch.xcr0 = XSTATE_FP;
6805
ad312c7c 6806 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6807
6808 return 0;
d0752060
HB		 6809}
6810EXPORT_SYMBOL_GPL(fx_init);
6811
98918833
SY		 6812static void fx_free(struct kvm_vcpu *vcpu)
6813{
6814 fpu_free(&vcpu->arch.guest_fpu);
6815}
6816
d0752060
HB		 6817void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6818{
2608d7a1 6819 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6820 return;
6821
2acf923e
DC		 6822 /*
6823 * Restore all possible states in the guest,
6824 * and assume host would use all available bits.
6825 * Guest xcr0 would be loaded later.
6826 */
6827 kvm_put_guest_xcr0(vcpu);
d0752060 6828 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6829 __kernel_fpu_begin();
98918833 6830 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6831 trace_kvm_fpu(1);
d0752060 6832}
d0752060
HB		 6833
6834void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6835{
2acf923e
DC		 6836 kvm_put_guest_xcr0(vcpu);
6837
d0752060
HB		 6838 if (!vcpu->guest_fpu_loaded)
6839 return;
6840
6841 vcpu->guest_fpu_loaded = 0;
98918833 6842 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6843 __kernel_fpu_end();
f096ed85 6844 ++vcpu->stat.fpu_reload;
a8eeb04a 6845 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6846 trace_kvm_fpu(0);
d0752060 6847}
e9b11c17
ZX		 6848
6849void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6850{
12f9a48f 6851 kvmclock_reset(vcpu);
7f1ea208 6852
f5f48ee1 6853 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6854 fx_free(vcpu);
e9b11c17
ZX		 6855 kvm_x86_ops->vcpu_free(vcpu);
6856}
6857
6858struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6859 unsigned int id)
6860{
6755bae8
ZA		 6861 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6862 printk_once(KERN_WARNING
6863 "kvm: SMP vm created on host with unstable TSC; "
6864 "guest TSC will not be reliable\n");
26e5215f
AK		 6865 return kvm_x86_ops->vcpu_create(kvm, id);
6866}
e9b11c17 6867
26e5215f
AK		 6868int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6869{
6870 int r;
e9b11c17 6871
0bed3b56 6872 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6873 r = vcpu_load(vcpu);
6874 if (r)
6875 return r;
57f252f2 6876 kvm_vcpu_reset(vcpu);
8a3c1a33 6877 kvm_mmu_setup(vcpu);
e9b11c17 6878 vcpu_put(vcpu);
e9b11c17 6879
26e5215f 6880 return r;
e9b11c17
ZX		 6881}
6882
42897d86
MT		 6883int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6884{
6885 int r;
8fe8ab46 6886 struct msr_data msr;
332967a3 6887 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6888
6889 r = vcpu_load(vcpu);
6890 if (r)
6891 return r;
8fe8ab46
WA		 6892 msr.data = 0x0;
6893 msr.index = MSR_IA32_TSC;
6894 msr.host_initiated = true;
6895 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6896 vcpu_put(vcpu);
6897
332967a3
AJ		 6898 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6899 KVMCLOCK_SYNC_PERIOD);
6900
42897d86
MT		 6901 return r;
6902}
6903
d40ccc62 6904void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6905{
9fc77441 6906 int r;
344d9588
GN		 6907 vcpu->arch.apf.msr_val = 0;
6908
9fc77441
MT		 6909 r = vcpu_load(vcpu);
6910 BUG_ON(r);
e9b11c17
ZX		 6911 kvm_mmu_unload(vcpu);
6912 vcpu_put(vcpu);
6913
98918833 6914 fx_free(vcpu);
e9b11c17
ZX		 6915 kvm_x86_ops->vcpu_free(vcpu);
6916}
6917
66450a21 6918void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6919{
7460fb4a
AK		 6920 atomic_set(&vcpu->arch.nmi_queued, 0);
6921 vcpu->arch.nmi_pending = 0;
448fa4a9 6922 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6923 kvm_clear_interrupt_queue(vcpu);
6924 kvm_clear_exception_queue(vcpu);
448fa4a9 6925
42dbaa5a 6926 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6927 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6928 kvm_update_dr6(vcpu);
42dbaa5a 6929 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6930 kvm_update_dr7(vcpu);
42dbaa5a 6931
3842d135 6932 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6933 vcpu->arch.apf.msr_val = 0;
c9aaa895 6934 vcpu->arch.st.msr_val = 0;
3842d135 6935
12f9a48f
GC		 6936 kvmclock_reset(vcpu);
6937
af585b92
GN		 6938 kvm_clear_async_pf_completion_queue(vcpu);
6939 kvm_async_pf_hash_reset(vcpu);
6940 vcpu->arch.apf.halted = false;
3842d135 6941
f5132b01
GN		 6942 kvm_pmu_reset(vcpu);
6943
66f7b72e
JS		 6944 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6945 vcpu->arch.regs_avail = ~0;
6946 vcpu->arch.regs_dirty = ~0;
6947
57f252f2 6948 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6949}
6950
66450a21
JK		 6951void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6952{
6953 struct kvm_segment cs;
6954
6955 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6956 cs.selector = vector << 8;
6957 cs.base = vector << 12;
6958 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6959 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6960}
6961
10474ae8 6962int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6963{
ca84d1a2
ZA		 6964 struct kvm *kvm;
6965 struct kvm_vcpu *vcpu;
6966 int i;
0dd6a6ed
ZA		 6967 int ret;
6968 u64 local_tsc;
6969 u64 max_tsc = 0;
6970 bool stable, backwards_tsc = false;
18863bdd
AK		 6971
6972 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6973 ret = kvm_x86_ops->hardware_enable(garbage);
6974 if (ret != 0)
6975 return ret;
6976
6977 local_tsc = native_read_tsc();
6978 stable = !check_tsc_unstable();
6979 list_for_each_entry(kvm, &vm_list, vm_list) {
6980 kvm_for_each_vcpu(i, vcpu, kvm) {
6981 if (!stable && vcpu->cpu == smp_processor_id())
6982 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6983 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6984 backwards_tsc = true;
6985 if (vcpu->arch.last_host_tsc > max_tsc)
6986 max_tsc = vcpu->arch.last_host_tsc;
6987 }
6988 }
6989 }
6990
6991 /*
6992 * Sometimes, even reliable TSCs go backwards. This happens on
6993 * platforms that reset TSC during suspend or hibernate actions, but
6994 * maintain synchronization. We must compensate. Fortunately, we can
6995 * detect that condition here, which happens early in CPU bringup,
6996 * before any KVM threads can be running. Unfortunately, we can't
6997 * bring the TSCs fully up to date with real time, as we aren't yet far
6998 * enough into CPU bringup that we know how much real time has actually
6999 * elapsed; our helper function, get_kernel_ns() will be using boot
7000 * variables that haven't been updated yet.
7001 *
7002 * So we simply find the maximum observed TSC above, then record the
7003 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7004 * the adjustment will be applied. Note that we accumulate
7005 * adjustments, in case multiple suspend cycles happen before some VCPU
7006 * gets a chance to run again. In the event that no KVM threads get a
7007 * chance to run, we will miss the entire elapsed period, as we'll have
7008 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7009 * loose cycle time. This isn't too big a deal, since the loss will be
7010 * uniform across all VCPUs (not to mention the scenario is extremely
7011 * unlikely). It is possible that a second hibernate recovery happens
7012 * much faster than a first, causing the observed TSC here to be
7013 * smaller; this would require additional padding adjustment, which is
7014 * why we set last_host_tsc to the local tsc observed here.
7015 *
7016 * N.B. - this code below runs only on platforms with reliable TSC,
7017 * as that is the only way backwards_tsc is set above. Also note
7018 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7019 * have the same delta_cyc adjustment applied if backwards_tsc
7020 * is detected. Note further, this adjustment is only done once,
7021 * as we reset last_host_tsc on all VCPUs to stop this from being
7022 * called multiple times (one for each physical CPU bringup).
7023 *
4a969980 7024 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7025 * will be compensated by the logic in vcpu_load, which sets the TSC to
7026 * catchup mode. This will catchup all VCPUs to real time, but cannot
7027 * guarantee that they stay in perfect synchronization.
7028 */
7029 if (backwards_tsc) {
7030 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7031 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7032 list_for_each_entry(kvm, &vm_list, vm_list) {
7033 kvm_for_each_vcpu(i, vcpu, kvm) {
7034 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7035 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 7036 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
7037 &vcpu->requests);
0dd6a6ed
ZA		 7038 }
7039
7040 /*
7041 * We have to disable TSC offset matching.. if you were
7042 * booting a VM while issuing an S4 host suspend....
7043 * you may have some problem. Solving this issue is
7044 * left as an exercise to the reader.
7045 */
7046 kvm->arch.last_tsc_nsec = 0;
7047 kvm->arch.last_tsc_write = 0;
7048 }
7049
7050 }
7051 return 0;
e9b11c17
ZX		 7052}
7053
7054void kvm_arch_hardware_disable(void *garbage)
7055{
7056 kvm_x86_ops->hardware_disable(garbage);
3548bab5 7057 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 7058}
7059
7060int kvm_arch_hardware_setup(void)
7061{
7062 return kvm_x86_ops->hardware_setup();
7063}
7064
7065void kvm_arch_hardware_unsetup(void)
7066{
7067 kvm_x86_ops->hardware_unsetup();
7068}
7069
7070void kvm_arch_check_processor_compat(void *rtn)
7071{
7072 kvm_x86_ops->check_processor_compatibility(rtn);
7073}
7074
3e515705
AK		 7075bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7076{
7077 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7078}
7079
54e9818f
GN		 7080struct static_key kvm_no_apic_vcpu __read_mostly;
7081
e9b11c17
ZX		 7082int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7083{
7084 struct page *page;
7085 struct kvm *kvm;
7086 int r;
7087
7088 BUG_ON(vcpu->kvm == NULL);
7089 kvm = vcpu->kvm;
7090
6aef266c 7091 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7092 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7093 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7094 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7095 else
a4535290 7096 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7097
7098 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7099 if (!page) {
7100 r = -ENOMEM;
7101 goto fail;
7102 }
ad312c7c 7103 vcpu->arch.pio_data = page_address(page);
e9b11c17 7104
cc578287 7105 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7106
e9b11c17
ZX		 7107 r = kvm_mmu_create(vcpu);
7108 if (r < 0)
7109 goto fail_free_pio_data;
7110
7111 if (irqchip_in_kernel(kvm)) {
7112 r = kvm_create_lapic(vcpu);
7113 if (r < 0)
7114 goto fail_mmu_destroy;
54e9818f
GN		 7115 } else
7116 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7117
890ca9ae
HY		 7118 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7119 GFP_KERNEL);
7120 if (!vcpu->arch.mce_banks) {
7121 r = -ENOMEM;
443c39bc 7122 goto fail_free_lapic;
890ca9ae
HY		 7123 }
7124 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7125
f1797359
WY		 7126 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7127 r = -ENOMEM;
f5f48ee1 7128 goto fail_free_mce_banks;
f1797359 7129 }
f5f48ee1 7130
66f7b72e
JS		 7131 r = fx_init(vcpu);
7132 if (r)
7133 goto fail_free_wbinvd_dirty_mask;
7134
ba904635 7135 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7136 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7137
7138 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7139 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7140
af585b92 7141 kvm_async_pf_hash_reset(vcpu);
f5132b01 7142 kvm_pmu_init(vcpu);
af585b92 7143
e9b11c17 7144 return 0;
66f7b72e
JS		 7145fail_free_wbinvd_dirty_mask:
7146 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7147fail_free_mce_banks:
7148 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7149fail_free_lapic:
7150 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7151fail_mmu_destroy:
7152 kvm_mmu_destroy(vcpu);
7153fail_free_pio_data:
ad312c7c 7154 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7155fail:
7156 return r;
7157}
7158
7159void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7160{
f656ce01
MT		 7161 int idx;
7162
f5132b01 7163 kvm_pmu_destroy(vcpu);
36cb93fd 7164 kfree(vcpu->arch.mce_banks);
e9b11c17 7165 kvm_free_lapic(vcpu);
f656ce01 7166 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7167 kvm_mmu_destroy(vcpu);
f656ce01 7168 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7169 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7170 if (!irqchip_in_kernel(vcpu->kvm))
7171 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7172}
d19a9cd2 7173
e790d9ef
RK		 7174void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7175{
7176}
7177
e08b9637 7178int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7179{
e08b9637
CO		 7180 if (type)
7181 return -EINVAL;
7182
f05e70ac 7183 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7184 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7185 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7186 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7187
5550af4d
SY		 7188 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7189 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7190 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7191 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7192 &kvm->arch.irq_sources_bitmap);
5550af4d 7193
038f8c11 7194 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7195 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7196 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7197
7198 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7199
7e44e449 7200 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7201 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7202
d89f5eff 7203 return 0;
d19a9cd2
ZX		 7204}
7205
7206static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7207{
9fc77441
MT		 7208 int r;
7209 r = vcpu_load(vcpu);
7210 BUG_ON(r);
d19a9cd2
ZX		 7211 kvm_mmu_unload(vcpu);
7212 vcpu_put(vcpu);
7213}
7214
7215static void kvm_free_vcpus(struct kvm *kvm)
7216{
7217 unsigned int i;
988a2cae 7218 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7219
7220 /*
7221 * Unpin any mmu pages first.
7222 */
af585b92
GN		 7223 kvm_for_each_vcpu(i, vcpu, kvm) {
7224 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7225 kvm_unload_vcpu_mmu(vcpu);
af585b92 7226 }
988a2cae
GN		 7227 kvm_for_each_vcpu(i, vcpu, kvm)
7228 kvm_arch_vcpu_free(vcpu);
7229
7230 mutex_lock(&kvm->lock);
7231 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7232 kvm->vcpus[i] = NULL;
d19a9cd2 7233
988a2cae
GN		 7234 atomic_set(&kvm->online_vcpus, 0);
7235 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7236}
7237
ad8ba2cd
SY		 7238void kvm_arch_sync_events(struct kvm *kvm)
7239{
332967a3 7240 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7241 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7242 kvm_free_all_assigned_devices(kvm);
aea924f6 7243 kvm_free_pit(kvm);
ad8ba2cd
SY		 7244}
7245
d19a9cd2
ZX		 7246void kvm_arch_destroy_vm(struct kvm *kvm)
7247{
27469d29
AH		 7248 if (current->mm == kvm->mm) {
7249 /*
7250 * Free memory regions allocated on behalf of userspace,
7251 * unless the the memory map has changed due to process exit
7252 * or fd copying.
7253 */
7254 struct kvm_userspace_memory_region mem;
7255 memset(&mem, 0, sizeof(mem));
7256 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7257 kvm_set_memory_region(kvm, &mem);
7258
7259 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7260 kvm_set_memory_region(kvm, &mem);
7261
7262 mem.slot = TSS_PRIVATE_MEMSLOT;
7263 kvm_set_memory_region(kvm, &mem);
7264 }
6eb55818 7265 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7266 kfree(kvm->arch.vpic);
7267 kfree(kvm->arch.vioapic);
d19a9cd2 7268 kvm_free_vcpus(kvm);
3d45830c
AK		 7269 if (kvm->arch.apic_access_page)
7270 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7271 if (kvm->arch.ept_identity_pagetable)
7272 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7273 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7274}
0de10343 7275
5587027c 7276void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7277 struct kvm_memory_slot *dont)
7278{
7279 int i;
7280
d89cc617
TY		 7281 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7282 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7283 kvm_kvfree(free->arch.rmap[i]);
7284 free->arch.rmap[i] = NULL;
77d11309 7285 }
d89cc617
TY		 7286 if (i == 0)
7287 continue;
7288
7289 if (!dont || free->arch.lpage_info[i - 1] !=
7290 dont->arch.lpage_info[i - 1]) {
7291 kvm_kvfree(free->arch.lpage_info[i - 1]);
7292 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7293 }
7294 }
7295}
7296
5587027c
AK		 7297int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7298 unsigned long npages)
db3fe4eb
TY		 7299{
7300 int i;
7301
d89cc617 7302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7303 unsigned long ugfn;
7304 int lpages;
d89cc617 7305 int level = i + 1;
db3fe4eb
TY		 7306
7307 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7308 slot->base_gfn, level) + 1;
7309
d89cc617
TY		 7310 slot->arch.rmap[i] =
7311 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7312 if (!slot->arch.rmap[i])
77d11309 7313 goto out_free;
d89cc617
TY		 7314 if (i == 0)
7315 continue;
77d11309 7316
d89cc617
TY		 7317 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7318 sizeof(*slot->arch.lpage_info[i - 1]));
7319 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7320 goto out_free;
7321
7322 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7323 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7324 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7325 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7326 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7327 /*
7328 * If the gfn and userspace address are not aligned wrt each
7329 * other, or if explicitly asked to, disable large page
7330 * support for this slot
7331 */
7332 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7333 !kvm_largepages_enabled()) {
7334 unsigned long j;
7335
7336 for (j = 0; j < lpages; ++j)
d89cc617 7337 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7338 }
7339 }
7340
7341 return 0;
7342
7343out_free:
d89cc617
TY		 7344 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7345 kvm_kvfree(slot->arch.rmap[i]);
7346 slot->arch.rmap[i] = NULL;
7347 if (i == 0)
7348 continue;
7349
7350 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7351 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7352 }
7353 return -ENOMEM;
7354}
7355
e59dbe09
TY		 7356void kvm_arch_memslots_updated(struct kvm *kvm)
7357{
e6dff7d1
TY		 7358 /*
7359 * memslots->generation has been incremented.
7360 * mmio generation may have reached its maximum value.
7361 */
7362 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7363}
7364
f7784b8e
MT		 7365int kvm_arch_prepare_memory_region(struct kvm *kvm,
7366 struct kvm_memory_slot *memslot,
f7784b8e 7367 struct kvm_userspace_memory_region *mem,
7b6195a9 7368 enum kvm_mr_change change)
0de10343 7369{
7a905b14
TY		 7370 /*
7371 * Only private memory slots need to be mapped here since
7372 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7373 */
7b6195a9 7374 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7375 unsigned long userspace_addr;
604b38ac 7376
7a905b14
TY		 7377 /*
7378 * MAP_SHARED to prevent internal slot pages from being moved
7379 * by fork()/COW.
7380 */
7b6195a9 7381 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7382 PROT_READ | PROT_WRITE,
7383 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7384
7a905b14
TY		 7385 if (IS_ERR((void *)userspace_addr))
7386 return PTR_ERR((void *)userspace_addr);
604b38ac 7387
7a905b14 7388 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7389 }
7390
f7784b8e
MT		 7391 return 0;
7392}
7393
7394void kvm_arch_commit_memory_region(struct kvm *kvm,
7395 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7396 const struct kvm_memory_slot *old,
7397 enum kvm_mr_change change)
f7784b8e
MT		 7398{
7399
8482644a 7400 int nr_mmu_pages = 0;
f7784b8e 7401
8482644a 7402 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7403 int ret;
7404
8482644a
TY		 7405 ret = vm_munmap(old->userspace_addr,
7406 old->npages * PAGE_SIZE);
f7784b8e
MT		 7407 if (ret < 0)
7408 printk(KERN_WARNING
7409 "kvm_vm_ioctl_set_memory_region: "
7410 "failed to munmap memory\n");
7411 }
7412
48c0e4e9
XG		 7413 if (!kvm->arch.n_requested_mmu_pages)
7414 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7415
48c0e4e9 7416 if (nr_mmu_pages)
0de10343 7417 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7418 /*
7419 * Write protect all pages for dirty logging.
c126d94f
XG		 7420 *
7421 * All the sptes including the large sptes which point to this
7422 * slot are set to readonly. We can not create any new large
7423 * spte on this slot until the end of the logging.
7424 *
7425 * See the comments in fast_page_fault().
c972f3b1 7426 */
8482644a 7427 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7428 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7429}
1d737c8a 7430
2df72e9b 7431void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7432{
6ca18b69 7433 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7434}
7435
2df72e9b
MT		 7436void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7437 struct kvm_memory_slot *slot)
7438{
6ca18b69 7439 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7440}
7441
1d737c8a
ZX		 7442int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7443{
b6b8a145
JK		 7444 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7445 kvm_x86_ops->check_nested_events(vcpu, false);
7446
af585b92
GN		 7447 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7448 !vcpu->arch.apf.halted)
7449 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7450 || kvm_apic_has_events(vcpu)
6aef266c 7451 || vcpu->arch.pv.pv_unhalted
7460fb4a 7452 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7453 (kvm_arch_interrupt_allowed(vcpu) &&
7454 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7455}
5736199a 7456
b6d33834 7457int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7458{
b6d33834 7459 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7460}
78646121
GN		 7461
7462int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7463{
7464 return kvm_x86_ops->interrupt_allowed(vcpu);
7465}
229456fc 7466
f92653ee
JK		 7467bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7468{
7469 unsigned long current_rip = kvm_rip_read(vcpu) +
7470 get_segment_base(vcpu, VCPU_SREG_CS);
7471
7472 return current_rip == linear_rip;
7473}
7474EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7475
94fe45da
JK		 7476unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7477{
7478 unsigned long rflags;
7479
7480 rflags = kvm_x86_ops->get_rflags(vcpu);
7481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7482 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7483 return rflags;
7484}
7485EXPORT_SYMBOL_GPL(kvm_get_rflags);
7486
6addfc42 7487static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7488{
7489 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7490 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7491 rflags |= X86_EFLAGS_TF;
94fe45da 7492 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7493}
7494
7495void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7496{
7497 __kvm_set_rflags(vcpu, rflags);
3842d135 7498 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7499}
7500EXPORT_SYMBOL_GPL(kvm_set_rflags);
7501
56028d08
GN		 7502void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7503{
7504 int r;
7505
fb67e14f 7506 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7507 work->wakeup_all)
56028d08
GN		 7508 return;
7509
7510 r = kvm_mmu_reload(vcpu);
7511 if (unlikely(r))
7512 return;
7513
fb67e14f
XG		 7514 if (!vcpu->arch.mmu.direct_map &&
7515 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7516 return;
7517
56028d08
GN		 7518 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7519}
7520
af585b92
GN		 7521static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7522{
7523 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7524}
7525
7526static inline u32 kvm_async_pf_next_probe(u32 key)
7527{
7528 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7529}
7530
7531static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7532{
7533 u32 key = kvm_async_pf_hash_fn(gfn);
7534
7535 while (vcpu->arch.apf.gfns[key] != ~0)
7536 key = kvm_async_pf_next_probe(key);
7537
7538 vcpu->arch.apf.gfns[key] = gfn;
7539}
7540
7541static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7542{
7543 int i;
7544 u32 key = kvm_async_pf_hash_fn(gfn);
7545
7546 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7547 (vcpu->arch.apf.gfns[key] != gfn &&
7548 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7549 key = kvm_async_pf_next_probe(key);
7550
7551 return key;
7552}
7553
7554bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7555{
7556 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7557}
7558
7559static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7560{
7561 u32 i, j, k;
7562
7563 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7564 while (true) {
7565 vcpu->arch.apf.gfns[i] = ~0;
7566 do {
7567 j = kvm_async_pf_next_probe(j);
7568 if (vcpu->arch.apf.gfns[j] == ~0)
7569 return;
7570 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7571 /*
7572 * k lies cyclically in ]i,j]
7573 * | i.k.j |
7574 * |....j i.k.| or |.k..j i...|
7575 */
7576 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7577 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7578 i = j;
7579 }
7580}
7581
7c90705b
GN		 7582static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7583{
7584
7585 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7586 sizeof(val));
7587}
7588
af585b92
GN		 7589void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7590 struct kvm_async_pf *work)
7591{
6389ee94
AK		 7592 struct x86_exception fault;
7593
7c90705b 7594 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7595 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7596
7597 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7598 (vcpu->arch.apf.send_user_only &&
7599 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7600 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7601 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7602 fault.vector = PF_VECTOR;
7603 fault.error_code_valid = true;
7604 fault.error_code = 0;
7605 fault.nested_page_fault = false;
7606 fault.address = work->arch.token;
7607 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7608 }
af585b92
GN		 7609}
7610
7611void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7612 struct kvm_async_pf *work)
7613{
6389ee94
AK		 7614 struct x86_exception fault;
7615
7c90705b 7616 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7617 if (work->wakeup_all)
7c90705b
GN		 7618 work->arch.token = ~0; /* broadcast wakeup */
7619 else
7620 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7621
7622 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7623 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7624 fault.vector = PF_VECTOR;
7625 fault.error_code_valid = true;
7626 fault.error_code = 0;
7627 fault.nested_page_fault = false;
7628 fault.address = work->arch.token;
7629 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7630 }
e6d53e3b 7631 vcpu->arch.apf.halted = false;
a4fa1635 7632 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7633}
7634
7635bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7636{
7637 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7638 return true;
7639 else
7640 return !kvm_event_needs_reinjection(vcpu) &&
7641 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7642}
7643
e0f0bbc5
AW		 7644void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7645{
7646 atomic_inc(&kvm->arch.noncoherent_dma_count);
7647}
7648EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7649
7650void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7651{
7652 atomic_dec(&kvm->arch.noncoherent_dma_count);
7653}
7654EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7655
7656bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7657{
7658 return atomic_read(&kvm->arch.noncoherent_dma_count);
7659}
7660EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7661
229456fc
MT		 7662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7672EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git