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Commit | Line | Data |
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887e2ec9 | 1 | /* |
5a5958b7 | 2 | * (C) Copyright 2006-2007 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
83a49c8d | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 SR |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
13628884 SR |
26 | #include <libfdt.h> |
27 | #include <fdt_support.h> | |
28 | #include <ppc440.h> | |
b05e8bf5 | 29 | #include <asm/gpio.h> |
887e2ec9 | 30 | #include <asm/processor.h> |
5a5958b7 | 31 | #include <asm/io.h> |
83a49c8d | 32 | #include <asm/bitops.h> |
1f84021a | 33 | #include <asm/ppc4xx-intvec.h> |
887e2ec9 SR |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
83a49c8d | 37 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
887e2ec9 | 38 | |
1b3c360c SR |
39 | ulong flash_get_size (ulong base, int banknum); |
40 | ||
887e2ec9 SR |
41 | int board_early_init_f(void) |
42 | { | |
a78bc443 SR |
43 | u32 sdr0_cust0; |
44 | u32 sdr0_pfc1, sdr0_pfc2; | |
45 | u32 reg; | |
887e2ec9 SR |
46 | |
47 | mtdcr(ebccfga, xbcfg); | |
48 | mtdcr(ebccfgd, 0xb8400000); | |
49 | ||
83a49c8d | 50 | /* |
887e2ec9 | 51 | * Setup the interrupt controller polarities, triggers, etc. |
83a49c8d | 52 | */ |
887e2ec9 SR |
53 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
54 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
55 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
56 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ | |
57 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
58 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
59 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
60 | ||
61 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
62 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
63 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
64 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
65 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
66 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
67 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
68 | ||
69 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
70 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
71 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
72 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
73 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
74 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
75 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
76 | ||
77 | /* 50MHz tmrclk */ | |
d3471173 | 78 | out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00); |
887e2ec9 SR |
79 | |
80 | /* clear write protects */ | |
d3471173 | 81 | out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00); |
887e2ec9 SR |
82 | |
83 | /* enable Ethernet */ | |
d3471173 | 84 | out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00); |
887e2ec9 SR |
85 | |
86 | /* enable USB device */ | |
d3471173 | 87 | out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20); |
887e2ec9 SR |
88 | |
89 | /* select Ethernet pins */ | |
90 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
83a49c8d MF |
91 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
92 | SDR0_PFC1_SELECT_CONFIG_4; | |
887e2ec9 | 93 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
83a49c8d MF |
94 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
95 | SDR0_PFC2_SELECT_CONFIG_4; | |
887e2ec9 SR |
96 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
97 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
98 | ||
99 | /* PCI arbiter enabled */ | |
100 | mfsdr(sdr_pci0, reg); | |
101 | mtsdr(sdr_pci0, 0x80000000 | reg); | |
102 | ||
103 | /* setup NAND FLASH */ | |
104 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 105 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
106 | SDR0_CUST0_NDFC_ENABLE | |
107 | SDR0_CUST0_NDFC_BW_8_BIT | | |
108 | SDR0_CUST0_NDFC_ARE_MASK | | |
109 | (0x80000000 >> (28 + CFG_NAND_CS)); | |
511d0c72 | 110 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
111 | |
112 | return 0; | |
113 | } | |
114 | ||
887e2ec9 SR |
115 | int misc_init_r(void) |
116 | { | |
117 | uint pbcr; | |
118 | int size_val = 0; | |
a78bc443 | 119 | u32 reg; |
854bc8da | 120 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
121 | unsigned long usb2d0cr = 0; |
122 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
123 | unsigned long sdr0_pfc1; | |
124 | char *act = getenv("usbact"); | |
854bc8da | 125 | #endif |
887e2ec9 | 126 | |
83a49c8d | 127 | /* Re-do flash sizing to get full correct info */ |
1b3c360c SR |
128 | |
129 | /* adjust flash start and offset */ | |
130 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
131 | gd->bd->bi_flashoffset = 0; | |
132 | ||
887e2ec9 SR |
133 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
134 | mtdcr(ebccfga, pb3cr); | |
135 | #else | |
136 | mtdcr(ebccfga, pb0cr); | |
137 | #endif | |
138 | pbcr = mfdcr(ebccfgd); | |
83a49c8d | 139 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
887e2ec9 SR |
140 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
141 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
142 | mtdcr(ebccfga, pb3cr); | |
143 | #else | |
144 | mtdcr(ebccfga, pb0cr); | |
145 | #endif | |
146 | mtdcr(ebccfgd, pbcr); | |
147 | ||
1b3c360c SR |
148 | /* |
149 | * Re-check to get correct base address | |
150 | */ | |
151 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 SR |
152 | |
153 | #ifdef CFG_ENV_IS_IN_FLASH | |
154 | /* Monitor protection ON by default */ | |
155 | (void)flash_protect(FLAG_PROTECT_SET, | |
156 | -CFG_MONITOR_LEN, | |
157 | 0xffffffff, | |
158 | &flash_info[0]); | |
159 | ||
160 | /* Env protection ON by default */ | |
161 | (void)flash_protect(FLAG_PROTECT_SET, | |
162 | CFG_ENV_ADDR_REDUND, | |
163 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
164 | &flash_info[0]); | |
165 | #endif | |
166 | ||
167 | /* | |
168 | * USB suff... | |
169 | */ | |
854bc8da | 170 | #ifdef CONFIG_440EPX |
83a49c8d | 171 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
887e2ec9 | 172 | /* SDR Setting */ |
511d0c72 | 173 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 174 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
175 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
176 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
177 | |
178 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 179 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 180 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 181 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 182 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 183 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 184 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 185 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 186 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 187 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 | 188 | |
83a49c8d MF |
189 | /* |
190 | * An 8-bit/60MHz interface is the only possible alternative | |
191 | * when connecting the Device to the PHY | |
192 | */ | |
511d0c72 | 193 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
83a49c8d | 194 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 195 | |
83a49c8d MF |
196 | /* |
197 | * To enable the USB 2.0 Device function | |
198 | * through the UTMI interface | |
199 | */ | |
511d0c72 | 200 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
83a49c8d | 201 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; |
887e2ec9 | 202 | |
511d0c72 | 203 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
83a49c8d | 204 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; |
887e2ec9 | 205 | |
511d0c72 | 206 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 207 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
208 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
209 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
210 | |
211 | /*clear resets*/ | |
212 | udelay (1000); | |
213 | mtsdr(SDR0_SRST1, 0x00000000); | |
214 | udelay (1000); | |
215 | mtsdr(SDR0_SRST0, 0x00000000); | |
216 | ||
217 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
218 | ||
219 | } else if (strcmp(act, "dev") == 0) { | |
220 | /*-------------------PATCH-------------------------------*/ | |
221 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
222 | ||
223 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 224 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
887e2ec9 | 225 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 226 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 227 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 228 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 229 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 230 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 SR |
231 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
232 | ||
233 | udelay (1000); | |
234 | mtsdr(SDR0_SRST1, 0x672c6000); | |
235 | ||
236 | udelay (1000); | |
237 | mtsdr(SDR0_SRST0, 0x00000080); | |
238 | ||
239 | udelay (1000); | |
240 | mtsdr(SDR0_SRST1, 0x60206000); | |
241 | ||
242 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
243 | ||
244 | udelay (1000); | |
245 | mtsdr(SDR0_SRST1, 0x60306000); | |
246 | /*-------------------PATCH-------------------------------*/ | |
247 | ||
248 | /* SDR Setting */ | |
511d0c72 | 249 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 | 250 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
f780b833 | 251 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
252 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
253 | ||
254 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 255 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 256 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 257 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; |
887e2ec9 | 258 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 259 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; |
887e2ec9 | 260 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 261 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; |
887e2ec9 | 262 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 263 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; |
887e2ec9 SR |
264 | |
265 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
83a49c8d | 266 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; |
887e2ec9 SR |
267 | |
268 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
83a49c8d | 269 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; |
887e2ec9 SR |
270 | |
271 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
83a49c8d | 272 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; |
887e2ec9 | 273 | |
511d0c72 WD |
274 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
275 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
f780b833 | 276 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
277 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
278 | ||
83a49c8d | 279 | /* clear resets */ |
887e2ec9 SR |
280 | udelay (1000); |
281 | mtsdr(SDR0_SRST1, 0x00000000); | |
282 | udelay (1000); | |
283 | mtsdr(SDR0_SRST0, 0x00000000); | |
284 | ||
285 | printf("USB: Device(int phy)\n"); | |
286 | } | |
854bc8da | 287 | #endif /* CONFIG_440EPX */ |
887e2ec9 | 288 | |
8ce16f55 JO |
289 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
290 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); | |
291 | mtsdr(SDR0_SRST1, reg); | |
292 | ||
a78bc443 SR |
293 | /* |
294 | * Clear PLB4A0_ACR[WRP] | |
295 | * This fix will make the MAL burst disabling patch for the Linux | |
296 | * EMAC driver obsolete. | |
297 | */ | |
298 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; | |
299 | mtdcr(plb4_acr, reg); | |
300 | ||
887e2ec9 SR |
301 | return 0; |
302 | } | |
303 | ||
304 | int checkboard(void) | |
305 | { | |
306 | char *s = getenv("serial#"); | |
e0b9ea8c SR |
307 | u8 rev; |
308 | u8 val; | |
887e2ec9 | 309 | |
854bc8da | 310 | #ifdef CONFIG_440EPX |
887e2ec9 | 311 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
312 | #else |
313 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
314 | #endif | |
e0b9ea8c | 315 | |
5a5958b7 SR |
316 | rev = in_8((void *)(CFG_BCSR_BASE + 0)); |
317 | val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; | |
e0b9ea8c SR |
318 | printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); |
319 | ||
887e2ec9 SR |
320 | if (s != NULL) { |
321 | puts(", serial# "); | |
322 | puts(s); | |
323 | } | |
324 | putc('\n'); | |
325 | ||
326 | return (0); | |
327 | } | |
328 | ||
329 | #if defined(CFG_DRAM_TEST) | |
330 | int testdram(void) | |
331 | { | |
332 | unsigned long *mem = (unsigned long *)0; | |
333 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
334 | unsigned long k, n; | |
335 | ||
336 | mtmsr(0); | |
337 | ||
338 | for (k = 0; k < CFG_MBYTES_SDRAM; | |
339 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
340 | if ((k & 1023) == 0) { | |
341 | printf("%3d MB\r", k / 1024); | |
342 | } | |
343 | ||
344 | memset(mem, 0xaaaaaaaa, 1024); | |
345 | for (n = 0; n < kend; ++n) { | |
346 | if (mem[n] != 0xaaaaaaaa) { | |
347 | printf("SDRAM test fails at: %08x\n", | |
348 | (uint) & mem[n]); | |
349 | return 1; | |
350 | } | |
351 | } | |
352 | ||
353 | memset(mem, 0x55555555, 1024); | |
354 | for (n = 0; n < kend; ++n) { | |
355 | if (mem[n] != 0x55555555) { | |
356 | printf("SDRAM test fails at: %08x\n", | |
357 | (uint) & mem[n]); | |
358 | return 1; | |
359 | } | |
360 | } | |
361 | } | |
362 | printf("SDRAM test passes\n"); | |
363 | return 0; | |
364 | } | |
365 | #endif | |
366 | ||
1f84021a MF |
367 | #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) |
368 | /* | |
369 | * Assign interrupts to PCI devices. | |
370 | */ | |
371 | void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) | |
372 | { | |
373 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); | |
374 | } | |
375 | #endif | |
376 | ||
83a49c8d MF |
377 | /* |
378 | * pci_pre_init | |
887e2ec9 | 379 | * |
83a49c8d MF |
380 | * This routine is called just prior to registering the hose and gives |
381 | * the board the opportunity to check things. Returning a value of zero | |
382 | * indicates that things are bad & PCI initialization should be aborted. | |
887e2ec9 | 383 | * |
83a49c8d MF |
384 | * Different boards may wish to customize the pci controller structure |
385 | * (add regions, override default access routines, etc) or perform | |
386 | * certain pre-initialization actions. | |
387 | */ | |
466fff1a | 388 | #if defined(CONFIG_PCI) |
887e2ec9 SR |
389 | int pci_pre_init(struct pci_controller *hose) |
390 | { | |
391 | unsigned long addr; | |
887e2ec9 | 392 | |
83a49c8d MF |
393 | /* |
394 | * Set priority for all PLB3 devices to 0. | |
395 | * Set PLB3 arbiter to fair mode. | |
396 | */ | |
887e2ec9 SR |
397 | mfsdr(sdr_amp1, addr); |
398 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
399 | addr = mfdcr(plb3_acr); | |
400 | mtdcr(plb3_acr, addr | 0x80000000); | |
401 | ||
83a49c8d MF |
402 | /* |
403 | * Set priority for all PLB4 devices to 0. | |
404 | */ | |
887e2ec9 SR |
405 | mfsdr(sdr_amp0, addr); |
406 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
407 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
408 | mtdcr(plb4_acr, addr); | |
409 | ||
83a49c8d MF |
410 | /* |
411 | * Set Nebula PLB4 arbiter to fair mode. | |
412 | */ | |
887e2ec9 SR |
413 | /* Segment0 */ |
414 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
415 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
416 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
417 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
418 | mtdcr(plb0_acr, addr); | |
419 | ||
420 | /* Segment1 */ | |
421 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
422 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
423 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
424 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
425 | mtdcr(plb1_acr, addr); | |
426 | ||
1f84021a MF |
427 | #ifdef CONFIG_PCI_PNP |
428 | hose->fixup_irq = sequoia_pci_fixup_irq; | |
429 | #endif | |
887e2ec9 SR |
430 | return 1; |
431 | } | |
466fff1a | 432 | #endif /* defined(CONFIG_PCI) */ |
887e2ec9 | 433 | |
83a49c8d MF |
434 | /* |
435 | * pci_target_init | |
887e2ec9 | 436 | * |
83a49c8d MF |
437 | * The bootstrap configuration provides default settings for the pci |
438 | * inbound map (PIM). But the bootstrap config choices are limited and | |
439 | * may not be sufficient for a given board. | |
440 | */ | |
887e2ec9 SR |
441 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
442 | void pci_target_init(struct pci_controller *hose) | |
443 | { | |
83a49c8d | 444 | /* |
887e2ec9 | 445 | * Set up Direct MMIO registers |
83a49c8d MF |
446 | */ |
447 | /* | |
448 | * PowerPC440EPX PCI Master configuration. | |
449 | * Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
450 | * PLB address 0xA0000000-0xDFFFFFFF | |
451 | * ==> PCI address 0xA0000000-0xDFFFFFFF | |
452 | * Use byte reversed out routines to handle endianess. | |
453 | * Make this region non-prefetchable. | |
454 | */ | |
455 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ | |
456 | /* - disabled b4 setting */ | |
887e2ec9 | 457 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
83a49c8d | 458 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
887e2ec9 | 459 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
83a49c8d MF |
460 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ |
461 | /* and enable region */ | |
887e2ec9 | 462 | |
83a49c8d MF |
463 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ |
464 | /* - disabled b4 setting */ | |
887e2ec9 | 465 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
83a49c8d | 466 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
887e2ec9 | 467 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
83a49c8d MF |
468 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ |
469 | /* and enable region */ | |
887e2ec9 SR |
470 | |
471 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
83a49c8d MF |
472 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
473 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
474 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
887e2ec9 | 475 | |
83a49c8d | 476 | /* |
887e2ec9 | 477 | * Set up Configuration registers |
83a49c8d | 478 | */ |
887e2ec9 SR |
479 | |
480 | /* Program the board's subsystem id/vendor id */ | |
481 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
482 | CFG_PCI_SUBSYS_VENDORID); | |
483 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
484 | ||
485 | /* Configure command register as bus master */ | |
486 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
487 | ||
488 | /* 240nS PCI clock */ | |
489 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
490 | ||
491 | /* No error reporting */ | |
492 | pci_write_config_word(0, PCI_ERREN, 0); | |
493 | ||
494 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
495 | ||
496 | } | |
83a49c8d | 497 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
887e2ec9 | 498 | |
887e2ec9 SR |
499 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
500 | void pci_master_init(struct pci_controller *hose) | |
501 | { | |
502 | unsigned short temp_short; | |
503 | ||
83a49c8d MF |
504 | /* |
505 | * Write the PowerPC440 EP PCI Configuration regs. | |
506 | * Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
507 | * Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
508 | */ | |
887e2ec9 SR |
509 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
510 | pci_write_config_word(0, PCI_COMMAND, | |
511 | temp_short | PCI_COMMAND_MASTER | | |
512 | PCI_COMMAND_MEMORY); | |
513 | } | |
83a49c8d | 514 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
887e2ec9 | 515 | |
83a49c8d MF |
516 | /* |
517 | * is_pci_host | |
887e2ec9 | 518 | * |
83a49c8d MF |
519 | * This routine is called to determine if a pci scan should be |
520 | * performed. With various hardware environments (especially cPCI and | |
521 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
522 | * bit in the strap register, or generic host/adapter assumptions. | |
887e2ec9 | 523 | * |
83a49c8d MF |
524 | * Rather than hard-code a bad assumption in the general 440 code, the |
525 | * 440 pci code requires the board to decide at runtime. | |
887e2ec9 | 526 | * |
83a49c8d MF |
527 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
528 | */ | |
887e2ec9 SR |
529 | #if defined(CONFIG_PCI) |
530 | int is_pci_host(struct pci_controller *hose) | |
531 | { | |
532 | /* Cactus is always configured as host. */ | |
533 | return (1); | |
534 | } | |
83a49c8d MF |
535 | #endif /* defined(CONFIG_PCI) */ |
536 | ||
a11e0696 IL |
537 | #if defined(CONFIG_POST) |
538 | /* | |
539 | * Returns 1 if keys pressed to start the power-on long-running tests | |
540 | * Called from board_init_f(). | |
541 | */ | |
542 | int post_hotkeys_pressed(void) | |
543 | { | |
544 | return 0; /* No hotkeys supported */ | |
545 | } | |
546 | #endif /* CONFIG_POST */ | |
13628884 SR |
547 | |
548 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
549 | void ft_board_setup(void *blob, bd_t *bd) | |
550 | { | |
551 | u32 val[4]; | |
552 | int rc; | |
553 | ||
554 | ft_cpu_setup(blob, bd); | |
555 | ||
556 | /* Fixup NOR mapping */ | |
557 | val[0] = 0; /* chip select number */ | |
558 | val[1] = 0; /* always 0 */ | |
559 | val[2] = gd->bd->bi_flashstart; | |
560 | val[3] = gd->bd->bi_flashsize; | |
561 | rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", | |
562 | val, sizeof(val), 1); | |
563 | if (rc) | |
564 | printf("Unable to update property NOR mapping, err=%s\n", | |
565 | fdt_strerror(rc)); | |
566 | } | |
567 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |