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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 MK |
32 | #include <asm/byteorder.h> |
33 | ||
34 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 35 | # include <pci.h> |
477434c6 SP |
36 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
37 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
38 | #endif | |
ddf83a2f | 39 | #endif |
3e326ece MK |
40 | |
41 | #include <malloc.h> | |
42 | #include <usb.h> | |
2731b9a8 JCPV |
43 | |
44 | #include "ohci.h" | |
3e326ece | 45 | |
e8da58f2 WD |
46 | #ifdef CONFIG_AT91RM9200 |
47 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
48 | #endif | |
49 | ||
f2168440 | 50 | #if defined(CONFIG_CPU_ARM920T) || \ |
ac67804f | 51 | defined(CONFIG_S3C24X0) || \ |
ae3b770e | 52 | defined(CONFIG_440EP) || \ |
4dae14ce | 53 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 54 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 55 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
56 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
57 | #endif | |
58 | ||
3e326ece | 59 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
60 | #undef DEBUG |
61 | #undef SHOW_INFO | |
62 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
63 | |
64 | /* For initializing controller (mask in an HCFS mode too) */ | |
65 | #define OHCI_CONTROL_INIT \ | |
66 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
67 | ||
4dae14ce ZW |
68 | #ifdef CONFIG_PCI_OHCI |
69 | static struct pci_device_id ohci_pci_ids[] = { | |
70 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 71 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 72 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
73 | /* Please add supported PCI OHCI controller ids here */ |
74 | {0, 0} | |
75 | }; | |
76 | #endif | |
77 | ||
e90fb6af YT |
78 | #ifdef CONFIG_PCI_EHCI_DEVNO |
79 | static struct pci_device_id ehci_pci_ids[] = { | |
80 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
81 | /* Please add supported PCI EHCI controller ids here */ | |
82 | {0, 0} | |
83 | }; | |
84 | #endif | |
85 | ||
3e326ece MK |
86 | #ifdef DEBUG |
87 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
88 | #else | |
6f5794a6 | 89 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
90 | #endif /* DEBUG */ |
91 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
92 | #ifdef SHOW_INFO |
93 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
94 | #else | |
6f5794a6 | 95 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
96 | #endif |
97 | ||
6d0f6bcf | 98 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
99 | # define m16_swap(x) cpu_to_be16(x) |
100 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 101 | #else |
fc43be47 MK |
102 | # define m16_swap(x) cpu_to_le16(x) |
103 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 104 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece MK |
105 | |
106 | /* global ohci_t */ | |
107 | static ohci_t gohci; | |
108 | /* this must be aligned to a 256 byte boundary */ | |
109 | struct ohci_hcca ghcca[1]; | |
110 | /* a pointer to the aligned storage */ | |
111 | struct ohci_hcca *phcca; | |
3e326ece | 112 | |
6f5794a6 | 113 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 114 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 115 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 116 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 117 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 118 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 119 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 120 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 121 | |
3e326ece | 122 | /* forward declaration */ |
c5613df5 HG |
123 | static int hc_interrupt(ohci_t *ohci); |
124 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, | |
125 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
126 | struct devrequest *setup, urb_priv_t *urb, |
127 | int interval); | |
3e326ece MK |
128 | |
129 | /*-------------------------------------------------------------------------* | |
130 | * URB support functions | |
131 | *-------------------------------------------------------------------------*/ | |
132 | ||
133 | /* free HCD-private data associated with this URB */ | |
134 | ||
6f5794a6 | 135 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
136 | { |
137 | int i; | |
138 | int last; | |
6f5794a6 | 139 | struct td *td; |
3e326ece MK |
140 | |
141 | last = urb->length - 1; | |
142 | if (last >= 0) { | |
143 | for (i = 0; i <= last; i++) { | |
144 | td = urb->td[i]; | |
145 | if (td) { | |
146 | td->usb_dev = NULL; | |
147 | urb->td[i] = NULL; | |
148 | } | |
149 | } | |
150 | } | |
4dae14ce | 151 | free(urb); |
3e326ece MK |
152 | } |
153 | ||
154 | /*-------------------------------------------------------------------------*/ | |
155 | ||
156 | #ifdef DEBUG | |
c5613df5 | 157 | static int sohci_get_current_frame_number(ohci_t *ohci); |
3e326ece MK |
158 | |
159 | /* debug| print the main components of an URB | |
160 | * small: 0) header + data packets 1) just header */ | |
161 | ||
c5613df5 | 162 | static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, |
6f5794a6 RB |
163 | unsigned long pipe, void *buffer, int transfer_len, |
164 | struct devrequest *setup, char *str, int small) | |
3e326ece | 165 | { |
6f5794a6 | 166 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 167 | str, |
c5613df5 | 168 | sohci_get_current_frame_number(ohci), |
6f5794a6 RB |
169 | usb_pipedevice(pipe), |
170 | usb_pipeendpoint(pipe), | |
171 | usb_pipeout(pipe)? 'O': 'I', | |
172 | usb_pipetype(pipe) < 2 ? \ | |
173 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
174 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 175 | (purb ? purb->actual_length : 0), |
3e326ece MK |
176 | transfer_len, dev->status); |
177 | #ifdef OHCI_VERBOSE_DEBUG | |
178 | if (!small) { | |
179 | int i, len; | |
180 | ||
6f5794a6 RB |
181 | if (usb_pipecontrol(pipe)) { |
182 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 183 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
184 | printf(" %02x", ((__u8 *) setup) [i]); |
185 | printf("\n"); | |
3e326ece MK |
186 | } |
187 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 188 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 189 | (purb ? purb->actual_length : 0), |
3e326ece | 190 | transfer_len); |
6f5794a6 | 191 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 192 | (purb ? purb->actual_length : 0); |
3e326ece | 193 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
194 | printf(" %02x", ((__u8 *) buffer) [i]); |
195 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
196 | } |
197 | } | |
198 | #endif | |
199 | } | |
200 | ||
6f5794a6 RB |
201 | /* just for debugging; prints non-empty branches of the int ed tree |
202 | * inclusive iso eds */ | |
203 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
204 | { | |
3e326ece | 205 | int i, j; |
6f5794a6 RB |
206 | __u32 *ed_p; |
207 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
208 | j = 5; |
209 | ed_p = &(ohci->hcca->int_table [i]); | |
210 | if (*ed_p == 0) | |
211 | continue; | |
6f5794a6 | 212 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
213 | while (*ed_p != 0 && j--) { |
214 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
6f5794a6 | 215 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
216 | ed_p = &ed->hwNextED; |
217 | } | |
6f5794a6 | 218 | printf("\n"); |
3e326ece MK |
219 | } |
220 | } | |
221 | ||
6f5794a6 | 222 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 223 | { |
6f5794a6 | 224 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
225 | label, |
226 | mask, | |
227 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
228 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
229 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
230 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
231 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
232 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
233 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
234 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
235 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
236 | ); | |
237 | } | |
238 | ||
6f5794a6 | 239 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
240 | { |
241 | ed_t *edp = (ed_t *)value; | |
242 | ||
243 | if (value) { | |
6f5794a6 RB |
244 | dbg("%s %08x", label, value); |
245 | dbg("%08x", edp->hwINFO); | |
246 | dbg("%08x", edp->hwTailP); | |
247 | dbg("%08x", edp->hwHeadP); | |
248 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
249 | } |
250 | } | |
251 | ||
6f5794a6 | 252 | static char *hcfs2string(int state) |
3e326ece MK |
253 | { |
254 | switch (state) { | |
6f5794a6 RB |
255 | case OHCI_USB_RESET: return "reset"; |
256 | case OHCI_USB_RESUME: return "resume"; | |
257 | case OHCI_USB_OPER: return "operational"; | |
258 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
259 | } |
260 | return "?"; | |
261 | } | |
262 | ||
263 | /* dump control and status registers */ | |
6f5794a6 | 264 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
265 | { |
266 | struct ohci_regs *regs = controller->regs; | |
267 | __u32 temp; | |
268 | ||
a5496a18 | 269 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 270 | if (temp != 0x10) |
6f5794a6 | 271 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 272 | |
a5496a18 | 273 | temp = ohci_readl(®s->control); |
6f5794a6 | 274 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
275 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
276 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
277 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 278 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
279 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
280 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
281 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
282 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
283 | temp & OHCI_CTRL_CBSR | |
284 | ); | |
285 | ||
a5496a18 | 286 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 287 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
288 | (temp & OHCI_SOC) >> 16, |
289 | (temp & OHCI_OCR) ? " OCR" : "", | |
290 | (temp & OHCI_BLF) ? " BLF" : "", | |
291 | (temp & OHCI_CLF) ? " CLF" : "", | |
292 | (temp & OHCI_HCR) ? " HCR" : "" | |
293 | ); | |
294 | ||
a5496a18 BB |
295 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
296 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 297 | |
a5496a18 BB |
298 | maybe_print_eds("ed_periodcurrent", |
299 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 300 | |
a5496a18 BB |
301 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
302 | maybe_print_eds("ed_controlcurrent", | |
303 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 304 | |
a5496a18 BB |
305 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
306 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 307 | |
a5496a18 | 308 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
309 | } |
310 | ||
6f5794a6 | 311 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
312 | { |
313 | __u32 temp, ndp, i; | |
314 | ||
6f5794a6 | 315 | temp = roothub_a(controller); |
3e326ece MK |
316 | ndp = (temp & RH_A_NDP); |
317 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
318 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
319 | #endif |
320 | if (verbose) { | |
6f5794a6 | 321 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
322 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
323 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
324 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
325 | (temp & RH_A_DT) ? " DT" : "", | |
326 | (temp & RH_A_NPS) ? " NPS" : "", | |
327 | (temp & RH_A_PSM) ? " PSM" : "", | |
328 | ndp | |
329 | ); | |
6f5794a6 RB |
330 | temp = roothub_b(controller); |
331 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
332 | temp, |
333 | (temp & RH_B_PPCM) >> 16, | |
334 | (temp & RH_B_DR) | |
335 | ); | |
6f5794a6 RB |
336 | temp = roothub_status(controller); |
337 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
338 | temp, |
339 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
340 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
341 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
342 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
343 | (temp & RH_HS_OCI) ? " OCI" : "", | |
344 | (temp & RH_HS_LPS) ? " LPS" : "" | |
345 | ); | |
346 | } | |
347 | ||
348 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
349 | temp = roothub_portstatus(controller, i); |
350 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
351 | i, |
352 | temp, | |
353 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
354 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
355 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
356 | (temp & RH_PS_PESC) ? " PESC" : "", | |
357 | (temp & RH_PS_CSC) ? " CSC" : "", | |
358 | ||
359 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
360 | (temp & RH_PS_PPS) ? " PPS" : "", | |
361 | (temp & RH_PS_PRS) ? " PRS" : "", | |
362 | (temp & RH_PS_POCI) ? " POCI" : "", | |
363 | (temp & RH_PS_PSS) ? " PSS" : "", | |
364 | ||
365 | (temp & RH_PS_PES) ? " PES" : "", | |
366 | (temp & RH_PS_CCS) ? " CCS" : "" | |
367 | ); | |
368 | } | |
369 | } | |
370 | ||
6f5794a6 | 371 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 372 | { |
6f5794a6 | 373 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
374 | |
375 | /* dumps some of the state we know about */ | |
6f5794a6 | 376 | ohci_dump_status(controller); |
3e326ece | 377 | if (verbose) |
6f5794a6 RB |
378 | ep_print_int_eds(controller, "hcca"); |
379 | dbg("hcca frame #%04x", controller->hcca->frame_no); | |
380 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 381 | } |
3e326ece MK |
382 | #endif /* DEBUG */ |
383 | ||
384 | /*-------------------------------------------------------------------------* | |
385 | * Interface functions (URB) | |
386 | *-------------------------------------------------------------------------*/ | |
387 | ||
388 | /* get a transfer request */ | |
389 | ||
19d95d57 HG |
390 | int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, |
391 | struct devrequest *setup) | |
3e326ece | 392 | { |
6f5794a6 | 393 | ed_t *ed; |
4dae14ce | 394 | urb_priv_t *purb_priv = urb; |
3e326ece | 395 | int i, size = 0; |
4dae14ce ZW |
396 | struct usb_device *dev = urb->dev; |
397 | unsigned long pipe = urb->pipe; | |
398 | void *buffer = urb->transfer_buffer; | |
399 | int transfer_len = urb->transfer_buffer_length; | |
400 | int interval = urb->interval; | |
3e326ece | 401 | |
3e326ece MK |
402 | /* when controller's hung, permit only roothub cleanup attempts |
403 | * such as powering down ports */ | |
404 | if (ohci->disabled) { | |
405 | err("sohci_submit_job: EPIPE"); | |
406 | return -1; | |
407 | } | |
ae79f606 | 408 | |
6f5794a6 RB |
409 | /* we're about to begin a new transaction here so mark the |
410 | * URB unfinished */ | |
4dae14ce | 411 | urb->finished = 0; |
3e326ece MK |
412 | |
413 | /* every endpoint has a ed, locate and fill it */ | |
19d95d57 | 414 | ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); |
6f5794a6 | 415 | if (!ed) { |
3e326ece MK |
416 | err("sohci_submit_job: ENOMEM"); |
417 | return -1; | |
418 | } | |
419 | ||
420 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
421 | switch (usb_pipetype(pipe)) { |
422 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
423 | size = (transfer_len - 1) / 4096 + 1; | |
424 | break; | |
425 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
426 | size = (transfer_len == 0)? 2: | |
427 | (transfer_len - 1) / 4096 + 3; | |
428 | break; | |
429 | case PIPE_INTERRUPT: /* 1 TD */ | |
430 | size = 1; | |
431 | break; | |
3e326ece MK |
432 | } |
433 | ||
4dae14ce ZW |
434 | ed->purb = urb; |
435 | ||
3e326ece MK |
436 | if (size >= (N_URB_TD - 1)) { |
437 | err("need %d TDs, only have %d", size, N_URB_TD); | |
438 | return -1; | |
439 | } | |
3e326ece MK |
440 | purb_priv->pipe = pipe; |
441 | ||
442 | /* fill the private part of the URB */ | |
443 | purb_priv->length = size; | |
444 | purb_priv->ed = ed; | |
445 | purb_priv->actual_length = 0; | |
446 | ||
447 | /* allocate the TDs */ | |
448 | /* note that td[0] was allocated in ep_add_ed */ | |
449 | for (i = 0; i < size; i++) { | |
6f5794a6 | 450 | purb_priv->td[i] = td_alloc(dev); |
3e326ece MK |
451 | if (!purb_priv->td[i]) { |
452 | purb_priv->length = i; | |
6f5794a6 | 453 | urb_free_priv(purb_priv); |
3e326ece MK |
454 | err("sohci_submit_job: ENOMEM"); |
455 | return -1; | |
456 | } | |
457 | } | |
458 | ||
459 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 460 | urb_free_priv(purb_priv); |
3e326ece MK |
461 | err("sohci_submit_job: EINVAL"); |
462 | return -1; | |
463 | } | |
464 | ||
465 | /* link the ed into a chain if is not already */ | |
466 | if (ed->state != ED_OPER) | |
6f5794a6 | 467 | ep_link(ohci, ed); |
3e326ece MK |
468 | |
469 | /* fill the TDs and link it to the ed */ | |
c5613df5 | 470 | td_submit_job(ohci, dev, pipe, buffer, transfer_len, |
6f5794a6 | 471 | setup, purb_priv, interval); |
3e326ece MK |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
4dae14ce ZW |
476 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
477 | { | |
478 | struct ohci_regs *regs = hc->regs; | |
479 | ||
6f5794a6 | 480 | switch (usb_pipetype(urb->pipe)) { |
4dae14ce ZW |
481 | case PIPE_INTERRUPT: |
482 | /* implicitly requeued */ | |
483 | if (urb->dev->irq_handle && | |
484 | (urb->dev->irq_act_len = urb->actual_length)) { | |
a5496a18 BB |
485 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
486 | ohci_readl(®s->intrenable); /* PCI posting flush */ | |
4dae14ce | 487 | urb->dev->irq_handle(urb->dev); |
a5496a18 BB |
488 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
489 | ohci_readl(®s->intrdisable); /* PCI posting flush */ | |
4dae14ce ZW |
490 | } |
491 | urb->actual_length = 0; | |
c5613df5 | 492 | td_submit_job( hc, |
4dae14ce ZW |
493 | urb->dev, |
494 | urb->pipe, | |
495 | urb->transfer_buffer, | |
496 | urb->transfer_buffer_length, | |
497 | NULL, | |
498 | urb, | |
499 | urb->interval); | |
500 | break; | |
501 | case PIPE_CONTROL: | |
502 | case PIPE_BULK: | |
503 | break; | |
504 | default: | |
505 | return 0; | |
506 | } | |
507 | return 1; | |
508 | } | |
509 | ||
3e326ece MK |
510 | /*-------------------------------------------------------------------------*/ |
511 | ||
512 | #ifdef DEBUG | |
513 | /* tell us the current USB frame number */ | |
c5613df5 | 514 | static int sohci_get_current_frame_number(ohci_t *ohci) |
3e326ece | 515 | { |
6f5794a6 | 516 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
517 | } |
518 | #endif | |
519 | ||
4dae14ce ZW |
520 | /*-------------------------------------------------------------------------* |
521 | * ED handling functions | |
522 | *-------------------------------------------------------------------------*/ | |
523 | ||
524 | /* search for the right branch to insert an interrupt ed into the int tree | |
525 | * do some load ballancing; | |
526 | * returns the branch and | |
527 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
528 | ||
6f5794a6 | 529 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
530 | { |
531 | int i, branch = 0; | |
532 | ||
533 | /* search for the least loaded interrupt endpoint | |
534 | * branch of all 32 branches | |
535 | */ | |
536 | for (i = 0; i < 32; i++) | |
537 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
538 | branch = i; | |
539 | ||
540 | branch = branch % interval; | |
541 | for (i = branch; i < 32; i += interval) | |
542 | ohci->ohci_int_load [i] += load; | |
543 | ||
544 | return branch; | |
545 | } | |
546 | ||
547 | /*-------------------------------------------------------------------------*/ | |
548 | ||
549 | /* 2^int( ld (inter)) */ | |
550 | ||
6f5794a6 | 551 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
552 | { |
553 | int i; | |
6f5794a6 | 554 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
555 | return 1 << i; |
556 | } | |
557 | ||
558 | /*-------------------------------------------------------------------------*/ | |
559 | ||
560 | /* the int tree is a binary tree | |
6f5794a6 RB |
561 | * in order to process it sequentially the indexes of the branches have to |
562 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
563 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
564 | { |
565 | int i, wout = 0; | |
566 | ||
567 | for (i = 0; i < num_bits; i++) | |
568 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
569 | return wout; | |
570 | } | |
571 | ||
3e326ece MK |
572 | /*-------------------------------------------------------------------------* |
573 | * ED handling functions | |
574 | *-------------------------------------------------------------------------*/ | |
575 | ||
576 | /* link an ed into one of the HC chains */ | |
577 | ||
6f5794a6 | 578 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
579 | { |
580 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
581 | int int_branch; |
582 | int i; | |
583 | int inter; | |
584 | int interval; | |
585 | int load; | |
6f5794a6 | 586 | __u32 *ed_p; |
3e326ece MK |
587 | |
588 | ed->state = ED_OPER; | |
4dae14ce | 589 | ed->int_interval = 0; |
3e326ece MK |
590 | |
591 | switch (ed->type) { | |
592 | case PIPE_CONTROL: | |
593 | ed->hwNextED = 0; | |
6f5794a6 | 594 | if (ohci->ed_controltail == NULL) |
a5496a18 | 595 | ohci_writel(ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
596 | else |
597 | ohci->ed_controltail->hwNextED = | |
598 | m32_swap((unsigned long)ed); | |
599 | ||
3e326ece MK |
600 | ed->ed_prev = ohci->ed_controltail; |
601 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
602 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
603 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 604 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
605 | } |
606 | ohci->ed_controltail = edi; | |
607 | break; | |
608 | ||
609 | case PIPE_BULK: | |
610 | ed->hwNextED = 0; | |
6f5794a6 | 611 | if (ohci->ed_bulktail == NULL) |
a5496a18 | 612 | ohci_writel(ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
613 | else |
614 | ohci->ed_bulktail->hwNextED = | |
615 | m32_swap((unsigned long)ed); | |
616 | ||
3e326ece MK |
617 | ed->ed_prev = ohci->ed_bulktail; |
618 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
619 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
620 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 621 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
622 | } |
623 | ohci->ed_bulktail = edi; | |
624 | break; | |
4dae14ce ZW |
625 | |
626 | case PIPE_INTERRUPT: | |
627 | load = ed->int_load; | |
6f5794a6 | 628 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 629 | ed->int_interval = interval; |
6f5794a6 | 630 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
631 | ed->int_branch = int_branch; |
632 | ||
6f5794a6 | 633 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 634 | inter = 1; |
6f5794a6 RB |
635 | for (ed_p = &(ohci->hcca->int_table[\ |
636 | ep_rev(5, i) + int_branch]); | |
637 | (*ed_p != 0) && | |
638 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 639 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
640 | inter = ep_rev(6, |
641 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 642 | ed->hwNextED = *ed_p; |
4a8527ef | 643 | *ed_p = m32_swap((unsigned long)ed); |
4dae14ce ZW |
644 | } |
645 | break; | |
3e326ece MK |
646 | } |
647 | return 0; | |
648 | } | |
649 | ||
650 | /*-------------------------------------------------------------------------*/ | |
651 | ||
4dae14ce | 652 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
653 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
654 | unsigned index, unsigned period) | |
4dae14ce ZW |
655 | { |
656 | for (; index < NUM_INTS; index += period) { | |
657 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
658 | ||
659 | /* ED might have been unlinked through another path */ | |
660 | while (*ed_p != 0) { | |
6f5794a6 RB |
661 | if (((struct ed *) |
662 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce ZW |
663 | *ed_p = ed->hwNextED; |
664 | break; | |
665 | } | |
6f5794a6 RB |
666 | ed_p = &(((struct ed *) |
667 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
668 | } |
669 | } | |
670 | } | |
671 | ||
3e326ece MK |
672 | /* unlink an ed from one of the HC chains. |
673 | * just the link to the ed is unlinked. | |
674 | * the link from the ed still points to another operational ed or 0 | |
675 | * so the HC can eventually finish the processing of the unlinked ed */ | |
676 | ||
6f5794a6 | 677 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 678 | { |
53e336e9 | 679 | volatile ed_t *ed = edi; |
4dae14ce | 680 | int i; |
53e336e9 | 681 | |
6f5794a6 | 682 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
3e326ece MK |
683 | |
684 | switch (ed->type) { | |
685 | case PIPE_CONTROL: | |
686 | if (ed->ed_prev == NULL) { | |
687 | if (!ed->hwNextED) { | |
688 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
689 | ohci_writel(ohci->hc_control, |
690 | &ohci->regs->control); | |
3e326ece | 691 | } |
a5496a18 | 692 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 693 | &ohci->regs->ed_controlhead); |
3e326ece MK |
694 | } else { |
695 | ed->ed_prev->hwNextED = ed->hwNextED; | |
696 | } | |
697 | if (ohci->ed_controltail == ed) { | |
698 | ohci->ed_controltail = ed->ed_prev; | |
699 | } else { | |
6f5794a6 RB |
700 | ((ed_t *)m32_swap( |
701 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
702 | } |
703 | break; | |
704 | ||
705 | case PIPE_BULK: | |
706 | if (ed->ed_prev == NULL) { | |
707 | if (!ed->hwNextED) { | |
708 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
709 | ohci_writel(ohci->hc_control, |
710 | &ohci->regs->control); | |
3e326ece | 711 | } |
a5496a18 | 712 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 713 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
714 | } else { |
715 | ed->ed_prev->hwNextED = ed->hwNextED; | |
716 | } | |
717 | if (ohci->ed_bulktail == ed) { | |
718 | ohci->ed_bulktail = ed->ed_prev; | |
719 | } else { | |
6f5794a6 RB |
720 | ((ed_t *)m32_swap( |
721 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
722 | } |
723 | break; | |
4dae14ce ZW |
724 | |
725 | case PIPE_INTERRUPT: | |
6f5794a6 | 726 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
727 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
728 | ohci->ohci_int_load[i] -= ed->int_load; | |
729 | break; | |
3e326ece MK |
730 | } |
731 | ed->state = ED_UNLINK; | |
732 | return 0; | |
733 | } | |
734 | ||
3e326ece MK |
735 | /*-------------------------------------------------------------------------*/ |
736 | ||
ddf83a2f MK |
737 | /* add/reinit an endpoint; this should be done once at the |
738 | * usb_set_configuration command, but the USB stack is a little bit | |
739 | * stateless so we do it at every transaction if the state of the ed | |
740 | * is ED_NEW then a dummy td is added and the state is changed to | |
741 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
742 | * info fields are setted anyway even though most of them should not | |
743 | * change | |
744 | */ | |
19d95d57 HG |
745 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, |
746 | unsigned long pipe, int interval, int load) | |
3e326ece MK |
747 | { |
748 | td_t *td; | |
749 | ed_t *ed_ret; | |
750 | volatile ed_t *ed; | |
751 | ||
19d95d57 | 752 | ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | |
6f5794a6 | 753 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; |
3e326ece MK |
754 | |
755 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
756 | err("ep_add_ed: pending delete"); | |
757 | /* pending delete request */ | |
758 | return NULL; | |
759 | } | |
760 | ||
761 | if (ed->state == ED_NEW) { | |
3e326ece | 762 | /* dummy td; end of td list for ed */ |
6f5794a6 RB |
763 | td = td_alloc(usb_dev); |
764 | ed->hwTailP = m32_swap((unsigned long)td); | |
3e326ece MK |
765 | ed->hwHeadP = ed->hwTailP; |
766 | ed->state = ED_UNLINK; | |
6f5794a6 | 767 | ed->type = usb_pipetype(pipe); |
19d95d57 | 768 | ohci_dev->ed_cnt++; |
3e326ece MK |
769 | } |
770 | ||
6f5794a6 RB |
771 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
772 | | usb_pipeendpoint(pipe) << 7 | |
773 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
774 | | (usb_pipecontrol(pipe)? 0: \ | |
775 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 776 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 777 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 778 | |
4dae14ce ZW |
779 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
780 | ed->int_period = interval; | |
781 | ed->int_load = load; | |
782 | } | |
783 | ||
3e326ece MK |
784 | return ed_ret; |
785 | } | |
786 | ||
787 | /*-------------------------------------------------------------------------* | |
788 | * TD handling functions | |
789 | *-------------------------------------------------------------------------*/ | |
790 | ||
791 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
792 | ||
6f5794a6 | 793 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
794 | void *data, int len, |
795 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
796 | { | |
797 | volatile td_t *td, *td_pt; | |
798 | #ifdef OHCI_FILL_TRACE | |
799 | int i; | |
800 | #endif | |
801 | ||
802 | if (index > urb_priv->length) { | |
803 | err("index > length"); | |
804 | return; | |
805 | } | |
806 | /* use this td as the next dummy */ | |
807 | td_pt = urb_priv->td [index]; | |
808 | td_pt->hwNextTD = 0; | |
809 | ||
810 | /* fill the old dummy TD */ | |
6f5794a6 RB |
811 | td = urb_priv->td [index] = |
812 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
813 | |
814 | td->ed = urb_priv->ed; | |
815 | td->next_dl_td = NULL; | |
816 | td->index = index; | |
817 | td->data = (__u32)data; | |
818 | #ifdef OHCI_FILL_TRACE | |
48867208 | 819 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 820 | for (i = 0; i < len; i++) |
6f5794a6 | 821 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
822 | printf("\n"); |
823 | } | |
824 | #endif | |
825 | if (!len) | |
826 | data = 0; | |
827 | ||
6f5794a6 RB |
828 | td->hwINFO = m32_swap(info); |
829 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 830 | if (data) |
6f5794a6 | 831 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
832 | else |
833 | td->hwBE = 0; | |
6f5794a6 RB |
834 | |
835 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
3e326ece MK |
836 | |
837 | /* append to queue */ | |
838 | td->ed->hwTailP = td->hwNextTD; | |
839 | } | |
840 | ||
841 | /*-------------------------------------------------------------------------*/ | |
842 | ||
843 | /* prepare all TDs of a transfer */ | |
844 | ||
c5613df5 HG |
845 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, |
846 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
847 | struct devrequest *setup, urb_priv_t *urb, |
848 | int interval) | |
3e326ece | 849 | { |
3e326ece MK |
850 | int data_len = transfer_len; |
851 | void *data; | |
852 | int cnt = 0; | |
853 | __u32 info = 0; | |
854 | unsigned int toggle = 0; | |
855 | ||
6f5794a6 RB |
856 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
857 | * bits for reseting */ | |
858 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
859 | toggle = TD_T_TOGGLE; |
860 | } else { | |
861 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
862 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
863 | usb_pipeout(pipe), 1); | |
3e326ece MK |
864 | } |
865 | urb->td_cnt = 0; | |
866 | if (data_len) | |
867 | data = buffer; | |
868 | else | |
869 | data = 0; | |
870 | ||
6f5794a6 | 871 | switch (usb_pipetype(pipe)) { |
3e326ece | 872 | case PIPE_BULK: |
6f5794a6 | 873 | info = usb_pipeout(pipe)? |
3e326ece | 874 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
875 | while (data_len > 4096) { |
876 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
877 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
878 | data += 4096; data_len -= 4096; cnt++; |
879 | } | |
6f5794a6 | 880 | info = usb_pipeout(pipe)? |
3e326ece | 881 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
882 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
883 | data_len, dev, cnt, urb); | |
3e326ece MK |
884 | cnt++; |
885 | ||
6f5794a6 RB |
886 | if (!ohci->sleeping) { |
887 | /* start bulk list */ | |
a5496a18 | 888 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 889 | } |
3e326ece MK |
890 | break; |
891 | ||
892 | case PIPE_CONTROL: | |
6f5794a6 | 893 | /* Setup phase */ |
3e326ece | 894 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
6f5794a6 RB |
895 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
896 | ||
897 | /* Optional Data phase */ | |
3e326ece | 898 | if (data_len > 0) { |
6f5794a6 RB |
899 | info = usb_pipeout(pipe)? |
900 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
901 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 902 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
903 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
904 | } | |
905 | ||
906 | /* Status phase */ | |
907 | info = usb_pipeout(pipe)? | |
908 | TD_CC | TD_DP_IN | TD_T_DATA1: | |
909 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
910 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
911 | ||
912 | if (!ohci->sleeping) { | |
913 | /* start Control list */ | |
a5496a18 | 914 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 915 | } |
3e326ece | 916 | break; |
4dae14ce ZW |
917 | |
918 | case PIPE_INTERRUPT: | |
6f5794a6 | 919 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
920 | TD_CC | TD_DP_OUT | toggle: |
921 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 922 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 923 | break; |
3e326ece MK |
924 | } |
925 | if (urb->length != cnt) | |
926 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
927 | } | |
928 | ||
929 | /*-------------------------------------------------------------------------* | |
930 | * Done List handling functions | |
931 | *-------------------------------------------------------------------------*/ | |
932 | ||
3e326ece MK |
933 | /* calculate the transfer length and update the urb */ |
934 | ||
6f5794a6 | 935 | static void dl_transfer_length(td_t *td) |
3e326ece | 936 | { |
6bc52ef3 | 937 | __u32 tdBE, tdCBP; |
4dae14ce | 938 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 939 | |
6f5794a6 RB |
940 | tdBE = m32_swap(td->hwBE); |
941 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 942 | |
48867208 | 943 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
944 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
945 | if (tdBE != 0) { | |
946 | if (td->hwCBP == 0) | |
947 | lurb_priv->actual_length += tdBE - td->data + 1; | |
948 | else | |
949 | lurb_priv->actual_length += tdCBP - td->data; | |
950 | } | |
951 | } | |
952 | } | |
953 | ||
954 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
955 | static void check_status(td_t *td_list) |
956 | { | |
957 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
958 | int urb_len = lurb_priv->length; | |
959 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
960 | int cc; | |
961 | ||
962 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
963 | if (cc) { | |
964 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
965 | ||
966 | if (*phwHeadP & m32_swap(0x1)) { | |
967 | if (lurb_priv && | |
968 | ((td_list->index + 1) < urb_len)) { | |
969 | *phwHeadP = | |
970 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
971 | m32_swap(0xfffffff0)) | | |
972 | (*phwHeadP & m32_swap(0x2)); | |
973 | ||
974 | lurb_priv->td_cnt += urb_len - | |
975 | td_list->index - 1; | |
976 | } else | |
977 | *phwHeadP &= m32_swap(0xfffffff2); | |
978 | } | |
979 | #ifdef CONFIG_MPC5200 | |
980 | td_list->hwNextTD = 0; | |
981 | #endif | |
982 | } | |
983 | } | |
3e326ece MK |
984 | |
985 | /* replies to the request have to be on a FIFO basis so | |
986 | * we reverse the reversed done-list */ | |
6f5794a6 | 987 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
988 | { |
989 | __u32 td_list_hc; | |
990 | td_t *td_rev = NULL; | |
991 | td_t *td_list = NULL; | |
3e326ece | 992 | |
6f5794a6 | 993 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece MK |
994 | ohci->hcca->done_head = 0; |
995 | ||
996 | while (td_list_hc) { | |
997 | td_list = (td_t *)td_list_hc; | |
6f5794a6 | 998 | check_status(td_list); |
3e326ece MK |
999 | td_list->next_dl_td = td_rev; |
1000 | td_rev = td_list; | |
6f5794a6 | 1001 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1002 | } |
1003 | return td_list; | |
1004 | } | |
1005 | ||
6f5794a6 | 1006 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1007 | /*-------------------------------------------------------------------------*/ |
1008 | ||
6f5794a6 RB |
1009 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1010 | { | |
1011 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
1012 | urb->finished = sohci_return_job(ohci, urb); | |
1013 | else | |
1014 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1015 | } | |
1016 | ||
1017 | /* | |
1018 | * Used to take back a TD from the host controller. This would normally be | |
1019 | * called from within dl_done_list, however it may be called directly if the | |
1020 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1021 | * two frames). This bug has been observed on ZF Micro systems. | |
1022 | */ | |
1023 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1024 | { |
3e326ece | 1025 | ed_t *ed; |
6f5794a6 | 1026 | int cc; |
3e326ece MK |
1027 | int stat = 0; |
1028 | /* urb_t *urb; */ | |
1029 | urb_priv_t *lurb_priv; | |
1030 | __u32 tdINFO, edHeadP, edTailP; | |
1031 | ||
6f5794a6 | 1032 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1033 | |
6f5794a6 RB |
1034 | ed = td_list->ed; |
1035 | lurb_priv = ed->purb; | |
3e326ece | 1036 | |
6f5794a6 | 1037 | dl_transfer_length(td_list); |
3e326ece | 1038 | |
6f5794a6 | 1039 | lurb_priv->td_cnt++; |
3e326ece | 1040 | |
6f5794a6 RB |
1041 | /* error code of transfer */ |
1042 | cc = TD_CC_GET(tdINFO); | |
1043 | if (cc) { | |
1044 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1045 | stat = cc_to_error[cc]; | |
1046 | } | |
ae79f606 | 1047 | |
6f5794a6 RB |
1048 | /* see if this done list makes for all TD's of current URB, |
1049 | * and mark the URB finished if so */ | |
1050 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1051 | finish_urb(ohci, lurb_priv, ed->state); | |
1052 | ||
1053 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1054 | lurb_priv->td_cnt, lurb_priv->length); | |
1055 | ||
48867208 | 1056 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
6f5794a6 RB |
1057 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1058 | edTailP = m32_swap(ed->hwTailP); | |
1059 | ||
1060 | /* unlink eds if they are not busy */ | |
1061 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1062 | ep_unlink(ohci, ed); | |
1063 | } | |
1064 | return stat; | |
1065 | } | |
3e326ece | 1066 | |
6f5794a6 RB |
1067 | static int dl_done_list(ohci_t *ohci) |
1068 | { | |
1069 | int stat = 0; | |
1070 | td_t *td_list = dl_reverse_done_list(ohci); | |
1071 | ||
1072 | while (td_list) { | |
1073 | td_t *td_next = td_list->next_dl_td; | |
1074 | stat = takeback_td(ohci, td_list); | |
1075 | td_list = td_next; | |
3e326ece MK |
1076 | } |
1077 | return stat; | |
1078 | } | |
1079 | ||
1080 | /*-------------------------------------------------------------------------* | |
1081 | * Virtual Root Hub | |
1082 | *-------------------------------------------------------------------------*/ | |
1083 | ||
eb838e7d | 1084 | #include <usbroothubdes.h> |
3e326ece MK |
1085 | |
1086 | /* Hub class-specific descriptor is constructed dynamically */ | |
1087 | ||
3e326ece MK |
1088 | /*-------------------------------------------------------------------------*/ |
1089 | ||
1090 | #define OK(x) len = (x); break | |
1091 | #ifdef DEBUG | |
a5496a18 | 1092 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
c5613df5 | 1093 | &ohci->regs->roothub.status); } |
6f5794a6 | 1094 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ |
c5613df5 | 1095 | (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1096 | #else |
c5613df5 | 1097 | #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) |
a5496a18 | 1098 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ |
c5613df5 | 1099 | &ohci->regs->roothub.portstatus[wIndex-1]) |
3e326ece | 1100 | #endif |
c5613df5 HG |
1101 | #define RD_RH_STAT roothub_status(ohci) |
1102 | #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) | |
3e326ece MK |
1103 | |
1104 | /* request to virtual root hub */ | |
1105 | ||
1106 | int rh_check_port_status(ohci_t *controller) | |
1107 | { | |
1108 | __u32 temp, ndp, i; | |
1109 | int res; | |
1110 | ||
1111 | res = -1; | |
6f5794a6 | 1112 | temp = roothub_a(controller); |
3e326ece MK |
1113 | ndp = (temp & RH_A_NDP); |
1114 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1115 | ndp = (ndp == 2) ? 1:0; | |
1116 | #endif | |
1117 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1118 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1119 | /* check for a device disconnect */ |
1120 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1121 | (RH_PS_PESC | RH_PS_CSC)) && | |
1122 | ((temp & RH_PS_CCS) == 0)) { | |
1123 | res = i; | |
1124 | break; | |
1125 | } | |
1126 | } | |
1127 | return res; | |
1128 | } | |
1129 | ||
c5613df5 HG |
1130 | static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, |
1131 | unsigned long pipe, void *buffer, int transfer_len, | |
1132 | struct devrequest *cmd) | |
3e326ece | 1133 | { |
6f5794a6 | 1134 | void *data = buffer; |
3e326ece MK |
1135 | int leni = transfer_len; |
1136 | int len = 0; | |
1137 | int stat = 0; | |
3e326ece MK |
1138 | __u16 bmRType_bReq; |
1139 | __u16 wValue; | |
1140 | __u16 wIndex; | |
1141 | __u16 wLength; | |
f1273f11 | 1142 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1143 | |
3e326ece | 1144 | #ifdef DEBUG |
c5613df5 | 1145 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1146 | cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece | 1147 | #else |
5b84dd67 | 1148 | mdelay(1); |
3e326ece | 1149 | #endif |
48867208 | 1150 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1151 | info("Root-Hub submit IRQ: NOT implemented"); |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1156 | wValue = le16_to_cpu(cmd->value); |
1157 | wIndex = le16_to_cpu(cmd->index); | |
1158 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1159 | |
1160 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1161 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1162 | ||
1163 | switch (bmRType_bReq) { | |
1164 | /* Request Destination: | |
1165 | without flags: Device, | |
1166 | RH_INTERFACE: interface, | |
1167 | RH_ENDPOINT: endpoint, | |
1168 | RH_CLASS means HUB here, | |
1169 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1170 | */ | |
1171 | ||
1172 | case RH_GET_STATUS: | |
f1273f11 | 1173 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1174 | OK(2); |
3e326ece | 1175 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1176 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1177 | OK(2); |
3e326ece | 1178 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1179 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1180 | OK(2); |
3e326ece | 1181 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1182 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1183 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1184 | OK(4); |
3e326ece | 1185 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1186 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1187 | OK(4); |
3e326ece MK |
1188 | |
1189 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1190 | switch (wValue) { | |
6f5794a6 RB |
1191 | case (RH_ENDPOINT_STALL): |
1192 | OK(0); | |
3e326ece MK |
1193 | } |
1194 | break; | |
1195 | ||
1196 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1197 | switch (wValue) { | |
6f5794a6 RB |
1198 | case RH_C_HUB_LOCAL_POWER: |
1199 | OK(0); | |
1200 | case (RH_C_HUB_OVER_CURRENT): | |
1201 | WR_RH_STAT(RH_HS_OCIC); | |
1202 | OK(0); | |
3e326ece MK |
1203 | } |
1204 | break; | |
1205 | ||
1206 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1207 | switch (wValue) { | |
6f5794a6 RB |
1208 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1209 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1210 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1211 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1212 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1213 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1214 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1215 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1216 | } |
1217 | break; | |
1218 | ||
1219 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1220 | switch (wValue) { | |
6f5794a6 RB |
1221 | case (RH_PORT_SUSPEND): |
1222 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1223 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1224 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1225 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1226 | OK(0); | |
1227 | case (RH_PORT_POWER): | |
1228 | WR_RH_PORTSTAT(RH_PS_PPS); | |
5b84dd67 | 1229 | mdelay(100); |
6f5794a6 RB |
1230 | OK(0); |
1231 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1232 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1233 | WR_RH_PORTSTAT(RH_PS_PES); | |
1234 | OK(0); | |
3e326ece MK |
1235 | } |
1236 | break; | |
1237 | ||
6f5794a6 | 1238 | case RH_SET_ADDRESS: |
c5613df5 | 1239 | ohci->rh.devnum = wValue; |
6f5794a6 | 1240 | OK(0); |
3e326ece MK |
1241 | |
1242 | case RH_GET_DESCRIPTOR: | |
1243 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1244 | case (0x01): /* device descriptor */ |
1245 | len = min_t(unsigned int, | |
1246 | leni, | |
1247 | min_t(unsigned int, | |
1248 | sizeof(root_hub_dev_des), | |
1249 | wLength)); | |
f1273f11 | 1250 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1251 | case (0x02): /* configuration descriptor */ |
1252 | len = min_t(unsigned int, | |
1253 | leni, | |
1254 | min_t(unsigned int, | |
1255 | sizeof(root_hub_config_des), | |
1256 | wLength)); | |
f1273f11 | 1257 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1258 | case (0x03): /* string descriptors */ |
1259 | if (wValue == 0x0300) { | |
3e326ece | 1260 | len = min_t(unsigned int, |
6f5794a6 RB |
1261 | leni, |
1262 | min_t(unsigned int, | |
1263 | sizeof(root_hub_str_index0), | |
1264 | wLength)); | |
f1273f11 | 1265 | databuf = root_hub_str_index0; |
6f5794a6 | 1266 | OK(len); |
3e326ece | 1267 | } |
6f5794a6 RB |
1268 | if (wValue == 0x0301) { |
1269 | len = min_t(unsigned int, | |
1270 | leni, | |
1271 | min_t(unsigned int, | |
1272 | sizeof(root_hub_str_index1), | |
1273 | wLength)); | |
f1273f11 | 1274 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1275 | OK(len); |
1276 | } | |
1277 | default: | |
1278 | stat = USB_ST_STALLED; | |
3e326ece MK |
1279 | } |
1280 | break; | |
1281 | ||
1282 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1283 | { | |
c5613df5 | 1284 | __u32 temp = roothub_a(ohci); |
3e326ece | 1285 | |
f1273f11 TK |
1286 | databuf[0] = 9; /* min length; */ |
1287 | databuf[1] = 0x29; | |
1288 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1289 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1290 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1291 | #endif |
f1273f11 | 1292 | databuf[3] = 0; |
3e326ece | 1293 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1294 | databuf[3] |= 0x1; |
3e326ece | 1295 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1296 | databuf[3] |= 0x10; |
6f5794a6 | 1297 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1298 | databuf[3] |= 0x8; |
3e326ece | 1299 | |
f1273f11 TK |
1300 | databuf[4] = 0; |
1301 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1302 | databuf[6] = 0; | |
c5613df5 | 1303 | temp = roothub_b(ohci); |
f1273f11 TK |
1304 | databuf[7] = temp & RH_B_DR; |
1305 | if (databuf[2] < 7) { | |
1306 | databuf[8] = 0xff; | |
3e326ece | 1307 | } else { |
f1273f11 TK |
1308 | databuf[0] += 2; |
1309 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1310 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1311 | } |
1312 | ||
1313 | len = min_t(unsigned int, leni, | |
f1273f11 | 1314 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1315 | OK(len); |
3e326ece MK |
1316 | } |
1317 | ||
5f6aa03f | 1318 | case RH_GET_CONFIGURATION: |
f1273f11 | 1319 | databuf[0] = 0x01; |
5f6aa03f | 1320 | OK(1); |
3e326ece | 1321 | |
5f6aa03f MV |
1322 | case RH_SET_CONFIGURATION: |
1323 | WR_RH_STAT(0x10000); | |
1324 | OK(0); | |
3e326ece MK |
1325 | |
1326 | default: | |
6f5794a6 | 1327 | dbg("unsupported root hub command"); |
3e326ece MK |
1328 | stat = USB_ST_STALLED; |
1329 | } | |
1330 | ||
1331 | #ifdef DEBUG | |
c5613df5 | 1332 | ohci_dump_roothub(ohci, 1); |
3e326ece | 1333 | #else |
5b84dd67 | 1334 | mdelay(1); |
3e326ece MK |
1335 | #endif |
1336 | ||
1337 | len = min_t(int, len, leni); | |
f1273f11 TK |
1338 | if (data != databuf) |
1339 | memcpy(data, databuf, len); | |
3e326ece MK |
1340 | dev->act_len = len; |
1341 | dev->status = stat; | |
1342 | ||
1343 | #ifdef DEBUG | |
c5613df5 | 1344 | pkt_print(ohci, NULL, dev, pipe, buffer, |
6f5794a6 | 1345 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece | 1346 | #else |
5b84dd67 | 1347 | mdelay(1); |
3e326ece MK |
1348 | #endif |
1349 | ||
1350 | return stat; | |
1351 | } | |
1352 | ||
1353 | /*-------------------------------------------------------------------------*/ | |
1354 | ||
1355 | /* common code for handling submit messages - used for all but root hub */ | |
1356 | /* accesses. */ | |
c5613df5 HG |
1357 | static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, |
1358 | unsigned long pipe, void *buffer, int transfer_len, | |
1359 | struct devrequest *setup, int interval) | |
3e326ece MK |
1360 | { |
1361 | int stat = 0; | |
1362 | int maxsize = usb_maxpacket(dev, pipe); | |
1363 | int timeout; | |
4dae14ce ZW |
1364 | urb_priv_t *urb; |
1365 | ||
1366 | urb = malloc(sizeof(urb_priv_t)); | |
1367 | memset(urb, 0, sizeof(urb_priv_t)); | |
1368 | ||
1369 | urb->dev = dev; | |
1370 | urb->pipe = pipe; | |
1371 | urb->transfer_buffer = buffer; | |
1372 | urb->transfer_buffer_length = transfer_len; | |
1373 | urb->interval = interval; | |
3e326ece | 1374 | |
3e326ece | 1375 | #ifdef DEBUG |
4dae14ce | 1376 | urb->actual_length = 0; |
c5613df5 | 1377 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1378 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1379 | #else |
5b84dd67 | 1380 | mdelay(1); |
3e326ece MK |
1381 | #endif |
1382 | if (!maxsize) { | |
1383 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1384 | pipe); | |
1385 | return -1; | |
1386 | } | |
1387 | ||
19d95d57 | 1388 | if (sohci_submit_job(ohci, &ohci->ohci_dev, urb, setup) < 0) { |
3e326ece MK |
1389 | err("sohci_submit_job failed"); |
1390 | return -1; | |
1391 | } | |
1392 | ||
ae3b770e | 1393 | #if 0 |
5b84dd67 | 1394 | mdelay(10); |
c5613df5 | 1395 | /* ohci_dump_status(ohci); */ |
ae3b770e | 1396 | #endif |
3e326ece | 1397 | |
96820a35 | 1398 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1399 | |
1400 | /* wait for it to complete */ | |
1401 | for (;;) { | |
1402 | /* check whether the controller is done */ | |
c5613df5 | 1403 | stat = hc_interrupt(ohci); |
3e326ece MK |
1404 | if (stat < 0) { |
1405 | stat = USB_ST_CRC_ERR; | |
1406 | break; | |
1407 | } | |
ddf83a2f | 1408 | |
ddf83a2f MK |
1409 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1410 | * handle only one URB at a time, we cannot assume the | |
1411 | * transaction finished on the first successful return from | |
1412 | * hc_interrupt().. unless the flag for current URB is set, | |
1413 | * meaning that all TD's to/from device got actually | |
1414 | * transferred and processed. If the current URB is not | |
1415 | * finished we need to re-iterate this loop so as | |
1416 | * hc_interrupt() gets called again as there needs to be some | |
1417 | * more TD's to process still */ | |
4dae14ce | 1418 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1419 | /* 0xff is returned for an SF-interrupt */ |
1420 | break; | |
1421 | } | |
ddf83a2f | 1422 | |
3e326ece | 1423 | if (--timeout) { |
5b84dd67 | 1424 | mdelay(1); |
4dae14ce | 1425 | if (!urb->finished) |
6f5794a6 | 1426 | dbg("*"); |
4dae14ce | 1427 | |
3e326ece MK |
1428 | } else { |
1429 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1430 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1431 | urb->finished = 1; |
3e326ece MK |
1432 | stat = USB_ST_CRC_ERR; |
1433 | break; | |
1434 | } | |
1435 | } | |
3e326ece MK |
1436 | |
1437 | dev->status = stat; | |
522c9564 | 1438 | dev->act_len = urb->actual_length; |
3e326ece MK |
1439 | |
1440 | #ifdef DEBUG | |
c5613df5 | 1441 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1442 | setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece | 1443 | #else |
5b84dd67 | 1444 | mdelay(1); |
3e326ece MK |
1445 | #endif |
1446 | ||
1447 | /* free TDs in urb_priv */ | |
48867208 | 1448 | if (!usb_pipeint(pipe)) |
6f5794a6 | 1449 | urb_free_priv(urb); |
3e326ece MK |
1450 | return 0; |
1451 | } | |
1452 | ||
1453 | /* submit routines called from usb.c */ | |
1454 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1455 | int transfer_len) | |
1456 | { | |
1457 | info("submit_bulk_msg"); | |
c5613df5 HG |
1458 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, |
1459 | NULL, 0); | |
1460 | } | |
1461 | ||
1462 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1463 | int transfer_len, int interval) | |
1464 | { | |
1465 | info("submit_int_msg"); | |
1466 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, | |
1467 | interval); | |
3e326ece MK |
1468 | } |
1469 | ||
c5613df5 HG |
1470 | static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, |
1471 | unsigned long pipe, void *buffer, int transfer_len, | |
1472 | struct devrequest *setup) | |
3e326ece MK |
1473 | { |
1474 | int maxsize = usb_maxpacket(dev, pipe); | |
1475 | ||
1476 | info("submit_control_msg"); | |
1477 | #ifdef DEBUG | |
c5613df5 | 1478 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1479 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1480 | #else |
5b84dd67 | 1481 | mdelay(1); |
3e326ece MK |
1482 | #endif |
1483 | if (!maxsize) { | |
1484 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1485 | pipe); | |
1486 | return -1; | |
1487 | } | |
c5613df5 HG |
1488 | if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { |
1489 | ohci->rh.dev = dev; | |
3e326ece | 1490 | /* root hub - redirect */ |
c5613df5 HG |
1491 | return ohci_submit_rh_msg(ohci, dev, pipe, buffer, |
1492 | transfer_len, setup); | |
3e326ece MK |
1493 | } |
1494 | ||
c5613df5 HG |
1495 | return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, |
1496 | setup, 0); | |
3e326ece MK |
1497 | } |
1498 | ||
1499 | /*-------------------------------------------------------------------------* | |
1500 | * HC functions | |
1501 | *-------------------------------------------------------------------------*/ | |
1502 | ||
1503 | /* reset the HC and BUS */ | |
1504 | ||
6f5794a6 | 1505 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1506 | { |
e90fb6af YT |
1507 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1508 | pci_dev_t pdev; | |
1509 | #endif | |
3e326ece MK |
1510 | int timeout = 30; |
1511 | int smm_timeout = 50; /* 0,5 sec */ | |
1512 | ||
1513 | dbg("%s\n", __FUNCTION__); | |
1514 | ||
e90fb6af YT |
1515 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1516 | /* | |
1517 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1518 | * resetting via EHCI registers only. | |
1519 | */ | |
1520 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1521 | if (pdev != -1) { | |
1522 | u32 base; | |
1523 | int timeout = 1000; | |
1524 | ||
1525 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1526 | base += EHCI_USBCMD_OFF; |
1527 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1528 | |
a5496a18 | 1529 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1530 | if (timeout-- <= 0) { |
1531 | printf("USB RootHub reset timed out!"); | |
1532 | break; | |
1533 | } | |
1534 | udelay(1); | |
1535 | } | |
1536 | } else | |
1537 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1538 | #endif | |
a5496a18 BB |
1539 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1540 | /* SMM owns the HC, request ownership */ | |
1541 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1542 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1543 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1544 | mdelay(10); |
3e326ece MK |
1545 | if (--smm_timeout == 0) { |
1546 | err("USB HC TakeOver failed!"); | |
1547 | return -1; | |
1548 | } | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | /* Disable HC interrupts */ | |
a5496a18 | 1553 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1554 | |
1555 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1556 | ohci->slot_name, | |
a5496a18 | 1557 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1558 | |
1559 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1560 | ohci->hc_control = 0; |
a5496a18 | 1561 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1562 | |
1563 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1564 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1565 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1566 | if (--timeout == 0) { |
1567 | err("USB HC reset timed out!"); | |
1568 | return -1; | |
1569 | } | |
6f5794a6 | 1570 | udelay(1); |
3e326ece MK |
1571 | } |
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | /*-------------------------------------------------------------------------*/ | |
1576 | ||
1577 | /* Start an OHCI controller, set the BUS operational | |
1578 | * enable interrupts | |
1579 | * connect the virtual root hub */ | |
1580 | ||
6f5794a6 | 1581 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1582 | { |
1583 | __u32 mask; | |
1584 | unsigned int fminterval; | |
1585 | ||
1586 | ohci->disabled = 1; | |
1587 | ||
1588 | /* Tell the controller where the control and bulk lists are | |
1589 | * The lists are empty now. */ | |
1590 | ||
a5496a18 BB |
1591 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1592 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1593 | |
a5496a18 BB |
1594 | ohci_writel((__u32)ohci->hcca, |
1595 | &ohci->regs->hcca); /* reset clears this */ | |
3e326ece MK |
1596 | |
1597 | fminterval = 0x2edf; | |
a5496a18 | 1598 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1599 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1600 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1601 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1602 | |
1603 | /* start controller operations */ | |
1604 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1605 | ohci->disabled = 0; | |
a5496a18 | 1606 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1607 | |
1608 | /* disable all interrupts */ | |
1609 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1610 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1611 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1612 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1613 | /* clear all interrupts */ |
1614 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1615 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1616 | /* Choose the interrupts we care about now - but w/o MIE */ |
1617 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1618 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1619 | |
1620 | #ifdef OHCI_USE_NPS | |
1621 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1622 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1623 | &ohci->regs->roothub.a); |
a5496a18 | 1624 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1625 | #endif /* OHCI_USE_NPS */ |
1626 | ||
3e326ece | 1627 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
6f5794a6 | 1628 | mdelay((roothub_a(ohci) >> 23) & 0x1fe); |
3e326ece MK |
1629 | |
1630 | /* connect the virtual root hub */ | |
1631 | ohci->rh.devnum = 0; | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | /*-------------------------------------------------------------------------*/ | |
1637 | ||
1638 | /* an interrupt happens */ | |
1639 | ||
c5613df5 | 1640 | static int hc_interrupt(ohci_t *ohci) |
3e326ece | 1641 | { |
3e326ece MK |
1642 | struct ohci_regs *regs = ohci->regs; |
1643 | int ints; | |
1644 | int stat = -1; | |
1645 | ||
ddf83a2f | 1646 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1647 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1648 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1649 | } else { |
a5496a18 | 1650 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1651 | if (ints == ~(u32)0) { |
1652 | ohci->disabled++; | |
1653 | err("%s device removed!", ohci->slot_name); | |
1654 | return -1; | |
1655 | } else { | |
a5496a18 | 1656 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1657 | if (ints == 0) { |
1658 | dbg("hc_interrupt: returning..\n"); | |
1659 | return 0xff; | |
1660 | } | |
1661 | } | |
ddf83a2f | 1662 | } |
ae79f606 | 1663 | |
6f5794a6 RB |
1664 | /* dbg("Interrupt: %x frame: %x", ints, |
1665 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1666 | |
6f5794a6 | 1667 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1668 | stat = 0xff; |
3e326ece MK |
1669 | |
1670 | if (ints & OHCI_INTR_UE) { | |
1671 | ohci->disabled++; | |
6f5794a6 | 1672 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1673 | ohci->slot_name); |
1674 | /* e.g. due to PCI Master/Target Abort */ | |
1675 | ||
1676 | #ifdef DEBUG | |
6f5794a6 | 1677 | ohci_dump(ohci, 1); |
3e326ece | 1678 | #else |
5b84dd67 | 1679 | mdelay(1); |
3e326ece MK |
1680 | #endif |
1681 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1682 | /* Make some non-interrupt context restart the controller. */ | |
1683 | /* Count and limit the retries though; either hardware or */ | |
1684 | /* software errors can go forever... */ | |
6f5794a6 | 1685 | hc_reset(ohci); |
3e326ece MK |
1686 | return -1; |
1687 | } | |
1688 | ||
1689 | if (ints & OHCI_INTR_WDH) { | |
5b84dd67 | 1690 | mdelay(1); |
a5496a18 BB |
1691 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1692 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
c5613df5 | 1693 | stat = dl_done_list(ohci); |
a5496a18 BB |
1694 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1695 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1696 | } |
1697 | ||
1698 | if (ints & OHCI_INTR_SO) { | |
1699 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1700 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1701 | stat = -1; |
1702 | } | |
1703 | ||
1704 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1705 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1706 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1707 | mdelay(1); |
a5496a18 | 1708 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1709 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1710 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1711 | stat = 0xff; |
1712 | } | |
1713 | ||
a5496a18 | 1714 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1715 | return stat; |
1716 | } | |
1717 | ||
1718 | /*-------------------------------------------------------------------------*/ | |
1719 | ||
1720 | /*-------------------------------------------------------------------------*/ | |
1721 | ||
1722 | /* De-allocate all resources.. */ | |
1723 | ||
6f5794a6 | 1724 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1725 | { |
6f5794a6 | 1726 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1727 | |
1728 | if (!ohci->disabled) | |
6f5794a6 | 1729 | hc_reset(ohci); |
3e326ece MK |
1730 | } |
1731 | ||
1732 | /*-------------------------------------------------------------------------*/ | |
1733 | ||
1734 | /* | |
1735 | * low level initalisation routine, called from usb.c | |
1736 | */ | |
1737 | static char ohci_inited = 0; | |
1738 | ||
06d513ec | 1739 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 1740 | { |
4dae14ce ZW |
1741 | #ifdef CONFIG_PCI_OHCI |
1742 | pci_dev_t pdev; | |
1743 | #endif | |
24e37645 | 1744 | |
6d0f6bcf | 1745 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1746 | /* cpu dependant init */ |
6f5794a6 | 1747 | if (usb_cpu_init()) |
3e326ece | 1748 | return -1; |
24e37645 | 1749 | #endif |
3e326ece | 1750 | |
6d0f6bcf | 1751 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1752 | /* board dependant init */ |
16297cfb | 1753 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
1754 | return -1; |
1755 | #endif | |
6f5794a6 | 1756 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1757 | |
1758 | /* align the storage */ | |
1759 | if ((__u32)&ghcca[0] & 0xff) { | |
1760 | err("HCCA not aligned!!"); | |
1761 | return -1; | |
1762 | } | |
1763 | phcca = &ghcca[0]; | |
1764 | info("aligned ghcca %p", phcca); | |
3e326ece MK |
1765 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); |
1766 | if ((__u32)gtd & 0x7) { | |
1767 | err("TDs not aligned!!"); | |
1768 | return -1; | |
1769 | } | |
1770 | ptd = gtd; | |
1771 | gohci.hcca = phcca; | |
6f5794a6 | 1772 | memset(phcca, 0, sizeof(struct ohci_hcca)); |
3e326ece MK |
1773 | |
1774 | gohci.disabled = 1; | |
1775 | gohci.sleeping = 0; | |
1776 | gohci.irq = -1; | |
4dae14ce | 1777 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1778 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1779 | |
1780 | if (pdev != -1) { | |
1781 | u16 vid, did; | |
1782 | u32 base; | |
1783 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1784 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1785 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1786 | vid, did, (pdev >> 16) & 0xff, | |
1787 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1788 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1789 | printf("OHCI regs address 0x%08x\n", base); | |
1790 | gohci.regs = (struct ohci_regs *)base; | |
1791 | } else | |
1792 | return -1; | |
1793 | #else | |
6d0f6bcf | 1794 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1795 | #endif |
3e326ece MK |
1796 | |
1797 | gohci.flags = 0; | |
6d0f6bcf | 1798 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1799 | |
1800 | if (hc_reset (&gohci) < 0) { | |
1801 | hc_release_ohci (&gohci); | |
1802 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1803 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1804 | /* board dependant cleanup */ |
16297cfb | 1805 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
1806 | #endif |
1807 | ||
6d0f6bcf | 1808 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1809 | /* cpu dependant cleanup */ |
ddf83a2f | 1810 | usb_cpu_init_fail(); |
24e37645 | 1811 | #endif |
3e326ece MK |
1812 | return -1; |
1813 | } | |
1814 | ||
6f5794a6 RB |
1815 | if (hc_start(&gohci) < 0) { |
1816 | err("can't start usb-%s", gohci.slot_name); | |
1817 | hc_release_ohci(&gohci); | |
3e326ece | 1818 | /* Initialization failed */ |
6d0f6bcf | 1819 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1820 | /* board dependant cleanup */ |
1821 | usb_board_stop(); | |
1822 | #endif | |
1823 | ||
6d0f6bcf | 1824 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1825 | /* cpu dependant cleanup */ |
1826 | usb_cpu_stop(); | |
1827 | #endif | |
3e326ece MK |
1828 | return -1; |
1829 | } | |
1830 | ||
1831 | #ifdef DEBUG | |
6f5794a6 | 1832 | ohci_dump(&gohci, 1); |
3e326ece | 1833 | #else |
5b84dd67 | 1834 | mdelay(1); |
3e326ece MK |
1835 | #endif |
1836 | ohci_inited = 1; | |
1837 | return 0; | |
1838 | } | |
1839 | ||
c7e3b2b5 | 1840 | int usb_lowlevel_stop(int index) |
3e326ece MK |
1841 | { |
1842 | /* this gets called really early - before the controller has */ | |
1843 | /* even been initialized! */ | |
1844 | if (!ohci_inited) | |
1845 | return 0; | |
1846 | /* TODO release any interrupts, etc. */ | |
1847 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 1848 | hc_reset(&gohci); |
3e326ece | 1849 | |
6d0f6bcf | 1850 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 1851 | /* board dependant cleanup */ |
6f5794a6 | 1852 | if (usb_board_stop()) |
3e326ece | 1853 | return -1; |
24e37645 MK |
1854 | #endif |
1855 | ||
6d0f6bcf | 1856 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1857 | /* cpu dependant cleanup */ |
6f5794a6 | 1858 | if (usb_cpu_stop()) |
24e37645 MK |
1859 | return -1; |
1860 | #endif | |
eba1f2fc RB |
1861 | /* This driver is no longer initialised. It needs a new low-level |
1862 | * init (board/cpu) before it can be used again. */ | |
1863 | ohci_inited = 0; | |
3e326ece MK |
1864 | return 0; |
1865 | } | |
c5613df5 HG |
1866 | |
1867 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, | |
1868 | void *buffer, int transfer_len, struct devrequest *setup) | |
1869 | { | |
1870 | return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, | |
1871 | transfer_len, setup); | |
1872 | } |