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Commit | Line | Data |
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991425fe | 1 | /* |
2ae18241 | 2 | * (C) Copyright 2006-2010 |
991425fe MB |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
991425fe MB |
6 | */ |
7 | ||
8 | /* | |
9 | * mpc8349emds board configuration file | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
fdfaa29e KP |
16 | #define CONFIG_SYS_GENERIC_BOARD |
17 | #define CONFIG_DISPLAY_BOARDINFO | |
18 | ||
991425fe MB |
19 | /* |
20 | * High Level Configuration Options | |
21 | */ | |
22 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 23 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
991425fe MB |
24 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
25 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
26 | ||
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
28 | ||
29 | #define CONFIG_PCI_66M | |
30 | #ifdef CONFIG_PCI_66M | |
991425fe MB |
31 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
32 | #else | |
33 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
34 | #endif | |
35 | ||
447ad576 IS |
36 | #ifdef CONFIG_PCISLAVE |
37 | #define CONFIG_PCI | |
38 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ | |
39 | #endif /* CONFIG_PCISLAVE */ | |
40 | ||
991425fe | 41 | #ifndef CONFIG_SYS_CLK_FREQ |
2ae18241 | 42 | #ifdef CONFIG_PCI_66M |
991425fe | 43 | #define CONFIG_SYS_CLK_FREQ 66000000 |
8fe9bf61 | 44 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
45 | #else |
46 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 47 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
48 | #endif |
49 | #endif | |
50 | ||
51 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
52 | ||
6d0f6bcf | 53 | #define CONFIG_SYS_IMMR 0xE0000000 |
991425fe | 54 | |
32795eca | 55 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
57 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
991425fe MB |
58 | |
59 | /* | |
60 | * DDR Setup | |
61 | */ | |
8d172c0f | 62 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 63 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
64 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
65 | ||
d4b91066 | 66 | /* |
5614e71b | 67 | * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver |
d4b91066 YS |
68 | * undefine it to use old spd_sdram.c |
69 | */ | |
5614e71b YS |
70 | #define CONFIG_SYS_FSL_DDR2 |
71 | #ifdef CONFIG_SYS_FSL_DDR2 | |
1df99080 | 72 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
d4b91066 YS |
73 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
74 | #define SPD_EEPROM_ADDRESS1 0x52 | |
75 | #define SPD_EEPROM_ADDRESS2 0x51 | |
76 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
77 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
78 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
79 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
80 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
81 | #endif | |
82 | ||
dc9e499c RJ |
83 | /* |
84 | * 32-bit data path mode. | |
cf48eb9a | 85 | * |
dc9e499c RJ |
86 | * Please note that using this mode for devices with the real density of 64-bit |
87 | * effectively reduces the amount of available memory due to the effect of | |
88 | * wrapping around while translating address to row/columns, for example in the | |
89 | * 256MB module the upper 128MB get aliased with contents of the lower | |
90 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 91 | * data path. |
dc9e499c RJ |
92 | */ |
93 | #undef CONFIG_DDR_32BIT | |
94 | ||
32795eca JH |
95 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
96 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 97 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
32795eca JH |
98 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
99 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
991425fe MB |
100 | #undef CONFIG_DDR_2T_TIMING |
101 | ||
8d172c0f XX |
102 | /* |
103 | * DDRCDR - DDR Control Driver Register | |
104 | */ | |
6d0f6bcf | 105 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
8d172c0f | 106 | |
991425fe | 107 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
108 | /* |
109 | * Determine DDR configuration from I2C interface. | |
110 | */ | |
111 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 112 | #else |
dc9e499c RJ |
113 | /* |
114 | * Manually set up DDR parameters | |
115 | */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
8d172c0f | 117 | #if defined(CONFIG_DDR_II) |
6d0f6bcf | 118 | #define CONFIG_SYS_DDRCDR 0x80080001 |
32795eca | 119 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
6d0f6bcf | 120 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
32795eca JH |
121 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
122 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
123 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
124 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
125 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
127 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
32795eca | 128 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
130 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
8d172c0f | 131 | #else |
2e651b24 | 132 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
32795eca JH |
133 | | CSCONFIG_ROW_BIT_13 \ |
134 | | CSCONFIG_COL_BIT_10) | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
136 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
32795eca | 137 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
6d0f6bcf | 138 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
dc9e499c RJ |
139 | |
140 | #if defined(CONFIG_DDR_32BIT) | |
141 | /* set burst length to 8 for 32-bit data path */ | |
32795eca JH |
142 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
143 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
dc9e499c RJ |
144 | #else |
145 | /* the default burst length is 4 - for 64-bit data path */ | |
32795eca JH |
146 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
147 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
dc9e499c | 148 | #endif |
991425fe | 149 | #endif |
8d172c0f | 150 | #endif |
991425fe MB |
151 | |
152 | /* | |
153 | * SDRAM on the Local Bus | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
156 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
991425fe MB |
157 | |
158 | /* | |
159 | * FLASH on the Local Bus | |
160 | */ | |
32795eca JH |
161 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
162 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
32795eca JH |
164 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
165 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
6d0f6bcf | 166 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
991425fe | 167 | |
7d6a0982 JH |
168 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
169 | | BR_PS_16 /* 16 bit port */ \ | |
170 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
171 | | BR_V) /* valid */ | |
172 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
32795eca JH |
173 | | OR_UPM_XAM \ |
174 | | OR_GPCM_CSNT \ | |
175 | | OR_GPCM_ACS_DIV2 \ | |
176 | | OR_GPCM_XACS \ | |
177 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
178 | | OR_GPCM_TRLX_SET \ |
179 | | OR_GPCM_EHTR_SET \ | |
32795eca | 180 | | OR_GPCM_EAD) |
7d6a0982 | 181 | |
32795eca JH |
182 | /* window base at flash base */ |
183 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 184 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
991425fe | 185 | |
32795eca JH |
186 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
187 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
991425fe | 188 | |
6d0f6bcf JCPV |
189 | #undef CONFIG_SYS_FLASH_CHECKSUM |
190 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
191 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
991425fe | 192 | |
14d0a02a | 193 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
991425fe | 194 | |
6d0f6bcf JCPV |
195 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
196 | #define CONFIG_SYS_RAMBOOT | |
991425fe | 197 | #else |
6d0f6bcf | 198 | #undef CONFIG_SYS_RAMBOOT |
991425fe MB |
199 | #endif |
200 | ||
201 | /* | |
202 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
203 | */ | |
32795eca JH |
204 | #define CONFIG_SYS_BCSR 0xE2400000 |
205 | /* Access window base at BCSR base */ | |
206 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
207 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
208 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
209 | | BR_PS_8 \ | |
210 | | BR_MS_GPCM \ | |
211 | | BR_V) | |
212 | /* 0x00000801 */ | |
213 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
214 | | OR_GPCM_XAM \ | |
215 | | OR_GPCM_CSNT \ | |
216 | | OR_GPCM_SCY_15 \ | |
217 | | OR_GPCM_TRLX_CLEAR \ | |
218 | | OR_GPCM_EHTR_CLEAR) | |
219 | /* 0xFFFFE8F0 */ | |
991425fe | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
32795eca JH |
222 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
223 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
991425fe | 224 | |
32795eca JH |
225 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
226 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 227 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
991425fe | 228 | |
32795eca | 229 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 230 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
991425fe MB |
231 | |
232 | /* | |
233 | * Local Bus LCRR and LBCR regs | |
234 | * LCRR: DLL bypass, Clock divider is 4 | |
235 | * External Local Bus rate is | |
236 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
237 | */ | |
32795eca JH |
238 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
239 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 240 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
991425fe | 241 | |
8d172c0f XX |
242 | /* |
243 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
6d0f6bcf | 244 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
8d172c0f | 245 | */ |
6d0f6bcf | 246 | #undef CONFIG_SYS_LB_SDRAM |
991425fe | 247 | |
6d0f6bcf | 248 | #ifdef CONFIG_SYS_LB_SDRAM |
991425fe MB |
249 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
250 | /* | |
251 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 252 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
991425fe MB |
253 | * |
254 | * For BR2, need: | |
255 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
256 | * port-size = 32-bits = BR2[19:20] = 11 | |
257 | * no parity checking = BR2[21:22] = 00 | |
258 | * SDRAM for MSEL = BR2[24:26] = 011 | |
259 | * Valid = BR[31] = 1 | |
260 | * | |
261 | * 0 4 8 12 16 20 24 28 | |
262 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
991425fe MB |
263 | */ |
264 | ||
7d6a0982 JH |
265 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
266 | | BR_PS_32 /* 32-bit port */ \ | |
267 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
268 | | BR_V) /* Valid */ | |
269 | /* 0xF0001861 */ | |
270 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
271 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
991425fe MB |
272 | |
273 | /* | |
6d0f6bcf | 274 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
991425fe MB |
275 | * |
276 | * For OR2, need: | |
277 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
278 | * XAM, OR2[17:18] = 11 | |
279 | * 9 columns OR2[19-21] = 010 | |
280 | * 13 rows OR2[23-25] = 100 | |
281 | * EAD set for extra time OR[31] = 1 | |
282 | * | |
283 | * 0 4 8 12 16 20 24 28 | |
284 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
285 | */ | |
286 | ||
7d6a0982 JH |
287 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
288 | | OR_SDRAM_XAM \ | |
289 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
290 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
291 | | OR_SDRAM_EAD) | |
292 | /* 0xFC006901 */ | |
991425fe | 293 | |
32795eca JH |
294 | /* LB sdram refresh timer, about 6us */ |
295 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
296 | /* LB refresh timer prescal, 266MHz/32 */ | |
297 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
991425fe | 298 | |
32795eca | 299 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
540dcf1c KG |
300 | | LSDMR_BSMA1516 \ |
301 | | LSDMR_RFCR8 \ | |
302 | | LSDMR_PRETOACT6 \ | |
303 | | LSDMR_ACTTORW3 \ | |
304 | | LSDMR_BL8 \ | |
305 | | LSDMR_WRC3 \ | |
32795eca | 306 | | LSDMR_CL3) |
991425fe MB |
307 | |
308 | /* | |
309 | * SDRAM Controller configuration sequence. | |
310 | */ | |
540dcf1c KG |
311 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
312 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
313 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
314 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
315 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
991425fe MB |
316 | #endif |
317 | ||
318 | /* | |
319 | * Serial Port | |
320 | */ | |
321 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_NS16550 |
323 | #define CONFIG_SYS_NS16550_SERIAL | |
324 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
325 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
991425fe | 326 | |
6d0f6bcf | 327 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
32795eca | 328 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
991425fe | 329 | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
331 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
991425fe | 332 | |
22d71a71 | 333 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 334 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
991425fe | 335 | /* Use the HUSH parser */ |
6d0f6bcf | 336 | #define CONFIG_SYS_HUSH_PARSER |
991425fe | 337 | |
bf0b542d | 338 | /* pass open firmware flat tree */ |
35cc4e48 | 339 | #define CONFIG_OF_LIBFDT 1 |
bf0b542d | 340 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 341 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
bf0b542d | 342 | |
991425fe | 343 | /* I2C */ |
00f792e0 HS |
344 | #define CONFIG_SYS_I2C |
345 | #define CONFIG_SYS_I2C_FSL | |
346 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
347 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
348 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
349 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
350 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
351 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
352 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
991425fe | 353 | |
80ddd226 | 354 | /* SPI */ |
8931ab17 | 355 | #define CONFIG_MPC8XXX_SPI |
80ddd226 | 356 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
80ddd226 BW |
357 | |
358 | /* GPIOs. Used as SPI chip selects */ | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_GPIO1_PRELIM |
360 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
361 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
80ddd226 | 362 | |
991425fe | 363 | /* TSEC */ |
6d0f6bcf | 364 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
32795eca | 365 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 366 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
32795eca | 367 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
991425fe | 368 | |
8fe9bf61 | 369 | /* USB */ |
6d0f6bcf | 370 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
991425fe MB |
371 | |
372 | /* | |
373 | * General PCI | |
374 | * Addresses are mapped 1-1. | |
375 | */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
377 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
378 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
379 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
380 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
381 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
382 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
383 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
384 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
6d0f6bcf JCPV |
385 | |
386 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
387 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
388 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
389 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
390 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
391 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
392 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
393 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
394 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
395 | |
396 | #if defined(CONFIG_PCI) | |
397 | ||
8fe9bf61 | 398 | #define PCI_ONE_PCI1 |
991425fe MB |
399 | #if defined(PCI_64BIT) |
400 | #undef PCI_ALL_PCI1 | |
401 | #undef PCI_TWO_PCI1 | |
402 | #undef PCI_ONE_PCI1 | |
403 | #endif | |
404 | ||
991425fe | 405 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
162338e1 | 406 | #define CONFIG_83XX_PCI_STREAMING |
991425fe MB |
407 | |
408 | #undef CONFIG_EEPRO100 | |
409 | #undef CONFIG_TULIP | |
410 | ||
411 | #if !defined(CONFIG_PCI_PNP) | |
412 | #define PCI_ENET0_IOADDR 0xFIXME | |
413 | #define PCI_ENET0_MEMADDR 0xFIXME | |
53677ef1 | 414 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
991425fe MB |
415 | #endif |
416 | ||
417 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 418 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
991425fe MB |
419 | |
420 | #endif /* CONFIG_PCI */ | |
421 | ||
422 | /* | |
423 | * TSEC configuration | |
424 | */ | |
32795eca | 425 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
991425fe MB |
426 | |
427 | #if defined(CONFIG_TSEC_ENET) | |
991425fe MB |
428 | |
429 | #define CONFIG_GMII 1 /* MII PHY management */ | |
32795eca | 430 | #define CONFIG_TSEC1 1 |
255a3577 | 431 | #define CONFIG_TSEC1_NAME "TSEC0" |
32795eca | 432 | #define CONFIG_TSEC2 1 |
255a3577 | 433 | #define CONFIG_TSEC2_NAME "TSEC1" |
991425fe MB |
434 | #define TSEC1_PHY_ADDR 0 |
435 | #define TSEC2_PHY_ADDR 1 | |
436 | #define TSEC1_PHYIDX 0 | |
437 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
438 | #define TSEC1_FLAGS TSEC_GIGABIT |
439 | #define TSEC2_FLAGS TSEC_GIGABIT | |
991425fe MB |
440 | |
441 | /* Options are: TSEC[0-1] */ | |
442 | #define CONFIG_ETHPRIME "TSEC0" | |
443 | ||
444 | #endif /* CONFIG_TSEC_ENET */ | |
445 | ||
446 | /* | |
447 | * Configure on-board RTC | |
448 | */ | |
32795eca JH |
449 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
450 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
991425fe MB |
451 | |
452 | /* | |
453 | * Environment | |
454 | */ | |
6d0f6bcf | 455 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 456 | #define CONFIG_ENV_IS_IN_FLASH 1 |
32795eca JH |
457 | #define CONFIG_ENV_ADDR \ |
458 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
459 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
460 | #define CONFIG_ENV_SIZE 0x2000 | |
991425fe MB |
461 | |
462 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
463 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
464 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
991425fe MB |
465 | |
466 | #else | |
32795eca | 467 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 468 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 469 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 470 | #define CONFIG_ENV_SIZE 0x2000 |
991425fe MB |
471 | #endif |
472 | ||
473 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 474 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
991425fe | 475 | |
8ea5499a | 476 | |
659e2f67 JL |
477 | /* |
478 | * BOOTP options | |
479 | */ | |
480 | #define CONFIG_BOOTP_BOOTFILESIZE | |
481 | #define CONFIG_BOOTP_BOOTPATH | |
482 | #define CONFIG_BOOTP_GATEWAY | |
483 | #define CONFIG_BOOTP_HOSTNAME | |
484 | ||
485 | ||
8ea5499a JL |
486 | /* |
487 | * Command line configuration. | |
488 | */ | |
8ea5499a JL |
489 | #define CONFIG_CMD_PING |
490 | #define CONFIG_CMD_I2C | |
491 | #define CONFIG_CMD_DATE | |
492 | #define CONFIG_CMD_MII | |
493 | ||
991425fe | 494 | #if defined(CONFIG_PCI) |
8ea5499a | 495 | #define CONFIG_CMD_PCI |
991425fe | 496 | #endif |
8ea5499a | 497 | |
991425fe MB |
498 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
499 | ||
500 | /* | |
501 | * Miscellaneous configurable options | |
502 | */ | |
6d0f6bcf JCPV |
503 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
504 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
991425fe | 505 | |
8ea5499a | 506 | #if defined(CONFIG_CMD_KGDB) |
32795eca | 507 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
991425fe | 508 | #else |
32795eca | 509 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
991425fe MB |
510 | #endif |
511 | ||
32795eca JH |
512 | /* Print Buffer Size */ |
513 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
514 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
515 | /* Boot Argument Buffer Size */ | |
516 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
991425fe MB |
517 | |
518 | /* | |
519 | * For booting Linux, the board info and command line data | |
9f530d59 | 520 | * have to be in the first 256 MB of memory, since this is |
991425fe MB |
521 | * the maximum mapped by the Linux kernel during initialization. |
522 | */ | |
32795eca JH |
523 | /* Initial Memory map for Linux*/ |
524 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
991425fe | 525 | |
6d0f6bcf | 526 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
991425fe MB |
527 | |
528 | #if 1 /*528/264*/ | |
6d0f6bcf | 529 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
530 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
531 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 532 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
533 | HRCWL_VCO_1X2 |\ |
534 | HRCWL_CORE_TO_CSB_2X1) | |
535 | #elif 0 /*396/132*/ | |
6d0f6bcf | 536 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
537 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
538 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 539 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
540 | HRCWL_VCO_1X4 |\ |
541 | HRCWL_CORE_TO_CSB_3X1) | |
542 | #elif 0 /*264/132*/ | |
6d0f6bcf | 543 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
544 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
545 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 546 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
547 | HRCWL_VCO_1X4 |\ |
548 | HRCWL_CORE_TO_CSB_2X1) | |
549 | #elif 0 /*132/132*/ | |
6d0f6bcf | 550 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
551 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
552 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 553 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
554 | HRCWL_VCO_1X4 |\ |
555 | HRCWL_CORE_TO_CSB_1X1) | |
556 | #elif 0 /*264/264 */ | |
6d0f6bcf | 557 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
558 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
559 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 560 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
561 | HRCWL_VCO_1X4 |\ |
562 | HRCWL_CORE_TO_CSB_1X1) | |
563 | #endif | |
564 | ||
447ad576 | 565 | #ifdef CONFIG_PCISLAVE |
6d0f6bcf | 566 | #define CONFIG_SYS_HRCW_HIGH (\ |
447ad576 IS |
567 | HRCWH_PCI_AGENT |\ |
568 | HRCWH_64_BIT_PCI |\ | |
569 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
570 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
571 | HRCWH_CORE_ENABLE |\ | |
572 | HRCWH_FROM_0X00000100 |\ | |
573 | HRCWH_BOOTSEQ_DISABLE |\ | |
574 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
575 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
576 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 577 | HRCWH_TSEC2M_IN_GMII) |
447ad576 | 578 | #else |
991425fe | 579 | #if defined(PCI_64BIT) |
6d0f6bcf | 580 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
581 | HRCWH_PCI_HOST |\ |
582 | HRCWH_64_BIT_PCI |\ | |
583 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
584 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
585 | HRCWH_CORE_ENABLE |\ | |
586 | HRCWH_FROM_0X00000100 |\ | |
587 | HRCWH_BOOTSEQ_DISABLE |\ | |
588 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
589 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
590 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 591 | HRCWH_TSEC2M_IN_GMII) |
991425fe | 592 | #else |
6d0f6bcf | 593 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
594 | HRCWH_PCI_HOST |\ |
595 | HRCWH_32_BIT_PCI |\ | |
596 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
597 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
598 | HRCWH_CORE_ENABLE |\ | |
599 | HRCWH_FROM_0X00000100 |\ | |
600 | HRCWH_BOOTSEQ_DISABLE |\ | |
601 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
602 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
603 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 604 | HRCWH_TSEC2M_IN_GMII) |
447ad576 IS |
605 | #endif /* PCI_64BIT */ |
606 | #endif /* CONFIG_PCISLAVE */ | |
991425fe | 607 | |
a5fe514e LN |
608 | /* |
609 | * System performance | |
610 | */ | |
6d0f6bcf | 611 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
32795eca | 612 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
613 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
614 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
615 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
616 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
a5fe514e | 617 | |
991425fe | 618 | /* System IO Config */ |
3c9b1ee1 | 619 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 620 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
991425fe | 621 | |
6d0f6bcf | 622 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
32795eca JH |
623 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
624 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
991425fe | 625 | |
32795eca | 626 | /* #define CONFIG_SYS_HID0_FINAL (\ |
991425fe MB |
627 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
628 | HID0_ENABLE_M_BIT |\ | |
32795eca | 629 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
991425fe MB |
630 | |
631 | ||
6d0f6bcf | 632 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 633 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
991425fe MB |
634 | |
635 | /* DDR @ 0x00000000 */ | |
32795eca | 636 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 637 | | BATL_PP_RW \ |
32795eca JH |
638 | | BATL_MEMCOHERENCE) |
639 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
640 | | BATU_BL_256M \ | |
641 | | BATU_VS \ | |
642 | | BATU_VP) | |
991425fe MB |
643 | |
644 | /* PCI @ 0x80000000 */ | |
645 | #ifdef CONFIG_PCI | |
842033e6 | 646 | #define CONFIG_PCI_INDIRECT_BRIDGE |
32795eca | 647 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 648 | | BATL_PP_RW \ |
32795eca JH |
649 | | BATL_MEMCOHERENCE) |
650 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
651 | | BATU_BL_256M \ | |
652 | | BATU_VS \ | |
653 | | BATU_VP) | |
654 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 655 | | BATL_PP_RW \ |
32795eca JH |
656 | | BATL_CACHEINHIBIT \ |
657 | | BATL_GUARDEDSTORAGE) | |
658 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
659 | | BATU_BL_256M \ | |
660 | | BATU_VS \ | |
661 | | BATU_VP) | |
991425fe | 662 | #else |
6d0f6bcf JCPV |
663 | #define CONFIG_SYS_IBAT1L (0) |
664 | #define CONFIG_SYS_IBAT1U (0) | |
665 | #define CONFIG_SYS_IBAT2L (0) | |
666 | #define CONFIG_SYS_IBAT2U (0) | |
991425fe MB |
667 | #endif |
668 | ||
8fe9bf61 | 669 | #ifdef CONFIG_MPC83XX_PCI2 |
32795eca | 670 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 671 | | BATL_PP_RW \ |
32795eca JH |
672 | | BATL_MEMCOHERENCE) |
673 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
674 | | BATU_BL_256M \ | |
675 | | BATU_VS \ | |
676 | | BATU_VP) | |
677 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 678 | | BATL_PP_RW \ |
32795eca JH |
679 | | BATL_CACHEINHIBIT \ |
680 | | BATL_GUARDEDSTORAGE) | |
681 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
682 | | BATU_BL_256M \ | |
683 | | BATU_VS \ | |
684 | | BATU_VP) | |
8fe9bf61 | 685 | #else |
6d0f6bcf JCPV |
686 | #define CONFIG_SYS_IBAT3L (0) |
687 | #define CONFIG_SYS_IBAT3U (0) | |
688 | #define CONFIG_SYS_IBAT4L (0) | |
689 | #define CONFIG_SYS_IBAT4U (0) | |
8fe9bf61 | 690 | #endif |
991425fe | 691 | |
8fe9bf61 | 692 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
32795eca | 693 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 694 | | BATL_PP_RW \ |
32795eca JH |
695 | | BATL_CACHEINHIBIT \ |
696 | | BATL_GUARDEDSTORAGE) | |
697 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
698 | | BATU_BL_256M \ | |
699 | | BATU_VS \ | |
700 | | BATU_VP) | |
991425fe | 701 | |
8fe9bf61 | 702 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
32795eca | 703 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 JH |
704 | | BATL_PP_RW \ |
705 | | BATL_MEMCOHERENCE \ | |
706 | | BATL_GUARDEDSTORAGE) | |
32795eca JH |
707 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
708 | | BATU_BL_256M \ | |
709 | | BATU_VS \ | |
710 | | BATU_VP) | |
6d0f6bcf JCPV |
711 | |
712 | #define CONFIG_SYS_IBAT7L (0) | |
713 | #define CONFIG_SYS_IBAT7U (0) | |
714 | ||
715 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
716 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
717 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
718 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
719 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
720 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
721 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
722 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
723 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
724 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
725 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
726 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
727 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
728 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
729 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
730 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
991425fe | 731 | |
8ea5499a | 732 | #if defined(CONFIG_CMD_KGDB) |
991425fe | 733 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
991425fe MB |
734 | #endif |
735 | ||
736 | /* | |
737 | * Environment Configuration | |
738 | */ | |
739 | #define CONFIG_ENV_OVERWRITE | |
740 | ||
741 | #if defined(CONFIG_TSEC_ENET) | |
991425fe | 742 | #define CONFIG_HAS_ETH1 |
10327dc5 | 743 | #define CONFIG_HAS_ETH0 |
991425fe MB |
744 | #endif |
745 | ||
991425fe | 746 | #define CONFIG_HOSTNAME mpc8349emds |
8b3637c6 | 747 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 748 | #define CONFIG_BOOTFILE "uImage" |
991425fe | 749 | |
32795eca | 750 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
991425fe MB |
751 | |
752 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
32795eca | 753 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
991425fe MB |
754 | |
755 | #define CONFIG_BAUDRATE 115200 | |
756 | ||
757 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 758 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
991425fe MB |
759 | "echo" |
760 | ||
761 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
762 | "netdev=eth0\0" \ | |
763 | "hostname=mpc8349emds\0" \ | |
764 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
765 | "nfsroot=${serverip}:${rootpath}\0" \ | |
766 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
767 | "addip=setenv bootargs ${bootargs} " \ | |
768 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
769 | ":${hostname}:${netdev}:off panic=1\0" \ | |
770 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
771 | "flash_nfs=run nfsargs addip addtty;" \ | |
772 | "bootm ${kernel_addr}\0" \ | |
773 | "flash_self=run ramargs addip addtty;" \ | |
774 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
775 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
776 | "bootm\0" \ | |
991425fe MB |
777 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
778 | "update=protect off fe000000 fe03ffff; " \ | |
32795eca | 779 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
d8ab58b2 | 780 | "upd=run load update\0" \ |
79f516bc | 781 | "fdtaddr=780000\0" \ |
cc861f71 | 782 | "fdtfile=mpc834x_mds.dtb\0" \ |
991425fe MB |
783 | "" |
784 | ||
32795eca JH |
785 | #define CONFIG_NFSBOOTCOMMAND \ |
786 | "setenv bootargs root=/dev/nfs rw " \ | |
787 | "nfsroot=$serverip:$rootpath " \ | |
788 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
789 | "$netdev:off " \ | |
790 | "console=$consoledev,$baudrate $othbootargs;" \ | |
791 | "tftp $loadaddr $bootfile;" \ | |
792 | "tftp $fdtaddr $fdtfile;" \ | |
793 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d KP |
794 | |
795 | #define CONFIG_RAMBOOTCOMMAND \ | |
32795eca JH |
796 | "setenv bootargs root=/dev/ram rw " \ |
797 | "console=$consoledev,$baudrate $othbootargs;" \ | |
798 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
799 | "tftp $loadaddr $bootfile;" \ | |
800 | "tftp $fdtaddr $fdtfile;" \ | |
801 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
bf0b542d | 802 | |
991425fe MB |
803 | #define CONFIG_BOOTCOMMAND "run flash_self" |
804 | ||
805 | #endif /* __CONFIG_H */ |