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Commit | Line | Data |
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d4ca31c4 | 1 | /* |
23c5d253 | 2 | * (C) Copyright 2000-2014 |
d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d4ca31c4 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
21 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
24 | ||
66ca92a5 | 25 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
6d0f6bcf JCPV |
26 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
27 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
66ca92a5 | 28 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ |
c178d3da WD |
29 | /* (it will be used if there is no */ |
30 | /* 'cpuclk' variable with valid value) */ | |
d4ca31c4 | 31 | |
6d0f6bcf | 32 | #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ |
75d1ea7f WD |
33 | /* (function measure_gclk() */ |
34 | /* will be called) */ | |
6d0f6bcf JCPV |
35 | #ifdef CONFIG_SYS_MEASURE_CPUCLK |
36 | #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
75d1ea7f WD |
37 | #endif |
38 | ||
c178d3da | 39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
40 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
41 | #define CONFIG_SYS_MAXIDLE 10 | |
d4ca31c4 | 42 | |
c178d3da | 43 | #define CONFIG_BOOTCOUNT_LIMIT |
d4ca31c4 | 44 | |
d4ca31c4 WD |
45 | |
46 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
47 | ||
c178d3da | 48 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 49 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d4ca31c4 WD |
50 | "echo" |
51 | ||
52 | #undef CONFIG_BOOTARGS | |
53 | ||
c178d3da | 54 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
d4ca31c4 WD |
55 | "netdev=eth0\0" \ |
56 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 57 | "nfsroot=${serverip}:${rootpath}\0" \ |
d4ca31c4 | 58 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
59 | "addip=setenv bootargs ${bootargs} " \ |
60 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
61 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d4ca31c4 | 62 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 63 | "bootm ${kernel_addr}\0" \ |
d4ca31c4 | 64 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
65 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
66 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d4ca31c4 | 67 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
68 | "hostname=TQM866M\0" \ |
69 | "bootfile=TQM866M/uImage\0" \ | |
9ef57bbe MK |
70 | "fdt_addr=400C0000\0" \ |
71 | "kernel_addr=40100000\0" \ | |
eb6da805 | 72 | "ramdisk_addr=40280000\0" \ |
29f8f58f | 73 | "u-boot=TQM866M/u-image.bin\0" \ |
9ef57bbe | 74 | "load=tftp 200000 ${u-boot}\0" \ |
29f8f58f WD |
75 | "update=prot off 40000000 +${filesize};" \ |
76 | "era 40000000 +${filesize};" \ | |
9ef57bbe | 77 | "cp.b 200000 40000000 ${filesize};" \ |
29f8f58f | 78 | "sete filesize;save\0" \ |
d4ca31c4 WD |
79 | "" |
80 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
81 | ||
82 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 83 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
d4ca31c4 WD |
84 | |
85 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
86 | ||
d4ca31c4 WD |
87 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
88 | ||
89 | /* enable I2C and select the hardware/software driver */ | |
ea818dbb HS |
90 | #define CONFIG_SYS_I2C |
91 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
92 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
93 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
d4ca31c4 | 94 | |
d4ca31c4 WD |
95 | /* |
96 | * Software (bit-bang) I2C driver configuration | |
97 | */ | |
98 | #define PB_SCL 0x00000020 /* PB 26 */ | |
99 | #define PB_SDA 0x00000010 /* PB 27 */ | |
100 | ||
101 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
102 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
103 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
104 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
105 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
c178d3da | 106 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
d4ca31c4 | 107 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
c178d3da | 108 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
d4ca31c4 | 109 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
d4ca31c4 | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ |
112 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
114 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
d4ca31c4 | 115 | |
37d4bb70 JL |
116 | /* |
117 | * BOOTP options | |
118 | */ | |
119 | #define CONFIG_BOOTP_SUBNETMASK | |
120 | #define CONFIG_BOOTP_GATEWAY | |
121 | #define CONFIG_BOOTP_HOSTNAME | |
122 | #define CONFIG_BOOTP_BOOTPATH | |
123 | #define CONFIG_BOOTP_BOOTFILESIZE | |
124 | ||
a6cccaea WD |
125 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
126 | ||
127 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
d4ca31c4 | 128 | |
2694690e JL |
129 | /* |
130 | * Command line configuration. | |
131 | */ | |
29f8f58f WD |
132 | |
133 | #define CONFIG_NETCONSOLE | |
2694690e | 134 | |
d4ca31c4 WD |
135 | /* |
136 | * Miscellaneous configurable options | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d4ca31c4 | 139 | |
2751a95a | 140 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
d4ca31c4 | 141 | |
2694690e | 142 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 143 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4ca31c4 | 144 | #else |
6d0f6bcf | 145 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d4ca31c4 | 146 | #endif |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d4ca31c4 | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
152 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d4ca31c4 | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
d4ca31c4 | 155 | |
d4ca31c4 WD |
156 | /* |
157 | * Low Level Configuration Settings | |
158 | * (address mappings, register initial values, etc.) | |
159 | * You should know what you are doing if you make changes here. | |
160 | */ | |
161 | /*----------------------------------------------------------------------- | |
162 | * Internal Memory Mapped Register | |
163 | */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_IMMR 0xFFF00000 |
d4ca31c4 WD |
165 | |
166 | /*----------------------------------------------------------------------- | |
167 | * Definitions for initial stack pointer and data area (in DPRAM) | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 170 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 171 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d4ca31c4 WD |
173 | |
174 | /*----------------------------------------------------------------------- | |
175 | * Start addresses for the final memory configuration | |
176 | * (Set up by the startup code) | |
6d0f6bcf | 177 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d4ca31c4 | 178 | */ |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
180 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
181 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
182 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
183 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
d4ca31c4 WD |
184 | |
185 | /* | |
186 | * For booting Linux, the board info and command line data | |
187 | * have to be in the first 8 MB of memory, since this is | |
188 | * the maximum mapped by the Linux kernel during initialization. | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d4ca31c4 WD |
191 | |
192 | /*----------------------------------------------------------------------- | |
193 | * FLASH organization | |
194 | */ | |
e318d9e9 | 195 | /* use CFI flash driver */ |
6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 197 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
199 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
200 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
202 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
d4ca31c4 | 203 | |
5a1aceb0 | 204 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
205 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
206 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
207 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
d4ca31c4 WD |
208 | |
209 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
210 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
211 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
d4ca31c4 | 212 | |
6d0f6bcf | 213 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 214 | |
7c803be2 WD |
215 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
216 | ||
29f8f58f WD |
217 | /*----------------------------------------------------------------------- |
218 | * Dynamic MTD partition support | |
219 | */ | |
68d7d651 | 220 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
221 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
222 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
223 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
224 | ||
225 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
226 | "128k(dtb)," \ | |
227 | "1920k(kernel)," \ | |
228 | "5632(rootfs)," \ | |
cd82919e | 229 | "4m(data)" |
29f8f58f | 230 | |
d4ca31c4 WD |
231 | /*----------------------------------------------------------------------- |
232 | * Hardware Information Block | |
233 | */ | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
235 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
236 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
d4ca31c4 WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * Cache Configuration | |
240 | */ | |
6d0f6bcf | 241 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 242 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 243 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
d4ca31c4 WD |
244 | #endif |
245 | ||
246 | /*----------------------------------------------------------------------- | |
247 | * SYPCR - System Protection Control 11-9 | |
248 | * SYPCR can only be written once after reset! | |
249 | *----------------------------------------------------------------------- | |
250 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
251 | */ | |
252 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 253 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
d4ca31c4 WD |
254 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
255 | #else | |
6d0f6bcf | 256 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
d4ca31c4 WD |
257 | #endif |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * SIUMCR - SIU Module Configuration 11-6 | |
261 | *----------------------------------------------------------------------- | |
262 | * PCMCIA config., multi-function pin tri-state | |
263 | */ | |
c178d3da | 264 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf | 265 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 | 266 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 267 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 WD |
268 | #endif /* CONFIG_CAN_DRIVER */ |
269 | ||
270 | /*----------------------------------------------------------------------- | |
271 | * TBSCR - Time Base Status and Control 11-26 | |
272 | *----------------------------------------------------------------------- | |
273 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
274 | */ | |
6d0f6bcf | 275 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
d4ca31c4 | 276 | |
d4ca31c4 WD |
277 | /*----------------------------------------------------------------------- |
278 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
279 | *----------------------------------------------------------------------- | |
280 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
281 | */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
d4ca31c4 | 283 | |
d4ca31c4 WD |
284 | /*----------------------------------------------------------------------- |
285 | * SCCR - System Clock and reset Control Register 15-27 | |
286 | *----------------------------------------------------------------------- | |
287 | * Set clock output, timebase and RTC source and divider, | |
288 | * power management and some other internal clocks | |
289 | */ | |
290 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 291 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d4ca31c4 WD |
292 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
293 | SCCR_DFALCD00) | |
d4ca31c4 WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * PCMCIA stuff | |
297 | *----------------------------------------------------------------------- | |
298 | * | |
299 | */ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
301 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
302 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
303 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
304 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
305 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
306 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
307 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
d4ca31c4 WD |
308 | |
309 | /*----------------------------------------------------------------------- | |
310 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
311 | *----------------------------------------------------------------------- | |
312 | */ | |
313 | ||
8d1165e1 | 314 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
c178d3da | 315 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
d4ca31c4 | 316 | |
c178d3da WD |
317 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
318 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
d4ca31c4 WD |
319 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
320 | ||
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
322 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
d4ca31c4 | 323 | |
6d0f6bcf | 324 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
d4ca31c4 | 325 | |
6d0f6bcf | 326 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
d4ca31c4 WD |
327 | |
328 | /* Offset for data I/O */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
330 | |
331 | /* Offset for normal register accesses */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
333 | |
334 | /* Offset for alternate registers */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
d4ca31c4 WD |
336 | |
337 | /*----------------------------------------------------------------------- | |
338 | * | |
339 | *----------------------------------------------------------------------- | |
340 | * | |
341 | */ | |
6d0f6bcf | 342 | #define CONFIG_SYS_DER 0 |
d4ca31c4 WD |
343 | |
344 | /* | |
345 | * Init Memory Controller: | |
346 | * | |
347 | * BR0/1 and OR0/1 (FLASH) | |
348 | */ | |
349 | ||
350 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
351 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
352 | ||
353 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
354 | * restrict access enough to keep SRAM working (if any) | |
355 | * but not too much to meddle with FLASH accesses | |
356 | */ | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
358 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
d4ca31c4 WD |
359 | |
360 | /* | |
c178d3da | 361 | * FLASH timing: Default value of OR0 after reset |
d4ca31c4 | 362 | */ |
6d0f6bcf | 363 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
c178d3da | 364 | OR_SCY_15_CLK | OR_TRLX) |
d4ca31c4 | 365 | |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
367 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
368 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 | 369 | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
371 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
372 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 WD |
373 | |
374 | /* | |
375 | * BR2/3 and OR2/3 (SDRAM) | |
376 | * | |
377 | */ | |
378 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
379 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
c178d3da | 380 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
d4ca31c4 WD |
381 | |
382 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
d4ca31c4 | 384 | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
386 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 387 | |
c178d3da | 388 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf JCPV |
389 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
390 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 391 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
393 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
394 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
395 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
d4ca31c4 WD |
396 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
397 | #endif /* CONFIG_CAN_DRIVER */ | |
398 | ||
c178d3da | 399 | /* |
c178d3da WD |
400 | * 4096 Rows from SDRAM example configuration |
401 | * 1000 factor s -> ms | |
402 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
403 | * 4 Number of refresh cycles per period | |
404 | * 64 Refresh cycle in ms per number of rows | |
405 | */ | |
6d0f6bcf | 406 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
c178d3da | 407 | |
d4ca31c4 | 408 | /* |
d43e489b MK |
409 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
410 | * | |
411 | * CPUclock(MHz) * 31.2 | |
6d0f6bcf | 412 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
d43e489b MK |
413 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
414 | * | |
6d0f6bcf JCPV |
415 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
416 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
417 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
418 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
d43e489b MK |
419 | * |
420 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
421 | * be met also in the default configuration, i.e. if environment variable | |
422 | * 'cpuclk' is not set. | |
d4ca31c4 | 423 | */ |
6d0f6bcf | 424 | #define CONFIG_SYS_MAMR_PTA 97 |
d4ca31c4 WD |
425 | |
426 | /* | |
d43e489b | 427 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
d4ca31c4 | 428 | */ |
d43e489b | 429 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 430 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
d43e489b | 431 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 432 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
d4ca31c4 WD |
433 | |
434 | /* | |
435 | * MAMR settings for SDRAM | |
436 | */ | |
437 | ||
438 | /* 8 column SDRAM */ | |
6d0f6bcf | 439 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
440 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
441 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
442 | /* 9 column SDRAM */ | |
6d0f6bcf | 443 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
444 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
445 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
c178d3da | 446 | /* 10 column SDRAM */ |
6d0f6bcf | 447 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
c178d3da WD |
448 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
449 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
d4ca31c4 | 450 | |
d4ca31c4 WD |
451 | #define CONFIG_SCC1_ENET |
452 | #define CONFIG_FEC_ENET | |
48690d80 | 453 | #define CONFIG_ETHPRIME "SCC" |
d4ca31c4 | 454 | |
7026ead0 HS |
455 | #define CONFIG_HWCONFIG 1 |
456 | ||
d4ca31c4 | 457 | #endif /* __CONFIG_H */ |