[people/ms/u-boot.git] / include / configs / TQM866M.h

/*
 * (C) Copyright 2000-2014
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
#define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
#define CONFIG_8xx_CPUCLK_DEFAULT	50000000	/*  50 MHz - CPU default clock	*/
						/* (it will be used if there is no	*/
						/* 'cpuclk' variable with valid value)	*/

#undef CONFIG_SYS_MEASURE_CPUCLK			/* Measure real cpu clock	*/
						/* (function measure_gclk()	*/
						/* will be called)		*/
#ifdef CONFIG_SYS_MEASURE_CPUCLK
#define CONFIG_SYS_8XX_XIN		10000000	/* measure_gclk() needs this	*/
#endif

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT


#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"hostname=TQM866M\0"						\
	"bootfile=TQM866M/uImage\0"					\
	"fdt_addr=400C0000\0"						\
	"kernel_addr=40100000\0"					\
	"ramdisk_addr=40280000\0"					\
	"u-boot=TQM866M/u-image.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=prot off 40000000 +${filesize};"			\
		"era 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"sete filesize;save\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_DOS_PARTITION

#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/

/*
 * Command line configuration.
 */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2

#define CONFIG_NETCONSOLE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"

#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
						"128k(dtb),"		\
						"1920k(kernel),"	\
						"5632(rootfs),"		\
						"4m(data)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
				 OR_SCY_15_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/*
 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 *
 *                        CPUclock(MHz) * 31.2
 * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 *
 * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 *
 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 * be met also in the default configuration, i.e. if environment variable
 * 'cpuclk' is not set.
 */
#define CONFIG_SYS_MAMR_PTA		97

/*
 * Memory Periodic Timer Prescaler Register (MPTPR) values.
 */
/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME		"SCC"

#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
d4ca31c4	1	/*
23c5d253	2	* (C) Copyright 2000-2014
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
d4ca31c4 WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
d4ca31c4 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
	21	#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	24
66ca92a5	25	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
6d0f6bcf JCPV	26	#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
6d0f6bcf JCPV	27	#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
66ca92a5	28	#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
c178d3da WD	29	/* (it will be used if there is no */
c178d3da WD	30	/* 'cpuclk' variable with valid value) */
d4ca31c4	31
6d0f6bcf	32	#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
75d1ea7f WD	33	/* (function measure_gclk() */
75d1ea7f WD	34	/* will be called) */
6d0f6bcf JCPV	35	#ifdef CONFIG_SYS_MEASURE_CPUCLK
6d0f6bcf JCPV	36	#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
75d1ea7f WD	37	#endif
75d1ea7f WD	38
c178d3da	39	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
3cb7a480 WD	40	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	41	#define CONFIG_SYS_MAXIDLE 10
d4ca31c4 WD	42	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
d4ca31c4 WD	43
c178d3da	44	#define CONFIG_BOOTCOUNT_LIMIT
d4ca31c4	45
d4ca31c4 WD	46
	47	#define CONFIG_BOARD_TYPES 1 /* support board types */
	48
c178d3da	49	#define CONFIG_PREBOOT "echo;" \
32bf3d14	50	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
d4ca31c4 WD	51	"echo"
	52
	53	#undef CONFIG_BOOTARGS
	54
c178d3da	55	#define CONFIG_EXTRA_ENV_SETTINGS \
d4ca31c4 WD	56	"netdev=eth0\0" \
d4ca31c4 WD	57	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	58	"nfsroot=${serverip}:${rootpath}\0" \
d4ca31c4	59	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	60	"addip=setenv bootargs ${bootargs} " \
	61	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	62	":${hostname}:${netdev}:off panic=1\0" \
d4ca31c4	63	"flash_nfs=run nfsargs addip;" \
fe126d8b	64	"bootm ${kernel_addr}\0" \
d4ca31c4	65	"flash_self=run ramargs addip;" \
fe126d8b WD	66	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	67	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
d4ca31c4	68	"rootpath=/opt/eldk/ppc_8xx\0" \
29f8f58f WD	69	"hostname=TQM866M\0" \
29f8f58f WD	70	"bootfile=TQM866M/uImage\0" \
9ef57bbe MK	71	"fdt_addr=400C0000\0" \
9ef57bbe MK	72	"kernel_addr=40100000\0" \
eb6da805	73	"ramdisk_addr=40280000\0" \
29f8f58f	74	"u-boot=TQM866M/u-image.bin\0" \
9ef57bbe	75	"load=tftp 200000 ${u-boot}\0" \
29f8f58f WD	76	"update=prot off 40000000 +${filesize};" \
29f8f58f WD	77	"era 40000000 +${filesize};" \
9ef57bbe	78	"cp.b 200000 40000000 ${filesize};" \
29f8f58f	79	"sete filesize;save\0" \
d4ca31c4 WD	80	""
	81	#define CONFIG_BOOTCOMMAND "run flash_self"
	82
	83	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	84	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
d4ca31c4 WD	85
	86	#undef CONFIG_WATCHDOG /* watchdog disabled */
	87
d4ca31c4 WD	88	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	89
	90	/* enable I2C and select the hardware/software driver */
ea818dbb HS	91	#define CONFIG_SYS_I2C
	92	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	93	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	94	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
d4ca31c4	95
d4ca31c4 WD	96	/*
	97	* Software (bit-bang) I2C driver configuration
	98	*/
	99	#define PB_SCL 0x00000020 /* PB 26 */
	100	#define PB_SDA 0x00000010 /* PB 27 */
	101
	102	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	103	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	104	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	105	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	106	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
c178d3da	107	else immr->im_cpm.cp_pbdat &= ~PB_SDA
d4ca31c4	108	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
c178d3da	109	else immr->im_cpm.cp_pbdat &= ~PB_SCL
d4ca31c4	110	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
d4ca31c4	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
	113	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
	114	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	115	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
d4ca31c4	116
37d4bb70 JL	117	/*
	118	* BOOTP options
	119	*/
	120	#define CONFIG_BOOTP_SUBNETMASK
	121	#define CONFIG_BOOTP_GATEWAY
	122	#define CONFIG_BOOTP_HOSTNAME
	123	#define CONFIG_BOOTP_BOOTPATH
	124	#define CONFIG_BOOTP_BOOTFILESIZE
	125
d4ca31c4 WD	126	#define CONFIG_DOS_PARTITION
d4ca31c4 WD	127
a6cccaea WD	128	#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
	129
	130	#define CONFIG_TIMESTAMP /* but print image timestmps */
d4ca31c4	131
2694690e JL	132	/*
	133	* Command line configuration.
	134	*/
2694690e	135	#define CONFIG_CMD_EEPROM
2694690e	136	#define CONFIG_CMD_IDE
29f8f58f	137	#define CONFIG_CMD_JFFS2
29f8f58f WD	138
29f8f58f WD	139	#define CONFIG_NETCONSOLE
2694690e	140
d4ca31c4 WD	141	/*
	142	* Miscellaneous configurable options
	143	*/
6d0f6bcf	144	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d4ca31c4	145
2751a95a	146	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
d4ca31c4	147
2694690e	148	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	149	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
d4ca31c4	150	#else
6d0f6bcf	151	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
d4ca31c4	152	#endif
6d0f6bcf JCPV	153	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	154	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	155	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
d4ca31c4	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	158	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
d4ca31c4	159
6d0f6bcf	160	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
d4ca31c4	161
d4ca31c4 WD	162	/*
	163	* Low Level Configuration Settings
	164	* (address mappings, register initial values, etc.)
	165	* You should know what you are doing if you make changes here.
	166	*/
	167	/*-----------------------------------------------------------------------
	168	* Internal Memory Mapped Register
	169	*/
6d0f6bcf	170	#define CONFIG_SYS_IMMR 0xFFF00000
d4ca31c4 WD	171
	172	/*-----------------------------------------------------------------------
	173	* Definitions for initial stack pointer and data area (in DPRAM)
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	176	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	177	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	178	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d4ca31c4 WD	179
	180	/*-----------------------------------------------------------------------
	181	* Start addresses for the final memory configuration
	182	* (Set up by the startup code)
6d0f6bcf	183	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
d4ca31c4	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	186	#define CONFIG_SYS_FLASH_BASE 0x40000000
	187	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	188	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	189	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
d4ca31c4 WD	190
	191	/*
	192	* For booting Linux, the board info and command line data
	193	* have to be in the first 8 MB of memory, since this is
	194	* the maximum mapped by the Linux kernel during initialization.
	195	*/
6d0f6bcf	196	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
d4ca31c4 WD	197
	198	/*-----------------------------------------------------------------------
	199	* FLASH organization
	200	*/
e318d9e9	201	/* use CFI flash driver */
6d0f6bcf	202	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	203	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	205	#define CONFIG_SYS_FLASH_EMPTY_INFO
	206	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	207	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	208	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
d4ca31c4	209
5a1aceb0	210	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	211	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	212	#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
	213	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
d4ca31c4 WD	214
d4ca31c4 WD	215	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	216	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	217	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
d4ca31c4	218
6d0f6bcf	219	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
67c31036	220
7c803be2 WD	221	#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
7c803be2 WD	222
29f8f58f WD	223	/*-----------------------------------------------------------------------
	224	* Dynamic MTD partition support
	225	*/
68d7d651	226	#define CONFIG_CMD_MTDPARTS
942556a9 SR	227	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	228	#define CONFIG_FLASH_CFI_MTD
29f8f58f WD	229	#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
	230
	231	#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
	232	"128k(dtb)," \
	233	"1920k(kernel)," \
	234	"5632(rootfs)," \
cd82919e	235	"4m(data)"
29f8f58f	236
d4ca31c4 WD	237	/*-----------------------------------------------------------------------
	238	* Hardware Information Block
	239	*/
6d0f6bcf JCPV	240	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	241	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	242	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
d4ca31c4 WD	243
	244	/*-----------------------------------------------------------------------
	245	* Cache Configuration
	246	*/
6d0f6bcf	247	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	248	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	249	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
d4ca31c4 WD	250	#endif
	251
	252	/*-----------------------------------------------------------------------
	253	* SYPCR - System Protection Control 11-9
	254	* SYPCR can only be written once after reset!
	255	*-----------------------------------------------------------------------
	256	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	257	*/
	258	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	259	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
d4ca31c4 WD	260	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
d4ca31c4 WD	261	#else
6d0f6bcf	262	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
d4ca31c4 WD	263	#endif
	264
	265	/*-----------------------------------------------------------------------
	266	* SIUMCR - SIU Module Configuration 11-6
	267	*-----------------------------------------------------------------------
	268	* PCMCIA config., multi-function pin tri-state
	269	*/
c178d3da	270	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	271	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
d4ca31c4	272	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	273	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
d4ca31c4 WD	274	#endif /* CONFIG_CAN_DRIVER */
	275
	276	/*-----------------------------------------------------------------------
	277	* TBSCR - Time Base Status and Control 11-26
	278	*-----------------------------------------------------------------------
	279	* Clear Reference Interrupt Status, Timebase freezing enabled
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
d4ca31c4	282
d4ca31c4 WD	283	/*-----------------------------------------------------------------------
	284	* PISCR - Periodic Interrupt Status and Control 11-31
	285	*-----------------------------------------------------------------------
	286	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	287	*/
6d0f6bcf	288	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
d4ca31c4	289
d4ca31c4 WD	290	/*-----------------------------------------------------------------------
	291	* SCCR - System Clock and reset Control Register 15-27
	292	*-----------------------------------------------------------------------
	293	* Set clock output, timebase and RTC source and divider,
	294	* power management and some other internal clocks
	295	*/
	296	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	297	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
d4ca31c4 WD	298	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
d4ca31c4 WD	299	SCCR_DFALCD00)
d4ca31c4 WD	300
	301	/*-----------------------------------------------------------------------
	302	* PCMCIA stuff
	303	*-----------------------------------------------------------------------
	304	*
	305	*/
6d0f6bcf JCPV	306	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	307	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	308	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	309	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	310	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	311	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	312	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	313	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
d4ca31c4 WD	314
	315	/*-----------------------------------------------------------------------
	316	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	317	*-----------------------------------------------------------------------
	318	*/
	319
8d1165e1	320	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
c178d3da	321	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
d4ca31c4	322
c178d3da WD	323	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
c178d3da WD	324	#undef CONFIG_IDE_LED /* LED for ide not supported */
d4ca31c4 WD	325	#undef CONFIG_IDE_RESET /* reset for ide not supported */
d4ca31c4 WD	326
6d0f6bcf JCPV	327	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	328	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
d4ca31c4	329
6d0f6bcf	330	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
d4ca31c4	331
6d0f6bcf	332	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
d4ca31c4 WD	333
d4ca31c4 WD	334	/* Offset for data I/O */
6d0f6bcf	335	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
d4ca31c4 WD	336
d4ca31c4 WD	337	/* Offset for normal register accesses */
6d0f6bcf	338	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
d4ca31c4 WD	339
d4ca31c4 WD	340	/* Offset for alternate registers */
6d0f6bcf	341	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
d4ca31c4 WD	342
	343	/*-----------------------------------------------------------------------
	344	*
	345	*-----------------------------------------------------------------------
	346	*
	347	*/
6d0f6bcf	348	#define CONFIG_SYS_DER 0
d4ca31c4 WD	349
	350	/*
	351	* Init Memory Controller:
	352	*
	353	* BR0/1 and OR0/1 (FLASH)
	354	*/
	355
	356	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	357	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	358
	359	/* used to re-map FLASH both when starting from SRAM or FLASH:
	360	* restrict access enough to keep SRAM working (if any)
	361	* but not too much to meddle with FLASH accesses
	362	*/
6d0f6bcf JCPV	363	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	364	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
d4ca31c4 WD	365
d4ca31c4 WD	366	/*
c178d3da	367	* FLASH timing: Default value of OR0 after reset
d4ca31c4	368	*/
6d0f6bcf	369	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_MSK \| OR_BI \| \
c178d3da	370	OR_SCY_15_CLK \| OR_TRLX)
d4ca31c4	371
6d0f6bcf JCPV	372	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	373	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	374	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
d4ca31c4	375
6d0f6bcf JCPV	376	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	377	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	378	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
d4ca31c4 WD	379
	380	/*
	381	* BR2/3 and OR2/3 (SDRAM)
	382	*
	383	*/
	384	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	385	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
c178d3da	386	#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
d4ca31c4 WD	387
d4ca31c4 WD	388	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	389	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
d4ca31c4	390
6d0f6bcf JCPV	391	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	392	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
d4ca31c4	393
c178d3da	394	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	395	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	396	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
d4ca31c4	397	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	398	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	399	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	400	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	401	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
d4ca31c4 WD	402	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	403	#endif /* CONFIG_CAN_DRIVER */
	404
c178d3da	405	/*
c178d3da WD	406	* 4096 Rows from SDRAM example configuration
	407	* 1000 factor s -> ms
	408	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	409	* 4 Number of refresh cycles per period
	410	* 64 Refresh cycle in ms per number of rows
	411	*/
6d0f6bcf	412	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
c178d3da	413
d4ca31c4	414	/*
d43e489b MK	415	* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
	416	*
	417	* CPUclock(MHz) * 31.2
6d0f6bcf	418	* CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
d43e489b MK	419	* 2^(2SCCR[DFBRG]) MPTPR_PTP_DIV16
d43e489b MK	420	*
6d0f6bcf JCPV	421	* CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
	422	* CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
	423	* CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
	424	* CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
d43e489b MK	425	*
	426	* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
	427	* be met also in the default configuration, i.e. if environment variable
	428	* 'cpuclk' is not set.
d4ca31c4	429	*/
6d0f6bcf	430	#define CONFIG_SYS_MAMR_PTA 97
d4ca31c4 WD	431
d4ca31c4 WD	432	/*
d43e489b	433	* Memory Periodic Timer Prescaler Register (MPTPR) values.
d4ca31c4	434	*/
d43e489b	435	/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
6d0f6bcf	436	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
d43e489b	437	/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
6d0f6bcf	438	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
d4ca31c4 WD	439
	440	/*
	441	* MAMR settings for SDRAM
	442	*/
	443
	444	/* 8 column SDRAM */
6d0f6bcf	445	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
d4ca31c4 WD	446	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	447	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	448	/* 9 column SDRAM */
6d0f6bcf	449	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
d4ca31c4 WD	450	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
d4ca31c4 WD	451	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
c178d3da	452	/* 10 column SDRAM */
6d0f6bcf	453	#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
c178d3da WD	454	MAMR_AMA_TYPE_2 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A9 \| \
c178d3da WD	455	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
d4ca31c4	456
d4ca31c4 WD	457	#define CONFIG_SCC1_ENET
d4ca31c4 WD	458	#define CONFIG_FEC_ENET
48690d80	459	#define CONFIG_ETHPRIME "SCC"
d4ca31c4	460
7026ead0 HS	461	#define CONFIG_HWCONFIG 1
7026ead0 HS	462
d4ca31c4	463	#endif /* __CONFIG_H */