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f749db3a | 1 | /* |
89a168f7 | 2 | * Copyright 2017 NXP |
f749db3a YS |
3 | * Copyright (C) 2014 Freescale Semiconductor |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __LS2_COMMON_H | |
9 | #define __LS2_COMMON_H | |
10 | ||
f749db3a | 11 | #define CONFIG_REMAKE_ELF |
9f3183d2 | 12 | #define CONFIG_FSL_LAYERSCAPE |
9f3183d2 | 13 | #define CONFIG_MP |
f749db3a | 14 | #define CONFIG_GICV3 |
9c66ce66 | 15 | #define CONFIG_FSL_TZPC_BP147 |
f749db3a | 16 | |
08c5130d | 17 | #include <asm/arch/stream_id_lsch3.h> |
9f3183d2 | 18 | #include <asm/arch/config.h> |
31d34c6c | 19 | |
9f3183d2 MH |
20 | /* Link Definitions */ |
21 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
22 | ||
422cb08a | 23 | /* We need architecture specific misc initializations */ |
422cb08a | 24 | |
f749db3a | 25 | /* Link Definitions */ |
a646f669 | 26 | #ifndef CONFIG_QSPI_BOOT |
b2d5ac59 SW |
27 | #ifdef CONFIG_SPL |
28 | #define CONFIG_SYS_TEXT_BASE 0x80400000 | |
29 | #else | |
f3f8c564 | 30 | #define CONFIG_SYS_TEXT_BASE 0x30100000 |
b2d5ac59 | 31 | #endif |
89a168f7 PJ |
32 | #else |
33 | #define CONFIG_SYS_TEXT_BASE 0x20100000 | |
34 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
35 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
36 | #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ | |
37 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
a646f669 | 38 | #endif |
f749db3a | 39 | |
f749db3a YS |
40 | #define CONFIG_SUPPORT_RAW_INITRD |
41 | ||
42 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
f749db3a | 43 | |
b2d5ac59 | 44 | #ifndef CONFIG_SPL |
f749db3a | 45 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
b2d5ac59 | 46 | #endif |
f749db3a | 47 | #ifndef CONFIG_SYS_FSL_DDR4 |
f749db3a YS |
48 | #define CONFIG_SYS_DDR_RAW_TIMING |
49 | #endif | |
f749db3a YS |
50 | |
51 | #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ | |
52 | ||
9f3183d2 | 53 | #define CONFIG_VERY_BIG_RAM |
f749db3a YS |
54 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
55 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
56 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
57 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL | |
d9c68b14 YS |
58 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 |
59 | ||
8bfa301b YS |
60 | /* |
61 | * SMP Definitinos | |
62 | */ | |
63 | #define CPU_RELEASE_ADDR secondary_boot_func | |
64 | ||
d9c68b14 | 65 | #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
44937214 | 66 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
d9c68b14 YS |
67 | #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL |
68 | /* | |
69 | * DDR controller use 0 as the base address for binding. | |
70 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
71 | */ | |
72 | #define CONFIG_SYS_DP_DDR_BASE_PHY 0 | |
73 | #define CONFIG_DP_DDR_CTRL 2 | |
74 | #define CONFIG_DP_DDR_NUM_CTRLS 1 | |
44937214 | 75 | #endif |
f749db3a YS |
76 | |
77 | /* Generic Timer Definitions */ | |
207774b2 YS |
78 | /* |
79 | * This is not an accurate number. It is used in start.S. The frequency | |
80 | * will be udpated later when get_bus_freq(0) is available. | |
81 | */ | |
82 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
f749db3a YS |
83 | |
84 | /* Size of malloc() pool */ | |
aa66acbf | 85 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
f749db3a YS |
86 | |
87 | /* I2C */ | |
f749db3a YS |
88 | #define CONFIG_SYS_I2C |
89 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
90 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
91 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e YS |
92 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
93 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ | |
f749db3a YS |
94 | |
95 | /* Serial Port */ | |
7288c2c2 | 96 | #define CONFIG_CONS_INDEX 1 |
f749db3a YS |
97 | #define CONFIG_SYS_NS16550_SERIAL |
98 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
3564208e | 99 | #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) |
f749db3a | 100 | |
f749db3a YS |
101 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
102 | ||
103 | /* IFC */ | |
104 | #define CONFIG_FSL_IFC | |
f3f8c564 | 105 | |
f749db3a | 106 | /* |
7288c2c2 YS |
107 | * During booting, IFC is mapped at the region of 0x30000000. |
108 | * But this region is limited to 256MB. To accommodate NOR, promjet | |
109 | * and FPGA. This region is divided as below: | |
110 | * 0x30000000 - 0x37ffffff : 128MB : NOR flash | |
111 | * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet | |
112 | * 0x3C000000 - 0x40000000 : 64MB : FPGA etc | |
113 | * | |
114 | * To accommodate bigger NOR flash and other devices, we will map IFC | |
115 | * chip selects to as below: | |
116 | * 0x5_1000_0000..0x5_1fff_ffff Memory Hole | |
117 | * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) | |
118 | * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB | |
119 | * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) | |
120 | * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) | |
121 | * | |
122 | * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. | |
f749db3a YS |
123 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
124 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
125 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
126 | * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting | |
127 | */ | |
7288c2c2 | 128 | |
f749db3a YS |
129 | #define CONFIG_SYS_FLASH_BASE 0x580000000ULL |
130 | #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 | |
131 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
132 | ||
7288c2c2 YS |
133 | #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 |
134 | #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 | |
135 | ||
7288c2c2 YS |
136 | #ifndef __ASSEMBLY__ |
137 | unsigned long long get_qixis_addr(void); | |
138 | #endif | |
139 | #define QIXIS_BASE get_qixis_addr() | |
140 | #define QIXIS_BASE_PHYS 0x20000000 | |
141 | #define QIXIS_BASE_PHYS_EARLY 0xC000000 | |
8b06460e YL |
142 | #define QIXIS_STAT_PRES1 0xb |
143 | #define QIXIS_SDID_MASK 0x07 | |
144 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 | |
7288c2c2 YS |
145 | |
146 | #define CONFIG_SYS_NAND_BASE 0x530000000ULL | |
147 | #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 | |
e211c12e | 148 | |
f749db3a | 149 | /* MC firmware */ |
f749db3a | 150 | /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ |
125e2bc1 GR |
151 | #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
152 | #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 | |
153 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 | |
154 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 | |
3c1d218a | 155 | /* For LS2085A */ |
c1000c12 GR |
156 | #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 |
157 | #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 | |
f749db3a | 158 | |
5c055089 PK |
159 | /* |
160 | * Carve out a DDR region which will not be used by u-boot/Linux | |
161 | * | |
162 | * It will be used by MC and Debug Server. The MC region must be | |
163 | * 512MB aligned, so the min size to hide is 512MB. | |
164 | */ | |
b63a9506 | 165 | #ifdef CONFIG_FSL_MC_ENET |
52c11d4f | 166 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) |
f749db3a YS |
167 | #endif |
168 | ||
169 | /* Command line configuration */ | |
f749db3a | 170 | #define CONFIG_CMD_ENV |
f749db3a YS |
171 | |
172 | /* Miscellaneous configurable options */ | |
173 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
174 | ||
175 | /* Physical Memory Map */ | |
176 | /* fixme: these need to be checked against the board */ | |
177 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
f749db3a | 178 | |
d9c68b14 | 179 | #define CONFIG_NR_DRAM_BANKS 3 |
f749db3a | 180 | |
f749db3a YS |
181 | #define CONFIG_HWCONFIG |
182 | #define HWCONFIG_BUFFER_SIZE 128 | |
183 | ||
1d3a76fa AW |
184 | /* Allow to overwrite serial and ethaddr */ |
185 | #define CONFIG_ENV_OVERWRITE | |
186 | ||
f749db3a YS |
187 | /* Initial environment variables */ |
188 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
189 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
190 | "loadaddr=0x80100000\0" \ | |
191 | "kernel_addr=0x100000\0" \ | |
192 | "ramdisk_addr=0x800000\0" \ | |
193 | "ramdisk_size=0x2000000\0" \ | |
f3f8c564 | 194 | "fdt_high=0xa0000000\0" \ |
f749db3a | 195 | "initrd_high=0xffffffffffffffff\0" \ |
f5bf23d8 | 196 | "kernel_start=0x581000000\0" \ |
052ddd5c | 197 | "kernel_load=0xa0000000\0" \ |
97421bd2 | 198 | "kernel_size=0x2800000\0" \ |
16ed8560 | 199 | "console=ttyAMA0,38400n8\0" \ |
f5bf23d8 SK |
200 | "mcinitcmd=fsl_mc start mc 0x580a00000" \ |
201 | " 0x580e00000 \0" | |
f749db3a | 202 | |
56cd0760 | 203 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
ed77b704 | 204 | "earlycon=uart8250,mmio,0x21c0500 " \ |
34cc7546 | 205 | "ramdisk_size=0x2000000 default_hugepagesz=2m" \ |
9e71bb9c | 206 | " hugepagesz=2m hugepages=256" |
f5bf23d8 | 207 | #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ |
9f3e1b8a PK |
208 | " cp.b $kernel_start $kernel_load" \ |
209 | " $kernel_size && bootm $kernel_load" | |
f749db3a | 210 | |
f749db3a YS |
211 | /* Monitor Command Prompt */ |
212 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
f749db3a YS |
213 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
214 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
f749db3a YS |
215 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
216 | #define CONFIG_SYS_LONGHELP | |
217 | #define CONFIG_CMDLINE_EDITING 1 | |
f3f8c564 | 218 | #define CONFIG_AUTO_COMPLETE |
f749db3a YS |
219 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
220 | ||
f3f8c564 PK |
221 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
222 | ||
b2d5ac59 SW |
223 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
224 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 | |
b2d5ac59 | 225 | #define CONFIG_SPL_FRAMEWORK |
b2d5ac59 | 226 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
b2d5ac59 | 227 | #define CONFIG_SPL_MAX_SIZE 0x16000 |
b2d5ac59 SW |
228 | #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) |
229 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
230 | #define CONFIG_SPL_TEXT_BASE 0x1800a000 | |
231 | ||
232 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 | |
233 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
234 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 | |
235 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
74cac00c | 236 | #define CONFIG_SYS_MONITOR_LEN (640 * 1024) |
b2d5ac59 | 237 | |
34cc7546 BS |
238 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
239 | ||
bcb55f67 AB |
240 | /* Hash command with SHA acceleration supported in hardware */ |
241 | #ifdef CONFIG_FSL_CAAM | |
242 | #define CONFIG_CMD_HASH | |
243 | #define CONFIG_SHA_HW_ACCEL | |
244 | #endif | |
245 | ||
f749db3a | 246 | #endif /* __LS2_COMMON_H */ |