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6e7fb6ea SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * John Otken, jotken@softadvances.com | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6e7fb6ea SR |
7 | */ |
8 | ||
9 | /************************************************************************ | |
10 | * luan.h - configuration for LUAN board | |
11 | ***********************************************************************/ | |
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /*----------------------------------------------------------------------- | |
16 | * High Level Configuration Options | |
17 | *----------------------------------------------------------------------*/ | |
18 | #define CONFIG_LUAN 1 /* Board is Luan */ | |
19 | #define CONFIG_440SP 1 /* Specific PPC440SP support */ | |
6e7fb6ea SR |
20 | #define CONFIG_440 1 |
21 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 |
24 | ||
490f2040 SR |
25 | /* |
26 | * Include common defines/options for all AMCC eval boards | |
27 | */ | |
28 | #define CONFIG_HOSTNAME luan | |
29 | #include "amcc-common.h" | |
30 | ||
00cdb4ce | 31 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
6e7fb6ea SR |
32 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
33 | ||
34 | /*----------------------------------------------------------------------- | |
35 | * Base addresses -- Note these are effective addresses where the | |
36 | * actual resources get mapped (not physical addresses) | |
37 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
38 | #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ |
39 | #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ | |
40 | #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ | |
bf560807 | 41 | #define CONFIG_SYS_SRAM_SIZE (1 << 20) |
6d0f6bcf | 42 | #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ |
6e7fb6ea | 43 | |
6d0f6bcf | 44 | #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ |
6e7fb6ea | 45 | |
6d0f6bcf JCPV |
46 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
47 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
48 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ | |
6e7fb6ea | 49 | |
6d0f6bcf JCPV |
50 | #if CONFIG_SYS_LARGE_FLASH == 0xffc00000 |
51 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH | |
6e7fb6ea | 52 | #else |
6d0f6bcf | 53 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH |
6e7fb6ea SR |
54 | #endif |
55 | ||
6d0f6bcf JCPV |
56 | #if CONFIG_SYS_SRAM_BASE |
57 | #define CONFIG_SYS_KBYTES_SDRAM 1024*2 | |
6e7fb6ea | 58 | #else |
6d0f6bcf | 59 | #define CONFIG_SYS_KBYTES_SDRAM 1024 |
6e7fb6ea SR |
60 | #endif |
61 | ||
62 | /*----------------------------------------------------------------------- | |
63 | * Initial RAM & stack pointer (placed in SDRAM) | |
64 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 65 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE |
553f0982 | 66 | #define CONFIG_SYS_INIT_RAM_SIZE (8 << 10) |
25ddd1fb | 67 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 68 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6e7fb6ea SR |
69 | |
70 | /*----------------------------------------------------------------------- | |
71 | * Serial Port | |
72 | *----------------------------------------------------------------------*/ | |
550650dd | 73 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 74 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ |
6e7fb6ea | 75 | |
6e7fb6ea SR |
76 | /*----------------------------------------------------------------------- |
77 | * Environment | |
78 | *----------------------------------------------------------------------*/ | |
79 | /* | |
80 | * Define here the location of the environment variables (FLASH or EEPROM). | |
81 | * Note: DENX encourages to use redundant environment in FLASH. | |
82 | */ | |
5a1aceb0 | 83 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
6e7fb6ea SR |
84 | |
85 | /*----------------------------------------------------------------------- | |
86 | * FLASH related | |
87 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
89 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ | |
6e7fb6ea | 90 | |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
92 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
6e7fb6ea | 93 | |
6d0f6bcf | 94 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
6e7fb6ea | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
97 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa | |
98 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
6e7fb6ea | 99 | |
5a1aceb0 | 100 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 101 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 102 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 103 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
6e7fb6ea SR |
104 | |
105 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
106 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
107 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 108 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
6e7fb6ea SR |
109 | |
110 | /*----------------------------------------------------------------------- | |
111 | * DDR SDRAM | |
112 | *----------------------------------------------------------------------*/ | |
00cdb4ce SR |
113 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
114 | #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ | |
e4bbed28 | 115 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
6e7fb6ea SR |
116 | |
117 | /*----------------------------------------------------------------------- | |
118 | * I2C | |
119 | *----------------------------------------------------------------------*/ | |
880540de | 120 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
6e7fb6ea | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
123 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
124 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
125 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
126 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4f92ed5f | 127 | |
490f2040 SR |
128 | /* |
129 | * Default environment variables | |
130 | */ | |
131 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
132 | CONFIG_AMCC_DEF_ENV \ | |
133 | CONFIG_AMCC_DEF_ENV_PPC \ | |
134 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
6e7fb6ea SR |
135 | "kernel_addr=fc000000\0" \ |
136 | "ramdisk_addr=fc100000\0" \ | |
6e7fb6ea | 137 | "" |
6e7fb6ea | 138 | |
a00eccfe | 139 | #define CONFIG_HAS_ETH0 |
6e7fb6ea SR |
140 | #define CONFIG_PHY_ADDR 1 |
141 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
142 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
143 | ||
6e7fb6ea SR |
144 | #ifdef DEBUG |
145 | #define CONFIG_PANIC_HANG | |
146 | #else | |
147 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
148 | #endif | |
149 | ||
7f5c0157 | 150 | /* |
490f2040 | 151 | * Commands additional to the ones defined in amcc-common.h |
7f5c0157 | 152 | */ |
9bbb1c08 | 153 | #define CONFIG_CMD_PCI |
9bbb1c08 | 154 | #define CONFIG_CMD_SDRAM |
6e7fb6ea | 155 | |
6e7fb6ea SR |
156 | /*----------------------------------------------------------------------- |
157 | * PCI stuff | |
158 | *----------------------------------------------------------------------- | |
159 | */ | |
9bbb1c08 | 160 | #if defined(CONFIG_CMD_PCI) |
6e7fb6ea SR |
161 | |
162 | /* General PCI */ | |
163 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 164 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
6e7fb6ea SR |
165 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
166 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
167 | ||
168 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_PCI_TARGET_INIT |
170 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
6e7fb6ea | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
173 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ | |
6e7fb6ea | 174 | |
9bbb1c08 | 175 | #endif |
6e7fb6ea | 176 | |
6e7fb6ea | 177 | #endif /* __CONFIG_H */ |