[people/ms/u-boot.git] / include / configs / socfpga_common.h

/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET

/*
 * High level configuration
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_CLOCKS

#define CONFIG_CRC32_VERIFY

#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/* add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x0
#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE

#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE		0x08000040
#else
#define CONFIG_SYS_TEXT_BASE		0x01000040
#endif

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
#endif

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * EPCS/EPCQx1 Serial Flash Controller
 */
#ifdef CONFIG_ALTERA_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
/*
 * The base address is configurable in QSys, each board must specify the
 * base address based on it's particular FPGA configuration. Please note
 * that the address here is incremented by  0x400  from the Base address
 * selected in QSys, since the SPI registers are at offset +0x400.
 * #define CONFIG_SYS_SPI_BASE		0xff240400
 */
#endif

/*
 * Ethernet on SoC (EMAC)
 */
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
#define CONFIG_PHY_GIGE
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_SOCFPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TIMER_RATE		2400000
#else
#define CONFIG_SYS_TIMER_RATE		25000000
#endif

/*
 * L4 Watchdog
 */
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000
#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	30000
#endif

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE	512
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
#endif

/*
 * I2C support
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BUS_MAX		4
#define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SPEED3		100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE		0x02
#define CONFIG_SYS_I2C_SLAVE1		0x02
#define CONFIG_SYS_I2C_SLAVE2		0x02
#define CONFIG_SYS_I2C_SLAVE3		0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
#endif

/*
 * QSPI support
 */
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_CQSPI_DECODER		0
#define CONFIG_BOUNCE_BUFFER

/*
 * Designware SPI support
 */

/*
 * Serial Driver
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_NS16550_CLK		1000000
#else
#define CONFIG_SYS_NS16550_CLK		100000000
#endif
#define CONFIG_CONS_INDEX		1

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#endif

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_FUNCTION_MASS_STORAGE

#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE			4096
#endif

/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
#endif

/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET		0x00100000
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#endif

/*
 * mtd partitioning for serial NOR flash
 *
 * device nor0 <ff705000.spi.0>, # parts = 6
 * #: name                size            offset          mask_flags
 * 0: u-boot              0x00100000      0x00000000      0
 * 1: env1                0x00040000      0x00100000      0
 * 2: env2                0x00040000      0x00140000      0
 * 3: UBI                 0x03e80000      0x00180000      0
 * 4: boot                0x00e80000      0x00180000      0
 * 5: rootfs              0x01000000      0x01000000      0
 *
 */
#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
#define MTDPARTS_DEFAULT	"mtdparts=ff705000.spi.0:"\
				"1m(u-boot),"		\
				"256k(env1),"		\
				"256k(env2),"		\
				"14848k(boot),"		\
				"16m(rootfs),"		\
				"-@1536k(UBI)\0"
#endif

/* UBI and UBIFS support */
#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#endif

/*
 * SPL
 *
 * SRAM Memory layout:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Malloc area
 * 0xFFFF_zzzz ...... Global Data
 * 0xFFFF_FF00 ...... End of SRAM
 */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE		(64 * 1024)

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	2
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
#endif
#endif

/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
#endif

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#endif

/*
 * Stack setup
 */
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
5095ee08 PM	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
48275c96 DN	6	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	7	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	8
5095ee08 PM	9	/* Virtual target or real hardware */
	10	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
	11
5095ee08 PM	12	/*
	13	* High level configuration
	14	*/
7287d5f0	15	#define CONFIG_DISPLAY_BOARDINFO_LATE
5095ee08 PM	16	#define CONFIG_CLOCKS
5095ee08 PM	17
251faa20 MV	18	#define CONFIG_CRC32_VERIFY
251faa20 MV	19
5095ee08 PM	20	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	21
	22	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	23
dc0a1a08 MV	24	/* add target to build it automatically upon "make" */
	25	#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
	26
5095ee08 PM	27	/*
	28	* Memory configurations
	29	*/
	30	#define CONFIG_NR_DRAM_BANKS 1
	31	#define PHYS_SDRAM_1 0x0
0223a95c	32	#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
5095ee08 PM	33	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	34	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
	35
	36	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
7599b53d MV	37	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	38	#define CONFIG_SYS_INIT_SP_OFFSET \
	39	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	40	#define CONFIG_SYS_INIT_SP_ADDR \
	41	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
5095ee08 PM	42
	43	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	44	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	45	#define CONFIG_SYS_TEXT_BASE 0x08000040
	46	#else
	47	#define CONFIG_SYS_TEXT_BASE 0x01000040
	48	#endif
	49
	50	/*
	51	* U-Boot general configurations
	52	*/
	53	#define CONFIG_SYS_LONGHELP
	54	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	55	#define CONFIG_SYS_PBSIZE \
	56	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	57	/* Print buffer size */
	58	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	59	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	60	/* Boot argument buffer size */
5095ee08 PM	61	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
5095ee08 PM	62	#define CONFIG_CMDLINE_EDITING /* Command history etc */
5095ee08	63
ea082346 MV	64	#ifndef CONFIG_SYS_HOSTNAME
	65	#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
	66	#endif
	67
5095ee08 PM	68	/*
	69	* Cache
	70	*/
5095ee08 PM	71	#define CONFIG_SYS_L2_PL310
	72	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	73
8a78ca9e MV	74	/*
	75	* EPCS/EPCQx1 Serial Flash Controller
	76	*/
	77	#ifdef CONFIG_ALTERA_SPI
8a78ca9e	78	#define CONFIG_SF_DEFAULT_SPEED 30000000
8a78ca9e MV	79	/*
	80	* The base address is configurable in QSys, each board must specify the
	81	* base address based on it's particular FPGA configuration. Please note
	82	* that the address here is incremented by 0x400 from the Base address
	83	* selected in QSys, since the SPI registers are at offset +0x400.
	84	* #define CONFIG_SYS_SPI_BASE 0xff240400
	85	*/
	86	#endif
	87
5095ee08 PM	88	/*
	89	* Ethernet on SoC (EMAC)
	90	*/
	91	#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
5095ee08 PM	92	#define CONFIG_DW_ALTDESCRIPTOR
	93	#define CONFIG_MII
	94	#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
5095ee08 PM	95	#define CONFIG_PHY_GIGE
	96	#endif
	97
	98	/*
	99	* FPGA Driver
	100	*/
	101	#ifdef CONFIG_CMD_FPGA
	102	#define CONFIG_FPGA
	103	#define CONFIG_FPGA_ALTERA
	104	#define CONFIG_FPGA_SOCFPGA
	105	#define CONFIG_FPGA_COUNT 1
	106	#endif
	107
	108	/*
	109	* L4 OSC1 Timer 0
	110	*/
	111	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	112	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	113	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	114	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	115	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	116	#define CONFIG_SYS_TIMER_RATE 2400000
	117	#else
	118	#define CONFIG_SYS_TIMER_RATE 25000000
	119	#endif
	120
	121	/*
	122	* L4 Watchdog
	123	*/
	124	#ifdef CONFIG_HW_WATCHDOG
	125	#define CONFIG_DESIGNWARE_WATCHDOG
	126	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	127	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
d0e932de	128	#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
5095ee08 PM	129	#endif
	130
	131	/*
	132	* MMC Driver
	133	*/
	134	#ifdef CONFIG_CMD_MMC
5095ee08	135	#define CONFIG_BOUNCE_BUFFER
5095ee08 PM	136	/* FIXME */
	137	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	138	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	139	#endif
	140
c339ea5b MV	141	/*
	142	* NAND Support
	143	*/
	144	#ifdef CONFIG_NAND_DENALI
	145	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	146	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	147	#define CONFIG_SYS_NAND_ONFI_DETECTION
	148	#define CONFIG_NAND_DENALI_ECC_SIZE 512
	149	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
	150	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
	151	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	152	#endif
	153
7fb0f596	154	/*
ebcaf966 SR	155	* I2C support
	156	*/
	157	#define CONFIG_SYS_I2C
ebcaf966 SR	158	#define CONFIG_SYS_I2C_BUS_MAX 4
	159	#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
	160	#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
	161	#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
	162	#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
	163	/* Using standard mode which the speed up to 100Kb/s */
	164	#define CONFIG_SYS_I2C_SPEED 100000
	165	#define CONFIG_SYS_I2C_SPEED1 100000
	166	#define CONFIG_SYS_I2C_SPEED2 100000
	167	#define CONFIG_SYS_I2C_SPEED3 100000
	168	/* Address of device when used as slave */
	169	#define CONFIG_SYS_I2C_SLAVE 0x02
	170	#define CONFIG_SYS_I2C_SLAVE1 0x02
	171	#define CONFIG_SYS_I2C_SLAVE2 0x02
	172	#define CONFIG_SYS_I2C_SLAVE3 0x02
	173	#ifndef __ASSEMBLY__
	174	/* Clock supplied to I2C controller in unit of MHz */
	175	unsigned int cm_get_l4_sp_clk_hz(void);
	176	#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
	177	#endif
ebcaf966	178
7fb0f596 SR	179	/*
	180	* QSPI support
	181	*/
7fb0f596	182	/* Enable multiple SPI NOR flash manufacturers */
cbc9544d	183	#ifndef CONFIG_SPL_BUILD
7fb0f596	184	#define CONFIG_SPI_FLASH_MTD
55b4312b MV	185	#define CONFIG_CMD_MTDPARTS
	186	#define CONFIG_MTD_DEVICE
	187	#define CONFIG_MTD_PARTITIONS
55702fe2	188	#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
cbc9544d	189	#endif
7fb0f596 SR	190	/* QSPI reference clock */
	191	#ifndef __ASSEMBLY__
	192	unsigned int cm_get_qspi_controller_clk_hz(void);
	193	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	194	#endif
	195	#define CONFIG_CQSPI_DECODER 0
57897c13	196	#define CONFIG_BOUNCE_BUFFER
7fb0f596	197
0c745d00 MV	198	/*
	199	* Designware SPI support
	200	*/
a6e73591	201
5095ee08 PM	202	/*
	203	* Serial Driver
	204	*/
5095ee08 PM	205	#define CONFIG_SYS_NS16550_SERIAL
	206	#define CONFIG_SYS_NS16550_REG_SIZE -4
	207	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
	208	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	209	#define CONFIG_SYS_NS16550_CLK 1000000
	210	#else
	211	#define CONFIG_SYS_NS16550_CLK 100000000
	212	#endif
	213	#define CONFIG_CONS_INDEX 1
5095ee08	214
20cadbbe MV	215	/*
	216	* USB
	217	*/
	218	#ifdef CONFIG_CMD_USB
	219	#define CONFIG_USB_DWC2
20cadbbe MV	220	#endif
20cadbbe MV	221
0223a95c MV	222	/*
	223	* USB Gadget (DFU, UMS)
	224	*/
	225	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
01acd6ab	226	#define CONFIG_USB_FUNCTION_MASS_STORAGE
0223a95c	227
55ce55fa	228	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
0223a95c MV	229	#define DFU_DEFAULT_POLL_TIMEOUT 300
	230
	231	/* USB IDs */
e6c0bc06 SP	232	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	233	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	234	#endif
0223a95c MV	235
5095ee08 PM	236	/*
	237	* U-Boot environment
	238	*/
ead2fb29	239	#if !defined(CONFIG_ENV_SIZE)
5095ee08	240	#define CONFIG_ENV_SIZE 4096
ead2fb29	241	#endif
5095ee08	242
79cc48e7 CLS	243	/* Environment for SDMMC boot */
	244	#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
	245	#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
	246	#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
	247	#endif
	248
ec8b7528 CLS	249	/* Environment for QSPI boot */
	250	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
	251	#define CONFIG_ENV_OFFSET 0x00100000
	252	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	253	#endif
	254
55702fe2 CLS	255	/*
	256	* mtd partitioning for serial NOR flash
	257	*
	258	* device nor0 <ff705000.spi.0>, # parts = 6
	259	* #: name size offset mask_flags
	260	* 0: u-boot 0x00100000 0x00000000 0
	261	* 1: env1 0x00040000 0x00100000 0
	262	* 2: env2 0x00040000 0x00140000 0
	263	* 3: UBI 0x03e80000 0x00180000 0
	264	* 4: boot 0x00e80000 0x00180000 0
	265	* 5: rootfs 0x01000000 0x01000000 0
	266	*
	267	*/
	268	#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
	269	#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
	270	"1m(u-boot)," \
	271	"256k(env1)," \
	272	"256k(env2)," \
	273	"14848k(boot)," \
	274	"16m(rootfs)," \
	275	"-@1536k(UBI)\0"
	276	#endif
	277
6cdd465c CLS	278	/* UBI and UBIFS support */
6cdd465c CLS	279	#if defined(CONFIG_CMD_SF) \|\| defined(CONFIG_CMD_NAND)
6cdd465c CLS	280	#define CONFIG_CMD_UBIFS
	281	#define CONFIG_RBTREE
	282	#define CONFIG_LZO
	283	#endif
	284
5095ee08 PM	285	/*
5095ee08 PM	286	* SPL
34584d19 MV	287	*
	288	* SRAM Memory layout:
	289	*
	290	* 0xFFFF_0000 ...... Start of SRAM
	291	* 0xFFFF_xxxx ...... Top of stack (grows down)
	292	* 0xFFFF_yyyy ...... Malloc area
	293	* 0xFFFF_zzzz ...... Global Data
	294	* 0xFFFF_FF00 ...... End of SRAM
5095ee08 PM	295	*/
5095ee08 PM	296	#define CONFIG_SPL_FRAMEWORK
34584d19	297	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
6868160a	298	#define CONFIG_SPL_MAX_SIZE (64 * 1024)
5095ee08	299
d3f34e75 MV	300	/* SPL SDMMC boot support */
	301	#ifdef CONFIG_SPL_MMC_SUPPORT
	302	#if defined(CONFIG_SPL_FAT_SUPPORT) \|\| defined(CONFIG_SPL_EXT_SUPPORT)
	303	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
	304	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
d3f34e75 MV	305	#endif
d3f34e75 MV	306	#endif
5095ee08	307
346d6f56 MV	308	/* SPL QSPI boot support */
346d6f56 MV	309	#ifdef CONFIG_SPL_SPI_SUPPORT
346d6f56 MV	310	#define CONFIG_SPL_SPI_LOAD
	311	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
	312	#endif
	313
c339ea5b MV	314	/* SPL NAND boot support */
	315	#ifdef CONFIG_SPL_NAND_SUPPORT
	316	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	317	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	318	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	319	#endif
	320
a717b811 DN	321	/*
	322	* Stack setup
	323	*/
	324	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	325
48275c96	326	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */