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a06ea964 NC |
1 | /* aarch64-tbl.h -- AArch64 opcode description table and instruction |
2 | operand description table. | |
d87bef3a | 3 | Copyright (C) 2012-2023 Free Software Foundation, Inc. |
a06ea964 NC |
4 | |
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the | |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
21 | ||
22 | #include "aarch64-opc.h" | |
23 | ||
20f55f38 SN |
24 | #ifndef VERIFIER |
25 | #error VERIFIER must be defined. | |
26 | #endif | |
27 | ||
a06ea964 NC |
28 | /* Operand type. */ |
29 | ||
30 | #define OPND(x) AARCH64_OPND_##x | |
31 | #define OP0() {} | |
32 | #define OP1(a) {OPND(a)} | |
33 | #define OP2(a,b) {OPND(a), OPND(b)} | |
34 | #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} | |
35 | #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} | |
36 | #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} | |
37 | ||
38 | #define QLF(x) AARCH64_OPND_QLF_##x | |
39 | #define QLF1(a) {QLF(a)} | |
40 | #define QLF2(a,b) {QLF(a), QLF(b)} | |
41 | #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} | |
42 | #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} | |
43 | #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} | |
44 | ||
45 | /* Qualifiers list. */ | |
46 | ||
47 | /* e.g. MSR <systemreg>, <Xt>. */ | |
48 | #define QL_SRC_X \ | |
49 | { \ | |
50 | QLF2(NIL,X), \ | |
51 | } | |
52 | ||
53 | /* e.g. MRS <Xt>, <systemreg>. */ | |
54 | #define QL_DST_X \ | |
55 | { \ | |
56 | QLF2(X,NIL), \ | |
57 | } | |
58 | ||
59 | /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ | |
60 | #define QL_SYS \ | |
61 | { \ | |
a6a51754 | 62 | QLF5(NIL,CR,CR,NIL,X), \ |
a06ea964 NC |
63 | } |
64 | ||
65 | /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ | |
66 | #define QL_SYSL \ | |
67 | { \ | |
a6a51754 | 68 | QLF5(X,NIL,CR,CR,NIL), \ |
a06ea964 NC |
69 | } |
70 | ||
71 | /* e.g. ADRP <Xd>, <label>. */ | |
72 | #define QL_ADRP \ | |
73 | { \ | |
74 | QLF2(X,NIL), \ | |
75 | } | |
76 | ||
b83b4b13 SD |
77 | /* e.g. TCANCEL #<imm>. */ |
78 | #define QL_IMM_NIL \ | |
79 | { \ | |
80 | QLF1(NIL), \ | |
81 | } | |
82 | ||
a06ea964 NC |
83 | /* e.g. B.<cond> <label>. */ |
84 | #define QL_PCREL_NIL \ | |
85 | { \ | |
86 | QLF1(NIL), \ | |
87 | } | |
88 | ||
89 | /* e.g. TBZ <Xt>, #<imm>, <label>. */ | |
90 | #define QL_PCREL_14 \ | |
91 | { \ | |
92 | QLF3(X,imm_0_63,NIL), \ | |
93 | } | |
94 | ||
95 | /* e.g. BL <label>. */ | |
96 | #define QL_PCREL_26 \ | |
97 | { \ | |
98 | QLF1(NIL), \ | |
99 | } | |
100 | ||
101 | /* e.g. LDRSW <Xt>, <label>. */ | |
102 | #define QL_X_PCREL \ | |
103 | { \ | |
104 | QLF2(X,NIL), \ | |
105 | } | |
106 | ||
107 | /* e.g. LDR <Wt>, <label>. */ | |
108 | #define QL_R_PCREL \ | |
109 | { \ | |
110 | QLF2(W,NIL), \ | |
111 | QLF2(X,NIL), \ | |
112 | } | |
113 | ||
114 | /* e.g. LDR <Dt>, <label>. */ | |
115 | #define QL_FP_PCREL \ | |
116 | { \ | |
117 | QLF2(S_S,NIL), \ | |
118 | QLF2(S_D,NIL), \ | |
119 | QLF2(S_Q,NIL), \ | |
120 | } | |
121 | ||
122 | /* e.g. PRFM <prfop>, <label>. */ | |
123 | #define QL_PRFM_PCREL \ | |
124 | { \ | |
125 | QLF2(NIL,NIL), \ | |
126 | } | |
127 | ||
128 | /* e.g. BR <Xn>. */ | |
129 | #define QL_I1X \ | |
130 | { \ | |
131 | QLF1(X), \ | |
132 | } | |
133 | ||
bd7ceb8d | 134 | /* e.g. STG <Xt|SP>, [<Xn|SP>, #<imm9>]. */ |
fb3265b3 SD |
135 | #define QL_LDST_AT \ |
136 | { \ | |
69105ce4 | 137 | QLF2(X, imm_tag), \ |
bd7ceb8d | 138 | QLF2(SP, imm_tag), \ |
fb3265b3 SD |
139 | } |
140 | ||
a06ea964 NC |
141 | /* e.g. RBIT <Wd>, <Wn>. */ |
142 | #define QL_I2SAME \ | |
143 | { \ | |
144 | QLF2(W,W), \ | |
145 | QLF2(X,X), \ | |
146 | } | |
147 | ||
148 | /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ | |
149 | #define QL_I2_EXT \ | |
150 | { \ | |
151 | QLF2(W,W), \ | |
152 | QLF2(X,W), \ | |
153 | QLF2(X,X), \ | |
154 | } | |
155 | ||
156 | /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ | |
157 | #define QL_I2SP \ | |
158 | { \ | |
159 | QLF2(WSP,W), \ | |
160 | QLF2(W,WSP), \ | |
161 | QLF2(SP,X), \ | |
162 | QLF2(X,SP), \ | |
163 | } | |
164 | ||
165 | /* e.g. REV <Wd>, <Wn>. */ | |
166 | #define QL_I2SAMEW \ | |
167 | { \ | |
168 | QLF2(W,W), \ | |
169 | } | |
170 | ||
171 | /* e.g. REV32 <Xd>, <Xn>. */ | |
172 | #define QL_I2SAMEX \ | |
173 | { \ | |
174 | QLF2(X,X), \ | |
175 | } | |
176 | ||
177 | #define QL_I2SAMER \ | |
178 | { \ | |
179 | QLF2(W,W), \ | |
180 | QLF2(X,X), \ | |
181 | } | |
182 | ||
e60bb1dd YZ |
183 | /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ |
184 | #define QL_I3SAMEW \ | |
185 | { \ | |
186 | QLF3(W,W,W), \ | |
187 | } | |
188 | ||
a06ea964 NC |
189 | /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ |
190 | #define QL_I3SAMEX \ | |
191 | { \ | |
192 | QLF3(X,X,X), \ | |
193 | } | |
194 | ||
e60bb1dd YZ |
195 | /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ |
196 | #define QL_I3WWX \ | |
197 | { \ | |
198 | QLF3(W,W,X), \ | |
199 | } | |
200 | ||
a06ea964 NC |
201 | /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ |
202 | #define QL_I3SAMER \ | |
203 | { \ | |
204 | QLF3(W,W,W), \ | |
205 | QLF3(X,X,X), \ | |
206 | } | |
207 | ||
208 | /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ | |
209 | #define QL_I3_EXT \ | |
210 | { \ | |
211 | QLF3(W,W,W), \ | |
212 | QLF3(X,X,W), \ | |
213 | QLF3(X,X,X), \ | |
214 | } | |
215 | ||
216 | /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ | |
217 | #define QL_I4SAMER \ | |
218 | { \ | |
219 | QLF4(W,W,W,W), \ | |
220 | QLF4(X,X,X,X), \ | |
221 | } | |
222 | ||
223 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
224 | #define QL_I3SAMEL \ | |
225 | { \ | |
226 | QLF3(X,W,W), \ | |
227 | } | |
228 | ||
229 | /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ | |
230 | #define QL_I4SAMEL \ | |
231 | { \ | |
232 | QLF4(X,W,W,X), \ | |
233 | } | |
234 | ||
235 | /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ | |
236 | #define QL_CSEL \ | |
237 | { \ | |
238 | QLF4(W, W, W, NIL), \ | |
239 | QLF4(X, X, X, NIL), \ | |
240 | } | |
241 | ||
242 | /* e.g. CSET <Wd>, <cond>. */ | |
243 | #define QL_DST_R \ | |
244 | { \ | |
245 | QLF2(W, NIL), \ | |
246 | QLF2(X, NIL), \ | |
247 | } | |
248 | ||
249 | /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ | |
250 | #define QL_BF \ | |
251 | { \ | |
252 | QLF4(W,W,imm_0_31,imm_0_31), \ | |
253 | QLF4(X,X,imm_0_63,imm_0_63), \ | |
254 | } | |
255 | ||
193614f2 SD |
256 | /* e.g. ADDG <Xd>, <Xn>, #<uimm10>, #<uimm4>. */ |
257 | #define QL_ADDG \ | |
258 | { \ | |
259 | QLF4(X,X,NIL,imm_0_15), \ | |
260 | } \ | |
261 | ||
d685192a MW |
262 | /* e.g. BFC <Wd>, #<immr>, #<imms>. */ |
263 | #define QL_BF1 \ | |
264 | { \ | |
265 | QLF3 (W, imm_0_31, imm_1_32), \ | |
266 | QLF3 (X, imm_0_63, imm_1_64), \ | |
267 | } | |
268 | ||
a06ea964 NC |
269 | /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ |
270 | #define QL_BF2 \ | |
271 | { \ | |
272 | QLF4(W,W,imm_0_31,imm_1_32), \ | |
273 | QLF4(X,X,imm_0_63,imm_1_64), \ | |
274 | } | |
275 | ||
276 | /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ | |
277 | #define QL_FIX2FP \ | |
278 | { \ | |
279 | QLF3(S_D,W,imm_1_32), \ | |
280 | QLF3(S_S,W,imm_1_32), \ | |
281 | QLF3(S_D,X,imm_1_64), \ | |
282 | QLF3(S_S,X,imm_1_64), \ | |
283 | } | |
284 | ||
622b9eb1 MW |
285 | /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */ |
286 | #define QL_FIX2FP_H \ | |
287 | { \ | |
288 | QLF3 (S_H, W, imm_1_32), \ | |
289 | QLF3 (S_H, X, imm_1_64), \ | |
290 | } | |
291 | ||
a06ea964 NC |
292 | /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ |
293 | #define QL_FP2FIX \ | |
294 | { \ | |
295 | QLF3(W,S_D,imm_1_32), \ | |
296 | QLF3(W,S_S,imm_1_32), \ | |
297 | QLF3(X,S_D,imm_1_64), \ | |
298 | QLF3(X,S_S,imm_1_64), \ | |
299 | } | |
300 | ||
622b9eb1 MW |
301 | /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */ |
302 | #define QL_FP2FIX_H \ | |
303 | { \ | |
304 | QLF3 (W, S_H, imm_1_32), \ | |
305 | QLF3 (X, S_H, imm_1_64), \ | |
306 | } | |
307 | ||
a06ea964 NC |
308 | /* e.g. SCVTF <Dd>, <Wn>. */ |
309 | #define QL_INT2FP \ | |
310 | { \ | |
311 | QLF2(S_D,W), \ | |
312 | QLF2(S_S,W), \ | |
313 | QLF2(S_D,X), \ | |
314 | QLF2(S_S,X), \ | |
315 | } | |
316 | ||
cb366992 EB |
317 | /* e.g. FMOV <Dd>, <Xn>. */ |
318 | #define QL_INT2FP_FMOV \ | |
319 | { \ | |
320 | QLF2(S_S,W), \ | |
321 | QLF2(S_D,X), \ | |
322 | } | |
323 | ||
622b9eb1 MW |
324 | /* e.g. SCVTF <Hd>, <Wn>. */ |
325 | #define QL_INT2FP_H \ | |
326 | { \ | |
327 | QLF2 (S_H, W), \ | |
328 | QLF2 (S_H, X), \ | |
329 | } | |
330 | ||
a06ea964 NC |
331 | /* e.g. FCVTNS <Xd>, <Dn>. */ |
332 | #define QL_FP2INT \ | |
333 | { \ | |
334 | QLF2(W,S_D), \ | |
335 | QLF2(W,S_S), \ | |
336 | QLF2(X,S_D), \ | |
337 | QLF2(X,S_S), \ | |
338 | } | |
339 | ||
cb366992 EB |
340 | /* e.g. FMOV <Xd>, <Dn>. */ |
341 | #define QL_FP2INT_FMOV \ | |
342 | { \ | |
343 | QLF2(W,S_S), \ | |
344 | QLF2(X,S_D), \ | |
345 | } | |
346 | ||
622b9eb1 MW |
347 | /* e.g. FCVTNS <Hd>, <Wn>. */ |
348 | #define QL_FP2INT_H \ | |
349 | { \ | |
350 | QLF2 (W, S_H), \ | |
351 | QLF2 (X, S_H), \ | |
352 | } | |
353 | ||
ccfc90a3 SN |
354 | /* e.g. FJCVTZS <Wd>, <Dn>. */ |
355 | #define QL_FP2INT_W_D \ | |
356 | { \ | |
357 | QLF2 (W, S_D), \ | |
358 | } | |
359 | ||
a06ea964 NC |
360 | /* e.g. FMOV <Xd>, <Vn>.D[1]. */ |
361 | #define QL_XVD1 \ | |
362 | { \ | |
363 | QLF2(X,S_D), \ | |
364 | } | |
365 | ||
366 | /* e.g. FMOV <Vd>.D[1], <Xn>. */ | |
367 | #define QL_VD1X \ | |
368 | { \ | |
369 | QLF2(S_D,X), \ | |
370 | } | |
371 | ||
372 | /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ | |
373 | #define QL_EXTR \ | |
374 | { \ | |
375 | QLF4(W,W,W,imm_0_31), \ | |
376 | QLF4(X,X,X,imm_0_63), \ | |
377 | } | |
378 | ||
379 | /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ | |
380 | #define QL_SHIFT \ | |
381 | { \ | |
382 | QLF3(W,W,imm_0_31), \ | |
383 | QLF3(X,X,imm_0_63), \ | |
384 | } | |
385 | ||
386 | /* e.g. UXTH <Xd>, <Wn>. */ | |
387 | #define QL_EXT \ | |
388 | { \ | |
389 | QLF2(W,W), \ | |
390 | QLF2(X,W), \ | |
391 | } | |
392 | ||
393 | /* e.g. UXTW <Xd>, <Wn>. */ | |
394 | #define QL_EXT_W \ | |
395 | { \ | |
396 | QLF2(X,W), \ | |
397 | } | |
398 | ||
399 | /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ | |
400 | #define QL_SSHIFT \ | |
401 | { \ | |
402 | QLF3(S_B , S_B , S_B ), \ | |
403 | QLF3(S_H , S_H , S_H ), \ | |
404 | QLF3(S_S , S_S , S_S ), \ | |
405 | QLF3(S_D , S_D , S_D ) \ | |
406 | } | |
407 | ||
408 | /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ | |
409 | #define QL_SSHIFT_D \ | |
410 | { \ | |
411 | QLF3(S_D , S_D , S_D ) \ | |
412 | } | |
413 | ||
414 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
415 | #define QL_SSHIFT_SD \ | |
416 | { \ | |
417 | QLF3(S_S , S_S , S_S ), \ | |
418 | QLF3(S_D , S_D , S_D ) \ | |
419 | } | |
420 | ||
4fd0a9fd MW |
421 | /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
422 | #define QL_SSHIFT_H \ | |
423 | { \ | |
424 | QLF3 (S_H, S_H, S_H) \ | |
425 | } | |
426 | ||
a06ea964 NC |
427 | /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ |
428 | #define QL_SSHIFTN \ | |
429 | { \ | |
430 | QLF3(S_B , S_H , S_B ), \ | |
431 | QLF3(S_H , S_S , S_H ), \ | |
432 | QLF3(S_S , S_D , S_S ), \ | |
433 | } | |
434 | ||
435 | /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. | |
436 | The register operand variant qualifiers are deliberately used for the | |
437 | immediate operand to ease the operand encoding/decoding and qualifier | |
438 | sequence matching. */ | |
439 | #define QL_VSHIFT \ | |
440 | { \ | |
441 | QLF3(V_8B , V_8B , V_8B ), \ | |
442 | QLF3(V_16B, V_16B, V_16B), \ | |
443 | QLF3(V_4H , V_4H , V_4H ), \ | |
444 | QLF3(V_8H , V_8H , V_8H ), \ | |
445 | QLF3(V_2S , V_2S , V_2S ), \ | |
446 | QLF3(V_4S , V_4S , V_4S ), \ | |
447 | QLF3(V_2D , V_2D , V_2D ) \ | |
448 | } | |
449 | ||
450 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ | |
451 | #define QL_VSHIFT_SD \ | |
452 | { \ | |
453 | QLF3(V_2S , V_2S , V_2S ), \ | |
454 | QLF3(V_4S , V_4S , V_4S ), \ | |
455 | QLF3(V_2D , V_2D , V_2D ) \ | |
456 | } | |
457 | ||
b5b0f34c MW |
458 | /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
459 | #define QL_VSHIFT_H \ | |
460 | { \ | |
461 | QLF3 (V_4H, V_4H, V_4H), \ | |
462 | QLF3 (V_8H, V_8H, V_8H) \ | |
463 | } | |
464 | ||
a06ea964 NC |
465 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ |
466 | #define QL_VSHIFTN \ | |
467 | { \ | |
468 | QLF3(V_8B , V_8H , V_8B ), \ | |
469 | QLF3(V_4H , V_4S , V_4H ), \ | |
470 | QLF3(V_2S , V_2D , V_2S ), \ | |
471 | } | |
472 | ||
473 | /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ | |
474 | #define QL_VSHIFTN2 \ | |
475 | { \ | |
476 | QLF3(V_16B, V_8H, V_16B), \ | |
477 | QLF3(V_8H , V_4S , V_8H ), \ | |
478 | QLF3(V_4S , V_2D , V_4S ), \ | |
479 | } | |
480 | ||
481 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. | |
482 | the 3rd qualifier is used to help the encoding. */ | |
483 | #define QL_VSHIFTL \ | |
484 | { \ | |
485 | QLF3(V_8H , V_8B , V_8B ), \ | |
486 | QLF3(V_4S , V_4H , V_4H ), \ | |
487 | QLF3(V_2D , V_2S , V_2S ), \ | |
488 | } | |
489 | ||
490 | /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
491 | #define QL_VSHIFTL2 \ | |
492 | { \ | |
493 | QLF3(V_8H , V_16B, V_16B), \ | |
494 | QLF3(V_4S , V_8H , V_8H ), \ | |
495 | QLF3(V_2D , V_4S , V_4S ), \ | |
496 | } | |
497 | ||
498 | /* e.g. TBL. */ | |
499 | #define QL_TABLE \ | |
500 | { \ | |
501 | QLF3(V_8B , V_16B, V_8B ), \ | |
502 | QLF3(V_16B, V_16B, V_16B), \ | |
503 | } | |
504 | ||
505 | /* e.g. SHA1H. */ | |
506 | #define QL_2SAMES \ | |
507 | { \ | |
508 | QLF2(S_S, S_S), \ | |
509 | } | |
510 | ||
511 | /* e.g. ABS <V><d>, <V><n>. */ | |
512 | #define QL_2SAMED \ | |
513 | { \ | |
514 | QLF2(S_D, S_D), \ | |
515 | } | |
516 | ||
517 | /* e.g. CMGT <V><d>, <V><n>, #0. */ | |
518 | #define QL_SISD_CMP_0 \ | |
519 | { \ | |
520 | QLF3(S_D, S_D, NIL), \ | |
521 | } | |
522 | ||
523 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ | |
524 | #define QL_SISD_FCMP_0 \ | |
525 | { \ | |
526 | QLF3(S_S, S_S, NIL), \ | |
527 | QLF3(S_D, S_D, NIL), \ | |
528 | } | |
529 | ||
80776b29 MW |
530 | /* e.g. FCMEQ <V><d>, <V><n>, #0. */ |
531 | #define QL_SISD_FCMP_H_0 \ | |
532 | { \ | |
533 | QLF3 (S_H, S_H, NIL), \ | |
534 | } | |
535 | ||
a06ea964 NC |
536 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
537 | #define QL_SISD_PAIR \ | |
538 | { \ | |
539 | QLF2(S_S, V_2S), \ | |
540 | QLF2(S_D, V_2D), \ | |
541 | } | |
542 | ||
b195470d MW |
543 | /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
544 | #define QL_SISD_PAIR_H \ | |
545 | { \ | |
546 | QLF2 (S_H, V_2H), \ | |
547 | } | |
548 | ||
a06ea964 NC |
549 | /* e.g. ADDP <V><d>, <Vn>.<T>. */ |
550 | #define QL_SISD_PAIR_D \ | |
551 | { \ | |
552 | QLF2(S_D, V_2D), \ | |
553 | } | |
554 | ||
555 | /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ | |
556 | #define QL_S_2SAME \ | |
557 | { \ | |
558 | QLF2(S_B, S_B), \ | |
559 | QLF2(S_H, S_H), \ | |
560 | QLF2(S_S, S_S), \ | |
561 | QLF2(S_D, S_D), \ | |
562 | } | |
563 | ||
564 | /* e.g. FCVTNS <V><d>, <V><n>. */ | |
565 | #define QL_S_2SAMESD \ | |
566 | { \ | |
567 | QLF2(S_S, S_S), \ | |
568 | QLF2(S_D, S_D), \ | |
569 | } | |
570 | ||
80776b29 MW |
571 | /* e.g. FCVTNS <V><d>, <V><n>. */ |
572 | #define QL_S_2SAMEH \ | |
573 | { \ | |
574 | QLF2 (S_H, S_H), \ | |
575 | } | |
576 | ||
a06ea964 NC |
577 | /* e.g. SQXTN <Vb><d>, <Va><n>. */ |
578 | #define QL_SISD_NARROW \ | |
579 | { \ | |
580 | QLF2(S_B, S_H), \ | |
581 | QLF2(S_H, S_S), \ | |
582 | QLF2(S_S, S_D), \ | |
583 | } | |
584 | ||
585 | /* e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
586 | #define QL_SISD_NARROW_S \ | |
587 | { \ | |
588 | QLF2(S_S, S_D), \ | |
589 | } | |
590 | ||
591 | /* e.g. FCVT. */ | |
592 | #define QL_FCVT \ | |
593 | { \ | |
594 | QLF2(S_S, S_H), \ | |
595 | QLF2(S_S, S_D), \ | |
596 | QLF2(S_D, S_H), \ | |
597 | QLF2(S_D, S_S), \ | |
598 | QLF2(S_H, S_S), \ | |
599 | QLF2(S_H, S_D), \ | |
600 | } | |
601 | ||
602 | /* FMOV <Dd>, <Dn>. */ | |
603 | #define QL_FP2 \ | |
604 | { \ | |
605 | QLF2(S_S, S_S), \ | |
606 | QLF2(S_D, S_D), \ | |
607 | } | |
608 | ||
622b9eb1 MW |
609 | /* FMOV <Hd>, <Hn>. */ |
610 | #define QL_FP2_H \ | |
611 | { \ | |
612 | QLF2 (S_H, S_H), \ | |
613 | } | |
614 | ||
a06ea964 NC |
615 | /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ |
616 | #define QL_S_3SAME \ | |
617 | { \ | |
618 | QLF3(S_B, S_B, S_B), \ | |
619 | QLF3(S_H, S_H, S_H), \ | |
620 | QLF3(S_S, S_S, S_S), \ | |
621 | QLF3(S_D, S_D, S_D), \ | |
622 | } | |
623 | ||
624 | /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ | |
625 | #define QL_S_3SAMED \ | |
626 | { \ | |
627 | QLF3(S_D, S_D, S_D), \ | |
628 | } | |
629 | ||
630 | /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ | |
631 | #define QL_SISD_HS \ | |
632 | { \ | |
633 | QLF3(S_H, S_H, S_H), \ | |
634 | QLF3(S_S, S_S, S_S), \ | |
635 | } | |
636 | ||
637 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ | |
638 | #define QL_SISDL_HS \ | |
639 | { \ | |
640 | QLF3(S_S, S_H, S_H), \ | |
641 | QLF3(S_D, S_S, S_S), \ | |
642 | } | |
643 | ||
644 | /* FMUL <Sd>, <Sn>, <Sm>. */ | |
645 | #define QL_FP3 \ | |
646 | { \ | |
647 | QLF3(S_S, S_S, S_S), \ | |
648 | QLF3(S_D, S_D, S_D), \ | |
649 | } | |
650 | ||
622b9eb1 MW |
651 | /* FMUL <Hd>, <Hn>, <Hm>. */ |
652 | #define QL_FP3_H \ | |
653 | { \ | |
654 | QLF3 (S_H, S_H, S_H), \ | |
655 | } | |
656 | ||
a06ea964 NC |
657 | /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ |
658 | #define QL_FP4 \ | |
659 | { \ | |
660 | QLF4(S_S, S_S, S_S, S_S), \ | |
661 | QLF4(S_D, S_D, S_D, S_D), \ | |
662 | } | |
663 | ||
622b9eb1 MW |
664 | /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */ |
665 | #define QL_FP4_H \ | |
666 | { \ | |
667 | QLF4 (S_H, S_H, S_H, S_H), \ | |
668 | } | |
669 | ||
a06ea964 NC |
670 | /* e.g. FCMP <Dn>, #0.0. */ |
671 | #define QL_DST_SD \ | |
672 | { \ | |
673 | QLF2(S_S, NIL), \ | |
674 | QLF2(S_D, NIL), \ | |
675 | } | |
676 | ||
622b9eb1 MW |
677 | /* e.g. FCMP <Hn>, #0.0. */ |
678 | #define QL_DST_H \ | |
679 | { \ | |
680 | QLF2 (S_H, NIL), \ | |
681 | } | |
682 | ||
a06ea964 NC |
683 | /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ |
684 | #define QL_FP_COND \ | |
685 | { \ | |
686 | QLF4(S_S, S_S, S_S, NIL), \ | |
687 | QLF4(S_D, S_D, S_D, NIL), \ | |
688 | } | |
689 | ||
622b9eb1 MW |
690 | /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */ |
691 | #define QL_FP_COND_H \ | |
692 | { \ | |
693 | QLF4 (S_H, S_H, S_H, NIL), \ | |
694 | } | |
695 | ||
a06ea964 NC |
696 | /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ |
697 | #define QL_CCMP \ | |
698 | { \ | |
699 | QLF4(W, W, NIL, NIL), \ | |
700 | QLF4(X, X, NIL, NIL), \ | |
701 | } | |
702 | ||
703 | /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ | |
704 | #define QL_CCMP_IMM \ | |
705 | { \ | |
706 | QLF4(W, NIL, NIL, NIL), \ | |
707 | QLF4(X, NIL, NIL, NIL), \ | |
708 | } | |
709 | ||
710 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ | |
711 | #define QL_FCCMP \ | |
712 | { \ | |
713 | QLF4(S_S, S_S, NIL, NIL), \ | |
714 | QLF4(S_D, S_D, NIL, NIL), \ | |
715 | } | |
716 | ||
622b9eb1 MW |
717 | /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ |
718 | #define QL_FCCMP_H \ | |
719 | { \ | |
720 | QLF4 (S_H, S_H, NIL, NIL), \ | |
721 | } | |
722 | ||
a06ea964 NC |
723 | /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ |
724 | #define QL_DUP_VX \ | |
725 | { \ | |
726 | QLF2(V_8B , S_B ), \ | |
727 | QLF2(V_16B, S_B ), \ | |
728 | QLF2(V_4H , S_H ), \ | |
729 | QLF2(V_8H , S_H ), \ | |
730 | QLF2(V_2S , S_S ), \ | |
731 | QLF2(V_4S , S_S ), \ | |
732 | QLF2(V_2D , S_D ), \ | |
733 | } | |
734 | ||
735 | /* e.g. DUP <Vd>.<T>, <Wn>. */ | |
736 | #define QL_DUP_VR \ | |
737 | { \ | |
738 | QLF2(V_8B , W ), \ | |
739 | QLF2(V_16B, W ), \ | |
740 | QLF2(V_4H , W ), \ | |
741 | QLF2(V_8H , W ), \ | |
742 | QLF2(V_2S , W ), \ | |
743 | QLF2(V_4S , W ), \ | |
744 | QLF2(V_2D , X ), \ | |
745 | } | |
746 | ||
747 | /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ | |
748 | #define QL_INS_XR \ | |
749 | { \ | |
750 | QLF2(S_H , W ), \ | |
751 | QLF2(S_S , W ), \ | |
752 | QLF2(S_D , X ), \ | |
753 | QLF2(S_B , W ), \ | |
754 | } | |
755 | ||
756 | /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
757 | #define QL_SMOV \ | |
758 | { \ | |
759 | QLF2(W , S_H), \ | |
760 | QLF2(X , S_H), \ | |
761 | QLF2(X , S_S), \ | |
762 | QLF2(W , S_B), \ | |
763 | QLF2(X , S_B), \ | |
764 | } | |
765 | ||
766 | /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
767 | #define QL_UMOV \ | |
768 | { \ | |
769 | QLF2(W , S_H), \ | |
770 | QLF2(W , S_S), \ | |
771 | QLF2(X , S_D), \ | |
772 | QLF2(W , S_B), \ | |
773 | } | |
774 | ||
775 | /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ | |
776 | #define QL_MOV \ | |
777 | { \ | |
778 | QLF2(W , S_S), \ | |
779 | QLF2(X , S_D), \ | |
780 | } | |
781 | ||
782 | /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ | |
783 | #define QL_V2SAME \ | |
784 | { \ | |
785 | QLF2(V_8B , V_8B ), \ | |
786 | QLF2(V_16B, V_16B), \ | |
787 | QLF2(V_4H , V_4H ), \ | |
788 | QLF2(V_8H , V_8H ), \ | |
789 | QLF2(V_2S , V_2S ), \ | |
790 | QLF2(V_4S , V_4S ), \ | |
791 | QLF2(V_2D , V_2D ), \ | |
792 | } | |
793 | ||
794 | /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ | |
795 | #define QL_V2SAMES \ | |
796 | { \ | |
797 | QLF2(V_2S , V_2S ), \ | |
798 | QLF2(V_4S , V_4S ), \ | |
799 | } | |
800 | ||
801 | /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ | |
802 | #define QL_V2SAMEBH \ | |
803 | { \ | |
804 | QLF2(V_8B , V_8B ), \ | |
805 | QLF2(V_16B, V_16B), \ | |
806 | QLF2(V_4H , V_4H ), \ | |
807 | QLF2(V_8H , V_8H ), \ | |
808 | } | |
809 | ||
810 | /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ | |
811 | #define QL_V2SAMESD \ | |
812 | { \ | |
813 | QLF2(V_2S , V_2S ), \ | |
814 | QLF2(V_4S , V_4S ), \ | |
815 | QLF2(V_2D , V_2D ), \ | |
816 | } | |
817 | ||
818 | /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ | |
819 | #define QL_V2SAMEBHS \ | |
820 | { \ | |
821 | QLF2(V_8B , V_8B ), \ | |
822 | QLF2(V_16B, V_16B), \ | |
823 | QLF2(V_4H , V_4H ), \ | |
824 | QLF2(V_8H , V_8H ), \ | |
825 | QLF2(V_2S , V_2S ), \ | |
826 | QLF2(V_4S , V_4S ), \ | |
827 | } | |
828 | ||
f3aa142b MW |
829 | /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ |
830 | #define QL_V2SAMEH \ | |
831 | { \ | |
832 | QLF2 (V_4H, V_4H), \ | |
833 | QLF2 (V_8H, V_8H), \ | |
834 | } | |
835 | ||
a06ea964 NC |
836 | /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ |
837 | #define QL_V2SAMEB \ | |
838 | { \ | |
839 | QLF2(V_8B , V_8B ), \ | |
840 | QLF2(V_16B, V_16B), \ | |
841 | } | |
842 | ||
843 | /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ | |
844 | #define QL_V2PAIRWISELONGBHS \ | |
845 | { \ | |
846 | QLF2(V_4H , V_8B ), \ | |
847 | QLF2(V_8H , V_16B), \ | |
848 | QLF2(V_2S , V_4H ), \ | |
849 | QLF2(V_4S , V_8H ), \ | |
850 | QLF2(V_1D , V_2S ), \ | |
851 | QLF2(V_2D , V_4S ), \ | |
852 | } | |
853 | ||
854 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
855 | #define QL_V2LONGBHS \ | |
856 | { \ | |
857 | QLF2(V_8H , V_8B ), \ | |
858 | QLF2(V_4S , V_4H ), \ | |
859 | QLF2(V_2D , V_2S ), \ | |
860 | } | |
861 | ||
862 | /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ | |
863 | #define QL_V2LONGBHS2 \ | |
864 | { \ | |
865 | QLF2(V_8H , V_16B), \ | |
866 | QLF2(V_4S , V_8H ), \ | |
867 | QLF2(V_2D , V_4S ), \ | |
868 | } | |
869 | ||
870 | /* */ | |
871 | #define QL_V3SAME \ | |
872 | { \ | |
873 | QLF3(V_8B , V_8B , V_8B ), \ | |
874 | QLF3(V_16B, V_16B, V_16B), \ | |
875 | QLF3(V_4H , V_4H , V_4H ), \ | |
876 | QLF3(V_8H , V_8H , V_8H ), \ | |
877 | QLF3(V_2S , V_2S , V_2S ), \ | |
878 | QLF3(V_4S , V_4S , V_4S ), \ | |
879 | QLF3(V_2D , V_2D , V_2D ) \ | |
880 | } | |
881 | ||
882 | /* e.g. SHADD. */ | |
883 | #define QL_V3SAMEBHS \ | |
884 | { \ | |
885 | QLF3(V_8B , V_8B , V_8B ), \ | |
886 | QLF3(V_16B, V_16B, V_16B), \ | |
887 | QLF3(V_4H , V_4H , V_4H ), \ | |
888 | QLF3(V_8H , V_8H , V_8H ), \ | |
889 | QLF3(V_2S , V_2S , V_2S ), \ | |
890 | QLF3(V_4S , V_4S , V_4S ), \ | |
891 | } | |
892 | ||
893 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
894 | #define QL_V2NARRS \ | |
895 | { \ | |
896 | QLF2(V_2S , V_2D ), \ | |
897 | } | |
898 | ||
899 | /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
900 | #define QL_V2NARRS2 \ | |
901 | { \ | |
902 | QLF2(V_4S , V_2D ), \ | |
903 | } | |
904 | ||
905 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
906 | #define QL_V2NARRHS \ | |
907 | { \ | |
908 | QLF2(V_4H , V_4S ), \ | |
909 | QLF2(V_2S , V_2D ), \ | |
910 | } | |
911 | ||
912 | /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
913 | #define QL_V2NARRHS2 \ | |
914 | { \ | |
915 | QLF2(V_8H , V_4S ), \ | |
916 | QLF2(V_4S , V_2D ), \ | |
917 | } | |
918 | ||
919 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
920 | #define QL_V2LONGHS \ | |
921 | { \ | |
922 | QLF2(V_4S , V_4H ), \ | |
923 | QLF2(V_2D , V_2S ), \ | |
924 | } | |
925 | ||
926 | /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
927 | #define QL_V2LONGHS2 \ | |
928 | { \ | |
929 | QLF2(V_4S , V_8H ), \ | |
930 | QLF2(V_2D , V_4S ), \ | |
931 | } | |
932 | ||
933 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
934 | #define QL_V2NARRBHS \ | |
935 | { \ | |
936 | QLF2(V_8B , V_8H ), \ | |
937 | QLF2(V_4H , V_4S ), \ | |
938 | QLF2(V_2S , V_2D ), \ | |
939 | } | |
940 | ||
941 | /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
942 | #define QL_V2NARRBHS2 \ | |
943 | { \ | |
944 | QLF2(V_16B, V_8H ), \ | |
945 | QLF2(V_8H , V_4S ), \ | |
946 | QLF2(V_4S , V_2D ), \ | |
947 | } | |
948 | ||
949 | /* e.g. ORR. */ | |
950 | #define QL_V2SAMEB \ | |
951 | { \ | |
952 | QLF2(V_8B , V_8B ), \ | |
953 | QLF2(V_16B, V_16B), \ | |
954 | } | |
955 | ||
956 | /* e.g. AESE. */ | |
957 | #define QL_V2SAME16B \ | |
958 | { \ | |
959 | QLF2(V_16B, V_16B), \ | |
960 | } | |
961 | ||
962 | /* e.g. SHA1SU1. */ | |
963 | #define QL_V2SAME4S \ | |
964 | { \ | |
965 | QLF2(V_4S, V_4S), \ | |
966 | } | |
967 | ||
968 | /* e.g. SHA1SU0. */ | |
969 | #define QL_V3SAME4S \ | |
970 | { \ | |
971 | QLF3(V_4S, V_4S, V_4S), \ | |
972 | } | |
973 | ||
974 | /* e.g. SHADD. */ | |
975 | #define QL_V3SAMEB \ | |
976 | { \ | |
977 | QLF3(V_8B , V_8B , V_8B ), \ | |
978 | QLF3(V_16B, V_16B, V_16B), \ | |
979 | } | |
980 | ||
981 | /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ | |
982 | #define QL_VEXT \ | |
983 | { \ | |
984 | QLF4(V_8B , V_8B , V_8B , imm_0_7), \ | |
985 | QLF4(V_16B, V_16B, V_16B, imm_0_15), \ | |
986 | } | |
987 | ||
988 | /* e.g. . */ | |
989 | #define QL_V3SAMEHS \ | |
990 | { \ | |
991 | QLF3(V_4H , V_4H , V_4H ), \ | |
992 | QLF3(V_8H , V_8H , V_8H ), \ | |
993 | QLF3(V_2S , V_2S , V_2S ), \ | |
994 | QLF3(V_4S , V_4S , V_4S ), \ | |
995 | } | |
996 | ||
997 | /* */ | |
998 | #define QL_V3SAMESD \ | |
999 | { \ | |
1000 | QLF3(V_2S , V_2S , V_2S ), \ | |
1001 | QLF3(V_4S , V_4S , V_4S ), \ | |
1002 | QLF3(V_2D , V_2D , V_2D ) \ | |
1003 | } | |
1004 | ||
c2c4ff8d SN |
1005 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */ |
1006 | #define QL_V3SAMEHSD_ROT \ | |
1007 | { \ | |
1008 | QLF4 (V_4H, V_4H, V_4H, NIL), \ | |
1009 | QLF4 (V_8H, V_8H, V_8H, NIL), \ | |
1010 | QLF4 (V_2S, V_2S, V_2S, NIL), \ | |
1011 | QLF4 (V_4S, V_4S, V_4S, NIL), \ | |
1012 | QLF4 (V_2D, V_2D, V_2D, NIL), \ | |
1013 | } | |
1014 | ||
51d543ed MW |
1015 | /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */ |
1016 | #define QL_V3SAMEH \ | |
1017 | { \ | |
1018 | QLF3 (V_4H , V_4H , V_4H ), \ | |
1019 | QLF3 (V_8H , V_8H , V_8H ), \ | |
1020 | } | |
1021 | ||
a06ea964 NC |
1022 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
1023 | #define QL_V3LONGHS \ | |
1024 | { \ | |
1025 | QLF3(V_4S , V_4H , V_4H ), \ | |
1026 | QLF3(V_2D , V_2S , V_2S ), \ | |
1027 | } | |
1028 | ||
1029 | /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
1030 | #define QL_V3LONGHS2 \ | |
1031 | { \ | |
1032 | QLF3(V_4S , V_8H , V_8H ), \ | |
1033 | QLF3(V_2D , V_4S , V_4S ), \ | |
1034 | } | |
1035 | ||
1036 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
1037 | #define QL_V3LONGBHS \ | |
1038 | { \ | |
1039 | QLF3(V_8H , V_8B , V_8B ), \ | |
1040 | QLF3(V_4S , V_4H , V_4H ), \ | |
1041 | QLF3(V_2D , V_2S , V_2S ), \ | |
1042 | } | |
1043 | ||
1044 | /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ | |
1045 | #define QL_V3LONGBHS2 \ | |
1046 | { \ | |
1047 | QLF3(V_8H , V_16B , V_16B ), \ | |
1048 | QLF3(V_4S , V_8H , V_8H ), \ | |
1049 | QLF3(V_2D , V_4S , V_4S ), \ | |
1050 | } | |
1051 | ||
1052 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
1053 | #define QL_V3WIDEBHS \ | |
1054 | { \ | |
1055 | QLF3(V_8H , V_8H , V_8B ), \ | |
1056 | QLF3(V_4S , V_4S , V_4H ), \ | |
1057 | QLF3(V_2D , V_2D , V_2S ), \ | |
1058 | } | |
1059 | ||
1060 | /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ | |
1061 | #define QL_V3WIDEBHS2 \ | |
1062 | { \ | |
1063 | QLF3(V_8H , V_8H , V_16B ), \ | |
1064 | QLF3(V_4S , V_4S , V_8H ), \ | |
1065 | QLF3(V_2D , V_2D , V_4S ), \ | |
1066 | } | |
1067 | ||
1068 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
1069 | #define QL_V3NARRBHS \ | |
1070 | { \ | |
1071 | QLF3(V_8B , V_8H , V_8H ), \ | |
1072 | QLF3(V_4H , V_4S , V_4S ), \ | |
1073 | QLF3(V_2S , V_2D , V_2D ), \ | |
1074 | } | |
1075 | ||
1076 | /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ | |
1077 | #define QL_V3NARRBHS2 \ | |
1078 | { \ | |
1079 | QLF3(V_16B , V_8H , V_8H ), \ | |
1080 | QLF3(V_8H , V_4S , V_4S ), \ | |
1081 | QLF3(V_4S , V_2D , V_2D ), \ | |
1082 | } | |
1083 | ||
1084 | /* e.g. PMULL. */ | |
1085 | #define QL_V3LONGB \ | |
1086 | { \ | |
1087 | QLF3(V_8H , V_8B , V_8B ), \ | |
1088 | } | |
1089 | ||
1090 | /* e.g. PMULL crypto. */ | |
1091 | #define QL_V3LONGD \ | |
1092 | { \ | |
1093 | QLF3(V_1Q , V_1D , V_1D ), \ | |
1094 | } | |
1095 | ||
1096 | /* e.g. PMULL2. */ | |
1097 | #define QL_V3LONGB2 \ | |
1098 | { \ | |
1099 | QLF3(V_8H , V_16B, V_16B), \ | |
1100 | } | |
1101 | ||
1102 | /* e.g. PMULL2 crypto. */ | |
1103 | #define QL_V3LONGD2 \ | |
1104 | { \ | |
1105 | QLF3(V_1Q , V_2D , V_2D ), \ | |
1106 | } | |
1107 | ||
1108 | /* e.g. SHA1C. */ | |
1109 | #define QL_SHAUPT \ | |
1110 | { \ | |
1111 | QLF3(S_Q, S_S, V_4S), \ | |
1112 | } | |
1113 | ||
1114 | /* e.g. SHA256H2. */ | |
1115 | #define QL_SHA256UPT \ | |
1116 | { \ | |
1117 | QLF3(S_Q, S_Q, V_4S), \ | |
1118 | } | |
1119 | ||
1120 | /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ | |
1121 | #define QL_W1_LDST_EXC \ | |
1122 | { \ | |
1123 | QLF2(W, NIL), \ | |
1124 | } | |
1125 | ||
1126 | /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ | |
1127 | #define QL_R1NIL \ | |
1128 | { \ | |
1129 | QLF2(W, NIL), \ | |
1130 | QLF2(X, NIL), \ | |
1131 | } | |
1132 | ||
1133 | /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
1134 | #define QL_W2_LDST_EXC \ | |
1135 | { \ | |
1136 | QLF3(W, W, NIL), \ | |
1137 | } | |
1138 | ||
1139 | /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ | |
1140 | #define QL_R2_LDST_EXC \ | |
1141 | { \ | |
1142 | QLF3(W, W, NIL), \ | |
1143 | QLF3(W, X, NIL), \ | |
1144 | } | |
1145 | ||
fd65497d PW |
1146 | /* e.g. ST64B <Xs>, <Xt>, [<Xn|SP>]. */ |
1147 | #define QL_X2NIL \ | |
1148 | { \ | |
1149 | QLF3(X, X, NIL), \ | |
1150 | } | |
1151 | ||
3f06e550 SN |
1152 | /* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */ |
1153 | #define QL_X1NIL \ | |
1154 | { \ | |
1155 | QLF2(X, NIL), \ | |
1156 | } | |
1157 | ||
a06ea964 NC |
1158 | /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
1159 | #define QL_R2NIL \ | |
1160 | { \ | |
1161 | QLF3(W, W, NIL), \ | |
1162 | QLF3(X, X, NIL), \ | |
1163 | } | |
1164 | ||
ee804238 JW |
1165 | /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ |
1166 | #define QL_R4NIL \ | |
1167 | { \ | |
1168 | QLF5(W, W, W, W, NIL), \ | |
1169 | QLF5(X, X, X, X, NIL), \ | |
1170 | } | |
1171 | ||
a06ea964 NC |
1172 | /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
1173 | #define QL_R3_LDST_EXC \ | |
1174 | { \ | |
1175 | QLF4(W, W, W, NIL), \ | |
1176 | QLF4(W, X, X, NIL), \ | |
1177 | } | |
1178 | ||
1179 | /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1180 | #define QL_LDST_FP \ | |
1181 | { \ | |
1182 | QLF2(S_B, S_B), \ | |
1183 | QLF2(S_H, S_H), \ | |
1184 | QLF2(S_S, S_S), \ | |
1185 | QLF2(S_D, S_D), \ | |
1186 | QLF2(S_Q, S_Q), \ | |
1187 | } | |
1188 | ||
1189 | /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1190 | #define QL_LDST_R \ | |
1191 | { \ | |
1192 | QLF2(W, S_S), \ | |
1193 | QLF2(X, S_D), \ | |
1194 | } | |
1195 | ||
1196 | /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1197 | #define QL_LDST_W8 \ | |
1198 | { \ | |
1199 | QLF2(W, S_B), \ | |
1200 | } | |
1201 | ||
1202 | /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1203 | #define QL_LDST_R8 \ | |
1204 | { \ | |
1205 | QLF2(W, S_B), \ | |
1206 | QLF2(X, S_B), \ | |
1207 | } | |
1208 | ||
1209 | /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1210 | #define QL_LDST_W16 \ | |
1211 | { \ | |
1212 | QLF2(W, S_H), \ | |
1213 | } | |
1214 | ||
1215 | /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1216 | #define QL_LDST_X32 \ | |
1217 | { \ | |
1218 | QLF2(X, S_S), \ | |
1219 | } | |
1220 | ||
1221 | /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1222 | #define QL_LDST_R16 \ | |
1223 | { \ | |
1224 | QLF2(W, S_H), \ | |
1225 | QLF2(X, S_H), \ | |
1226 | } | |
1227 | ||
1228 | /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
1229 | #define QL_LDST_PRFM \ | |
1230 | { \ | |
1231 | QLF2(NIL, S_D), \ | |
1232 | } | |
1233 | ||
e6025b54 SD |
1234 | /* e.g. LDG <Xt>, [<Xn|SP>{, #<simm>}]. */ |
1235 | #define QL_LDG \ | |
1236 | { \ | |
1237 | QLF2(X, imm_tag), \ | |
1238 | } | |
1239 | ||
a06ea964 NC |
1240 | /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ |
1241 | #define QL_LDST_PAIR_X32 \ | |
1242 | { \ | |
1243 | QLF3(X, X, S_S), \ | |
1244 | } | |
1245 | ||
fb3265b3 SD |
1246 | /* e.g. STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ |
1247 | #define QL_STGP \ | |
1248 | { \ | |
1249 | QLF3(X, X, imm_tag), \ | |
1250 | } | |
1251 | ||
a06ea964 NC |
1252 | /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ |
1253 | #define QL_LDST_PAIR_R \ | |
1254 | { \ | |
1255 | QLF3(W, W, S_S), \ | |
1256 | QLF3(X, X, S_D), \ | |
1257 | } | |
1258 | ||
1259 | /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ | |
1260 | #define QL_LDST_PAIR_FP \ | |
1261 | { \ | |
1262 | QLF3(S_S, S_S, S_S), \ | |
1263 | QLF3(S_D, S_D, S_D), \ | |
1264 | QLF3(S_Q, S_Q, S_Q), \ | |
1265 | } | |
1266 | ||
1267 | /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
1268 | #define QL_SIMD_LDST \ | |
1269 | { \ | |
1270 | QLF2(V_8B, NIL), \ | |
1271 | QLF2(V_16B, NIL), \ | |
1272 | QLF2(V_4H, NIL), \ | |
1273 | QLF2(V_8H, NIL), \ | |
1274 | QLF2(V_2S, NIL), \ | |
1275 | QLF2(V_4S, NIL), \ | |
1276 | QLF2(V_2D, NIL), \ | |
1277 | } | |
1278 | ||
1279 | /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ | |
1280 | #define QL_SIMD_LDST_ANY \ | |
1281 | { \ | |
1282 | QLF2(V_8B, NIL), \ | |
1283 | QLF2(V_16B, NIL), \ | |
1284 | QLF2(V_4H, NIL), \ | |
1285 | QLF2(V_8H, NIL), \ | |
1286 | QLF2(V_2S, NIL), \ | |
1287 | QLF2(V_4S, NIL), \ | |
1288 | QLF2(V_1D, NIL), \ | |
1289 | QLF2(V_2D, NIL), \ | |
1290 | } | |
1291 | ||
1292 | /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ | |
1293 | #define QL_SIMD_LDSTONE \ | |
1294 | { \ | |
1295 | QLF2(S_B, NIL), \ | |
1296 | QLF2(S_H, NIL), \ | |
1297 | QLF2(S_S, NIL), \ | |
1298 | QLF2(S_D, NIL), \ | |
1299 | } | |
1300 | ||
1301 | /* e.g. ADDV <V><d>, <Vn>.<T>. */ | |
1302 | #define QL_XLANES \ | |
1303 | { \ | |
1304 | QLF2(S_B, V_8B), \ | |
1305 | QLF2(S_B, V_16B), \ | |
1306 | QLF2(S_H, V_4H), \ | |
1307 | QLF2(S_H, V_8H), \ | |
1308 | QLF2(S_S, V_4S), \ | |
1309 | } | |
1310 | ||
1311 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ | |
1312 | #define QL_XLANES_FP \ | |
1313 | { \ | |
1314 | QLF2(S_S, V_4S), \ | |
1315 | } | |
1316 | ||
bb515fea MW |
1317 | /* e.g. FMINV <V><d>, <Vn>.<T>. */ |
1318 | #define QL_XLANES_FP_H \ | |
1319 | { \ | |
1320 | QLF2 (S_H, V_4H), \ | |
1321 | QLF2 (S_H, V_8H), \ | |
1322 | } | |
1323 | ||
a06ea964 NC |
1324 | /* e.g. SADDLV <V><d>, <Vn>.<T>. */ |
1325 | #define QL_XLANES_L \ | |
1326 | { \ | |
1327 | QLF2(S_H, V_8B), \ | |
1328 | QLF2(S_H, V_16B), \ | |
1329 | QLF2(S_S, V_4H), \ | |
1330 | QLF2(S_S, V_8H), \ | |
1331 | QLF2(S_D, V_4S), \ | |
1332 | } | |
1333 | ||
1334 | /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ | |
1335 | #define QL_ELEMENT \ | |
1336 | { \ | |
1337 | QLF3(V_4H, V_4H, S_H), \ | |
1338 | QLF3(V_8H, V_8H, S_H), \ | |
1339 | QLF3(V_2S, V_2S, S_S), \ | |
1340 | QLF3(V_4S, V_4S, S_S), \ | |
1341 | } | |
1342 | ||
1343 | /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
1344 | #define QL_ELEMENT_L \ | |
1345 | { \ | |
1346 | QLF3(V_4S, V_4H, S_H), \ | |
1347 | QLF3(V_2D, V_2S, S_S), \ | |
1348 | } | |
1349 | ||
1350 | /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ | |
1351 | #define QL_ELEMENT_L2 \ | |
1352 | { \ | |
1353 | QLF3(V_4S, V_8H, S_H), \ | |
1354 | QLF3(V_2D, V_4S, S_S), \ | |
1355 | } | |
1356 | ||
1357 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ | |
1358 | #define QL_ELEMENT_FP \ | |
1359 | { \ | |
1360 | QLF3(V_2S, V_2S, S_S), \ | |
1361 | QLF3(V_4S, V_4S, S_S), \ | |
1362 | QLF3(V_2D, V_2D, S_D), \ | |
1363 | } | |
1364 | ||
42f23f62 MW |
1365 | /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ |
1366 | #define QL_ELEMENT_FP_H \ | |
1367 | { \ | |
1368 | QLF3 (V_4H, V_4H, S_H), \ | |
1369 | QLF3 (V_8H, V_8H, S_H), \ | |
1370 | } | |
1371 | ||
c2c4ff8d SN |
1372 | /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>. */ |
1373 | #define QL_ELEMENT_ROT \ | |
1374 | { \ | |
1375 | QLF4 (V_4H, V_4H, S_H, NIL), \ | |
1376 | QLF4 (V_8H, V_8H, S_H, NIL), \ | |
1377 | QLF4 (V_4S, V_4S, S_S, NIL), \ | |
1378 | } | |
1379 | ||
a06ea964 NC |
1380 | /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ |
1381 | #define QL_SIMD_IMM_S0W \ | |
1382 | { \ | |
1383 | QLF2(V_2S, LSL), \ | |
1384 | QLF2(V_4S, LSL), \ | |
1385 | } | |
1386 | ||
1387 | /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ | |
1388 | #define QL_SIMD_IMM_S1W \ | |
1389 | { \ | |
1390 | QLF2(V_2S, MSL), \ | |
1391 | QLF2(V_4S, MSL), \ | |
1392 | } | |
1393 | ||
1394 | /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ | |
1395 | #define QL_SIMD_IMM_S0H \ | |
1396 | { \ | |
1397 | QLF2(V_4H, LSL), \ | |
1398 | QLF2(V_8H, LSL), \ | |
1399 | } | |
1400 | ||
1401 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ | |
1402 | #define QL_SIMD_IMM_S \ | |
1403 | { \ | |
1404 | QLF2(V_2S, NIL), \ | |
1405 | QLF2(V_4S, NIL), \ | |
1406 | } | |
1407 | ||
f5555712 | 1408 | /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ |
a06ea964 NC |
1409 | #define QL_SIMD_IMM_B \ |
1410 | { \ | |
f5555712 YZ |
1411 | QLF2(V_8B, LSL), \ |
1412 | QLF2(V_16B, LSL), \ | |
a06ea964 NC |
1413 | } |
1414 | /* e.g. MOVI <Dd>, #<imm>. */ | |
1415 | #define QL_SIMD_IMM_D \ | |
1416 | { \ | |
1417 | QLF2(S_D, NIL), \ | |
1418 | } | |
1419 | ||
4b5fc357 MW |
1420 | /* e.g. FMOV <Vd>.<T>, #<imm>. */ |
1421 | #define QL_SIMD_IMM_H \ | |
1422 | { \ | |
1423 | QLF2 (V_4H, NIL), \ | |
1424 | QLF2 (V_8H, NIL), \ | |
1425 | } | |
1426 | ||
a06ea964 NC |
1427 | /* e.g. MOVI <Vd>.2D, #<imm>. */ |
1428 | #define QL_SIMD_IMM_V2D \ | |
1429 | { \ | |
1430 | QLF2(V_2D, NIL), \ | |
1431 | } | |
c0890d26 RS |
1432 | |
1433 | /* The naming convention for SVE macros is: | |
1434 | ||
1435 | OP_SVE_<operands>[_<sizes>]* | |
1436 | ||
1437 | <operands> contains one character per operand, using the following scheme: | |
1438 | ||
1439 | - U: the operand is unqualified (NIL). | |
1440 | ||
56723f69 RS |
1441 | - [BHSDQ]: the operand has a S_[BHSDQ] qualifier and the choice of |
1442 | qualifier is the same for all variants. This is used for: | |
1443 | ||
1444 | - .[BHSDQ] suffixes on an SVE vector or predicate | |
1445 | - .[BHSDQ] suffixes on an SME ZA operand | |
1446 | - vector registers and scalar FPRs of the form [BHSDQ]<number> | |
c0890d26 RS |
1447 | |
1448 | - [WX]: the operand has a [WX] qualifier and the choice of qualifier | |
1449 | is the same for all variants. | |
1450 | ||
1451 | - [ZM]: the operand has a /[ZM] suffix and the choice of suffix | |
1452 | is the same for all variants. | |
1453 | ||
1454 | - V: the operand has a S_[BHSD] qualifier and the choice of qualifier | |
56723f69 RS |
1455 | is not the same for all variants. This is used for the same kinds |
1456 | of operand as [BHSDQ] above. | |
c0890d26 RS |
1457 | |
1458 | - R: the operand has a [WX] qualifier and the choice of qualifier is | |
1459 | not the same for all variants. | |
1460 | ||
1461 | - P: the operand has a /[ZM] suffix and the choice of suffix is not | |
1462 | the same for all variants. | |
1463 | ||
1464 | The _<sizes>, if present, give the subset of [BHSD] that are accepted | |
1465 | by the V entries in <operands>. */ | |
1466 | #define OP_SVE_B \ | |
1467 | { \ | |
1468 | QLF1(S_B), \ | |
1469 | } | |
1470 | #define OP_SVE_BB \ | |
1471 | { \ | |
1472 | QLF2(S_B,S_B), \ | |
1473 | } | |
42e6288f MM |
1474 | #define OP_SVE_BBU \ |
1475 | { \ | |
1476 | QLF3(S_B,S_B,NIL), \ | |
1477 | } | |
1478 | #define OP_SVE_BBB \ | |
1479 | { \ | |
1480 | QLF3(S_B,S_B,S_B), \ | |
1481 | } | |
c0890d26 RS |
1482 | #define OP_SVE_BBBU \ |
1483 | { \ | |
1484 | QLF4(S_B,S_B,S_B,NIL), \ | |
1485 | } | |
1486 | #define OP_SVE_BMB \ | |
1487 | { \ | |
1488 | QLF3(S_B,P_M,S_B), \ | |
1489 | } | |
1490 | #define OP_SVE_BPB \ | |
1491 | { \ | |
1492 | QLF3(S_B,P_Z,S_B), \ | |
1493 | QLF3(S_B,P_M,S_B), \ | |
1494 | } | |
1495 | #define OP_SVE_BUB \ | |
1496 | { \ | |
1497 | QLF3(S_B,NIL,S_B), \ | |
1498 | } | |
1499 | #define OP_SVE_BUBB \ | |
1500 | { \ | |
1501 | QLF4(S_B,NIL,S_B,S_B), \ | |
1502 | } | |
1503 | #define OP_SVE_BUU \ | |
1504 | { \ | |
1505 | QLF3(S_B,NIL,NIL), \ | |
1506 | } | |
1507 | #define OP_SVE_BZ \ | |
1508 | { \ | |
1509 | QLF2(S_B,P_Z), \ | |
1510 | } | |
1511 | #define OP_SVE_BZB \ | |
1512 | { \ | |
1513 | QLF3(S_B,P_Z,S_B), \ | |
1514 | } | |
d3de0860 PW |
1515 | #define OP_SVE_NN_BHSD \ |
1516 | { \ | |
1517 | QLF3(NIL,NIL,S_B), \ | |
1518 | QLF3(NIL,NIL,S_H), \ | |
1519 | QLF3(NIL,NIL,S_S), \ | |
1520 | QLF3(NIL,NIL,S_D) \ | |
1521 | } | |
c0890d26 RS |
1522 | #define OP_SVE_BZBB \ |
1523 | { \ | |
1524 | QLF4(S_B,P_Z,S_B,S_B), \ | |
1525 | } | |
1526 | #define OP_SVE_BZU \ | |
1527 | { \ | |
1528 | QLF3(S_B,P_Z,NIL), \ | |
1529 | } | |
1530 | #define OP_SVE_DD \ | |
1531 | { \ | |
1532 | QLF2(S_D,S_D), \ | |
1533 | } | |
1534 | #define OP_SVE_DDD \ | |
1535 | { \ | |
1536 | QLF3(S_D,S_D,S_D), \ | |
1537 | } | |
a8cb21aa RS |
1538 | #define OP_SVE_DHH \ |
1539 | { \ | |
1540 | QLF3(S_D,S_H,S_H), \ | |
1541 | } | |
56723f69 RS |
1542 | #define OP_SVE_DMMD \ |
1543 | { \ | |
1544 | QLF4(S_D,P_M,P_M,S_D), \ | |
1545 | } | |
1546 | #define OP_SVE_DMMDD \ | |
1547 | { \ | |
1548 | QLF5(S_D,P_M,P_M,S_D,S_D) \ | |
1549 | } | |
1550 | #define OP_SVE_DMMHH \ | |
1551 | { \ | |
1552 | QLF5(S_D,P_M,P_M,S_H,S_H) \ | |
1553 | } | |
42e6288f MM |
1554 | #define OP_SVE_DDDD \ |
1555 | { \ | |
1556 | QLF4(S_D,S_D,S_D,S_D), \ | |
1557 | } | |
c0890d26 RS |
1558 | #define OP_SVE_DMD \ |
1559 | { \ | |
1560 | QLF3(S_D,P_M,S_D), \ | |
1561 | } | |
1562 | #define OP_SVE_DMH \ | |
1563 | { \ | |
1564 | QLF3(S_D,P_M,S_H), \ | |
1565 | } | |
1566 | #define OP_SVE_DMS \ | |
1567 | { \ | |
1568 | QLF3(S_D,P_M,S_S), \ | |
1569 | } | |
1570 | #define OP_SVE_DU \ | |
1571 | { \ | |
1572 | QLF2(S_D,NIL), \ | |
1573 | } | |
1574 | #define OP_SVE_DUD \ | |
1575 | { \ | |
1576 | QLF3(S_D,NIL,S_D), \ | |
1577 | } | |
1578 | #define OP_SVE_DUU \ | |
1579 | { \ | |
1580 | QLF3(S_D,NIL,NIL), \ | |
1581 | } | |
1582 | #define OP_SVE_DUV_BHS \ | |
1583 | { \ | |
1584 | QLF3(S_D,NIL,S_B), \ | |
1585 | QLF3(S_D,NIL,S_H), \ | |
1586 | QLF3(S_D,NIL,S_S), \ | |
1587 | } | |
1588 | #define OP_SVE_DUV_BHSD \ | |
1589 | { \ | |
1590 | QLF3(S_D,NIL,S_B), \ | |
1591 | QLF3(S_D,NIL,S_H), \ | |
1592 | QLF3(S_D,NIL,S_S), \ | |
1593 | QLF3(S_D,NIL,S_D), \ | |
1594 | } | |
1595 | #define OP_SVE_DZD \ | |
1596 | { \ | |
1597 | QLF3(S_D,P_Z,S_D), \ | |
1598 | } | |
1599 | #define OP_SVE_DZU \ | |
1600 | { \ | |
1601 | QLF3(S_D,P_Z,NIL), \ | |
1602 | } | |
1603 | #define OP_SVE_HB \ | |
1604 | { \ | |
1605 | QLF2(S_H,S_B), \ | |
1606 | } | |
42e6288f MM |
1607 | #define OP_SVE_HHH \ |
1608 | { \ | |
1609 | QLF3(S_H,S_H,S_H), \ | |
1610 | } | |
1611 | #define OP_SVE_HHHU \ | |
1612 | { \ | |
1613 | QLF4(S_H,S_H,S_H,NIL), \ | |
1614 | } | |
582e12bf RS |
1615 | #define OP_SVE_HMH \ |
1616 | { \ | |
1617 | QLF3(S_H,P_M,S_H), \ | |
1618 | } | |
c0890d26 RS |
1619 | #define OP_SVE_HMD \ |
1620 | { \ | |
1621 | QLF3(S_H,P_M,S_D), \ | |
1622 | } | |
1623 | #define OP_SVE_HMS \ | |
1624 | { \ | |
1625 | QLF3(S_H,P_M,S_S), \ | |
1626 | } | |
c04965ec RS |
1627 | #define OP_SVE_HS \ |
1628 | { \ | |
1629 | QLF2(S_H,S_S), \ | |
1630 | } | |
6efa6601 RS |
1631 | #define OP_SVE_HSU \ |
1632 | { \ | |
1633 | QLF3(S_H,S_S,NIL), \ | |
1634 | } | |
c0890d26 RS |
1635 | #define OP_SVE_HU \ |
1636 | { \ | |
1637 | QLF2(S_H,NIL), \ | |
1638 | } | |
1639 | #define OP_SVE_HUU \ | |
1640 | { \ | |
1641 | QLF3(S_H,NIL,NIL), \ | |
1642 | } | |
1643 | #define OP_SVE_HZU \ | |
1644 | { \ | |
1645 | QLF3(S_H,P_Z,NIL), \ | |
1646 | } | |
d09b87e0 RS |
1647 | #define OP_SVE_QMQ \ |
1648 | { \ | |
1649 | QLF3(S_Q,P_M,S_Q), \ | |
1650 | } | |
7bd1d20e RS |
1651 | #define OP_SVE_QQ \ |
1652 | { \ | |
1653 | QLF2(S_Q,S_Q), \ | |
1654 | } | |
d09b87e0 RS |
1655 | #define OP_SVE_QQQ \ |
1656 | { \ | |
1657 | QLF3(S_Q,S_Q,S_Q), \ | |
1658 | } | |
1659 | #define OP_SVE_QUU \ | |
1660 | { \ | |
1661 | QLF3(S_Q,NIL,NIL), \ | |
1662 | } | |
1663 | #define OP_SVE_QZU \ | |
1664 | { \ | |
1665 | QLF3(S_Q,P_Z,NIL), \ | |
1666 | } | |
c0890d26 RS |
1667 | #define OP_SVE_RR \ |
1668 | { \ | |
1669 | QLF2(W,W), \ | |
1670 | QLF2(X,X), \ | |
1671 | } | |
1672 | #define OP_SVE_RURV_BHSD \ | |
1673 | { \ | |
1674 | QLF4(W,NIL,W,S_B), \ | |
1675 | QLF4(W,NIL,W,S_H), \ | |
1676 | QLF4(W,NIL,W,S_S), \ | |
1677 | QLF4(X,NIL,X,S_D), \ | |
1678 | } | |
1679 | #define OP_SVE_RUV_BHSD \ | |
1680 | { \ | |
1681 | QLF3(W,NIL,S_B), \ | |
1682 | QLF3(W,NIL,S_H), \ | |
1683 | QLF3(W,NIL,S_S), \ | |
1684 | QLF3(X,NIL,S_D), \ | |
1685 | } | |
1686 | #define OP_SVE_SMD \ | |
1687 | { \ | |
1688 | QLF3(S_S,P_M,S_D), \ | |
1689 | } | |
56723f69 RS |
1690 | #define OP_SVE_SMMBB \ |
1691 | { \ | |
1692 | QLF5(S_S,P_M,P_M,S_B,S_B) \ | |
1693 | } | |
1694 | #define OP_SVE_SMMHH \ | |
1695 | { \ | |
1696 | QLF5(S_S,P_M,P_M,S_H,S_H), \ | |
1697 | } | |
1698 | #define OP_SVE_SMMS \ | |
1699 | { \ | |
1700 | QLF4(S_S,P_M,P_M,S_S), \ | |
1701 | } | |
1702 | #define OP_SVE_SMMSS \ | |
1703 | { \ | |
1704 | QLF5(S_S,P_M,P_M,S_S,S_S) \ | |
1705 | } | |
42e6288f MM |
1706 | #define OP_SVE_SSS \ |
1707 | { \ | |
1708 | QLF3(S_S,S_S,S_S), \ | |
1709 | } | |
1710 | #define OP_SVE_SSSU \ | |
1711 | { \ | |
1712 | QLF4(S_S,S_S,S_S,NIL), \ | |
1713 | } | |
c0890d26 RS |
1714 | #define OP_SVE_SMH \ |
1715 | { \ | |
1716 | QLF3(S_S,P_M,S_H), \ | |
1717 | } | |
42e6288f MM |
1718 | #define OP_SVE_SHH \ |
1719 | { \ | |
1720 | QLF3(S_S,S_H,S_H), \ | |
1721 | } | |
c0890d26 RS |
1722 | #define OP_SVE_SMS \ |
1723 | { \ | |
1724 | QLF3(S_S,P_M,S_S), \ | |
1725 | } | |
28ef4f20 RS |
1726 | #define OP_SVE_SS \ |
1727 | { \ | |
1728 | QLF2(S_S,S_S), \ | |
1729 | } | |
c0890d26 RS |
1730 | #define OP_SVE_SU \ |
1731 | { \ | |
1732 | QLF2(S_S,NIL), \ | |
1733 | } | |
1734 | #define OP_SVE_SUS \ | |
1735 | { \ | |
1736 | QLF3(S_S,NIL,S_S), \ | |
1737 | } | |
1738 | #define OP_SVE_SUU \ | |
1739 | { \ | |
1740 | QLF3(S_S,NIL,NIL), \ | |
1741 | } | |
1742 | #define OP_SVE_SZS \ | |
1743 | { \ | |
1744 | QLF3(S_S,P_Z,S_S), \ | |
1745 | } | |
8382113f MM |
1746 | #define OP_SVE_SBB \ |
1747 | { \ | |
1748 | QLF3(S_S,S_B,S_B), \ | |
1749 | } | |
42e6288f MM |
1750 | #define OP_SVE_SBBU \ |
1751 | { \ | |
1752 | QLF4(S_S,S_B,S_B,NIL), \ | |
1753 | } | |
1754 | #define OP_SVE_DSS \ | |
1755 | { \ | |
1756 | QLF3(S_D,S_S,S_S), \ | |
1757 | } | |
1758 | #define OP_SVE_DHHU \ | |
1759 | { \ | |
1760 | QLF4(S_D,S_H,S_H,NIL), \ | |
1761 | } | |
c0890d26 RS |
1762 | #define OP_SVE_SZU \ |
1763 | { \ | |
1764 | QLF3(S_S,P_Z,NIL), \ | |
1765 | } | |
1766 | #define OP_SVE_UB \ | |
1767 | { \ | |
1768 | QLF2(NIL,S_B), \ | |
1769 | } | |
1770 | #define OP_SVE_UUD \ | |
1771 | { \ | |
1772 | QLF3(NIL,NIL,S_D), \ | |
1773 | } | |
1774 | #define OP_SVE_UUS \ | |
1775 | { \ | |
1776 | QLF3(NIL,NIL,S_S), \ | |
1777 | } | |
cbd11b88 RS |
1778 | #define OP_SVE_UX \ |
1779 | { \ | |
1780 | QLF2(NIL,X), \ | |
1781 | } | |
8ff42920 RS |
1782 | #define OP_SVE_UXU \ |
1783 | { \ | |
1784 | QLF3(NIL,X,NIL), \ | |
1785 | } | |
c0890d26 RS |
1786 | #define OP_SVE_VMR_BHSD \ |
1787 | { \ | |
1788 | QLF3(S_B,P_M,W), \ | |
1789 | QLF3(S_H,P_M,W), \ | |
1790 | QLF3(S_S,P_M,W), \ | |
1791 | QLF3(S_D,P_M,X), \ | |
1792 | } | |
582e12bf | 1793 | #define OP_SVE_VMU_HSD \ |
c0890d26 | 1794 | { \ |
582e12bf | 1795 | QLF3(S_H,P_M,NIL), \ |
c0890d26 RS |
1796 | QLF3(S_S,P_M,NIL), \ |
1797 | QLF3(S_D,P_M,NIL), \ | |
1798 | } | |
1799 | #define OP_SVE_VMVD_BHS \ | |
1800 | { \ | |
1801 | QLF4(S_B,P_M,S_B,S_D), \ | |
1802 | QLF4(S_H,P_M,S_H,S_D), \ | |
1803 | QLF4(S_S,P_M,S_S,S_D), \ | |
1804 | } | |
1805 | #define OP_SVE_VMVU_BHSD \ | |
1806 | { \ | |
1807 | QLF4(S_B,P_M,S_B,NIL), \ | |
1808 | QLF4(S_H,P_M,S_H,NIL), \ | |
1809 | QLF4(S_S,P_M,S_S,NIL), \ | |
1810 | QLF4(S_D,P_M,S_D,NIL), \ | |
1811 | } | |
582e12bf | 1812 | #define OP_SVE_VMVU_HSD \ |
c0890d26 | 1813 | { \ |
582e12bf | 1814 | QLF4(S_H,P_M,S_H,NIL), \ |
c0890d26 RS |
1815 | QLF4(S_S,P_M,S_S,NIL), \ |
1816 | QLF4(S_D,P_M,S_D,NIL), \ | |
1817 | } | |
1818 | #define OP_SVE_VMVV_BHSD \ | |
1819 | { \ | |
1820 | QLF4(S_B,P_M,S_B,S_B), \ | |
1821 | QLF4(S_H,P_M,S_H,S_H), \ | |
1822 | QLF4(S_S,P_M,S_S,S_S), \ | |
1823 | QLF4(S_D,P_M,S_D,S_D), \ | |
1824 | } | |
582e12bf RS |
1825 | #define OP_SVE_VMVV_HSD \ |
1826 | { \ | |
1827 | QLF4(S_H,P_M,S_H,S_H), \ | |
1828 | QLF4(S_S,P_M,S_S,S_S), \ | |
1829 | QLF4(S_D,P_M,S_D,S_D), \ | |
1830 | } | |
c0890d26 RS |
1831 | #define OP_SVE_VMVV_SD \ |
1832 | { \ | |
1833 | QLF4(S_S,P_M,S_S,S_S), \ | |
1834 | QLF4(S_D,P_M,S_D,S_D), \ | |
1835 | } | |
582e12bf RS |
1836 | #define OP_SVE_VMVVU_HSD \ |
1837 | { \ | |
1838 | QLF5(S_H,P_M,S_H,S_H,NIL), \ | |
1839 | QLF5(S_S,P_M,S_S,S_S,NIL), \ | |
1840 | QLF5(S_D,P_M,S_D,S_D,NIL), \ | |
1841 | } | |
c0890d26 RS |
1842 | #define OP_SVE_VMV_BHSD \ |
1843 | { \ | |
1844 | QLF3(S_B,P_M,S_B), \ | |
1845 | QLF3(S_H,P_M,S_H), \ | |
1846 | QLF3(S_S,P_M,S_S), \ | |
1847 | QLF3(S_D,P_M,S_D), \ | |
1848 | } | |
56723f69 RS |
1849 | #define OP_SVE_VMV_BHSDQ \ |
1850 | { \ | |
1851 | QLF3(S_B,P_M,S_B), \ | |
1852 | QLF3(S_H,P_M,S_H), \ | |
1853 | QLF3(S_S,P_M,S_S), \ | |
1854 | QLF3(S_D,P_M,S_D), \ | |
1855 | QLF3(S_Q,P_M,S_Q) \ | |
1856 | } | |
c0890d26 RS |
1857 | #define OP_SVE_VMV_HSD \ |
1858 | { \ | |
1859 | QLF3(S_H,P_M,S_H), \ | |
1860 | QLF3(S_S,P_M,S_S), \ | |
1861 | QLF3(S_D,P_M,S_D), \ | |
1862 | } | |
42e6288f MM |
1863 | #define OP_SVE_VMV_HSD_BHS \ |
1864 | { \ | |
1865 | QLF3(S_H,P_M,S_B), \ | |
1866 | QLF3(S_S,P_M,S_H), \ | |
1867 | QLF3(S_D,P_M,S_S), \ | |
1868 | } | |
6efa6601 RS |
1869 | #define OP_SVE_VVU_BH_SD \ |
1870 | { \ | |
1871 | QLF3(S_B,S_S,NIL), \ | |
1872 | QLF3(S_H,S_D,NIL), \ | |
1873 | } | |
42e6288f MM |
1874 | #define OP_SVE_VVU_HSD_BHS \ |
1875 | { \ | |
1876 | QLF3(S_H,S_B,NIL), \ | |
1877 | QLF3(S_S,S_H,NIL), \ | |
1878 | QLF3(S_D,S_S,NIL), \ | |
1879 | } | |
c0890d26 RS |
1880 | #define OP_SVE_VMV_SD \ |
1881 | { \ | |
1882 | QLF3(S_S,P_M,S_S), \ | |
1883 | QLF3(S_D,P_M,S_D), \ | |
1884 | } | |
582e12bf | 1885 | #define OP_SVE_VM_HSD \ |
c0890d26 | 1886 | { \ |
582e12bf | 1887 | QLF2(S_H,P_M), \ |
c0890d26 RS |
1888 | QLF2(S_S,P_M), \ |
1889 | QLF2(S_D,P_M), \ | |
1890 | } | |
1891 | #define OP_SVE_VPU_BHSD \ | |
1892 | { \ | |
1893 | QLF3(S_B,P_Z,NIL), \ | |
1894 | QLF3(S_B,P_M,NIL), \ | |
1895 | QLF3(S_H,P_Z,NIL), \ | |
1896 | QLF3(S_H,P_M,NIL), \ | |
1897 | QLF3(S_S,P_Z,NIL), \ | |
1898 | QLF3(S_S,P_M,NIL), \ | |
1899 | QLF3(S_D,P_Z,NIL), \ | |
1900 | QLF3(S_D,P_M,NIL), \ | |
1901 | } | |
1902 | #define OP_SVE_VPV_BHSD \ | |
1903 | { \ | |
1904 | QLF3(S_B,P_Z,S_B), \ | |
1905 | QLF3(S_B,P_M,S_B), \ | |
1906 | QLF3(S_H,P_Z,S_H), \ | |
1907 | QLF3(S_H,P_M,S_H), \ | |
1908 | QLF3(S_S,P_Z,S_S), \ | |
1909 | QLF3(S_S,P_M,S_S), \ | |
1910 | QLF3(S_D,P_Z,S_D), \ | |
1911 | QLF3(S_D,P_M,S_D), \ | |
1912 | } | |
1913 | #define OP_SVE_VRR_BHSD \ | |
1914 | { \ | |
1915 | QLF3(S_B,W,W), \ | |
1916 | QLF3(S_H,W,W), \ | |
1917 | QLF3(S_S,W,W), \ | |
1918 | QLF3(S_D,X,X), \ | |
1919 | } | |
1920 | #define OP_SVE_VRU_BHSD \ | |
1921 | { \ | |
1922 | QLF3(S_B,W,NIL), \ | |
1923 | QLF3(S_H,W,NIL), \ | |
1924 | QLF3(S_S,W,NIL), \ | |
1925 | QLF3(S_D,X,NIL), \ | |
1926 | } | |
1927 | #define OP_SVE_VR_BHSD \ | |
1928 | { \ | |
1929 | QLF2(S_B,W), \ | |
1930 | QLF2(S_H,W), \ | |
1931 | QLF2(S_S,W), \ | |
1932 | QLF2(S_D,X), \ | |
1933 | } | |
1934 | #define OP_SVE_VUR_BHSD \ | |
1935 | { \ | |
1936 | QLF3(S_B,NIL,W), \ | |
1937 | QLF3(S_H,NIL,W), \ | |
1938 | QLF3(S_S,NIL,W), \ | |
1939 | QLF3(S_D,NIL,X), \ | |
1940 | } | |
cbd11b88 RS |
1941 | #define OP_SVE_VUU_BHS \ |
1942 | { \ | |
1943 | QLF3(S_B,NIL,NIL), \ | |
1944 | QLF3(S_H,NIL,NIL), \ | |
1945 | QLF3(S_S,NIL,NIL), \ | |
1946 | } | |
c0890d26 RS |
1947 | #define OP_SVE_VUU_BHSD \ |
1948 | { \ | |
1949 | QLF3(S_B,NIL,NIL), \ | |
1950 | QLF3(S_H,NIL,NIL), \ | |
1951 | QLF3(S_S,NIL,NIL), \ | |
1952 | QLF3(S_D,NIL,NIL), \ | |
1953 | } | |
1954 | #define OP_SVE_VUVV_BHSD \ | |
1955 | { \ | |
1956 | QLF4(S_B,NIL,S_B,S_B), \ | |
1957 | QLF4(S_H,NIL,S_H,S_H), \ | |
1958 | QLF4(S_S,NIL,S_S,S_S), \ | |
1959 | QLF4(S_D,NIL,S_D,S_D), \ | |
1960 | } | |
cbd11b88 RS |
1961 | #define OP_SVE_VUU_HS \ |
1962 | { \ | |
1963 | QLF3(S_H,NIL,NIL), \ | |
1964 | QLF3(S_S,NIL,NIL), \ | |
1965 | } | |
582e12bf | 1966 | #define OP_SVE_VUVV_HSD \ |
c0890d26 | 1967 | { \ |
582e12bf | 1968 | QLF4(S_H,NIL,S_H,S_H), \ |
c0890d26 RS |
1969 | QLF4(S_S,NIL,S_S,S_S), \ |
1970 | QLF4(S_D,NIL,S_D,S_D), \ | |
1971 | } | |
1972 | #define OP_SVE_VUV_BHSD \ | |
1973 | { \ | |
1974 | QLF3(S_B,NIL,S_B), \ | |
1975 | QLF3(S_H,NIL,S_H), \ | |
1976 | QLF3(S_S,NIL,S_S), \ | |
1977 | QLF3(S_D,NIL,S_D), \ | |
1978 | } | |
582e12bf RS |
1979 | #define OP_SVE_VUV_HSD \ |
1980 | { \ | |
1981 | QLF3(S_H,NIL,S_H), \ | |
1982 | QLF3(S_S,NIL,S_S), \ | |
1983 | QLF3(S_D,NIL,S_D), \ | |
1984 | } | |
c0890d26 RS |
1985 | #define OP_SVE_VUV_SD \ |
1986 | { \ | |
1987 | QLF3(S_S,NIL,S_S), \ | |
1988 | QLF3(S_D,NIL,S_D), \ | |
1989 | } | |
1990 | #define OP_SVE_VU_BHSD \ | |
1991 | { \ | |
1992 | QLF2(S_B,NIL), \ | |
1993 | QLF2(S_H,NIL), \ | |
1994 | QLF2(S_S,NIL), \ | |
1995 | QLF2(S_D,NIL), \ | |
1996 | } | |
1997 | #define OP_SVE_VU_HSD \ | |
1998 | { \ | |
1999 | QLF2(S_H,NIL), \ | |
2000 | QLF2(S_S,NIL), \ | |
2001 | QLF2(S_D,NIL), \ | |
2002 | } | |
582e12bf | 2003 | #define OP_SVE_VU_HSD \ |
c0890d26 | 2004 | { \ |
582e12bf | 2005 | QLF2(S_H,NIL), \ |
c0890d26 RS |
2006 | QLF2(S_S,NIL), \ |
2007 | QLF2(S_D,NIL), \ | |
2008 | } | |
2a3ed404 C |
2009 | #define OP_SVE_Vv_HSD \ |
2010 | { \ | |
2011 | QLF2(S_H,S_H), \ | |
2012 | QLF2(S_S,S_S), \ | |
2013 | QLF2(S_D,S_D), \ | |
2014 | QLF2(S_H,NIL), \ | |
2015 | QLF2(S_S,NIL), \ | |
2016 | QLF2(S_D,NIL), \ | |
2017 | } | |
c0890d26 RS |
2018 | #define OP_SVE_VVD_BHS \ |
2019 | { \ | |
2020 | QLF3(S_B,S_B,S_D), \ | |
2021 | QLF3(S_H,S_H,S_D), \ | |
2022 | QLF3(S_S,S_S,S_D), \ | |
2023 | } | |
2024 | #define OP_SVE_VVU_BHSD \ | |
2025 | { \ | |
2026 | QLF3(S_B,S_B,NIL), \ | |
2027 | QLF3(S_H,S_H,NIL), \ | |
2028 | QLF3(S_S,S_S,NIL), \ | |
2029 | QLF3(S_D,S_D,NIL), \ | |
2030 | } | |
582e12bf RS |
2031 | #define OP_SVE_VVVU_H \ |
2032 | { \ | |
2033 | QLF4(S_H,S_H,S_H,NIL), \ | |
2034 | } | |
2035 | #define OP_SVE_VVVU_S \ | |
c0890d26 RS |
2036 | { \ |
2037 | QLF4(S_S,S_S,S_S,NIL), \ | |
582e12bf | 2038 | } |
42e6288f MM |
2039 | #define OP_SVE_VVVU_SD_BH \ |
2040 | { \ | |
2041 | QLF4(S_S,S_B,S_B,NIL), \ | |
2042 | QLF4(S_D,S_H,S_H,NIL), \ | |
2043 | } | |
582e12bf RS |
2044 | #define OP_SVE_VVVU_HSD \ |
2045 | { \ | |
2046 | QLF4(S_H,S_H,S_H,NIL), \ | |
2047 | QLF4(S_S,S_S,S_S,NIL), \ | |
c0890d26 RS |
2048 | QLF4(S_D,S_D,S_D,NIL), \ |
2049 | } | |
42e6288f MM |
2050 | #define OP_SVE_VVVU_BHSD \ |
2051 | { \ | |
2052 | QLF4(S_B,S_B,S_B,NIL), \ | |
2053 | QLF4(S_H,S_H,S_H,NIL), \ | |
2054 | QLF4(S_S,S_S,S_S,NIL), \ | |
2055 | QLF4(S_D,S_D,S_D,NIL), \ | |
2056 | } | |
c0890d26 RS |
2057 | #define OP_SVE_VVV_BHSD \ |
2058 | { \ | |
2059 | QLF3(S_B,S_B,S_B), \ | |
2060 | QLF3(S_H,S_H,S_H), \ | |
2061 | QLF3(S_S,S_S,S_S), \ | |
2062 | QLF3(S_D,S_D,S_D), \ | |
2063 | } | |
582e12bf RS |
2064 | #define OP_SVE_VVV_D \ |
2065 | { \ | |
2066 | QLF3(S_D,S_D,S_D), \ | |
2067 | } | |
2068 | #define OP_SVE_VVV_D_H \ | |
2069 | { \ | |
2070 | QLF3(S_D,S_H,S_H), \ | |
2071 | } | |
2072 | #define OP_SVE_VVV_H \ | |
c0890d26 | 2073 | { \ |
582e12bf RS |
2074 | QLF3(S_H,S_H,S_H), \ |
2075 | } | |
2076 | #define OP_SVE_VVV_HSD \ | |
2077 | { \ | |
2078 | QLF3(S_H,S_H,S_H), \ | |
c0890d26 RS |
2079 | QLF3(S_S,S_S,S_S), \ |
2080 | QLF3(S_D,S_D,S_D), \ | |
2081 | } | |
582e12bf RS |
2082 | #define OP_SVE_VVV_S \ |
2083 | { \ | |
2084 | QLF3(S_S,S_S,S_S), \ | |
2085 | } | |
41be57ca MM |
2086 | #define OP_SVE_VVV_HD_BS \ |
2087 | { \ | |
2088 | QLF3(S_H,S_B,S_B), \ | |
2089 | QLF3(S_D,S_S,S_S), \ | |
2090 | } | |
582e12bf RS |
2091 | #define OP_SVE_VVV_S_B \ |
2092 | { \ | |
2093 | QLF3(S_S,S_B,S_B), \ | |
2094 | } | |
41be57ca | 2095 | #define OP_SVE_VVV_Q_D \ |
42e6288f MM |
2096 | { \ |
2097 | QLF3(S_Q,S_D,S_D), \ | |
42e6288f MM |
2098 | } |
2099 | #define OP_SVE_VVV_HSD_BHS \ | |
2100 | { \ | |
2101 | QLF3(S_H,S_B,S_B), \ | |
2102 | QLF3(S_S,S_H,S_H), \ | |
2103 | QLF3(S_D,S_S,S_S), \ | |
2104 | } | |
2105 | #define OP_SVE_VVV_HSD_BHS2 \ | |
2106 | { \ | |
2107 | QLF3(S_H,S_H,S_B), \ | |
2108 | QLF3(S_S,S_S,S_H), \ | |
2109 | QLF3(S_D,S_D,S_S), \ | |
2110 | } | |
2111 | #define OP_SVE_VVV_BHS_HSD \ | |
2112 | { \ | |
2113 | QLF3(S_B,S_H,S_H), \ | |
2114 | QLF3(S_H,S_S,S_S), \ | |
2115 | QLF3(S_S,S_D,S_D), \ | |
2116 | } | |
2117 | #define OP_SVE_VV_BHS_HSD \ | |
2118 | { \ | |
2119 | QLF2(S_B,S_H), \ | |
2120 | QLF2(S_H,S_S), \ | |
2121 | QLF2(S_S,S_D), \ | |
2122 | } | |
582e12bf RS |
2123 | #define OP_SVE_VVV_SD_BH \ |
2124 | { \ | |
2125 | QLF3(S_S,S_B,S_B), \ | |
2126 | QLF3(S_D,S_H,S_H), \ | |
2127 | } | |
42e6288f MM |
2128 | #define OP_SVE_VVV_SD \ |
2129 | { \ | |
2130 | QLF3(S_S,S_S,S_S), \ | |
2131 | QLF3(S_D,S_D,S_D), \ | |
2132 | } | |
c0890d26 RS |
2133 | #define OP_SVE_VV_BHSD \ |
2134 | { \ | |
2135 | QLF2(S_B,S_B), \ | |
2136 | QLF2(S_H,S_H), \ | |
2137 | QLF2(S_S,S_S), \ | |
2138 | QLF2(S_D,S_D), \ | |
2139 | } | |
582e12bf RS |
2140 | #define OP_SVE_VV_BHSDQ \ |
2141 | { \ | |
2142 | QLF2(S_B,S_B), \ | |
2143 | QLF2(S_H,S_H), \ | |
2144 | QLF2(S_S,S_S), \ | |
2145 | QLF2(S_D,S_D), \ | |
2146 | QLF2(S_Q,S_Q), \ | |
2147 | } | |
ce623e7a RS |
2148 | #define OP_SVE_VV_BH_SD \ |
2149 | { \ | |
2150 | QLF2(S_B,S_S), \ | |
2151 | QLF2(S_H,S_D), \ | |
2152 | } | |
582e12bf RS |
2153 | #define OP_SVE_VV_HSD \ |
2154 | { \ | |
2155 | QLF2(S_H,S_H), \ | |
2156 | QLF2(S_S,S_S), \ | |
2157 | QLF2(S_D,S_D), \ | |
2158 | } | |
42e6288f MM |
2159 | #define OP_SVE_VVU_BHS_HSD \ |
2160 | { \ | |
2161 | QLF3(S_B,S_H,NIL), \ | |
2162 | QLF3(S_H,S_S,NIL), \ | |
2163 | QLF3(S_S,S_D,NIL), \ | |
2164 | } | |
c0890d26 RS |
2165 | #define OP_SVE_VV_HSD_BHS \ |
2166 | { \ | |
2167 | QLF2(S_H,S_B), \ | |
2168 | QLF2(S_S,S_H), \ | |
2169 | QLF2(S_D,S_S), \ | |
2170 | } | |
2171 | #define OP_SVE_VV_SD \ | |
2172 | { \ | |
2173 | QLF2(S_S,S_S), \ | |
2174 | QLF2(S_D,S_D), \ | |
2175 | } | |
2176 | #define OP_SVE_VWW_BHSD \ | |
2177 | { \ | |
2178 | QLF3(S_B,W,W), \ | |
2179 | QLF3(S_H,W,W), \ | |
2180 | QLF3(S_S,W,W), \ | |
2181 | QLF3(S_D,W,W), \ | |
2182 | } | |
2183 | #define OP_SVE_VXX_BHSD \ | |
2184 | { \ | |
2185 | QLF3(S_B,X,X), \ | |
2186 | QLF3(S_H,X,X), \ | |
2187 | QLF3(S_S,X,X), \ | |
2188 | QLF3(S_D,X,X), \ | |
2189 | } | |
99e01a66 RS |
2190 | #define OP_SVE_VXXU_BHSD \ |
2191 | { \ | |
2192 | QLF4(S_B,X,X,NIL), \ | |
2193 | QLF4(S_H,X,X,NIL), \ | |
2194 | QLF4(S_S,X,X,NIL), \ | |
2195 | QLF4(S_D,X,X,NIL), \ | |
2196 | } | |
c0890d26 RS |
2197 | #define OP_SVE_VZVD_BHS \ |
2198 | { \ | |
2199 | QLF4(S_B,P_Z,S_B,S_D), \ | |
2200 | QLF4(S_H,P_Z,S_H,S_D), \ | |
2201 | QLF4(S_S,P_Z,S_S,S_D), \ | |
2202 | } | |
2203 | #define OP_SVE_VZVU_BHSD \ | |
2204 | { \ | |
2205 | QLF4(S_B,P_Z,S_B,NIL), \ | |
2206 | QLF4(S_H,P_Z,S_H,NIL), \ | |
2207 | QLF4(S_S,P_Z,S_S,NIL), \ | |
2208 | QLF4(S_D,P_Z,S_D,NIL), \ | |
2209 | } | |
2210 | #define OP_SVE_VZVV_BHSD \ | |
2211 | { \ | |
2212 | QLF4(S_B,P_Z,S_B,S_B), \ | |
2213 | QLF4(S_H,P_Z,S_H,S_H), \ | |
2214 | QLF4(S_S,P_Z,S_S,S_S), \ | |
2215 | QLF4(S_D,P_Z,S_D,S_D), \ | |
2216 | } | |
582e12bf | 2217 | #define OP_SVE_VZVV_HSD \ |
c0890d26 | 2218 | { \ |
582e12bf | 2219 | QLF4(S_H,P_Z,S_H,S_H), \ |
c0890d26 RS |
2220 | QLF4(S_S,P_Z,S_S,S_S), \ |
2221 | QLF4(S_D,P_Z,S_D,S_D), \ | |
2222 | } | |
42e6288f MM |
2223 | #define OP_SVE_VZVV_SD \ |
2224 | { \ | |
2225 | QLF4(S_S,P_Z,S_S,S_S), \ | |
2226 | QLF4(S_D,P_Z,S_D,S_D), \ | |
2227 | } | |
2228 | #define OP_SVE_VZVV_BH \ | |
2229 | { \ | |
2230 | QLF4(S_B,P_Z,S_B,S_B), \ | |
2231 | QLF4(S_H,P_Z,S_H,S_H), \ | |
2232 | } | |
2233 | #define OP_SVE_VZV_SD \ | |
2234 | { \ | |
2235 | QLF3(S_S,P_Z,S_S), \ | |
2236 | QLF3(S_D,P_Z,S_D), \ | |
2237 | } | |
582e12bf | 2238 | #define OP_SVE_VZV_HSD \ |
c0890d26 | 2239 | { \ |
582e12bf | 2240 | QLF3(S_H,P_Z,S_H), \ |
c0890d26 RS |
2241 | QLF3(S_S,P_Z,S_S), \ |
2242 | QLF3(S_D,P_Z,S_D), \ | |
2243 | } | |
99e01a66 RS |
2244 | #define OP_SVE_V_BHSD \ |
2245 | { \ | |
2246 | QLF1(S_B), \ | |
2247 | QLF1(S_H), \ | |
2248 | QLF1(S_S), \ | |
2249 | QLF1(S_D), \ | |
2250 | } | |
582e12bf | 2251 | #define OP_SVE_V_HSD \ |
c0890d26 | 2252 | { \ |
582e12bf | 2253 | QLF1(S_H), \ |
c0890d26 RS |
2254 | QLF1(S_S), \ |
2255 | QLF1(S_D), \ | |
2256 | } | |
2257 | #define OP_SVE_WU \ | |
2258 | { \ | |
2259 | QLF2(W,NIL), \ | |
2260 | } | |
2261 | #define OP_SVE_WV_BHSD \ | |
2262 | { \ | |
2263 | QLF2(W,S_B), \ | |
2264 | QLF2(W,S_H), \ | |
2265 | QLF2(W,S_S), \ | |
2266 | QLF2(W,S_D), \ | |
2267 | } | |
2268 | #define OP_SVE_XU \ | |
2269 | { \ | |
2270 | QLF2(X,NIL), \ | |
2271 | } | |
2272 | #define OP_SVE_XUV_BHSD \ | |
2273 | { \ | |
2274 | QLF3(X,NIL,S_B), \ | |
2275 | QLF3(X,NIL,S_H), \ | |
2276 | QLF3(X,NIL,S_S), \ | |
2277 | QLF3(X,NIL,S_D), \ | |
2278 | } | |
2279 | #define OP_SVE_XVW_BHSD \ | |
2280 | { \ | |
2281 | QLF3(X,S_B,W), \ | |
2282 | QLF3(X,S_H,W), \ | |
2283 | QLF3(X,S_S,W), \ | |
2284 | QLF3(X,S_D,W), \ | |
2285 | } | |
2286 | #define OP_SVE_XV_BHSD \ | |
2287 | { \ | |
2288 | QLF2(X,S_B), \ | |
2289 | QLF2(X,S_H), \ | |
2290 | QLF2(X,S_S), \ | |
2291 | QLF2(X,S_D), \ | |
2292 | } | |
2293 | #define OP_SVE_XWU \ | |
2294 | { \ | |
2295 | QLF3(X,W,NIL), \ | |
2296 | } | |
2297 | #define OP_SVE_XXU \ | |
2298 | { \ | |
2299 | QLF3(X,X,NIL), \ | |
2300 | } | |
971eda73 | 2301 | |
65a55fbb TC |
2302 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */ |
2303 | #define QL_V3DOT \ | |
2304 | { \ | |
2305 | QLF3(V_2S, V_8B, V_8B), \ | |
2306 | QLF3(V_4S, V_16B, V_16B),\ | |
2307 | } | |
2308 | ||
2309 | /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */ | |
2310 | #define QL_V2DOT \ | |
2311 | { \ | |
00c2093f TC |
2312 | QLF3(V_2S, V_8B, S_4B),\ |
2313 | QLF3(V_4S, V_16B, S_4B),\ | |
65a55fbb | 2314 | } |
1a7ed57c TC |
2315 | |
2316 | /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D\f. */ | |
2317 | #define QL_SHA512UPT \ | |
2318 | { \ | |
2319 | QLF3(S_Q, S_Q, V_2D), \ | |
2320 | } | |
2321 | ||
2322 | /* e.g. SHA512SU0 <Vd.2D>, <Vn>.2D\f. */ | |
2323 | #define QL_V2SAME2D \ | |
2324 | { \ | |
2325 | QLF2(V_2D, V_2D), \ | |
2326 | } | |
2327 | ||
2328 | /* e.g. SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D>. */ | |
2329 | #define QL_V3SAME2D \ | |
2330 | { \ | |
2331 | QLF3(V_2D, V_2D, V_2D), \ | |
2332 | } | |
2333 | ||
2334 | /* e.g. EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B. */ | |
2335 | #define QL_V4SAME16B \ | |
2336 | { \ | |
2337 | QLF4(V_16B, V_16B, V_16B, V_16B), \ | |
2338 | } | |
2339 | ||
2340 | /* e.g. SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S. */ | |
2341 | #define QL_V4SAME4S \ | |
2342 | { \ | |
2343 | QLF4(V_4S, V_4S, V_4S, V_4S), \ | |
2344 | } | |
2345 | ||
2346 | /* e.g. XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>. */ | |
2347 | #define QL_XAR \ | |
2348 | { \ | |
2349 | QLF4(V_2D, V_2D, V_2D, imm_0_63), \ | |
2350 | } | |
2351 | ||
2352 | /* e.g. SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]. */ | |
2353 | #define QL_SM3TT \ | |
2354 | { \ | |
2355 | QLF3(V_4S, V_4S, S_S),\ | |
2356 | } | |
2357 | ||
2358 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.2H. */ | |
2359 | #define QL_V3FML2S \ | |
2360 | { \ | |
2361 | QLF3(V_2S, V_2H, V_2H),\ | |
2362 | } | |
2363 | ||
2364 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.4H. */ | |
2365 | #define QL_V3FML4S \ | |
2366 | { \ | |
2367 | QLF3(V_4S, V_4H, V_4H),\ | |
2368 | } | |
2369 | ||
2370 | /* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.H[<index>]. */ | |
2371 | #define QL_V2FML2S \ | |
2372 | { \ | |
2373 | QLF3(V_2S, V_2H, S_H),\ | |
2374 | } | |
2375 | ||
2376 | /* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.H[<index>]. */ | |
2377 | #define QL_V2FML4S \ | |
2378 | { \ | |
2379 | QLF3(V_4S, V_4H, S_H),\ | |
2380 | } | |
2381 | ||
2382 | /* e.g. RMIF <Xn>, #<shift>, #<mask>. */ | |
2383 | #define QL_RMIF \ | |
2384 | { \ | |
2385 | QLF3(X, imm_0_63, imm_0_15),\ | |
2386 | } | |
2387 | ||
2388 | /* e.g. SETF8 <Wn>. */ | |
2389 | #define QL_SETF \ | |
2390 | { \ | |
2391 | QLF1(W), \ | |
2392 | } | |
2393 | ||
2394 | /* e.g. STLURB <Wt>, [<Xn|SP>{,#<simm>}]. */ | |
2395 | #define QL_STLW \ | |
2396 | { \ | |
2397 | QLF2(W, NIL), \ | |
2398 | } | |
2399 | ||
2400 | /* e.g. STLURB <Xt>, [<Xn|SP>{,#<simm>}]. */ | |
2401 | #define QL_STLX \ | |
2402 | { \ | |
2403 | QLF2(X, NIL), \ | |
2404 | } | |
df678013 MM |
2405 | |
2406 | /* e.g. BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> */ | |
2407 | #define QL_BFDOT64 \ | |
2408 | { \ | |
2409 | QLF3(V_2S, V_4H, V_4H),\ | |
2410 | QLF3(V_4S, V_8H, V_8H),\ | |
2411 | } | |
2412 | ||
2413 | /* e.g. BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2H[<index>] */ | |
2414 | #define QL_BFDOT64I \ | |
2415 | { \ | |
2416 | QLF3(V_2S, V_4H, S_2H),\ | |
2417 | QLF3(V_4S, V_8H, S_2H),\ | |
2418 | } | |
2419 | ||
8382113f MM |
2420 | /* e.g. SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B */ |
2421 | #define QL_MMLA64 \ | |
2422 | { \ | |
2423 | QLF3(V_4S, V_16B, V_16B),\ | |
2424 | } | |
2425 | ||
df678013 MM |
2426 | /* e.g. BFMMLA <Vd>.4s, <Vn>.8h, <Vm>.8h */ |
2427 | #define QL_BFMMLA \ | |
2428 | { \ | |
2429 | QLF3(V_4S, V_8H, V_8H),\ | |
2430 | } | |
2431 | ||
2432 | /* e.g. BFCVT <Hd>, <Sn> */ | |
2433 | #define QL_BFCVT64 \ | |
2434 | { \ | |
2435 | QLF2(S_H,S_S), \ | |
2436 | } | |
2437 | ||
2438 | /* e.g. BFCVT <Hd>, <Sn> */ | |
2439 | #define QL_BFCVTN64 \ | |
2440 | { \ | |
2441 | QLF2(V_4H,V_4S), \ | |
2442 | } | |
2443 | ||
2444 | /* e.g. BFCVT <Hd>, <Sn> */ | |
2445 | #define QL_BFCVTN2_64 \ | |
2446 | { \ | |
2447 | QLF2(V_8H,V_4S), \ | |
2448 | } | |
2449 | ||
2450 | /* e.g. BFMLAL2 <Vd>.4s, <Vn>.8h, <Vm>.H[<index>] */ | |
2451 | #define QL_V3BFML4S \ | |
2452 | { \ | |
2453 | QLF3(V_4S, V_8H, S_H), \ | |
2454 | } | |
a06ea964 | 2455 | \f |
205e4380 AC |
2456 | /* Opcode table. |
2457 | ||
2458 | Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its | |
2459 | bitmask, even if this is implied by other selected feature bits. This | |
2460 | allows verify_constraints to identify SVE instructions when selecting an | |
2461 | error message for MOVPRFX constraint violations. */ | |
a06ea964 NC |
2462 | |
2463 | static const aarch64_feature_set aarch64_feature_v8 = | |
2464 | AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); | |
2465 | static const aarch64_feature_set aarch64_feature_fp = | |
2466 | AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); | |
2467 | static const aarch64_feature_set aarch64_feature_simd = | |
2468 | AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); | |
e60bb1dd YZ |
2469 | static const aarch64_feature_set aarch64_feature_crc = |
2470 | AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); | |
ee804238 JW |
2471 | static const aarch64_feature_set aarch64_feature_lse = |
2472 | AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); | |
290806fd MW |
2473 | static const aarch64_feature_set aarch64_feature_lor = |
2474 | AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); | |
9e1f0fa7 MW |
2475 | static const aarch64_feature_set aarch64_feature_rdma = |
2476 | AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); | |
a4822788 VDN |
2477 | static const aarch64_feature_set aarch64_feature_v8_2a = |
2478 | AARCH64_FEATURE (AARCH64_FEATURE_V8_2A, 0); | |
3bd894a7 MW |
2479 | static const aarch64_feature_set aarch64_feature_fp_f16 = |
2480 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); | |
40d16a76 MW |
2481 | static const aarch64_feature_set aarch64_feature_simd_f16 = |
2482 | AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0); | |
c0890d26 RS |
2483 | static const aarch64_feature_set aarch64_feature_sve = |
2484 | AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0); | |
a4822788 VDN |
2485 | static const aarch64_feature_set aarch64_feature_v8_3a = |
2486 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3A, 0); | |
2487 | static const aarch64_feature_set aarch64_feature_fp_v8_3a = | |
2488 | AARCH64_FEATURE (AARCH64_FEATURE_V8_3A | AARCH64_FEATURE_FP, 0); | |
af1bd771 PW |
2489 | static const aarch64_feature_set aarch64_feature_pac = |
2490 | AARCH64_FEATURE (AARCH64_FEATURE_PAC, 0); | |
f482d304 RS |
2491 | static const aarch64_feature_set aarch64_feature_compnum = |
2492 | AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0); | |
d74d4880 SN |
2493 | static const aarch64_feature_set aarch64_feature_rcpc = |
2494 | AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0); | |
65a55fbb | 2495 | static const aarch64_feature_set aarch64_feature_dotprod = |
205e4380 | 2496 | AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0); |
c0e7cef7 NC |
2497 | static const aarch64_feature_set aarch64_feature_sha2 = |
2498 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0); | |
2499 | static const aarch64_feature_set aarch64_feature_aes = | |
2500 | AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0); | |
a4822788 VDN |
2501 | static const aarch64_feature_set aarch64_feature_v8_4a = |
2502 | AARCH64_FEATURE (AARCH64_FEATURE_V8_4A, 0); | |
b6b9ca0c | 2503 | static const aarch64_feature_set aarch64_feature_sm4 = |
205e4380 AC |
2504 | AARCH64_FEATURE (AARCH64_FEATURE_SM4 | AARCH64_FEATURE_SIMD |
2505 | | AARCH64_FEATURE_FP, 0); | |
b6b9ca0c | 2506 | static const aarch64_feature_set aarch64_feature_sha3 = |
205e4380 AC |
2507 | AARCH64_FEATURE (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SHA3 |
2508 | | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0); | |
a4822788 | 2509 | static const aarch64_feature_set aarch64_feature_fp_16_v8_2a = |
205e4380 AC |
2510 | AARCH64_FEATURE (AARCH64_FEATURE_F16_FML | AARCH64_FEATURE_F16 |
2511 | | AARCH64_FEATURE_FP, 0); | |
a4822788 VDN |
2512 | static const aarch64_feature_set aarch64_feature_v8_5a = |
2513 | AARCH64_FEATURE (AARCH64_FEATURE_V8_5A, 0); | |
13c60ad7 SD |
2514 | static const aarch64_feature_set aarch64_feature_flagmanip = |
2515 | AARCH64_FEATURE (AARCH64_FEATURE_FLAGMANIP, 0); | |
2516 | static const aarch64_feature_set aarch64_feature_frintts = | |
2517 | AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0); | |
68dfbb92 SD |
2518 | static const aarch64_feature_set aarch64_feature_sb = |
2519 | AARCH64_FEATURE (AARCH64_FEATURE_SB, 0); | |
2ac435d4 SD |
2520 | static const aarch64_feature_set aarch64_feature_predres = |
2521 | AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); | |
73b605ec | 2522 | static const aarch64_feature_set aarch64_feature_memtag = |
205e4380 | 2523 | AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0); |
df678013 MM |
2524 | static const aarch64_feature_set aarch64_feature_bfloat16 = |
2525 | AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0); | |
2526 | static const aarch64_feature_set aarch64_feature_bfloat16_sve = | |
2527 | AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16 | AARCH64_FEATURE_SVE, 0); | |
b83b4b13 SD |
2528 | static const aarch64_feature_set aarch64_feature_tme = |
2529 | AARCH64_FEATURE (AARCH64_FEATURE_TME, 0); | |
7ce2460a MM |
2530 | static const aarch64_feature_set aarch64_feature_sve2 = |
2531 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0); | |
2532 | static const aarch64_feature_set aarch64_feature_sve2aes = | |
2533 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0); | |
2534 | static const aarch64_feature_set aarch64_feature_sve2sha3 = | |
2535 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0); | |
2536 | static const aarch64_feature_set aarch64_feature_sve2sm4 = | |
2537 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0); | |
2538 | static const aarch64_feature_set aarch64_feature_sve2bitperm = | |
2539 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); | |
57f02370 PW |
2540 | static const aarch64_feature_set aarch64_feature_sme = |
2541 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME, 0); | |
78addeae | 2542 | static const aarch64_feature_set aarch64_feature_sme_f64f64 = |
57f02370 | 2543 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME |
78addeae RS |
2544 | | AARCH64_FEATURE_SME_F64F64, 0); |
2545 | static const aarch64_feature_set aarch64_feature_sme_i16i64 = | |
57f02370 | 2546 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME |
78addeae | 2547 | | AARCH64_FEATURE_SME_I16I64, 0); |
d8773a8a RS |
2548 | static const aarch64_feature_set aarch64_feature_sme2 = |
2549 | AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME | |
2550 | | AARCH64_FEATURE_SME2, 0); | |
a8cb21aa RS |
2551 | static const aarch64_feature_set aarch64_feature_sme2_i16i64 = |
2552 | AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_I16I64, 0); | |
80752eb0 RS |
2553 | static const aarch64_feature_set aarch64_feature_sme2_f64f64 = |
2554 | AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_F64F64, 0); | |
a4822788 VDN |
2555 | static const aarch64_feature_set aarch64_feature_v8_6a = |
2556 | AARCH64_FEATURE (AARCH64_FEATURE_V8_6A, 0); | |
2557 | static const aarch64_feature_set aarch64_feature_v8_7a = | |
2558 | AARCH64_FEATURE (AARCH64_FEATURE_V8_7A, 0); | |
8382113f | 2559 | static const aarch64_feature_set aarch64_feature_i8mm = |
205e4380 | 2560 | AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0); |
8382113f | 2561 | static const aarch64_feature_set aarch64_feature_i8mm_sve = |
205e4380 | 2562 | AARCH64_FEATURE (AARCH64_FEATURE_I8MM | AARCH64_FEATURE_SVE, 0); |
8382113f | 2563 | static const aarch64_feature_set aarch64_feature_f32mm_sve = |
205e4380 | 2564 | AARCH64_FEATURE (AARCH64_FEATURE_F32MM | AARCH64_FEATURE_SVE, 0); |
8382113f | 2565 | static const aarch64_feature_set aarch64_feature_f64mm_sve = |
205e4380 | 2566 | AARCH64_FEATURE (AARCH64_FEATURE_F64MM | AARCH64_FEATURE_SVE, 0); |
a4822788 VDN |
2567 | static const aarch64_feature_set aarch64_feature_v8r = |
2568 | AARCH64_FEATURE (AARCH64_FEATURE_V8R, 0); | |
fd65497d | 2569 | static const aarch64_feature_set aarch64_feature_ls64 = |
205e4380 | 2570 | AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0); |
e64441b1 PW |
2571 | static const aarch64_feature_set aarch64_feature_flagm = |
2572 | AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0); | |
6327658e RS |
2573 | static const aarch64_feature_set aarch64_feature_mops = |
2574 | AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0); | |
2575 | static const aarch64_feature_set aarch64_feature_mops_memtag = | |
2576 | AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0); | |
bcca550b RS |
2577 | static const aarch64_feature_set aarch64_feature_hbc = |
2578 | AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0); | |
1f7b42d5 AV |
2579 | static const aarch64_feature_set aarch64_feature_cssc = |
2580 | AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0); | |
a06ea964 | 2581 | |
4bd13cde NC |
2582 | #define CORE &aarch64_feature_v8 |
2583 | #define FP &aarch64_feature_fp | |
2584 | #define SIMD &aarch64_feature_simd | |
4bd13cde NC |
2585 | #define CRC &aarch64_feature_crc |
2586 | #define LSE &aarch64_feature_lse | |
2587 | #define LOR &aarch64_feature_lor | |
2588 | #define RDMA &aarch64_feature_rdma | |
2589 | #define FP_F16 &aarch64_feature_fp_f16 | |
40d16a76 | 2590 | #define SIMD_F16 &aarch64_feature_simd_f16 |
a4822788 | 2591 | #define ARMV8_2A &aarch64_feature_v8_2a |
c0890d26 | 2592 | #define SVE &aarch64_feature_sve |
a4822788 VDN |
2593 | #define ARMV8_3A &aarch64_feature_v8_3a |
2594 | #define FP_V8_3A &aarch64_feature_fp_v8_3a | |
af1bd771 | 2595 | #define PAC &aarch64_feature_pac |
f482d304 | 2596 | #define COMPNUM &aarch64_feature_compnum |
d74d4880 | 2597 | #define RCPC &aarch64_feature_rcpc |
c0e7cef7 NC |
2598 | #define SHA2 &aarch64_feature_sha2 |
2599 | #define AES &aarch64_feature_aes | |
a4822788 | 2600 | #define ARMV8_4A &aarch64_feature_v8_4a |
b6b9ca0c TC |
2601 | #define SHA3 &aarch64_feature_sha3 |
2602 | #define SM4 &aarch64_feature_sm4 | |
a4822788 | 2603 | #define FP_F16_V8_2A &aarch64_feature_fp_16_v8_2a |
65a55fbb | 2604 | #define DOTPROD &aarch64_feature_dotprod |
a4822788 | 2605 | #define ARMV8_5A &aarch64_feature_v8_5a |
13c60ad7 SD |
2606 | #define FLAGMANIP &aarch64_feature_flagmanip |
2607 | #define FRINTTS &aarch64_feature_frintts | |
68dfbb92 | 2608 | #define SB &aarch64_feature_sb |
2ac435d4 | 2609 | #define PREDRES &aarch64_feature_predres |
73b605ec | 2610 | #define MEMTAG &aarch64_feature_memtag |
b83b4b13 | 2611 | #define TME &aarch64_feature_tme |
7ce2460a MM |
2612 | #define SVE2 &aarch64_feature_sve2 |
2613 | #define SVE2_AES &aarch64_feature_sve2aes | |
2614 | #define SVE2_SHA3 &aarch64_feature_sve2sha3 | |
2615 | #define SVE2_SM4 &aarch64_feature_sve2sm4 | |
2616 | #define SVE2_BITPERM &aarch64_feature_sve2bitperm | |
57f02370 | 2617 | #define SME &aarch64_feature_sme |
78addeae RS |
2618 | #define SME_F64F64 &aarch64_feature_sme_f64f64 |
2619 | #define SME_I16I64 &aarch64_feature_sme_i16i64 | |
d8773a8a | 2620 | #define SME2 &aarch64_feature_sme2 |
a8cb21aa | 2621 | #define SME2_I16I64 &aarch64_feature_sme2_i16i64 |
80752eb0 | 2622 | #define SME2_F64F64 &aarch64_feature_sme2_f64f64 |
a4822788 VDN |
2623 | #define ARMV8_6A &aarch64_feature_v8_6a |
2624 | #define ARMV8_6A_SVE &aarch64_feature_v8_6a | |
df678013 MM |
2625 | #define BFLOAT16_SVE &aarch64_feature_bfloat16_sve |
2626 | #define BFLOAT16 &aarch64_feature_bfloat16 | |
8382113f MM |
2627 | #define I8MM_SVE &aarch64_feature_i8mm_sve |
2628 | #define F32MM_SVE &aarch64_feature_f32mm_sve | |
2629 | #define F64MM_SVE &aarch64_feature_f64mm_sve | |
2630 | #define I8MM &aarch64_feature_i8mm | |
a4822788 VDN |
2631 | #define ARMV8R &aarch64_feature_v8r |
2632 | #define ARMV8_7A &aarch64_feature_v8_7a | |
fd65497d | 2633 | #define LS64 &aarch64_feature_ls64 |
e64441b1 | 2634 | #define FLAGM &aarch64_feature_flagm |
6327658e RS |
2635 | #define MOPS &aarch64_feature_mops |
2636 | #define MOPS_MEMTAG &aarch64_feature_mops_memtag | |
bcca550b | 2637 | #define HBC &aarch64_feature_hbc |
1f7b42d5 | 2638 | #define CSSC &aarch64_feature_cssc |
4bd13cde | 2639 | |
9d30b0bd | 2640 | #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
eae424ae | 2641 | { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |
9d30b0bd | 2642 | #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
eae424ae | 2643 | { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } |
9d30b0bd | 2644 | #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
eae424ae | 2645 | { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } |
6456d318 TC |
2646 | #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \ |
2647 | { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER } | |
4bd13cde | 2648 | #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2649 | { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL } |
4bd13cde | 2650 | #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2651 | { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL } |
4bd13cde | 2652 | #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2653 | { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } |
4bd13cde | 2654 | #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2655 | { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } |
4bd13cde | 2656 | #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2657 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
4bd13cde | 2658 | #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2659 | { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } |
a4822788 VDN |
2660 | #define V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
2661 | { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
c0890d26 RS |
2662 | #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2663 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
eae424ae TC |
2664 | FLAGS | F_STRICT, 0, TIED, NULL } |
2665 | #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
2666 | { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ | |
2667 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
a4822788 VDN |
2668 | #define V8_3A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2669 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
af1bd771 PW |
2670 | #define PAC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2671 | { NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL } | |
f482d304 | 2672 | #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
eae424ae | 2673 | { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } |
d74d4880 | 2674 | #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2675 | { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL } |
c0e7cef7 | 2676 | #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2677 | { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL } |
c0e7cef7 | 2678 | #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2679 | { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } |
a4822788 VDN |
2680 | #define V8_4A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2681 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
b6b9ca0c | 2682 | #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2683 | { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } |
b6b9ca0c | 2684 | #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2685 | { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } |
a4822788 VDN |
2686 | #define FP16_V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2687 | { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
65a55fbb | 2688 | #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
eae424ae | 2689 | { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL } |
a4822788 VDN |
2690 | #define V8_5A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2691 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
13c60ad7 SD |
2692 | #define FLAGMANIP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2693 | { NAME, OPCODE, MASK, CLASS, 0, FLAGMANIP, OPS, QUALS, FLAGS, 0, 0, NULL } | |
2694 | #define FRINTTS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
2695 | { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL } | |
68dfbb92 SD |
2696 | #define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2697 | { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL } | |
2ac435d4 SD |
2698 | #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2699 | { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } | |
73b605ec SD |
2700 | #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2701 | { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } | |
b83b4b13 SD |
2702 | #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
2703 | { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } | |
7ce2460a MM |
2704 | #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2705 | { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ | |
2706 | FLAGS | F_STRICT, 0, TIED, NULL } | |
2707 | #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
2708 | { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ | |
2709 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
2710 | #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
2711 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ | |
2712 | FLAGS | F_STRICT, 0, TIED, NULL } | |
2713 | #define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
2714 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \ | |
2715 | FLAGS | F_STRICT, 0, TIED, NULL } | |
2716 | #define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ | |
2717 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ | |
2718 | FLAGS | F_STRICT, 0, TIED, NULL } | |
2719 | #define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ | |
2720 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ | |
2721 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
971eda73 PW |
2722 | #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2723 | { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ | |
a5791d58 | 2724 | F_STRICT | FLAGS, 0, TIED, NULL } |
78addeae RS |
2725 | #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2726 | { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ | |
a5791d58 | 2727 | F_STRICT | FLAGS, 0, TIED, NULL } |
78addeae RS |
2728 | #define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2729 | { NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \ | |
a5791d58 | 2730 | F_STRICT | FLAGS, 0, TIED, NULL } |
971eda73 PW |
2731 | #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ |
2732 | { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ | |
a5791d58 | 2733 | F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } |
d8773a8a RS |
2734 | #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2735 | { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ | |
2736 | F_STRICT | FLAGS, 0, TIED, NULL } | |
6a245d99 RS |
2737 | #define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ |
2738 | { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ | |
2739 | FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } | |
a8cb21aa RS |
2740 | #define SME2_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2741 | { NAME, OPCODE, MASK, CLASS, OP, SME2_I16I64, OPS, QUALS, \ | |
2742 | F_STRICT | FLAGS, 0, TIED, NULL } | |
80752eb0 RS |
2743 | #define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2744 | { NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \ | |
2745 | F_STRICT | FLAGS, 0, TIED, NULL } | |
7ce2460a MM |
2746 | #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
2747 | { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ | |
2748 | FLAGS | F_STRICT, 0, TIED, NULL } | |
a4822788 VDN |
2749 | #define V8_6A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2750 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_6A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
df678013 MM |
2751 | #define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2752 | { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL } | |
2753 | #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ | |
2754 | { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ | |
2755 | CONSTRAINTS, TIED, NULL } | |
2756 | #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
2757 | { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL } | |
8382113f MM |
2758 | #define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ |
2759 | { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } | |
2760 | #define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
2761 | { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL } | |
2762 | #define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ | |
2763 | { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL } | |
2764 | #define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ | |
2765 | { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } | |
2766 | #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ | |
2767 | { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } | |
a4822788 VDN |
2768 | #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2769 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } | |
2770 | #define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ | |
2771 | { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL } | |
fd65497d PW |
2772 | #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2773 | { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } | |
e64441b1 PW |
2774 | #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2775 | { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL } | |
6327658e RS |
2776 | #define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ |
2777 | { NAME, OPCODE, MASK, CLASS, 0, MOPS, OPS, QUALS, FLAGS, CONSTRAINTS, \ | |
2778 | 0, VERIFIER } | |
2779 | #define MOPS_MEMTAG_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ | |
2780 | { NAME, OPCODE, MASK, CLASS, 0, MOPS_MEMTAG, OPS, QUALS, FLAGS, \ | |
2781 | CONSTRAINTS, 0, VERIFIER } | |
bcca550b RS |
2782 | #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
2783 | { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL } | |
1f7b42d5 AV |
2784 | #define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ |
2785 | { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } | |
6327658e RS |
2786 | |
2787 | #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ | |
2788 | MOPS_INSN (NAME, OPCODE, MASK, 0, \ | |
2789 | OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \ | |
2790 | FLAGS, CONSTRAINTS, VERIFIER (three_different_regs)) | |
2791 | ||
63eff947 RS |
2792 | /* These instructions must remain consecutive, since we rely on the order |
2793 | when detecting invalid sequences. */ | |
6327658e | 2794 | #define MOPS_CPY_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK) \ |
63eff947 RS |
2795 | MOPS_CPY_OP1_OP2_PME_INSN (NAME "p" SUFFIX, OPCODE, MASK, F_SCAN, \ |
2796 | C_SCAN_MOPS_P), \ | |
2797 | MOPS_CPY_OP1_OP2_PME_INSN (NAME "m" SUFFIX, OPCODE | 0x400000, MASK, \ | |
2798 | 0, C_SCAN_MOPS_M), \ | |
2799 | MOPS_CPY_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x800000, MASK, \ | |
2800 | 0, C_SCAN_MOPS_E) | |
6327658e RS |
2801 | |
2802 | #define MOPS_CPY_OP1_INSN(NAME, SUFFIX, OPCODE, MASK) \ | |
2803 | MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX, OPCODE, MASK), \ | |
2804 | MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "wn", OPCODE | 0x4000, MASK), \ | |
2805 | MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \ | |
2806 | MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "n", OPCODE | 0xc000, MASK) | |
2807 | ||
2808 | #define MOPS_CPY_INSN(NAME, OPCODE, MASK) \ | |
2809 | MOPS_CPY_OP1_INSN (NAME, "", OPCODE, MASK), \ | |
2810 | MOPS_CPY_OP1_INSN (NAME, "wt", OPCODE | 0x1000, MASK), \ | |
2811 | MOPS_CPY_OP1_INSN (NAME, "rt", OPCODE | 0x2000, MASK), \ | |
2812 | MOPS_CPY_OP1_INSN (NAME, "t", OPCODE | 0x3000, MASK) | |
2813 | ||
2814 | #define MOPS_SET_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS, ISA) \ | |
2815 | ISA (NAME, OPCODE, MASK, 0, \ | |
2816 | OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \ | |
2817 | CONSTRAINTS, VERIFIER (three_different_regs)) | |
2818 | ||
63eff947 RS |
2819 | /* These instructions must remain consecutive, since we rely on the order |
2820 | when detecting invalid sequences. */ | |
6327658e | 2821 | #define MOPS_SET_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK, ISA) \ |
63eff947 RS |
2822 | MOPS_SET_OP1_OP2_PME_INSN (NAME "p" SUFFIX, OPCODE, MASK, \ |
2823 | F_SCAN, C_SCAN_MOPS_P, ISA), \ | |
6327658e | 2824 | MOPS_SET_OP1_OP2_PME_INSN (NAME "m" SUFFIX, OPCODE | 0x4000, MASK, \ |
63eff947 | 2825 | 0, C_SCAN_MOPS_M, ISA), \ |
6327658e | 2826 | MOPS_SET_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x8000, MASK, \ |
63eff947 | 2827 | 0, C_SCAN_MOPS_E, ISA) |
6327658e RS |
2828 | |
2829 | #define MOPS_SET_INSN(NAME, OPCODE, MASK, ISA) \ | |
2830 | MOPS_SET_OP1_OP2_INSN (NAME, "", OPCODE, MASK, ISA), \ | |
2831 | MOPS_SET_OP1_OP2_INSN (NAME, "t", OPCODE | 0x1000, MASK, ISA), \ | |
2832 | MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \ | |
2833 | MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA) | |
a06ea964 | 2834 | |
6c2ede01 | 2835 | const struct aarch64_opcode aarch64_opcode_table[] = |
a06ea964 NC |
2836 | { |
2837 | /* Add/subtract (with carry). */ | |
9d30b0bd RS |
2838 | CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
2839 | CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
2840 | CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
2841 | CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
2842 | CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
2843 | CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), | |
a06ea964 | 2844 | /* Add/subtract (extended register). */ |
9d30b0bd RS |
2845 | CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), |
2846 | CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
2847 | CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
2848 | CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), | |
2849 | CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), | |
2850 | CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), | |
a06ea964 | 2851 | /* Add/subtract (immediate). */ |
5ce912d8 | 2852 | CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
9d30b0bd RS |
2853 | CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), |
2854 | CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
2855 | CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
2856 | CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF), | |
2857 | CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
2858 | CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), | |
193614f2 SD |
2859 | MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0), |
2860 | MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0), | |
a06ea964 | 2861 | /* Add/subtract (shifted register). */ |
9d30b0bd RS |
2862 | CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
2863 | CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
2864 | CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
2865 | CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
2866 | CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), | |
2867 | CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
514cd3a0 | 2868 | CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1), |
9d30b0bd | 2869 | CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
a06ea964 | 2870 | /* AdvSIMD across lanes. */ |
9d30b0bd RS |
2871 | SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |
2872 | SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
2873 | SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
2874 | SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
2875 | SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), | |
2876 | SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
2877 | SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), | |
2878 | SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), | |
4bd13cde | 2879 | SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
9d30b0bd | 2880 | SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
4bd13cde | 2881 | SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
9d30b0bd | 2882 | SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
4bd13cde | 2883 | SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
9d30b0bd | 2884 | SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
4bd13cde | 2885 | SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
a06ea964 | 2886 | /* AdvSIMD three different. */ |
9d30b0bd RS |
2887 | SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
2888 | SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2889 | SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
2890 | SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
2891 | SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2892 | SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2893 | SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
2894 | SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
2895 | SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
2896 | SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
2897 | SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2898 | SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2899 | SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
2900 | SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
2901 | SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2902 | SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2903 | SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2904 | SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2905 | SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
2906 | SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
2907 | SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2908 | SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2909 | SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
2910 | SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
2911 | SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2912 | SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2913 | SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), | |
2914 | SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), | |
2915 | SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0), | |
c0e7cef7 | 2916 | AES_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0), |
9d30b0bd | 2917 | SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0), |
c0e7cef7 | 2918 | AES_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0), |
9d30b0bd RS |
2919 | SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
2920 | SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2921 | SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
2922 | SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
2923 | SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2924 | SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2925 | SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), | |
2926 | SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), | |
2927 | SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
2928 | SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
2929 | SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2930 | SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2931 | SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), | |
2932 | SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), | |
2933 | SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2934 | SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2935 | SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2936 | SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2937 | SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2938 | SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
2939 | SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), | |
2940 | SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), | |
a06ea964 | 2941 | /* AdvSIMD vector x indexed element. */ |
369c9167 TC |
2942 | SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
2943 | SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
45a28947 TC |
2944 | SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), |
2945 | SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2946 | SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2947 | SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2948 | SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2949 | SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2950 | SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
2951 | SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2952 | SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2953 | SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2954 | SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2955 | SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
2956 | SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
6456d318 | 2957 | _SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
369c9167 | 2958 | SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
6456d318 | 2959 | _SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
369c9167 | 2960 | SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
6456d318 | 2961 | _SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
369c9167 | 2962 | SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
45a28947 TC |
2963 | SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), |
2964 | SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2965 | SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2966 | SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
2967 | SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2968 | SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
2969 | SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), | |
2970 | SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), | |
6456d318 | 2971 | _SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)), |
369c9167 TC |
2972 | SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), |
2973 | RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
2974 | RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), | |
f482d304 | 2975 | CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ), |
a06ea964 | 2976 | /* AdvSIMD EXT. */ |
9d30b0bd | 2977 | SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), |
a06ea964 | 2978 | /* AdvSIMD modified immediate. */ |
9d30b0bd RS |
2979 | SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
2980 | SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
2981 | SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
2982 | SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
2983 | SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
2984 | SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ), | |
2985 | SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ), | |
4bd13cde | 2986 | SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ), |
9d30b0bd RS |
2987 | SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
2988 | SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), | |
2989 | SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
2990 | SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), | |
2991 | SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), | |
2992 | SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ), | |
2993 | SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
2994 | SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ), | |
a06ea964 | 2995 | /* AdvSIMD copy. */ |
9d30b0bd RS |
2996 | SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, 0, OP2 (Vd, En), QL_DUP_VX, F_T), |
2997 | SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, 0, OP2 (Vd, Rn), QL_DUP_VR, F_T), | |
2998 | SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q), | |
2999 | SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q), | |
3000 | SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q), | |
3001 | SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS), | |
3002 | SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS), | |
3003 | SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS), | |
3004 | SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_ALIAS), | |
a06ea964 | 3005 | /* AdvSIMD two-reg misc. */ |
13c60ad7 SD |
3006 | FRINTTS_INSN ("frint32z", 0x0e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
3007 | FRINTTS_INSN ("frint32x", 0x2e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
3008 | FRINTTS_INSN ("frint64z", 0x0e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
3009 | FRINTTS_INSN ("frint64x", 0x2e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
9d30b0bd RS |
3010 | SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
3011 | SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
3012 | SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
3013 | SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3014 | SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
3015 | SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
3016 | SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
3017 | SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3018 | SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
3019 | SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
3020 | SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
3021 | SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3022 | SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
3023 | SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
3024 | SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
3025 | SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
5ce912d8 RS |
3026 | SIMD_INSN ("fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC), |
3027 | SIMD_INSN ("fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC), | |
3028 | SIMD_INSN ("fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC), | |
3029 | SIMD_INSN ("fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC), | |
9d30b0bd | 3030 | SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3031 | SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3032 | SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3033 | SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3034 | SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3035 | SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3036 | SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3037 | SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3038 | SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3039 | SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3040 | SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3041 | SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3042 | SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3043 | SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3044 | SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3045 | SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3046 | SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3047 | SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3048 | SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3049 | SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3050 | SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3051 | SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3052 | SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3053 | SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3054 | SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3055 | SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3056 | SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3057 | SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd RS |
3058 | SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
3059 | SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
4bd13cde | 3060 | SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd RS |
3061 | SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ), |
3062 | SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
3063 | SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3064 | SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), | |
3065 | SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), | |
3066 | SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3067 | SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
3068 | SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), | |
3069 | SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), | |
3070 | SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
3071 | SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
3072 | SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ), | |
3073 | SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ), | |
3074 | SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), | |
3075 | SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), | |
3076 | SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS, 0), | |
3077 | SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS2, 0), | |
3078 | SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
4bd13cde | 3079 | SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3080 | SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3081 | SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3082 | SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3083 | SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3084 | SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3085 | SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3086 | SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3087 | SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3088 | SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3089 | SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd RS |
3090 | SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS), |
3091 | SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS), | |
3092 | SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), | |
3093 | SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), | |
4bd13cde | 3094 | SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3095 | SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3096 | SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3097 | SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3098 | SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3099 | SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3100 | SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3101 | SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3102 | SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3103 | SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3104 | SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd RS |
3105 | SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
3106 | SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), | |
4bd13cde | 3107 | SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
9d30b0bd | 3108 | SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
4bd13cde | 3109 | SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
a06ea964 | 3110 | /* AdvSIMD ZIP/UZP/TRN. */ |
9d30b0bd RS |
3111 | SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
3112 | SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3113 | SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3114 | SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3115 | SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3116 | SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
a06ea964 | 3117 | /* AdvSIMD three same. */ |
9d30b0bd RS |
3118 | SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
3119 | SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3120 | SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3121 | SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3122 | SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3123 | SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3124 | SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3125 | SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3126 | SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3127 | SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3128 | SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3129 | SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3130 | SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3131 | SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3132 | SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3133 | SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3134 | SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3135 | SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3136 | SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3137 | SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3138 | SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3139 | SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
3140 | SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3141 | SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
4bd13cde | 3142 | SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3143 | SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3144 | SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3145 | SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3146 | SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3147 | SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3148 | SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3149 | SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3150 | SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3151 | SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3152 | SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3153 | SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3154 | SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd RS |
3155 | SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
3156 | SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
3157 | SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
4bd13cde | 3158 | SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3159 | SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3160 | SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3161 | SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3162 | SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3163 | SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3164 | SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3165 | SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3166 | SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3167 | SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ), |
5ce912d8 | 3168 | SIMD_INSN ("mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV), |
9d30b0bd RS |
3169 | SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
3170 | SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3171 | SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3172 | SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3173 | SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3174 | SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3175 | SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3176 | SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3177 | SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3178 | SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3179 | SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3180 | SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3181 | SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3182 | SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3183 | SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3184 | SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3185 | SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3186 | SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), | |
3187 | SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3188 | SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
3189 | SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3190 | SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), | |
3191 | SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
3192 | SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
4bd13cde | 3193 | SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3194 | SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3195 | SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3196 | SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3197 | SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3198 | SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3199 | SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3200 | SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3201 | SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3202 | SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3203 | SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3204 | SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3205 | SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd RS |
3206 | SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
3207 | SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
3208 | SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), | |
4bd13cde | 3209 | SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3210 | SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3211 | SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3212 | SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3213 | SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3214 | SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3215 | SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd | 3216 | SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
4bd13cde | 3217 | SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
9d30b0bd RS |
3218 | SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
3219 | SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), | |
9e1f0fa7 | 3220 | /* AdvSIMD three same extension. */ |
10bba94b TC |
3221 | RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
3222 | RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), | |
f482d304 RS |
3223 | CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ), |
3224 | CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ), | |
a06ea964 | 3225 | /* AdvSIMD shift by immediate. */ |
9d30b0bd RS |
3226 | SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
3227 | SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3228 | SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3229 | SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3230 | SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
3231 | SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
3232 | SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3233 | SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3234 | SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3235 | SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3236 | SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3237 | SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3238 | SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3239 | SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3240 | SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
5ce912d8 | 3241 | SIMD_INSN ("sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
9d30b0bd | 3242 | SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
5ce912d8 | 3243 | SIMD_INSN ("sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
9d30b0bd | 3244 | SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
4bd13cde | 3245 | SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
9d30b0bd | 3246 | SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
4bd13cde | 3247 | SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
9d30b0bd RS |
3248 | SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
3249 | SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3250 | SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3251 | SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3252 | SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), | |
3253 | SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
3254 | SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
3255 | SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), | |
3256 | SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3257 | SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3258 | SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3259 | SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3260 | SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3261 | SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3262 | SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), | |
3263 | SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), | |
3264 | SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), | |
5ce912d8 | 3265 | SIMD_INSN ("uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
9d30b0bd | 3266 | SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
5ce912d8 | 3267 | SIMD_INSN ("uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
9d30b0bd | 3268 | SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
4bd13cde | 3269 | SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
9d30b0bd | 3270 | SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
4bd13cde | 3271 | SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
a06ea964 | 3272 | /* AdvSIMD TBL/TBX. */ |
9d30b0bd RS |
3273 | SIMD_INSN ("tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), |
3274 | SIMD_INSN ("tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), | |
a06ea964 | 3275 | /* AdvSIMD scalar three different. */ |
9d30b0bd RS |
3276 | SIMD_INSN ("sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), |
3277 | SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
3278 | SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), | |
a06ea964 | 3279 | /* AdvSIMD scalar x indexed element. */ |
45a28947 TC |
3280 | SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), |
3281 | SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
3282 | SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), | |
3283 | SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
3284 | SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
6456d318 | 3285 | _SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
369c9167 | 3286 | SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
6456d318 | 3287 | _SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
369c9167 | 3288 | SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
6456d318 | 3289 | _SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
369c9167 | 3290 | SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
6456d318 | 3291 | _SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)), |
369c9167 TC |
3292 | SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), |
3293 | RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
3294 | RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), | |
a06ea964 | 3295 | /* AdvSIMD load/store multiple structures. */ |
9d30b0bd RS |
3296 | SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
3297 | SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
3298 | SIMD_INSN ("st2", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
3299 | SIMD_INSN ("st3", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
3300 | SIMD_INSN ("ld4", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
3301 | SIMD_INSN ("ld1", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
3302 | SIMD_INSN ("ld2", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
3303 | SIMD_INSN ("ld3", 0xc400000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
a06ea964 | 3304 | /* AdvSIMD load/store multiple structures (post-indexed). */ |
9d30b0bd RS |
3305 | SIMD_INSN ("st4", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), |
3306 | SIMD_INSN ("st1", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
3307 | SIMD_INSN ("st2", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
3308 | SIMD_INSN ("st3", 0xc800000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
3309 | SIMD_INSN ("ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), | |
3310 | SIMD_INSN ("ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), | |
3311 | SIMD_INSN ("ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), | |
3312 | SIMD_INSN ("ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), | |
a06ea964 | 3313 | /* AdvSIMD load/store single structure. */ |
9d30b0bd RS |
3314 | SIMD_INSN ("st1", 0xd000000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), |
3315 | SIMD_INSN ("st3", 0xd002000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
3316 | SIMD_INSN ("st2", 0xd200000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), | |
3317 | SIMD_INSN ("st4", 0xd202000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
3318 | SIMD_INSN ("ld1", 0xd400000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), | |
3319 | SIMD_INSN ("ld3", 0xd402000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), | |
792f174f NC |
3320 | SIMD_INSN ("ld1r", 0xd40c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
3321 | SIMD_INSN ("ld3r", 0xd40e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
9d30b0bd RS |
3322 | SIMD_INSN ("ld2", 0xd600000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), |
3323 | SIMD_INSN ("ld4", 0xd602000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), | |
792f174f NC |
3324 | SIMD_INSN ("ld2r", 0xd60c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
3325 | SIMD_INSN ("ld4r", 0xd60e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
a06ea964 | 3326 | /* AdvSIMD load/store single structure (post-indexed). */ |
9d30b0bd RS |
3327 | SIMD_INSN ("st1", 0xd800000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), |
3328 | SIMD_INSN ("st3", 0xd802000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
3329 | SIMD_INSN ("st2", 0xda00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), | |
3330 | SIMD_INSN ("st4", 0xda02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
3331 | SIMD_INSN ("ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), | |
3332 | SIMD_INSN ("ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), | |
792f174f NC |
3333 | SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), |
3334 | SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), | |
9d30b0bd RS |
3335 | SIMD_INSN ("ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), |
3336 | SIMD_INSN ("ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), | |
792f174f NC |
3337 | SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), |
3338 | SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), | |
a06ea964 | 3339 | /* AdvSIMD scalar two-reg misc. */ |
9d30b0bd RS |
3340 | SIMD_INSN ("suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
3341 | SIMD_INSN ("sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
3342 | SIMD_INSN ("cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
3343 | SIMD_INSN ("cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
3344 | SIMD_INSN ("cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
3345 | SIMD_INSN ("abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
3346 | SIMD_INSN ("sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
3347 | SIMD_INSN ("fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), | |
4bd13cde | 3348 | SF16_INSN ("fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3349 | SIMD_INSN ("fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3350 | SF16_INSN ("fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3351 | SIMD_INSN ("fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3352 | SF16_INSN ("fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3353 | SIMD_INSN ("scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3354 | SF16_INSN ("scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3355 | SIMD_INSN ("fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
4bd13cde | 3356 | SF16_INSN ("fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3357 | SIMD_INSN ("fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
4bd13cde | 3358 | SF16_INSN ("fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3359 | SIMD_INSN ("fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
4bd13cde | 3360 | SF16_INSN ("fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3361 | SIMD_INSN ("fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3362 | SF16_INSN ("fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3363 | SIMD_INSN ("fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3364 | SF16_INSN ("fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3365 | SIMD_INSN ("frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3366 | SF16_INSN ("frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3367 | SIMD_INSN ("frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3368 | SF16_INSN ("frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd RS |
3369 | SIMD_INSN ("usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), |
3370 | SIMD_INSN ("sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), | |
3371 | SIMD_INSN ("cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
3372 | SIMD_INSN ("cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), | |
3373 | SIMD_INSN ("neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), | |
3374 | SIMD_INSN ("sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
3375 | SIMD_INSN ("uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), | |
5ce912d8 | 3376 | SIMD_INSN ("fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC), |
9d30b0bd | 3377 | SIMD_INSN ("fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3378 | SF16_INSN ("fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3379 | SIMD_INSN ("fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3380 | SF16_INSN ("fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3381 | SIMD_INSN ("fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3382 | SF16_INSN ("fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3383 | SIMD_INSN ("ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3384 | SF16_INSN ("ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3385 | SIMD_INSN ("fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
4bd13cde | 3386 | SF16_INSN ("fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3387 | SIMD_INSN ("fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), |
4bd13cde | 3388 | SF16_INSN ("fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3389 | SIMD_INSN ("fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3390 | SF16_INSN ("fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE), |
9d30b0bd | 3391 | SIMD_INSN ("fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3392 | SF16_INSN ("fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
9d30b0bd | 3393 | SIMD_INSN ("frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), |
4bd13cde | 3394 | SF16_INSN ("frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), |
a06ea964 | 3395 | /* AdvSIMD scalar copy. */ |
9d30b0bd RS |
3396 | SIMD_INSN ("dup", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS), |
3397 | SIMD_INSN ("mov", 0x5e000400, 0xffe0fc00, asisdone, 0, OP2 (Sd, En), QL_S_2SAME, F_ALIAS), | |
a06ea964 | 3398 | /* AdvSIMD scalar pairwise. */ |
9d30b0bd RS |
3399 | SIMD_INSN ("addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ), |
3400 | SIMD_INSN ("fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), | |
4bd13cde | 3401 | SF16_INSN ("fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
9d30b0bd | 3402 | SIMD_INSN ("faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
4bd13cde | 3403 | SF16_INSN ("faddp", 0x5e30d800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
9d30b0bd | 3404 | SIMD_INSN ("fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
4bd13cde | 3405 | SF16_INSN ("fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
9d30b0bd | 3406 | SIMD_INSN ("fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
4bd13cde | 3407 | SF16_INSN ("fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
9d30b0bd | 3408 | SIMD_INSN ("fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), |
4bd13cde | 3409 | SF16_INSN ("fminp", 0x5eb0f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), |
a06ea964 | 3410 | /* AdvSIMD scalar three same. */ |
9d30b0bd RS |
3411 | SIMD_INSN ("sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), |
3412 | SIMD_INSN ("sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3413 | SIMD_INSN ("sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3414 | SIMD_INSN ("sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3415 | SIMD_INSN ("sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
3416 | SIMD_INSN ("fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
4bd13cde | 3417 | SF16_INSN ("fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3418 | SIMD_INSN ("fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3419 | SF16_INSN ("fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3420 | SIMD_INSN ("frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3421 | SF16_INSN ("frecps", 0x5e403c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3422 | SIMD_INSN ("frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3423 | SF16_INSN ("frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd RS |
3424 | SIMD_INSN ("cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
3425 | SIMD_INSN ("cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3426 | SIMD_INSN ("sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3427 | SIMD_INSN ("srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3428 | SIMD_INSN ("add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3429 | SIMD_INSN ("cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3430 | SIMD_INSN ("uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3431 | SIMD_INSN ("uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3432 | SIMD_INSN ("uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3433 | SIMD_INSN ("uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), | |
3434 | SIMD_INSN ("sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
3435 | SIMD_INSN ("fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), | |
4bd13cde | 3436 | SF16_INSN ("fcmge", 0x7e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3437 | SIMD_INSN ("facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3438 | SF16_INSN ("facge", 0x7e402c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3439 | SIMD_INSN ("fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3440 | SF16_INSN ("fabd", 0x7ec01400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3441 | SIMD_INSN ("fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3442 | SF16_INSN ("fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd | 3443 | SIMD_INSN ("facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), |
4bd13cde | 3444 | SF16_INSN ("facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), |
9d30b0bd RS |
3445 | SIMD_INSN ("cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), |
3446 | SIMD_INSN ("cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3447 | SIMD_INSN ("ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3448 | SIMD_INSN ("urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3449 | SIMD_INSN ("sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
3450 | SIMD_INSN ("cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), | |
9e1f0fa7 | 3451 | /* AdvSIMDs scalar three same extension. */ |
4bd13cde NC |
3452 | RDMA_INSN ("sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), |
3453 | RDMA_INSN ("sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), | |
a06ea964 | 3454 | /* AdvSIMD scalar shift by immediate. */ |
9d30b0bd RS |
3455 | SIMD_INSN ("sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
3456 | SIMD_INSN ("ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3457 | SIMD_INSN ("srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3458 | SIMD_INSN ("srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3459 | SIMD_INSN ("shl", 0x5f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
3460 | SIMD_INSN ("sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
3461 | SIMD_INSN ("sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3462 | SIMD_INSN ("sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3463 | SIMD_INSN ("scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
4bd13cde | 3464 | SF16_INSN ("scvtf", 0x5f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
9d30b0bd | 3465 | SIMD_INSN ("fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
4bd13cde | 3466 | SF16_INSN ("fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
9d30b0bd RS |
3467 | SIMD_INSN ("ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), |
3468 | SIMD_INSN ("usra", 0x7f001400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3469 | SIMD_INSN ("urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3470 | SIMD_INSN ("ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3471 | SIMD_INSN ("sri", 0x7f004400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), | |
3472 | SIMD_INSN ("sli", 0x7f005400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), | |
3473 | SIMD_INSN ("sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
3474 | SIMD_INSN ("uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), | |
3475 | SIMD_INSN ("sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3476 | SIMD_INSN ("sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3477 | SIMD_INSN ("uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3478 | SIMD_INSN ("uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), | |
3479 | SIMD_INSN ("ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), | |
4bd13cde | 3480 | SF16_INSN ("ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
9d30b0bd | 3481 | SIMD_INSN ("fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), |
4bd13cde | 3482 | SF16_INSN ("fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), |
a06ea964 | 3483 | /* Bitfield. */ |
9d30b0bd | 3484 | CORE_INSN ("sbfm", 0x13000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
5ce912d8 RS |
3485 | CORE_INSN ("sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
3486 | CORE_INSN ("sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
9d30b0bd RS |
3487 | CORE_INSN ("sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), |
3488 | CORE_INSN ("sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), | |
3489 | CORE_INSN ("sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3), | |
5ce912d8 | 3490 | CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), |
9d30b0bd | 3491 | CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
5ce912d8 | 3492 | CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
a4822788 | 3493 | V8_2A_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV), |
5ce912d8 | 3494 | CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
9d30b0bd | 3495 | CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), |
5ce912d8 RS |
3496 | CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), |
3497 | CORE_INSN ("ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), | |
3498 | CORE_INSN ("uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
3499 | CORE_INSN ("uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3), | |
3500 | CORE_INSN ("lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
3501 | CORE_INSN ("lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), | |
a06ea964 | 3502 | /* Unconditional branch (immediate). */ |
5ce912d8 RS |
3503 | CORE_INSN ("b", 0x14000000, 0xfc000000, branch_imm, OP_B, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), |
3504 | CORE_INSN ("bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, OP1 (ADDR_PCREL26), QL_PCREL_26, 0), | |
a06ea964 | 3505 | /* Unconditional branch (register). */ |
9d30b0bd RS |
3506 | CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), |
3507 | CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, 0), | |
3508 | CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)), | |
3509 | CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
3510 | CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0), | |
af1bd771 PW |
3511 | PAC_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), |
3512 | PAC_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
3513 | PAC_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
3514 | PAC_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0), | |
3515 | PAC_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
3516 | PAC_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
3517 | PAC_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
3518 | PAC_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), | |
3519 | PAC_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
3520 | PAC_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
3521 | PAC_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
3522 | PAC_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0), | |
a06ea964 | 3523 | /* Compare & branch (immediate). */ |
9d30b0bd RS |
3524 | CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), |
3525 | CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), | |
a06ea964 | 3526 | /* Conditional branch (immediate). */ |
9d30b0bd | 3527 | CORE_INSN ("b.c", 0x54000000, 0xff000010, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND), |
a06ea964 | 3528 | /* Conditional compare (immediate). */ |
9d30b0bd RS |
3529 | CORE_INSN ("ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), |
3530 | CORE_INSN ("ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), | |
a06ea964 | 3531 | /* Conditional compare (register). */ |
9d30b0bd RS |
3532 | CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), |
3533 | CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), | |
a06ea964 | 3534 | /* Conditional select. */ |
9d30b0bd RS |
3535 | CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF), |
3536 | CORE_INSN ("csinc", 0x1a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), | |
5ce912d8 RS |
3537 | CORE_INSN ("cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
3538 | CORE_INSN ("cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
9d30b0bd | 3539 | CORE_INSN ("csinv", 0x5a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
5ce912d8 RS |
3540 | CORE_INSN ("cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
3541 | CORE_INSN ("csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV), | |
9d30b0bd | 3542 | CORE_INSN ("csneg", 0x5a800400, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), |
5ce912d8 | 3543 | CORE_INSN ("cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV), |
a06ea964 | 3544 | /* Crypto AES. */ |
c0e7cef7 NC |
3545 | AES_INSN ("aese", 0x4e284800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), |
3546 | AES_INSN ("aesd", 0x4e285800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
3547 | AES_INSN ("aesmc", 0x4e286800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
3548 | AES_INSN ("aesimc", 0x4e287800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), | |
a06ea964 | 3549 | /* Crypto two-reg SHA. */ |
c0e7cef7 NC |
3550 | SHA2_INSN ("sha1h", 0x5e280800, 0xfffffc00, cryptosha2, OP2 (Fd, Fn), QL_2SAMES, 0), |
3551 | SHA2_INSN ("sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
3552 | SHA2_INSN ("sha256su0",0x5e282800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
a06ea964 | 3553 | /* Crypto three-reg SHA. */ |
c0e7cef7 NC |
3554 | SHA2_INSN ("sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), |
3555 | SHA2_INSN ("sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
3556 | SHA2_INSN ("sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), | |
3557 | SHA2_INSN ("sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
3558 | SHA2_INSN ("sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
3559 | SHA2_INSN ("sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), | |
3560 | SHA2_INSN ("sha256su1",0x5e006000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
a06ea964 | 3561 | /* Data-processing (1 source). */ |
9d30b0bd RS |
3562 | CORE_INSN ("rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
3563 | CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
3564 | CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0), | |
3565 | CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), | |
a4822788 | 3566 | V8_2A_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), |
9d30b0bd RS |
3567 | CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), |
3568 | CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
3569 | CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0), | |
af1bd771 PW |
3570 | PAC_INSN ("pacia", 0xdac10000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), |
3571 | PAC_INSN ("pacib", 0xdac10400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3572 | PAC_INSN ("pacda", 0xdac10800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3573 | PAC_INSN ("pacdb", 0xdac10c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3574 | PAC_INSN ("autia", 0xdac11000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3575 | PAC_INSN ("autib", 0xdac11400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3576 | PAC_INSN ("autda", 0xdac11800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3577 | PAC_INSN ("autdb", 0xdac11c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0), | |
3578 | PAC_INSN ("paciza", 0xdac123e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3579 | PAC_INSN ("pacizb", 0xdac127e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3580 | PAC_INSN ("pacdza", 0xdac12be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3581 | PAC_INSN ("pacdzb", 0xdac12fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3582 | PAC_INSN ("autiza", 0xdac133e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3583 | PAC_INSN ("autizb", 0xdac137e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3584 | PAC_INSN ("autdza", 0xdac13be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3585 | PAC_INSN ("autdzb", 0xdac13fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3586 | PAC_INSN ("xpaci", 0xdac143e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
3587 | PAC_INSN ("xpacd", 0xdac147e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0), | |
a06ea964 | 3588 | /* Data-processing (2 source). */ |
9d30b0bd RS |
3589 | CORE_INSN ("udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
3590 | CORE_INSN ("sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
3591 | CORE_INSN ("lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
3592 | CORE_INSN ("lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
3593 | CORE_INSN ("lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
3594 | CORE_INSN ("lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
3595 | CORE_INSN ("asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
3596 | CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
3597 | CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), | |
3598 | CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), | |
b731bc3b SD |
3599 | MEMTAG_INSN ("subp", 0x9ac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, 0), |
3600 | MEMTAG_INSN ("subps", 0xbac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, F_HAS_ALIAS), | |
3601 | MEMTAG_INSN ("cmpp", 0xbac0001f, 0xffe0fc1f, dp_2src, OP2 (Rn_SP, Rm_SP), QL_I2SAMEX, F_ALIAS), | |
193614f2 SD |
3602 | MEMTAG_INSN ("irg", 0x9ac01000, 0xffe0fc00, dp_2src, OP3 (Rd_SP, Rn_SP, Rm), QL_I3SAMEX, F_OPD2_OPT | F_DEFAULT (0x1f)), |
3603 | MEMTAG_INSN ("gmi", 0x9ac01400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm), QL_I3SAMEX, 0), | |
af1bd771 | 3604 | PAC_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0), |
e60bb1dd | 3605 | /* CRC instructions. */ |
4bd13cde NC |
3606 | _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), |
3607 | _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
3608 | _CRC_INSN ("crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
3609 | _CRC_INSN ("crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
3610 | _CRC_INSN ("crc32cb",0x1ac05000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
3611 | _CRC_INSN ("crc32ch",0x1ac05400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
3612 | _CRC_INSN ("crc32cw",0x1ac05800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), | |
3613 | _CRC_INSN ("crc32cx",0x9ac05c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), | |
a06ea964 | 3614 | /* Data-processing (3 source). */ |
9d30b0bd RS |
3615 | CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), |
3616 | CORE_INSN ("mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
3617 | CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), | |
3618 | CORE_INSN ("mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), | |
3619 | CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
3620 | CORE_INSN ("smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
3621 | CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
3622 | CORE_INSN ("smnegl",0x9b20fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
3623 | CORE_INSN ("smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
3624 | CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
3625 | CORE_INSN ("umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
3626 | CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), | |
3627 | CORE_INSN ("umnegl",0x9ba0fc00, 0xffe0fc00, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), | |
3628 | CORE_INSN ("umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), | |
a06ea964 | 3629 | /* Excep'n generation. */ |
9d30b0bd RS |
3630 | CORE_INSN ("svc", 0xd4000001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), |
3631 | CORE_INSN ("hvc", 0xd4000002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
3632 | CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
3633 | CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
3634 | CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), | |
09c1e68a | 3635 | CORE_INSN ("udf", 0x00000000, 0xffff0000, exception, 0, OP1 (UNDEFINED), {}, 0), |
9d30b0bd RS |
3636 | CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), |
3637 | CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
3638 | CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), | |
a06ea964 | 3639 | /* Extract. */ |
9d30b0bd | 3640 | CORE_INSN ("extr", 0x13800000, 0x7fa00000, extract, 0, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N), |
5ce912d8 | 3641 | CORE_INSN ("ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV), |
a06ea964 | 3642 | /* Floating-point<->fixed-point conversions. */ |
9d30b0bd | 3643 | __FP_INSN ("scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
4bd13cde | 3644 | FF16_INSN ("scvtf", 0x1ec20000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
9d30b0bd | 3645 | __FP_INSN ("ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), |
4bd13cde | 3646 | FF16_INSN ("ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), |
9d30b0bd | 3647 | __FP_INSN ("fcvtzs",0x1e180000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
4bd13cde | 3648 | FF16_INSN ("fcvtzs",0x1ed80000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
9d30b0bd | 3649 | __FP_INSN ("fcvtzu",0x1e190000, 0x7f3f0000, float2fix, 0, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), |
4bd13cde | 3650 | FF16_INSN ("fcvtzu",0x1ed90000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), |
a06ea964 | 3651 | /* Floating-point<->integer conversions. */ |
9d30b0bd | 3652 | __FP_INSN ("fcvtns",0x1e200000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3653 | FF16_INSN ("fcvtns",0x1ee00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3654 | __FP_INSN ("fcvtnu",0x1e210000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3655 | FF16_INSN ("fcvtnu",0x1ee10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3656 | __FP_INSN ("scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
4bd13cde | 3657 | FF16_INSN ("scvtf", 0x1ee20000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
9d30b0bd | 3658 | __FP_INSN ("ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), |
4bd13cde | 3659 | FF16_INSN ("ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
9d30b0bd | 3660 | __FP_INSN ("fcvtas",0x1e240000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3661 | FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3662 | __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3663 | FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
cb366992 | 3664 | __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF), |
4bd13cde | 3665 | FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
cb366992 | 3666 | __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF), |
4bd13cde | 3667 | FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), |
9d30b0bd | 3668 | __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3669 | FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3670 | __FP_INSN ("fcvtpu",0x1e290000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3671 | FF16_INSN ("fcvtpu",0x1ee90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3672 | __FP_INSN ("fcvtms",0x1e300000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3673 | FF16_INSN ("fcvtms",0x1ef00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3674 | __FP_INSN ("fcvtmu",0x1e310000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3675 | FF16_INSN ("fcvtmu",0x1ef10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3676 | __FP_INSN ("fcvtzs",0x1e380000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3677 | FF16_INSN ("fcvtzs",0x1ef80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd | 3678 | __FP_INSN ("fcvtzu",0x1e390000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), |
4bd13cde | 3679 | FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |
9d30b0bd RS |
3680 | __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0), |
3681 | __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0), | |
a4822788 | 3682 | {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3A, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL }, |
a06ea964 | 3683 | /* Floating-point conditional compare. */ |
9d30b0bd | 3684 | __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
4bd13cde | 3685 | FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
9d30b0bd | 3686 | __FP_INSN ("fccmpe",0x1e200410, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), |
4bd13cde | 3687 | FF16_INSN ("fccmpe",0x1ee00410, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), |
a06ea964 | 3688 | /* Floating-point compare. */ |
9d30b0bd | 3689 | __FP_INSN ("fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
4bd13cde | 3690 | FF16_INSN ("fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3691 | __FP_INSN ("fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), |
4bd13cde | 3692 | FF16_INSN ("fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3693 | __FP_INSN ("fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
4bd13cde | 3694 | FF16_INSN ("fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3695 | __FP_INSN ("fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), |
4bd13cde | 3696 | FF16_INSN ("fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), |
13c60ad7 SD |
3697 | /* Data processing instructions ARMv8.5-A. */ |
3698 | FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0), | |
3699 | FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0), | |
3700 | FRINTTS_INSN ("frint32z", 0x1e284000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
3701 | FRINTTS_INSN ("frint32x", 0x1e28c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
3702 | FRINTTS_INSN ("frint64z", 0x1e294000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
3703 | FRINTTS_INSN ("frint64x", 0x1e29c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), | |
a06ea964 | 3704 | /* Floating-point data-processing (1 source). */ |
9d30b0bd | 3705 | __FP_INSN ("fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3706 | FF16_INSN ("fmov", 0x1ee04000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3707 | __FP_INSN ("fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3708 | FF16_INSN ("fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3709 | __FP_INSN ("fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3710 | FF16_INSN ("fneg", 0x1ee14000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3711 | __FP_INSN ("fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3712 | FF16_INSN ("fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
5ce912d8 | 3713 | __FP_INSN ("fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC), |
9d30b0bd | 3714 | __FP_INSN ("frintn",0x1e244000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3715 | FF16_INSN ("frintn",0x1ee44000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3716 | __FP_INSN ("frintp",0x1e24c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3717 | FF16_INSN ("frintp",0x1ee4c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3718 | __FP_INSN ("frintm",0x1e254000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3719 | FF16_INSN ("frintm",0x1ee54000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3720 | __FP_INSN ("frintz",0x1e25c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3721 | FF16_INSN ("frintz",0x1ee5c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3722 | __FP_INSN ("frinta",0x1e264000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3723 | FF16_INSN ("frinta",0x1ee64000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3724 | __FP_INSN ("frintx",0x1e274000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3725 | FF16_INSN ("frintx",0x1ee74000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
9d30b0bd | 3726 | __FP_INSN ("frinti",0x1e27c000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), |
4bd13cde | 3727 | FF16_INSN ("frinti",0x1ee7c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), |
a06ea964 | 3728 | /* Floating-point data-processing (2 source). */ |
9d30b0bd | 3729 | __FP_INSN ("fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3730 | FF16_INSN ("fmul", 0x1ee00800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3731 | __FP_INSN ("fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3732 | FF16_INSN ("fdiv", 0x1ee01800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3733 | __FP_INSN ("fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3734 | FF16_INSN ("fadd", 0x1ee02800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3735 | __FP_INSN ("fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3736 | FF16_INSN ("fsub", 0x1ee03800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3737 | __FP_INSN ("fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3738 | FF16_INSN ("fmax", 0x1ee04800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3739 | __FP_INSN ("fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3740 | FF16_INSN ("fmin", 0x1ee05800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3741 | __FP_INSN ("fmaxnm",0x1e206800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3742 | FF16_INSN ("fmaxnm",0x1ee06800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3743 | __FP_INSN ("fminnm",0x1e207800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3744 | FF16_INSN ("fminnm",0x1ee07800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
9d30b0bd | 3745 | __FP_INSN ("fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), |
4bd13cde | 3746 | FF16_INSN ("fnmul", 0x1ee08800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), |
a06ea964 | 3747 | /* Floating-point data-processing (3 source). */ |
9d30b0bd | 3748 | __FP_INSN ("fmadd", 0x1f000000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
4bd13cde | 3749 | FF16_INSN ("fmadd", 0x1fc00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
9d30b0bd | 3750 | __FP_INSN ("fmsub", 0x1f008000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
4bd13cde | 3751 | FF16_INSN ("fmsub", 0x1fc08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
9d30b0bd | 3752 | __FP_INSN ("fnmadd",0x1f200000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
4bd13cde | 3753 | FF16_INSN ("fnmadd",0x1fe00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
9d30b0bd | 3754 | __FP_INSN ("fnmsub",0x1f208000, 0xff208000, floatdp3, 0, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), |
4bd13cde | 3755 | FF16_INSN ("fnmsub",0x1fe08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), |
a06ea964 | 3756 | /* Floating-point immediate. */ |
9d30b0bd | 3757 | __FP_INSN ("fmov", 0x1e201000, 0xff201fe0, floatimm, 0, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE), |
4bd13cde | 3758 | FF16_INSN ("fmov", 0x1ee01000, 0xff201fe0, floatimm, OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE), |
a06ea964 | 3759 | /* Floating-point conditional select. */ |
9d30b0bd | 3760 | __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE), |
4bd13cde | 3761 | FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE), |
a06ea964 | 3762 | /* Load/store register (immediate indexed). */ |
9d30b0bd RS |
3763 | CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
3764 | CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
3765 | CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
3766 | CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
3767 | CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
3768 | CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3769 | CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3770 | CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
3771 | CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3772 | CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3773 | CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
fb3265b3 | 3774 | /* Load/store Allocation Tag instructions. */ |
bd7ceb8d SD |
3775 | MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), |
3776 | MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3777 | MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3778 | MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3779 | MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3780 | MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3781 | MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
3782 | MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0), | |
a06ea964 | 3783 | /* Load/store register (unsigned immediate). */ |
5ce912d8 RS |
3784 | CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), |
3785 | CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0), | |
3786 | CORE_INSN ("ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE), | |
3787 | CORE_INSN ("str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
3788 | CORE_INSN ("ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0), | |
3789 | CORE_INSN ("strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
3790 | CORE_INSN ("ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0), | |
3791 | CORE_INSN ("ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE), | |
3792 | CORE_INSN ("str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3793 | CORE_INSN ("ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3794 | CORE_INSN ("ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0), | |
3795 | CORE_INSN ("prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0), | |
a06ea964 | 3796 | /* Load/store register (register offset). */ |
9d30b0bd RS |
3797 | CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), |
3798 | CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), | |
3799 | CORE_INSN ("ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE), | |
3800 | CORE_INSN ("str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
3801 | CORE_INSN ("ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), | |
3802 | CORE_INSN ("strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
3803 | CORE_INSN ("ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), | |
3804 | CORE_INSN ("ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE), | |
3805 | CORE_INSN ("str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3806 | CORE_INSN ("ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3807 | CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0), | |
3808 | CORE_INSN ("prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0), | |
a06ea964 | 3809 | /* Load/store register (unprivileged). */ |
9d30b0bd RS |
3810 | CORE_INSN ("sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
3811 | CORE_INSN ("ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
3812 | CORE_INSN ("ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
3813 | CORE_INSN ("sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3814 | CORE_INSN ("ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3815 | CORE_INSN ("ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
3816 | CORE_INSN ("sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3817 | CORE_INSN ("ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3818 | CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
a06ea964 | 3819 | /* Load/store register (unscaled immediate). */ |
5ce912d8 RS |
3820 | CORE_INSN ("sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), |
3821 | CORE_INSN ("ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), | |
3822 | CORE_INSN ("ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), | |
3823 | CORE_INSN ("stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
3824 | CORE_INSN ("ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), | |
3825 | CORE_INSN ("sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3826 | CORE_INSN ("ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), | |
3827 | CORE_INSN ("ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), | |
3828 | CORE_INSN ("stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3829 | CORE_INSN ("ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), | |
3830 | CORE_INSN ("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), | |
3831 | CORE_INSN ("prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0), | |
e6025b54 | 3832 | MEMTAG_INSN ("ldg", 0xd9600000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDG, 0), |
3f06e550 | 3833 | /* Load/store register (scaled signed immediate). */ |
af1bd771 PW |
3834 | PAC_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), |
3835 | PAC_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0), | |
a06ea964 | 3836 | /* Load/store exclusive. */ |
9d30b0bd RS |
3837 | CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
3838 | CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3839 | CORE_INSN ("ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3840 | CORE_INSN ("ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3841 | CORE_INSN ("stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3842 | CORE_INSN ("ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3843 | CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3844 | CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3845 | CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3846 | CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3847 | CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
f311ba7e | 3848 | CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
9d30b0bd RS |
3849 | CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), |
3850 | CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), | |
3851 | CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
3852 | CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), | |
3853 | CORE_INSN ("ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
3854 | CORE_INSN ("ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
3855 | CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
3856 | CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), | |
3857 | CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
3858 | CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
d74d4880 SN |
3859 | RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |
3860 | RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3861 | RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
e54010f1 SD |
3862 | MEMTAG_INSN ("ldgm", 0xd9e00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), |
3863 | MEMTAG_INSN ("stgm", 0xd9a00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), | |
20a4ca55 | 3864 | MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), |
290806fd | 3865 | /* Limited Ordering Regions load/store instructions. */ |
4bd13cde NC |
3866 | _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), |
3867 | _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3868 | _LOR_INSN ("ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3869 | _LOR_INSN ("stllr", 0x889f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), | |
3870 | _LOR_INSN ("stllrb", 0x089f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
3871 | _LOR_INSN ("stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), | |
a06ea964 | 3872 | /* Load/store no-allocate pair (offset). */ |
9d30b0bd RS |
3873 | CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
3874 | CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
3875 | CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
3876 | CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
a06ea964 | 3877 | /* Load/store register pair (offset). */ |
9d30b0bd RS |
3878 | CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
3879 | CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
3880 | CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
3881 | CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
eae424ae | 3882 | {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
fb3265b3 | 3883 | MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0), |
a06ea964 | 3884 | /* Load/store register pair (indexed). */ |
9d30b0bd RS |
3885 | CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), |
3886 | CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), | |
3887 | CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
3888 | CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), | |
eae424ae | 3889 | {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)}, |
fb3265b3 | 3890 | MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0), |
a06ea964 | 3891 | /* Load register (literal). */ |
5ce912d8 RS |
3892 | CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q), |
3893 | CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0), | |
3894 | CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0), | |
3895 | CORE_INSN ("prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0), | |
fd65497d | 3896 | /* Atomic 64-byte load/store in Armv8.7. */ |
52efda82 TB |
3897 | _LS64_INSN ("ld64b", 0xf83fd000, 0xfffffc00, lse_atomic, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0), |
3898 | _LS64_INSN ("st64b", 0xf83f9000, 0xfffffc00, lse_atomic, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0), | |
3899 | _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0), | |
3900 | _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0), | |
a06ea964 | 3901 | /* Logical (immediate). */ |
9d30b0bd | 3902 | CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
5ce912d8 | 3903 | CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF), |
9d30b0bd | 3904 | CORE_INSN ("orr", 0x32000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
5ce912d8 | 3905 | CORE_INSN ("mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV), |
9d30b0bd RS |
3906 | CORE_INSN ("eor", 0x52000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF), |
3907 | CORE_INSN ("ands", 0x72000000, 0x7f800000, log_imm, 0, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), | |
3908 | CORE_INSN ("tst", 0x7200001f, 0x7f80001f, log_imm, 0, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF), | |
a06ea964 | 3909 | /* Logical (shifted register). */ |
9d30b0bd RS |
3910 | CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
3911 | CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
3912 | CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
57b64c41 | 3913 | CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), |
5ce912d8 | 3914 | CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO), |
9d30b0bd RS |
3915 | CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
3916 | CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
3917 | CORE_INSN ("eor", 0x4a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
3918 | CORE_INSN ("eon", 0x4a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
3919 | CORE_INSN ("ands", 0x6a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), | |
3920 | CORE_INSN ("tst", 0x6a00001f, 0x7f20001f, log_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), | |
3921 | CORE_INSN ("bics", 0x6a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), | |
ee804238 | 3922 | /* LSE extension (atomic). */ |
4bd13cde NC |
3923 | _LSE_INSN ("casb", 0x8a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), |
3924 | _LSE_INSN ("cash", 0x48a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3925 | _LSE_INSN ("cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3926 | _LSE_INSN ("casab", 0x8e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3927 | _LSE_INSN ("caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3928 | _LSE_INSN ("casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3929 | _LSE_INSN ("casah", 0x48e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3930 | _LSE_INSN ("caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3931 | _LSE_INSN ("casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3932 | _LSE_INSN ("casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3933 | _LSE_INSN ("casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3934 | _LSE_INSN ("casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3935 | _LSE_INSN ("casp", 0x8207c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
3936 | _LSE_INSN ("caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
3937 | _LSE_INSN ("caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
3938 | _LSE_INSN ("caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), | |
3939 | _LSE_INSN ("swpb", 0x38208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3940 | _LSE_INSN ("swph", 0x78208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3941 | _LSE_INSN ("swp", 0xb8208000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3942 | _LSE_INSN ("swpab", 0x38a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3943 | _LSE_INSN ("swplb", 0x38608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3944 | _LSE_INSN ("swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3945 | _LSE_INSN ("swpah", 0x78a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3946 | _LSE_INSN ("swplh", 0x78608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3947 | _LSE_INSN ("swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3948 | _LSE_INSN ("swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3949 | _LSE_INSN ("swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3950 | _LSE_INSN ("swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3951 | _LSE_INSN ("ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3952 | _LSE_INSN ("ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3953 | _LSE_INSN ("ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3954 | _LSE_INSN ("ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3955 | _LSE_INSN ("ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3956 | _LSE_INSN ("ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3957 | _LSE_INSN ("ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3958 | _LSE_INSN ("ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3959 | _LSE_INSN ("ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3960 | _LSE_INSN ("ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3961 | _LSE_INSN ("ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3962 | _LSE_INSN ("ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3963 | _LSE_INSN ("ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3964 | _LSE_INSN ("ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3965 | _LSE_INSN ("ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3966 | _LSE_INSN ("ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3967 | _LSE_INSN ("ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3968 | _LSE_INSN ("ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3969 | _LSE_INSN ("ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3970 | _LSE_INSN ("ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3971 | _LSE_INSN ("ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3972 | _LSE_INSN ("ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3973 | _LSE_INSN ("ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3974 | _LSE_INSN ("ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3975 | _LSE_INSN ("ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3976 | _LSE_INSN ("ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3977 | _LSE_INSN ("ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3978 | _LSE_INSN ("ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3979 | _LSE_INSN ("ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3980 | _LSE_INSN ("ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3981 | _LSE_INSN ("ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3982 | _LSE_INSN ("ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3983 | _LSE_INSN ("ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3984 | _LSE_INSN ("ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3985 | _LSE_INSN ("ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3986 | _LSE_INSN ("ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3987 | _LSE_INSN ("ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3988 | _LSE_INSN ("ldseth", 0x78203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3989 | _LSE_INSN ("ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3990 | _LSE_INSN ("ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3991 | _LSE_INSN ("ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3992 | _LSE_INSN ("ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3993 | _LSE_INSN ("ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3994 | _LSE_INSN ("ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
3995 | _LSE_INSN ("ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
3996 | _LSE_INSN ("ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3997 | _LSE_INSN ("ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
3998 | _LSE_INSN ("ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
3999 | _LSE_INSN ("ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4000 | _LSE_INSN ("ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4001 | _LSE_INSN ("ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4002 | _LSE_INSN ("ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4003 | _LSE_INSN ("ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4004 | _LSE_INSN ("ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4005 | _LSE_INSN ("ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4006 | _LSE_INSN ("ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4007 | _LSE_INSN ("ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4008 | _LSE_INSN ("ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4009 | _LSE_INSN ("ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4010 | _LSE_INSN ("ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4011 | _LSE_INSN ("ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4012 | _LSE_INSN ("ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4013 | _LSE_INSN ("ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4014 | _LSE_INSN ("ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4015 | _LSE_INSN ("ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4016 | _LSE_INSN ("ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4017 | _LSE_INSN ("ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4018 | _LSE_INSN ("ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4019 | _LSE_INSN ("ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4020 | _LSE_INSN ("ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4021 | _LSE_INSN ("ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4022 | _LSE_INSN ("ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4023 | _LSE_INSN ("ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4024 | _LSE_INSN ("ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4025 | _LSE_INSN ("ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4026 | _LSE_INSN ("ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4027 | _LSE_INSN ("ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4028 | _LSE_INSN ("ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4029 | _LSE_INSN ("ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4030 | _LSE_INSN ("ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4031 | _LSE_INSN ("ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4032 | _LSE_INSN ("ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4033 | _LSE_INSN ("ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4034 | _LSE_INSN ("ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4035 | _LSE_INSN ("lduminb", 0x38207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4036 | _LSE_INSN ("lduminh", 0x78207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4037 | _LSE_INSN ("ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4038 | _LSE_INSN ("lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4039 | _LSE_INSN ("lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4040 | _LSE_INSN ("lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4041 | _LSE_INSN ("lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4042 | _LSE_INSN ("lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), | |
4043 | _LSE_INSN ("lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), | |
4044 | _LSE_INSN ("ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4045 | _LSE_INSN ("lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), | |
4046 | _LSE_INSN ("lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), | |
4047 | _LSE_INSN ("staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4048 | _LSE_INSN ("staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4049 | _LSE_INSN ("stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4050 | _LSE_INSN ("staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4051 | _LSE_INSN ("staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4052 | _LSE_INSN ("staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4053 | _LSE_INSN ("stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4054 | _LSE_INSN ("stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4055 | _LSE_INSN ("stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4056 | _LSE_INSN ("stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4057 | _LSE_INSN ("stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4058 | _LSE_INSN ("stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4059 | _LSE_INSN ("steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4060 | _LSE_INSN ("steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4061 | _LSE_INSN ("steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4062 | _LSE_INSN ("steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4063 | _LSE_INSN ("steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4064 | _LSE_INSN ("steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4065 | _LSE_INSN ("stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4066 | _LSE_INSN ("stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4067 | _LSE_INSN ("stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4068 | _LSE_INSN ("stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4069 | _LSE_INSN ("stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4070 | _LSE_INSN ("stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4071 | _LSE_INSN ("stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4072 | _LSE_INSN ("stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4073 | _LSE_INSN ("stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4074 | _LSE_INSN ("stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4075 | _LSE_INSN ("stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4076 | _LSE_INSN ("stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4077 | _LSE_INSN ("stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4078 | _LSE_INSN ("stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4079 | _LSE_INSN ("stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4080 | _LSE_INSN ("stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4081 | _LSE_INSN ("stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4082 | _LSE_INSN ("stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4083 | _LSE_INSN ("stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4084 | _LSE_INSN ("stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4085 | _LSE_INSN ("stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4086 | _LSE_INSN ("stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4087 | _LSE_INSN ("stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4088 | _LSE_INSN ("stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4089 | _LSE_INSN ("stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4090 | _LSE_INSN ("stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4091 | _LSE_INSN ("stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
4092 | _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4093 | _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), | |
4094 | _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), | |
a06ea964 | 4095 | /* Move wide (immediate). */ |
5ce912d8 RS |
4096 | CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), |
4097 | CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
4098 | CORE_INSN ("movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), | |
4099 | CORE_INSN ("mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), | |
4100 | CORE_INSN ("movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, OP2 (Rd, HALF), QL_DST_R, F_SF), | |
a06ea964 | 4101 | /* PC-rel. addressing. */ |
9d30b0bd RS |
4102 | CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0), |
4103 | CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0), | |
b83b4b13 SD |
4104 | /* TME Instructions. */ |
4105 | _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), | |
4106 | _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), | |
4107 | _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), | |
4108 | _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0), | |
3dd032c5 PW |
4109 | /* SME instructions (aliases for MSR <sysreg> operations. */ |
4110 | SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), {}, F_SYS_WRITE, 0), | |
4111 | SME_INSN ("smstop", 0xd503467f, 0xffffffff, sme_stop, 0, OP0 (), {}, F_SYS_WRITE, 0), | |
4112 | SME_INSN ("smstart", 0xd503417f, 0xfffff1ff, sme_start, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), | |
4113 | SME_INSN ("smstop", 0xd503407f, 0xfffff1ff, sme_stop, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), | |
a06ea964 | 4114 | /* System. */ |
f9830ec1 | 4115 | CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), |
9d30b0bd RS |
4116 | CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), |
4117 | CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
be2e7d95 | 4118 | CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
8a6e1d1d | 4119 | CORE_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, 0, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)), |
9d30b0bd RS |
4120 | CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
4121 | CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4122 | CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4123 | CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4124 | CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
8a6e1d1d SD |
4125 | CORE_INSN ("dgh", 0xd50320df, 0xffffffff, ic_system, 0, OP0 (), {}, 0), |
4126 | CORE_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4127 | CORE_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4128 | CORE_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4129 | CORE_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4130 | CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4131 | CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4132 | CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), | |
c2e5c986 | 4133 | CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), |
bb5cb85b | 4134 | CORE_INSN ("clearbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
9d30b0bd | 4135 | CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), |
cde3679e | 4136 | CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), |
a4822788 VDN |
4137 | V8_7A_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS), |
4138 | V8R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), | |
cde3679e NC |
4139 | CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
4140 | CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
9d30b0bd RS |
4141 | CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0), |
4142 | CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), | |
68dfbb92 | 4143 | SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0), |
a6a51754 | 4144 | CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), |
9d30b0bd RS |
4145 | CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), |
4146 | CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), | |
4147 | CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
4148 | CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), | |
a4822788 VDN |
4149 | V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), |
4150 | V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), | |
2ac435d4 SD |
4151 | PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), |
4152 | PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
4153 | PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), | |
7568c93b TC |
4154 | /* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr |
4155 | below it. Usually we can resolve this by setting an alias condition on the flags, however that | |
4156 | depends on the disassembly masks to be able to quickly find the alias. The problem is the | |
4157 | cfinv instruction has no arguments, so all bits are set in the mask. Which means it will | |
4158 | potentially alias with too many instructions and so the tree can't be constructed. As a work | |
4159 | around we just place cfinv before msr. This means the order between these two shouldn't be | |
4160 | changed. */ | |
e64441b1 | 4161 | FLAGM_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0), |
f9830ec1 | 4162 | CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE), |
a6a51754 | 4163 | CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0), |
f9830ec1 | 4164 | CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ), |
8a6e1d1d SD |
4165 | CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |
4166 | CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4167 | CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4168 | CORE_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4169 | CORE_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4170 | CORE_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4171 | CORE_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
4172 | CORE_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), | |
a06ea964 | 4173 | /* Test & branch (immediate). */ |
9d30b0bd RS |
4174 | CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), |
4175 | CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), | |
a06ea964 | 4176 | /* The old UAL conditional branch mnemonics (to aid portability). */ |
9d30b0bd RS |
4177 | CORE_INSN ("beq", 0x54000000, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), |
4178 | CORE_INSN ("bne", 0x54000001, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4179 | CORE_INSN ("bcs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4180 | CORE_INSN ("bhs", 0x54000002, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4181 | CORE_INSN ("bcc", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4182 | CORE_INSN ("blo", 0x54000003, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4183 | CORE_INSN ("bmi", 0x54000004, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4184 | CORE_INSN ("bpl", 0x54000005, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4185 | CORE_INSN ("bvs", 0x54000006, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4186 | CORE_INSN ("bvc", 0x54000007, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4187 | CORE_INSN ("bhi", 0x54000008, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4188 | CORE_INSN ("bls", 0x54000009, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4189 | CORE_INSN ("bge", 0x5400000a, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4190 | CORE_INSN ("blt", 0x5400000b, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4191 | CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
4192 | CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), | |
c0890d26 | 4193 | /* SVE instructions. */ |
582e12bf | 4194 | _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0), |
01c1ee4a | 4195 | _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
c0890d26 | 4196 | _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0), |
582e12bf | 4197 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
c0890d26 RS |
4198 | _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0), |
4199 | _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), | |
503fae12 | 4200 | _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_MISC, 0), |
582e12bf | 4201 | _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), |
c0890d26 RS |
4202 | _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0), |
4203 | _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0), | |
eae424ae | 4204 | _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
c0890d26 | 4205 | _SVE_INSN ("mov", 0x0520c000, 0xff20c000, sve_size_bhsd, OP_MOV_Z_P_Z, OP3 (SVE_Zd, SVE_Pg4_10, SVE_Zn), OP_SVE_VMV_BHSD, F_ALIAS | F_MISC, 0), |
eae424ae | 4206 | _SVE_INSNC ("mov", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4207 | _SVE_INSN ("mov", 0x25004000, 0xfff0c210, sve_misc, OP_MOVZ_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), |
4208 | _SVE_INSN ("mov", 0x25004210, 0xfff0c210, sve_misc, OP_MOVM_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BMB, F_ALIAS | F_MISC, 0), | |
eae424ae | 4209 | _SVE_INSNC ("mov", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4210 | _SVE_INSN ("movs", 0x25c04000, 0xfff0c210, sve_misc, OP_MOVS_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), |
4211 | _SVE_INSN ("movs", 0x25404000, 0xfff0c210, sve_misc, OP_MOVZS_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
4212 | _SVE_INSN ("not", 0x25004200, 0xfff0c210, sve_misc, OP_NOT_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
4213 | _SVE_INSN ("nots", 0x25404200, 0xfff0c210, sve_misc, OP_NOTS_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0), | |
eae424ae | 4214 | _SVE_INSNC ("abs", 0x0416a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 | 4215 | _SVE_INSN ("add", 0x04200000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
eae424ae TC |
4216 | _SVE_INSNC ("add", 0x2520c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
4217 | _SVE_INSNC ("add", 0x04000000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4218 | _SVE_INSN ("addpl", 0x04605000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), |
4219 | _SVE_INSN ("addvl", 0x04205000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), | |
4220 | _SVE_INSN ("adr", 0x0420a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_SXTW), OP_SVE_DD, 0, 0), | |
4221 | _SVE_INSN ("adr", 0x0460a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_UXTW), OP_SVE_DD, 0, 0), | |
4222 | _SVE_INSN ("adr", 0x04a0a000, 0xffa0f000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_LSL), OP_SVE_VV_SD, 0, 0), | |
4223 | _SVE_INSN ("and", 0x04203000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
eae424ae TC |
4224 | _SVE_INSNC ("and", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
4225 | _SVE_INSNC ("and", 0x041a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4226 | _SVE_INSN ("and", 0x25004000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
4227 | _SVE_INSN ("ands", 0x25404000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
4228 | _SVE_INSN ("andv", 0x041a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
4229 | _SVE_INSN ("asr", 0x04208000, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
4230 | _SVE_INSN ("asr", 0x04209000, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
eae424ae TC |
4231 | _SVE_INSNC ("asr", 0x04108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
4232 | _SVE_INSNC ("asr", 0x04188000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
4233 | _SVE_INSNC ("asr", 0x04008000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4234 | _SVE_INSNC ("asrd", 0x04048000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4235 | _SVE_INSNC ("asrr", 0x04148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4236 | _SVE_INSN ("bic", 0x04e03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), |
eae424ae | 4237 | _SVE_INSNC ("bic", 0x041b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
c0890d26 RS |
4238 | _SVE_INSN ("bic", 0x25004010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
4239 | _SVE_INSN ("bics", 0x25404010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
4240 | _SVE_INSN ("brka", 0x25104000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
4241 | _SVE_INSN ("brkas", 0x25504000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
4242 | _SVE_INSN ("brkb", 0x25904000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0), | |
4243 | _SVE_INSN ("brkbs", 0x25d04000, 0xffffc210, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, 0, 0), | |
4244 | _SVE_INSN ("brkn", 0x25184000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
4245 | _SVE_INSN ("brkns", 0x25584000, 0xffffc210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pd), OP_SVE_BZBB, 0, 3), | |
4246 | _SVE_INSN ("brkpa", 0x2500c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
4247 | _SVE_INSN ("brkpas", 0x2540c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
4248 | _SVE_INSN ("brkpb", 0x2500c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
4249 | _SVE_INSN ("brkpbs", 0x2540c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
eae424ae | 4250 | _SVE_INSNC ("clasta", 0x05288000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
c0890d26 RS |
4251 | _SVE_INSN ("clasta", 0x052a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
4252 | _SVE_INSN ("clasta", 0x0530a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
eae424ae | 4253 | _SVE_INSNC ("clastb", 0x05298000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
c0890d26 RS |
4254 | _SVE_INSN ("clastb", 0x052b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2), |
4255 | _SVE_INSN ("clastb", 0x0531a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2), | |
eae424ae TC |
4256 | _SVE_INSNC ("cls", 0x0418a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
4257 | _SVE_INSNC ("clz", 0x0419a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4258 | _SVE_INSN ("cmpeq", 0x24002000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), |
4259 | _SVE_INSN ("cmpeq", 0x2400a000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
4260 | _SVE_INSN ("cmpeq", 0x25008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
4261 | _SVE_INSN ("cmpge", 0x24004000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4262 | _SVE_INSN ("cmpge", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
4263 | _SVE_INSN ("cmpge", 0x25000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
4264 | _SVE_INSN ("cmpgt", 0x24004010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4265 | _SVE_INSN ("cmpgt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
4266 | _SVE_INSN ("cmpgt", 0x25000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
4267 | _SVE_INSN ("cmphi", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
4268 | _SVE_INSN ("cmphi", 0x2400c010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4269 | _SVE_INSN ("cmphi", 0x24200010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
4270 | _SVE_INSN ("cmphs", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, F_HAS_ALIAS, 0), | |
4271 | _SVE_INSN ("cmphs", 0x2400c000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4272 | _SVE_INSN ("cmphs", 0x24200000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
4273 | _SVE_INSN ("cmple", 0x24006010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4274 | _SVE_INSN ("cmple", 0x25002010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
4275 | _SVE_INSN ("cmplo", 0x2400e000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4276 | _SVE_INSN ("cmplo", 0x24202000, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
4277 | _SVE_INSN ("cmpls", 0x2400e010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4278 | _SVE_INSN ("cmpls", 0x24202010, 0xff202010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_UIMM7), OP_SVE_VZVU_BHSD, 0, 0), | |
4279 | _SVE_INSN ("cmplt", 0x24006000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4280 | _SVE_INSN ("cmplt", 0x25002000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
4281 | _SVE_INSN ("cmpne", 0x24002010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0), | |
4282 | _SVE_INSN ("cmpne", 0x2400a010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0), | |
4283 | _SVE_INSN ("cmpne", 0x25008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0), | |
eae424ae TC |
4284 | _SVE_INSNC ("cnot", 0x041ba000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
4285 | _SVE_INSNC ("cnt", 0x041aa000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4286 | _SVE_INSN ("cntb", 0x0420e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4287 | _SVE_INSN ("cntd", 0x04e0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4288 | _SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4289 | _SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0), | |
4290 | _SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4291 | _SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0), | |
eae424ae TC |
4292 | _SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
4293 | _SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
4294 | _SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4295 | _SVE_INSN ("ctermeq", 0x25a02000, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), |
4296 | _SVE_INSN ("ctermne", 0x25a02010, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0), | |
4297 | _SVE_INSN ("decb", 0x0430e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
eae424ae | 4298 | _SVE_INSNC ("decd", 0x04f0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 | 4299 | _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
eae424ae | 4300 | _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 | 4301 | _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
2a3ed404 | 4302 | _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 | 4303 | _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
eae424ae | 4304 | _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4305 | _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4306 | _SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0), | |
582e12bf | 4307 | _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0), |
c0890d26 RS |
4308 | _SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), |
4309 | _SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0), | |
4310 | _SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
eae424ae TC |
4311 | _SVE_INSNC ("eor", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
4312 | _SVE_INSNC ("eor", 0x04190000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4313 | _SVE_INSN ("eor", 0x25004200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
4314 | _SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
4315 | _SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
eae424ae TC |
4316 | _SVE_INSNC ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), |
4317 | _SVE_INSNC ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4318 | _SVE_INSNC ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf RS |
4319 | _SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), |
4320 | _SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
4321 | _SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
eae424ae TC |
4322 | _SVE_INSNC ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4323 | _SVE_INSNC ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
582e12bf RS |
4324 | _SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2), |
4325 | _SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
eae424ae TC |
4326 | _SVE_INSNC ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 2), |
4327 | _SVE_INSNC ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4328 | _SVE_INSNC ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0), | |
4329 | _SVE_INSNC ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf RS |
4330 | _SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), |
4331 | _SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
4332 | _SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
4333 | _SVE_INSN ("fcmge", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
4334 | _SVE_INSN ("fcmgt", 0x65102010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
4335 | _SVE_INSN ("fcmgt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0), | |
4336 | _SVE_INSN ("fcmle", 0x65112010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
4337 | _SVE_INSN ("fcmlt", 0x65112000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
4338 | _SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0), | |
4339 | _SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
4340 | _SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0), | |
eae424ae TC |
4341 | _SVE_INSNC ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0), |
4342 | _SVE_INSNC ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4343 | _SVE_INSNC ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4344 | _SVE_INSNC ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4345 | _SVE_INSNC ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4346 | _SVE_INSNC ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4347 | _SVE_INSNC ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
83adff69 RS |
4348 | _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), |
4349 | _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4350 | _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4351 | _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4352 | _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4353 | _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4354 | _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4355 | _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4356 | _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4357 | _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4358 | _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4359 | _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4360 | _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4361 | _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
eae424ae TC |
4362 | _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4363 | _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
582e12bf RS |
4364 | _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0), |
4365 | _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), | |
eae424ae TC |
4366 | _SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4367 | _SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4368 | _SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4369 | _SVE_INSNC ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4370 | _SVE_INSNC ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
582e12bf RS |
4371 | _SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
4372 | _SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
eae424ae TC |
4373 | _SVE_INSNC ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4374 | _SVE_INSNC ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4375 | _SVE_INSNC ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4376 | _SVE_INSNC ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
582e12bf RS |
4377 | _SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), |
4378 | _SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0), | |
eae424ae TC |
4379 | _SVE_INSNC ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4380 | _SVE_INSNC ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
4381 | _SVE_INSNC ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
4382 | _SVE_INSNC ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
4383 | _SVE_INSNC ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4384 | _SVE_INSNC ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), | |
4385 | _SVE_INSNC ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
4386 | _SVE_INSNC ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), | |
4387 | _SVE_INSNC ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf | 4388 | _SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
eae424ae TC |
4389 | _SVE_INSNC ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4390 | _SVE_INSNC ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
582e12bf RS |
4391 | _SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), |
4392 | _SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0), | |
4393 | _SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0), | |
eae424ae TC |
4394 | _SVE_INSNC ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4395 | _SVE_INSNC ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4396 | _SVE_INSNC ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4397 | _SVE_INSNC ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4398 | _SVE_INSNC ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4399 | _SVE_INSNC ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf RS |
4400 | _SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
4401 | _SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
eae424ae TC |
4402 | _SVE_INSNC ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4403 | _SVE_INSNC ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4404 | _SVE_INSNC ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4405 | _SVE_INSNC ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4406 | _SVE_INSNC ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4407 | _SVE_INSNC ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4408 | _SVE_INSNC ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
4409 | _SVE_INSNC ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf RS |
4410 | _SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0), |
4411 | _SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
eae424ae TC |
4412 | _SVE_INSNC ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4413 | _SVE_INSNC ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
582e12bf | 4414 | _SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
eae424ae TC |
4415 | _SVE_INSNC ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), |
4416 | _SVE_INSNC ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4417 | _SVE_INSNC ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4418 | _SVE_INSNC ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2), | |
4419 | _SVE_INSNC ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, C_SCAN_MOVPRFX, 1), | |
582e12bf RS |
4420 | _SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
4421 | _SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
c0890d26 | 4422 | _SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
eae424ae | 4423 | _SVE_INSNC ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 | 4424 | _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
eae424ae | 4425 | _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 | 4426 | _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
2a3ed404 | 4427 | _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 | 4428 | _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
eae424ae | 4429 | _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4430 | _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4431 | _SVE_INSN ("index", 0x04204c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, Rm), OP_SVE_VRR_BHSD, 0, 0), | |
4432 | _SVE_INSN ("index", 0x04204000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, SVE_SIMM5B), OP_SVE_VUU_BHSD, 0, 0), | |
4433 | _SVE_INSN ("index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0), | |
4434 | _SVE_INSN ("index", 0x04204800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, Rm), OP_SVE_VUR_BHSD, 0, 0), | |
eae424ae TC |
4435 | _SVE_INSNC ("insr", 0x05243800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Rm), OP_SVE_VR_BHSD, 0, C_SCAN_MOVPRFX, 0), |
4436 | _SVE_INSNC ("insr", 0x05343800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Vm), OP_SVE_VV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4437 | _SVE_INSN ("lasta", 0x0520a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), |
4438 | _SVE_INSN ("lasta", 0x05228000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
4439 | _SVE_INSN ("lastb", 0x0521a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0), | |
4440 | _SVE_INSN ("lastb", 0x05238000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
4441 | _SVE_INSN ("ld1b", 0x84004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
4442 | _SVE_INSN ("ld1b", 0xa4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
4443 | _SVE_INSN ("ld1b", 0xa4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
4444 | _SVE_INSN ("ld1b", 0xa4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
4445 | _SVE_INSN ("ld1b", 0xa4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
4446 | _SVE_INSN ("ld1b", 0xc4004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4447 | _SVE_INSN ("ld1b", 0xc440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4448 | _SVE_INSN ("ld1b", 0x8420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
4449 | _SVE_INSN ("ld1b", 0xa400a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
4450 | _SVE_INSN ("ld1b", 0xa420a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4451 | _SVE_INSN ("ld1b", 0xa440a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4452 | _SVE_INSN ("ld1b", 0xa460a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4453 | _SVE_INSN ("ld1b", 0xc420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
4454 | _SVE_INSN ("ld1d", 0xa5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
4455 | _SVE_INSN ("ld1d", 0xc5804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4456 | _SVE_INSN ("ld1d", 0xc5a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
4457 | _SVE_INSN ("ld1d", 0xc5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4458 | _SVE_INSN ("ld1d", 0xc5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
4459 | _SVE_INSN ("ld1d", 0xa5e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4460 | _SVE_INSN ("ld1d", 0xc5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
4461 | _SVE_INSN ("ld1h", 0x84804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
4462 | _SVE_INSN ("ld1h", 0x84a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
4463 | _SVE_INSN ("ld1h", 0xa4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
4464 | _SVE_INSN ("ld1h", 0xa4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
4465 | _SVE_INSN ("ld1h", 0xa4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
4466 | _SVE_INSN ("ld1h", 0xc4804000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4467 | _SVE_INSN ("ld1h", 0xc4a04000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
4468 | _SVE_INSN ("ld1h", 0xc4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4469 | _SVE_INSN ("ld1h", 0xc4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
4470 | _SVE_INSN ("ld1h", 0x84a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
4471 | _SVE_INSN ("ld1h", 0xa4a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4472 | _SVE_INSN ("ld1h", 0xa4c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4473 | _SVE_INSN ("ld1h", 0xa4e0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4474 | _SVE_INSN ("ld1h", 0xc4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
4475 | _SVE_INSN ("ld1rb", 0x84408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_BZU, F_OD(1), 0), | |
4476 | _SVE_INSN ("ld1rb", 0x8440a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
4477 | _SVE_INSN ("ld1rb", 0x8440c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
4478 | _SVE_INSN ("ld1rb", 0x8440e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), | |
4479 | _SVE_INSN ("ld1rd", 0x85c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x8), OP_SVE_DZU, F_OD(1), 0), | |
4480 | _SVE_INSN ("ld1rh", 0x84c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_HZU, F_OD(1), 0), | |
4481 | _SVE_INSN ("ld1rh", 0x84c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
4482 | _SVE_INSN ("ld1rh", 0x84c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
582e12bf RS |
4483 | _SVE_INSN ("ld1rqb", 0xa4002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_BZU, F_OD(1), 0), |
4484 | _SVE_INSN ("ld1rqb", 0xa4000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
4485 | _SVE_INSN ("ld1rqd", 0xa5802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_DZU, F_OD(1), 0), | |
4486 | _SVE_INSN ("ld1rqd", 0xa5800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
4487 | _SVE_INSN ("ld1rqh", 0xa4802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_HZU, F_OD(1), 0), | |
4488 | _SVE_INSN ("ld1rqh", 0xa4800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
4489 | _SVE_INSN ("ld1rqw", 0xa5002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_SZU, F_OD(1), 0), | |
4490 | _SVE_INSN ("ld1rqw", 0xa5000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
c0890d26 RS |
4491 | _SVE_INSN ("ld1rsb", 0x85c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0), |
4492 | _SVE_INSN ("ld1rsb", 0x85c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0), | |
4493 | _SVE_INSN ("ld1rsb", 0x85c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0), | |
4494 | _SVE_INSN ("ld1rsh", 0x85408000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0), | |
4495 | _SVE_INSN ("ld1rsh", 0x8540a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0), | |
4496 | _SVE_INSN ("ld1rsw", 0x84c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
4497 | _SVE_INSN ("ld1rw", 0x8540c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_SZU, F_OD(1), 0), | |
4498 | _SVE_INSN ("ld1rw", 0x8540e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x4), OP_SVE_DZU, F_OD(1), 0), | |
4499 | _SVE_INSN ("ld1sb", 0x84000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
4500 | _SVE_INSN ("ld1sb", 0xa5804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), | |
4501 | _SVE_INSN ("ld1sb", 0xa5a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), | |
4502 | _SVE_INSN ("ld1sb", 0xa5c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), | |
4503 | _SVE_INSN ("ld1sb", 0xc4000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4504 | _SVE_INSN ("ld1sb", 0xc4408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4505 | _SVE_INSN ("ld1sb", 0x84208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
4506 | _SVE_INSN ("ld1sb", 0xa580a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4507 | _SVE_INSN ("ld1sb", 0xa5a0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4508 | _SVE_INSN ("ld1sb", 0xa5c0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4509 | _SVE_INSN ("ld1sb", 0xc4208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
4510 | _SVE_INSN ("ld1sh", 0x84800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
4511 | _SVE_INSN ("ld1sh", 0x84a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
4512 | _SVE_INSN ("ld1sh", 0xa5004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
4513 | _SVE_INSN ("ld1sh", 0xa5204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SZU, F_OD(1), 0), | |
4514 | _SVE_INSN ("ld1sh", 0xc4800000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4515 | _SVE_INSN ("ld1sh", 0xc4a00000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
4516 | _SVE_INSN ("ld1sh", 0xc4c08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4517 | _SVE_INSN ("ld1sh", 0xc4e08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
4518 | _SVE_INSN ("ld1sh", 0x84a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
4519 | _SVE_INSN ("ld1sh", 0xa500a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4520 | _SVE_INSN ("ld1sh", 0xa520a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4521 | _SVE_INSN ("ld1sh", 0xc4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
4522 | _SVE_INSN ("ld1sw", 0xa4804000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
4523 | _SVE_INSN ("ld1sw", 0xc5000000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4524 | _SVE_INSN ("ld1sw", 0xc5200000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
4525 | _SVE_INSN ("ld1sw", 0xc5408000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4526 | _SVE_INSN ("ld1sw", 0xc5608000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
4527 | _SVE_INSN ("ld1sw", 0xa480a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4528 | _SVE_INSN ("ld1sw", 0xc5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
4529 | _SVE_INSN ("ld1w", 0x85004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), | |
4530 | _SVE_INSN ("ld1w", 0x85204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
4531 | _SVE_INSN ("ld1w", 0xa5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
4532 | _SVE_INSN ("ld1w", 0xa5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DZU, F_OD(1), 0), | |
4533 | _SVE_INSN ("ld1w", 0xc5004000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), | |
4534 | _SVE_INSN ("ld1w", 0xc5204000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
4535 | _SVE_INSN ("ld1w", 0xc540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4536 | _SVE_INSN ("ld1w", 0xc560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
4537 | _SVE_INSN ("ld1w", 0x8520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
4538 | _SVE_INSN ("ld1w", 0xa540a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4539 | _SVE_INSN ("ld1w", 0xa560a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4540 | _SVE_INSN ("ld1w", 0xc520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
4541 | _SVE_INSN ("ld2b", 0xa420c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(2), 0), | |
4542 | _SVE_INSN ("ld2b", 0xa420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, F_OD(2), 0), | |
4543 | _SVE_INSN ("ld2d", 0xa5a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(2), 0), | |
4544 | _SVE_INSN ("ld2d", 0xa5a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, F_OD(2), 0), | |
4545 | _SVE_INSN ("ld2h", 0xa4a0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(2), 0), | |
4546 | _SVE_INSN ("ld2h", 0xa4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, F_OD(2), 0), | |
4547 | _SVE_INSN ("ld2w", 0xa520c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(2), 0), | |
4548 | _SVE_INSN ("ld2w", 0xa520e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, F_OD(2), 0), | |
4549 | _SVE_INSN ("ld3b", 0xa440c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(3), 0), | |
4550 | _SVE_INSN ("ld3b", 0xa440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BZU, F_OD(3), 0), | |
4551 | _SVE_INSN ("ld3d", 0xa5c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(3), 0), | |
4552 | _SVE_INSN ("ld3d", 0xa5c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DZU, F_OD(3), 0), | |
4553 | _SVE_INSN ("ld3h", 0xa4c0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(3), 0), | |
4554 | _SVE_INSN ("ld3h", 0xa4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HZU, F_OD(3), 0), | |
4555 | _SVE_INSN ("ld3w", 0xa540c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(3), 0), | |
4556 | _SVE_INSN ("ld3w", 0xa540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SZU, F_OD(3), 0), | |
4557 | _SVE_INSN ("ld4b", 0xa460c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(4), 0), | |
4558 | _SVE_INSN ("ld4b", 0xa460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, F_OD(4), 0), | |
4559 | _SVE_INSN ("ld4d", 0xa5e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(4), 0), | |
4560 | _SVE_INSN ("ld4d", 0xa5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, F_OD(4), 0), | |
4561 | _SVE_INSN ("ld4h", 0xa4e0c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(4), 0), | |
4562 | _SVE_INSN ("ld4h", 0xa4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, F_OD(4), 0), | |
4563 | _SVE_INSN ("ld4w", 0xa560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(4), 0), | |
4564 | _SVE_INSN ("ld4w", 0xa560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, F_OD(4), 0), | |
c8d59609 | 4565 | |
c0890d26 RS |
4566 | _SVE_INSN ("ldff1b", 0x84006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
4567 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, F_OD(1), 0), | |
c8d59609 | 4568 | _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, F_OD(1), 0), |
c0890d26 | 4569 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
c8d59609 | 4570 | _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
c0890d26 | 4571 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
c8d59609 | 4572 | _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
c0890d26 | 4573 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), |
c8d59609 | 4574 | _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 RS |
4575 | _SVE_INSN ("ldff1b", 0xc4006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4576 | _SVE_INSN ("ldff1b", 0xc440e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4577 | _SVE_INSN ("ldff1b", 0x8420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
4578 | _SVE_INSN ("ldff1b", 0xc420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4579 | |
c0890d26 | 4580 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, F_OD(1), 0), |
c8d59609 | 4581 | _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 RS |
4582 | _SVE_INSN ("ldff1d", 0xc5806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4583 | _SVE_INSN ("ldff1d", 0xc5a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0), | |
4584 | _SVE_INSN ("ldff1d", 0xc5c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4585 | _SVE_INSN ("ldff1d", 0xc5e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0), | |
4586 | _SVE_INSN ("ldff1d", 0xc5a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4587 | |
c0890d26 RS |
4588 | _SVE_INSN ("ldff1h", 0x84806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
4589 | _SVE_INSN ("ldff1h", 0x84a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
4590 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
c8d59609 | 4591 | _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
c0890d26 | 4592 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
c8d59609 | 4593 | _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
c0890d26 | 4594 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), |
c8d59609 | 4595 | _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 RS |
4596 | _SVE_INSN ("ldff1h", 0xc4806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4597 | _SVE_INSN ("ldff1h", 0xc4a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
4598 | _SVE_INSN ("ldff1h", 0xc4c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4599 | _SVE_INSN ("ldff1h", 0xc4e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
4600 | _SVE_INSN ("ldff1h", 0x84a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
4601 | _SVE_INSN ("ldff1h", 0xc4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4602 | |
c0890d26 RS |
4603 | _SVE_INSN ("ldff1sb", 0x84002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
4604 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0), | |
c8d59609 | 4605 | _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 | 4606 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0), |
c8d59609 | 4607 | _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
c0890d26 | 4608 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0), |
c8d59609 | 4609 | _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0), |
c0890d26 RS |
4610 | _SVE_INSN ("ldff1sb", 0xc4002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4611 | _SVE_INSN ("ldff1sb", 0xc440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4612 | _SVE_INSN ("ldff1sb", 0x8420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0), | |
4613 | _SVE_INSN ("ldff1sb", 0xc420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4614 | |
c0890d26 RS |
4615 | _SVE_INSN ("ldff1sh", 0x84802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
4616 | _SVE_INSN ("ldff1sh", 0x84a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0), | |
4617 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0), | |
c8d59609 | 4618 | _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 | 4619 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0), |
c8d59609 | 4620 | _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
c0890d26 RS |
4621 | _SVE_INSN ("ldff1sh", 0xc4802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4622 | _SVE_INSN ("ldff1sh", 0xc4a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0), | |
4623 | _SVE_INSN ("ldff1sh", 0xc4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4624 | _SVE_INSN ("ldff1sh", 0xc4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0), | |
4625 | _SVE_INSN ("ldff1sh", 0x84a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0), | |
4626 | _SVE_INSN ("ldff1sh", 0xc4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4627 | |
c0890d26 | 4628 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
c8d59609 | 4629 | _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 RS |
4630 | _SVE_INSN ("ldff1sw", 0xc5002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4631 | _SVE_INSN ("ldff1sw", 0xc5202000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
4632 | _SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4633 | _SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
4634 | _SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4635 | |
c0890d26 RS |
4636 | _SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), |
4637 | _SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), | |
4638 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
c8d59609 | 4639 | _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0), |
c0890d26 | 4640 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0), |
c8d59609 | 4641 | _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0), |
c0890d26 RS |
4642 | _SVE_INSN ("ldff1w", 0xc5006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0), |
4643 | _SVE_INSN ("ldff1w", 0xc5206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0), | |
4644 | _SVE_INSN ("ldff1w", 0xc540e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), | |
4645 | _SVE_INSN ("ldff1w", 0xc560e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), | |
4646 | _SVE_INSN ("ldff1w", 0x8520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0), | |
4647 | _SVE_INSN ("ldff1w", 0xc520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), | |
c8d59609 | 4648 | |
c0890d26 RS |
4649 | _SVE_INSN ("ldnf1b", 0xa410a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), |
4650 | _SVE_INSN ("ldnf1b", 0xa430a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4651 | _SVE_INSN ("ldnf1b", 0xa450a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4652 | _SVE_INSN ("ldnf1b", 0xa470a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4653 | _SVE_INSN ("ldnf1d", 0xa5f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4654 | _SVE_INSN ("ldnf1h", 0xa4b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4655 | _SVE_INSN ("ldnf1h", 0xa4d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4656 | _SVE_INSN ("ldnf1h", 0xa4f0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4657 | _SVE_INSN ("ldnf1sb", 0xa590a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4658 | _SVE_INSN ("ldnf1sb", 0xa5b0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4659 | _SVE_INSN ("ldnf1sb", 0xa5d0a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4660 | _SVE_INSN ("ldnf1sh", 0xa510a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4661 | _SVE_INSN ("ldnf1sh", 0xa530a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4662 | _SVE_INSN ("ldnf1sw", 0xa490a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4663 | _SVE_INSN ("ldnf1w", 0xa550a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4664 | _SVE_INSN ("ldnf1w", 0xa570a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4665 | _SVE_INSN ("ldnt1b", 0xa400c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), | |
4666 | _SVE_INSN ("ldnt1b", 0xa400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0), | |
4667 | _SVE_INSN ("ldnt1d", 0xa580c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
4668 | _SVE_INSN ("ldnt1d", 0xa580e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DZU, F_OD(1), 0), | |
4669 | _SVE_INSN ("ldnt1h", 0xa480c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
4670 | _SVE_INSN ("ldnt1h", 0xa480e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0), | |
4671 | _SVE_INSN ("ldnt1w", 0xa500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
4672 | _SVE_INSN ("ldnt1w", 0xa500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0), | |
4673 | _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
503fae12 | 4674 | _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0), |
c0890d26 RS |
4675 | _SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), |
4676 | _SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), | |
4677 | _SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
eae424ae TC |
4678 | _SVE_INSNC ("lsl", 0x04138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
4679 | _SVE_INSNC ("lsl", 0x041b8000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
4680 | _SVE_INSNC ("lsl", 0x04038000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4681 | _SVE_INSNC ("lslr", 0x04178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4682 | _SVE_INSN ("lsr", 0x04208400, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0), |
4683 | _SVE_INSN ("lsr", 0x04209400, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
eae424ae TC |
4684 | _SVE_INSNC ("lsr", 0x04118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
4685 | _SVE_INSNC ("lsr", 0x04198000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2), | |
4686 | _SVE_INSNC ("lsr", 0x04018000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4687 | _SVE_INSNC ("lsrr", 0x04158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4688 | _SVE_INSNC ("mad", 0x0400c000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
4689 | _SVE_INSNC ("mla", 0x04004000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
4690 | _SVE_INSNC ("mls", 0x04006000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
4691 | _SVE_INSNC ("movprfx", 0x0420bc00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), {}, F_SCAN, C_SCAN_MOVPRFX, 0), | |
4692 | _SVE_INSNC ("movprfx", 0x04102000, 0xff3ee000, sve_movprfx, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VPV_BHSD, F_SCAN, C_SCAN_MOVPRFX, 0), | |
4693 | _SVE_INSNC ("msb", 0x0400e000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
4694 | _SVE_INSNC ("mul", 0x2530c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
4695 | _SVE_INSNC ("mul", 0x04100000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4696 | _SVE_INSN ("nand", 0x25804210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
4697 | _SVE_INSN ("nands", 0x25c04210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
eae424ae | 4698 | _SVE_INSNC ("neg", 0x0417a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4699 | _SVE_INSN ("nor", 0x25804200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
4700 | _SVE_INSN ("nors", 0x25c04200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
eae424ae | 4701 | _SVE_INSNC ("not", 0x041ea000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4702 | _SVE_INSN ("orn", 0x25804010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), |
4703 | _SVE_INSN ("orns", 0x25c04010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0), | |
4704 | _SVE_INSN ("orr", 0x04603000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, F_HAS_ALIAS, 0), | |
eae424ae TC |
4705 | _SVE_INSNC ("orr", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1), |
4706 | _SVE_INSNC ("orr", 0x04180000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4707 | _SVE_INSN ("orr", 0x25804000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), |
4708 | _SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0), | |
4709 | _SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), | |
4710 | _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), | |
503fae12 | 4711 | _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_PNd), OP_SVE_B, 0, 0), |
c0890d26 RS |
4712 | _SVE_INSN ("pfirst", 0x2558c000, 0xfffffe10, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_BUB, 0, 2), |
4713 | _SVE_INSN ("pnext", 0x2519c400, 0xff3ffe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_VUV_BHSD, 0, 2), | |
4714 | _SVE_INSN ("prfb", 0x8400c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX), {}, 0, 0), | |
4715 | _SVE_INSN ("prfb", 0x84200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUS, 0, 0), | |
4716 | _SVE_INSN ("prfb", 0xc4200000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_UUD, 0, 0), | |
4717 | _SVE_INSN ("prfb", 0xc4608000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_UUD, 0, 0), | |
4718 | _SVE_INSN ("prfb", 0x8400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUS, 0, 0), | |
4719 | _SVE_INSN ("prfb", 0x85c00000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
4720 | _SVE_INSN ("prfb", 0xc400e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_UUD, 0, 0), | |
4721 | _SVE_INSN ("prfd", 0x84206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUS, 0, 0), | |
4722 | _SVE_INSN ("prfd", 0x8580c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL3), {}, 0, 0), | |
4723 | _SVE_INSN ("prfd", 0xc4206000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_UUD, 0, 0), | |
4724 | _SVE_INSN ("prfd", 0xc460e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_UUD, 0, 0), | |
4725 | _SVE_INSN ("prfd", 0x8580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUS, 0, 0), | |
4726 | _SVE_INSN ("prfd", 0x85c06000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
4727 | _SVE_INSN ("prfd", 0xc580e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_UUD, 0, 0), | |
4728 | _SVE_INSN ("prfh", 0x84202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUS, 0, 0), | |
4729 | _SVE_INSN ("prfh", 0x8480c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL1), {}, 0, 0), | |
4730 | _SVE_INSN ("prfh", 0xc4202000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_UUD, 0, 0), | |
4731 | _SVE_INSN ("prfh", 0xc460a000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_UUD, 0, 0), | |
4732 | _SVE_INSN ("prfh", 0x8480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUS, 0, 0), | |
4733 | _SVE_INSN ("prfh", 0x85c02000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
4734 | _SVE_INSN ("prfh", 0xc480e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_UUD, 0, 0), | |
4735 | _SVE_INSN ("prfw", 0x84204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUS, 0, 0), | |
4736 | _SVE_INSN ("prfw", 0x8500c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX_LSL2), {}, 0, 0), | |
4737 | _SVE_INSN ("prfw", 0xc4204000, 0xffa0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_UUD, 0, 0), | |
4738 | _SVE_INSN ("prfw", 0xc460c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_UUD, 0, 0), | |
4739 | _SVE_INSN ("prfw", 0x8500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUS, 0, 0), | |
4740 | _SVE_INSN ("prfw", 0x85c04000, 0xffc0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RI_S6xVL), {}, 0, 0), | |
4741 | _SVE_INSN ("prfw", 0xc500e000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_UUD, 0, 0), | |
4742 | _SVE_INSN ("ptest", 0x2550c000, 0xffffc21f, sve_misc, 0, OP2 (SVE_Pg4_10, SVE_Pn), OP_SVE_UB, 0, 0), | |
4743 | _SVE_INSN ("ptrue", 0x2518e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4744 | _SVE_INSN ("ptrues", 0x2519e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4745 | _SVE_INSN ("punpkhi", 0x05314000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
4746 | _SVE_INSN ("punpklo", 0x05304000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0), | |
eae424ae | 4747 | _SVE_INSNC ("rbit", 0x05278000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4748 | _SVE_INSN ("rdffr", 0x2519f000, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0), |
4749 | _SVE_INSN ("rdffr", 0x2518f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
4750 | _SVE_INSN ("rdffrs", 0x2558f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0), | |
4751 | _SVE_INSN ("rdvl", 0x04bf5000, 0xfffff800, sve_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), | |
4752 | _SVE_INSN ("rev", 0x05344000, 0xff3ffe10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_VV_BHSD, 0, 0), | |
4753 | _SVE_INSN ("rev", 0x05383800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHSD, 0, 0), | |
eae424ae TC |
4754 | _SVE_INSNC ("revb", 0x05248000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4755 | _SVE_INSNC ("revh", 0x05a58000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
4756 | _SVE_INSNC ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
4757 | _SVE_INSNC ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4758 | _SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0), |
83adff69 RS |
4759 | _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), |
4760 | _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4761 | _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4762 | _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4763 | _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4764 | _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4765 | _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
eae424ae TC |
4766 | _SVE_INSNC ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), |
4767 | _SVE_INSNC ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
4768 | _SVE_INSNC ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
4769 | _SVE_INSNC ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
4770 | _SVE_INSNC ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4771 | _SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0), |
4772 | _SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0), | |
4773 | _SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0), | |
eae424ae TC |
4774 | _SVE_INSNC ("smax", 0x2528c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
4775 | _SVE_INSNC ("smax", 0x04080000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4776 | _SVE_INSN ("smaxv", 0x04082000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
eae424ae TC |
4777 | _SVE_INSNC ("smin", 0x252ac000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
4778 | _SVE_INSNC ("smin", 0x040a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4779 | _SVE_INSN ("sminv", 0x040a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
eae424ae TC |
4780 | _SVE_INSNC ("smulh", 0x04120000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
4781 | _SVE_INSNC ("splice", 0x052c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4782 | _SVE_INSN ("sqadd", 0x04201000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
eae424ae | 4783 | _SVE_INSNC ("sqadd", 0x2524c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
c0890d26 RS |
4784 | _SVE_INSN ("sqdecb", 0x0430f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4785 | _SVE_INSN ("sqdecb", 0x0420f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
eae424ae | 4786 | _SVE_INSNC ("sqdecd", 0x04e0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4787 | _SVE_INSN ("sqdecd", 0x04f0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4788 | _SVE_INSN ("sqdecd", 0x04e0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
eae424ae | 4789 | _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4790 | _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4791 | _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
2a3ed404 | 4792 | _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4793 | _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
4794 | _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
eae424ae | 4795 | _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4796 | _SVE_INSN ("sqdecw", 0x04b0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4797 | _SVE_INSN ("sqdecw", 0x04a0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
4798 | _SVE_INSN ("sqincb", 0x0430f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4799 | _SVE_INSN ("sqincb", 0x0420f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
eae424ae | 4800 | _SVE_INSNC ("sqincd", 0x04e0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4801 | _SVE_INSN ("sqincd", 0x04f0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4802 | _SVE_INSN ("sqincd", 0x04e0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
eae424ae | 4803 | _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4804 | _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4805 | _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
2a3ed404 | 4806 | _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4807 | _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), |
4808 | _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), | |
eae424ae | 4809 | _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4810 | _SVE_INSN ("sqincw", 0x04b0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4811 | _SVE_INSN ("sqincw", 0x04a0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), | |
4812 | _SVE_INSN ("sqsub", 0x04201800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
eae424ae | 4813 | _SVE_INSNC ("sqsub", 0x2526c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
c0890d26 RS |
4814 | _SVE_INSN ("st1b", 0xe4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), |
4815 | _SVE_INSN ("st1b", 0xe4008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
4816 | _SVE_INSN ("st1b", 0xe400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
4817 | _SVE_INSN ("st1b", 0xe4204000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HUU, F_OD(1), 0), | |
4818 | _SVE_INSN ("st1b", 0xe4404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SUU, F_OD(1), 0), | |
4819 | _SVE_INSN ("st1b", 0xe4408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
4820 | _SVE_INSN ("st1b", 0xe4604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DUU, F_OD(1), 0), | |
4821 | _SVE_INSN ("st1b", 0xe400e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
4822 | _SVE_INSN ("st1b", 0xe420e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
4823 | _SVE_INSN ("st1b", 0xe440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DUD, F_OD(1), 0), | |
4824 | _SVE_INSN ("st1b", 0xe440e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
4825 | _SVE_INSN ("st1b", 0xe460a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SUS, F_OD(1), 0), | |
4826 | _SVE_INSN ("st1b", 0xe460e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
4827 | _SVE_INSN ("st1d", 0xe5808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
4828 | _SVE_INSN ("st1d", 0xe580a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
4829 | _SVE_INSN ("st1d", 0xe5a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_14), OP_SVE_DUD, F_OD(1), 0), | |
4830 | _SVE_INSN ("st1d", 0xe5a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DUD, F_OD(1), 0), | |
4831 | _SVE_INSN ("st1d", 0xe5e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
4832 | _SVE_INSN ("st1d", 0xe5c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DUD, F_OD(1), 0), | |
4833 | _SVE_INSN ("st1d", 0xe5e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
4834 | _SVE_INSN ("st1h", 0xe4808000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
4835 | _SVE_INSN ("st1h", 0xe480a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
4836 | _SVE_INSN ("st1h", 0xe4a04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
4837 | _SVE_INSN ("st1h", 0xe4a08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_DUD, F_OD(1), 0), | |
4838 | _SVE_INSN ("st1h", 0xe4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DUD, F_OD(1), 0), | |
4839 | _SVE_INSN ("st1h", 0xe4c04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_SUU, F_OD(1), 0), | |
4840 | _SVE_INSN ("st1h", 0xe4c08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
4841 | _SVE_INSN ("st1h", 0xe4e04000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_DUU, F_OD(1), 0), | |
4842 | _SVE_INSN ("st1h", 0xe4e08000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_14), OP_SVE_SUS, F_OD(1), 0), | |
4843 | _SVE_INSN ("st1h", 0xe4a0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
4844 | _SVE_INSN ("st1h", 0xe4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DUD, F_OD(1), 0), | |
4845 | _SVE_INSN ("st1h", 0xe4c0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
4846 | _SVE_INSN ("st1h", 0xe4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SUS, F_OD(1), 0), | |
4847 | _SVE_INSN ("st1h", 0xe4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
4848 | _SVE_INSN ("st1w", 0xe5008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0), | |
4849 | _SVE_INSN ("st1w", 0xe500a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0), | |
4850 | _SVE_INSN ("st1w", 0xe5208000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_DUD, F_OD(1), 0), | |
4851 | _SVE_INSN ("st1w", 0xe520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DUD, F_OD(1), 0), | |
4852 | _SVE_INSN ("st1w", 0xe5404000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
4853 | _SVE_INSN ("st1w", 0xe5408000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_SUS, F_OD(1), 0), | |
4854 | _SVE_INSN ("st1w", 0xe5604000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_DUU, F_OD(1), 0), | |
4855 | _SVE_INSN ("st1w", 0xe5608000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_14), OP_SVE_SUS, F_OD(1), 0), | |
4856 | _SVE_INSN ("st1w", 0xe540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DUD, F_OD(1), 0), | |
4857 | _SVE_INSN ("st1w", 0xe540e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
4858 | _SVE_INSN ("st1w", 0xe560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SUS, F_OD(1), 0), | |
4859 | _SVE_INSN ("st1w", 0xe560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
4860 | _SVE_INSN ("st2b", 0xe4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(2), 0), | |
4861 | _SVE_INSN ("st2b", 0xe430e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, F_OD(2), 0), | |
4862 | _SVE_INSN ("st2d", 0xe5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(2), 0), | |
4863 | _SVE_INSN ("st2d", 0xe5b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, F_OD(2), 0), | |
4864 | _SVE_INSN ("st2h", 0xe4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(2), 0), | |
4865 | _SVE_INSN ("st2h", 0xe4b0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, F_OD(2), 0), | |
4866 | _SVE_INSN ("st2w", 0xe5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(2), 0), | |
4867 | _SVE_INSN ("st2w", 0xe530e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, F_OD(2), 0), | |
4868 | _SVE_INSN ("st3b", 0xe4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(3), 0), | |
4869 | _SVE_INSN ("st3b", 0xe450e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_BUU, F_OD(3), 0), | |
4870 | _SVE_INSN ("st3d", 0xe5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(3), 0), | |
4871 | _SVE_INSN ("st3d", 0xe5d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_DUU, F_OD(3), 0), | |
4872 | _SVE_INSN ("st3h", 0xe4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(3), 0), | |
4873 | _SVE_INSN ("st3h", 0xe4d0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_HUU, F_OD(3), 0), | |
4874 | _SVE_INSN ("st3w", 0xe5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(3), 0), | |
4875 | _SVE_INSN ("st3w", 0xe550e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_SUU, F_OD(3), 0), | |
4876 | _SVE_INSN ("st4b", 0xe4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(4), 0), | |
4877 | _SVE_INSN ("st4b", 0xe470e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, F_OD(4), 0), | |
4878 | _SVE_INSN ("st4d", 0xe5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(4), 0), | |
4879 | _SVE_INSN ("st4d", 0xe5f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, F_OD(4), 0), | |
4880 | _SVE_INSN ("st4h", 0xe4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(4), 0), | |
4881 | _SVE_INSN ("st4h", 0xe4f0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, F_OD(4), 0), | |
4882 | _SVE_INSN ("st4w", 0xe5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(4), 0), | |
4883 | _SVE_INSN ("st4w", 0xe570e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, F_OD(4), 0), | |
4884 | _SVE_INSN ("stnt1b", 0xe4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0), | |
4885 | _SVE_INSN ("stnt1b", 0xe410e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BUU, F_OD(1), 0), | |
4886 | _SVE_INSN ("stnt1d", 0xe5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DUU, F_OD(1), 0), | |
4887 | _SVE_INSN ("stnt1d", 0xe590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_DUU, F_OD(1), 0), | |
4888 | _SVE_INSN ("stnt1h", 0xe4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HUU, F_OD(1), 0), | |
4889 | _SVE_INSN ("stnt1h", 0xe490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0), | |
4890 | _SVE_INSN ("stnt1w", 0xe5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0), | |
4891 | _SVE_INSN ("stnt1w", 0xe510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0), | |
4892 | _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0), | |
503fae12 | 4893 | _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0), |
c0890d26 RS |
4894 | _SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0), |
4895 | _SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
eae424ae TC |
4896 | _SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
4897 | _SVE_INSNC ("sub", 0x04010000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
4898 | _SVE_INSNC ("subr", 0x2523c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
4899 | _SVE_INSNC ("subr", 0x04030000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 RS |
4900 | _SVE_INSN ("sunpkhi", 0x05313800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
4901 | _SVE_INSN ("sunpklo", 0x05303800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
eae424ae TC |
4902 | _SVE_INSNC ("sxtb", 0x0410a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4903 | _SVE_INSNC ("sxth", 0x0492a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
4904 | _SVE_INSNC ("sxtw", 0x04d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4905 | _SVE_INSN ("tbl", 0x05203000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0), |
4906 | _SVE_INSN ("trn1", 0x05205000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
4907 | _SVE_INSN ("trn1", 0x05207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
4908 | _SVE_INSN ("trn2", 0x05205400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
4909 | _SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
eae424ae | 4910 | _SVE_INSNC ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
c0890d26 | 4911 | _SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0), |
83adff69 RS |
4912 | _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), |
4913 | _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4914 | _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4915 | _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4916 | _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4917 | _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
4918 | _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
eae424ae TC |
4919 | _SVE_INSNC ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), |
4920 | _SVE_INSNC ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2), | |
4921 | _SVE_INSNC ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
4922 | _SVE_INSNC ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), | |
4923 | _SVE_INSNC ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0), | |
4924 | _SVE_INSNC ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
4925 | _SVE_INSNC ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4926 | _SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
eae424ae TC |
4927 | _SVE_INSNC ("umin", 0x252bc000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
4928 | _SVE_INSNC ("umin", 0x040b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
c0890d26 | 4929 | _SVE_INSN ("uminv", 0x040b2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0), |
eae424ae | 4930 | _SVE_INSNC ("umulh", 0x04130000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
c0890d26 | 4931 | _SVE_INSN ("uqadd", 0x04201400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
eae424ae | 4932 | _SVE_INSNC ("uqadd", 0x2525c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
c0890d26 RS |
4933 | _SVE_INSN ("uqdecb", 0x0420fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4934 | _SVE_INSN ("uqdecb", 0x0430fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
eae424ae | 4935 | _SVE_INSNC ("uqdecd", 0x04e0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4936 | _SVE_INSN ("uqdecd", 0x04e0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4937 | _SVE_INSN ("uqdecd", 0x04f0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
eae424ae | 4938 | _SVE_INSNC ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4939 | _SVE_INSN ("uqdech", 0x0460fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4940 | _SVE_INSN ("uqdech", 0x0470fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
2a3ed404 | 4941 | _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4942 | _SVE_INSN ("uqdecp", 0x252b8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
4943 | _SVE_INSN ("uqdecp", 0x252b8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
eae424ae | 4944 | _SVE_INSNC ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4945 | _SVE_INSN ("uqdecw", 0x04a0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4946 | _SVE_INSN ("uqdecw", 0x04b0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4947 | _SVE_INSN ("uqincb", 0x0420f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4948 | _SVE_INSN ("uqincb", 0x0430f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
eae424ae | 4949 | _SVE_INSNC ("uqincd", 0x04e0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4950 | _SVE_INSN ("uqincd", 0x04e0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4951 | _SVE_INSN ("uqincd", 0x04f0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
eae424ae | 4952 | _SVE_INSNC ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4953 | _SVE_INSN ("uqinch", 0x0460f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4954 | _SVE_INSN ("uqinch", 0x0470f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
2a3ed404 | 4955 | _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_Vv_HSD, 0, C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4956 | _SVE_INSN ("uqincp", 0x25298800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0), |
4957 | _SVE_INSN ("uqincp", 0x25298c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), | |
eae424ae | 4958 | _SVE_INSNC ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), |
c0890d26 RS |
4959 | _SVE_INSN ("uqincw", 0x04a0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0), |
4960 | _SVE_INSN ("uqincw", 0x04b0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), | |
4961 | _SVE_INSN ("uqsub", 0x04201c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
eae424ae | 4962 | _SVE_INSNC ("uqsub", 0x2527c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1), |
c0890d26 RS |
4963 | _SVE_INSN ("uunpkhi", 0x05333800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
4964 | _SVE_INSN ("uunpklo", 0x05323800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), | |
eae424ae TC |
4965 | _SVE_INSNC ("uxtb", 0x0411a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), |
4966 | _SVE_INSNC ("uxth", 0x0493a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0), | |
4967 | _SVE_INSNC ("uxtw", 0x04d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0), | |
c0890d26 RS |
4968 | _SVE_INSN ("uzp1", 0x05204800, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), |
4969 | _SVE_INSN ("uzp1", 0x05206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
4970 | _SVE_INSN ("uzp2", 0x05204c00, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
4971 | _SVE_INSN ("uzp2", 0x05206c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
4972 | _SVE_INSN ("whilele", 0x25200410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
4973 | _SVE_INSN ("whilele", 0x25201410, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
4974 | _SVE_INSN ("whilelo", 0x25200c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
4975 | _SVE_INSN ("whilelo", 0x25201c00, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
4976 | _SVE_INSN ("whilels", 0x25200c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
4977 | _SVE_INSN ("whilels", 0x25201c10, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
4978 | _SVE_INSN ("whilelt", 0x25200400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
4979 | _SVE_INSN ("whilelt", 0x25201400, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
4980 | _SVE_INSN ("wrffr", 0x25289000, 0xfffffe1f, sve_misc, 0, OP1 (SVE_Pn), OP_SVE_B, 0, 0), | |
4981 | _SVE_INSN ("zip1", 0x05204000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
4982 | _SVE_INSN ("zip1", 0x05206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
4983 | _SVE_INSN ("zip2", 0x05204400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0), | |
4984 | _SVE_INSN ("zip2", 0x05206400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
eae424ae | 4985 | _SVE_INSNC ("bic", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
c0890d26 RS |
4986 | _SVE_INSN ("cmple", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), |
4987 | _SVE_INSN ("cmplo", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
4988 | _SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
4989 | _SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0), | |
eae424ae | 4990 | _SVE_INSNC ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), |
582e12bf RS |
4991 | _SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), |
4992 | _SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
4993 | _SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
4994 | _SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0), | |
4995 | _SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0), | |
eae424ae TC |
4996 | _SVE_INSNC ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 0), |
4997 | _SVE_INSNC ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1), | |
4bd13cde | 4998 | |
42e6288f MM |
4999 | /* SVE2 instructions. */ |
5000 | SVE2_INSNC ("adclb", 0x4500d000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0), | |
5001 | SVE2_INSNC ("adclt", 0x4500d400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0), | |
5002 | SVE2_INSN ("addhnb", 0x45206000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5003 | SVE2_INSN ("addhnt", 0x45206400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5004 | SVE2_INSNC ("addp", 0x4411a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5005 | SVE2_INSNC ("bcax", 0x04603800, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5006 | SVE2_INSNC ("bsl", 0x04203c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5007 | SVE2_INSNC ("bsl1n", 0x04603c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5008 | SVE2_INSNC ("bsl2n", 0x04a03c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5009 | SVE2_INSNC ("cadd", 0x4500d800, 0xff3ff800, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_IMM_ROT3), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
5010 | SVE2_INSNC ("cdot", 0x44801000, 0xffa0f000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_SD_BH, 0, C_SCAN_MOVPRFX, 0), | |
5011 | SVE2_INSNC ("cdot", 0x44e04000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_DHHU, 0, C_SCAN_MOVPRFX, 0), | |
5012 | SVE2_INSNC ("cdot", 0x44a04000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_SBBU, 0, C_SCAN_MOVPRFX, 0), | |
5013 | SVE2_INSNC ("cmla", 0x44002000, 0xff20f000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5014 | SVE2_INSNC ("cmla", 0x44a06000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0), | |
5015 | SVE2_INSNC ("cmla", 0x44e06000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0), | |
5016 | SVE2_INSNC ("eor3", 0x04203800, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5017 | SVE2_INSNC ("eorbt", 0x45009000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5018 | SVE2_INSNC ("eortb", 0x45009400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5019 | SVE2_INSN ("ext", 0x05600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_UIMM8_53), OP_SVE_BBU, F_OD(2), 0), | |
5020 | SVE2_INSNC ("faddp", 0x64108000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
5021 | SVE2_INSN ("fcvtlt", 0x6489a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0), | |
5022 | SVE2_INSN ("fcvtlt", 0x64cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0), | |
5023 | SVE2_INSN ("fcvtnt", 0x6488a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0), | |
5024 | SVE2_INSN ("fcvtnt", 0x64caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0), | |
5025 | SVE2_INSNC ("fcvtx", 0x650aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), | |
5026 | SVE2_INSN ("fcvtxnt", 0x640aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0), | |
5027 | SVE2_INSNC ("flogb", 0x6518a000, 0xfff9e000, sve_size_hsd2, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0), | |
5028 | SVE2_INSNC ("fmaxnmp", 0x64148000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
5029 | SVE2_INSNC ("fmaxp", 0x64168000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
5030 | SVE2_INSNC ("fminnmp", 0x64158000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
5031 | SVE2_INSNC ("fminp", 0x64178000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2), | |
5032 | SVE2_INSNC ("fmlalb", 0x64a04000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5033 | SVE2_INSNC ("fmlalb", 0x64a08000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5034 | SVE2_INSNC ("fmlalt", 0x64a04400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5035 | SVE2_INSNC ("fmlalt", 0x64a08400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5036 | SVE2_INSNC ("fmlslb", 0x64a06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5037 | SVE2_INSNC ("fmlslb", 0x64a0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5038 | SVE2_INSNC ("fmlslt", 0x64a06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5039 | SVE2_INSNC ("fmlslt", 0x64a0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5040 | SVE2_INSN ("histcnt", 0x45a0c000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0), | |
5041 | SVE2_INSN ("histseg", 0x4520a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_BBB, 0, 0), | |
5042 | SVE2_INSN ("ldnt1b", 0x8400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0), | |
5043 | SVE2_INSN ("ldnt1b", 0xc400c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0), | |
5044 | SVE2_INSN ("ldnt1d", 0xc580c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0), | |
5045 | SVE2_INSN ("ldnt1h", 0x8480a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0), | |
5046 | SVE2_INSN ("ldnt1h", 0xc480c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0), | |
5047 | SVE2_INSN ("ldnt1sb", 0x84008000, 0xbfe0e000, sve_size_sd2, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_VZV_SD, F_OD(1), 0), | |
5048 | SVE2_INSN ("ldnt1sh", 0x84808000, 0xbfe0e000, sve_size_sd2, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_VZV_SD, F_OD(1), 0), | |
5049 | SVE2_INSN ("ldnt1sw", 0xc5008000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0), | |
5050 | SVE2_INSN ("ldnt1w", 0x8500a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0), | |
5051 | SVE2_INSN ("ldnt1w", 0xc500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0), | |
5052 | SVE2_INSN ("match", 0x45208000, 0xffa0e010, sve_size_bh, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BH, 0, 0), | |
5053 | SVE2_INSNC ("mla", 0x44200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), | |
5054 | SVE2_INSNC ("mla", 0x44a00800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0), | |
5055 | SVE2_INSNC ("mla", 0x44e00800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0), | |
5056 | SVE2_INSNC ("mls", 0x44200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), | |
5057 | SVE2_INSNC ("mls", 0x44a00c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0), | |
5058 | SVE2_INSNC ("mls", 0x44e00c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0), | |
5059 | SVE2_INSN ("mul", 0x4420f800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0), | |
5060 | SVE2_INSN ("mul", 0x44a0f800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0), | |
5061 | SVE2_INSN ("mul", 0x44e0f800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0), | |
5062 | SVE2_INSN ("mul", 0x04206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5063 | SVE2_INSNC ("nbsl", 0x04e03c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1), | |
5064 | SVE2_INSN ("nmatch", 0x45208010, 0xffa0e010, sve_size_bh, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BH, 0, 0), | |
5065 | SVE2_INSN ("pmul", 0x04206400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_BBB, 0, 0), | |
41be57ca MM |
5066 | SVE2_INSN ("pmullb", 0x45406800, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0), |
5067 | SVE2_INSN ("pmullt", 0x45406c00, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0), | |
42e6288f MM |
5068 | SVE2_INSN ("raddhnb", 0x45206800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), |
5069 | SVE2_INSN ("raddhnt", 0x45206c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5070 | SVE2_INSN ("rshrnb", 0x45201800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5071 | SVE2_INSN ("rshrnt", 0x45201c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5072 | SVE2_INSN ("rsubhnb", 0x45207800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5073 | SVE2_INSN ("rsubhnt", 0x45207c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5074 | SVE2_INSNC ("saba", 0x4500f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5075 | SVE2_INSNC ("sabalb", 0x4500c000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5076 | SVE2_INSNC ("sabalt", 0x4500c400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5077 | SVE2_INSN ("sabdlb", 0x45003000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5078 | SVE2_INSN ("sabdlt", 0x45003400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5079 | SVE2_INSNC ("sadalp", 0x4404a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5080 | SVE2_INSN ("saddlb", 0x45000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5081 | SVE2_INSN ("saddlbt", 0x45008000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5082 | SVE2_INSN ("saddlt", 0x45000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5083 | SVE2_INSN ("saddwb", 0x45004000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5084 | SVE2_INSN ("saddwt", 0x45004400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5085 | SVE2_INSNC ("sbclb", 0x4580d000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0), | |
5086 | SVE2_INSNC ("sbclt", 0x4580d400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0), | |
5087 | SVE2_INSNC ("shadd", 0x44108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5088 | SVE2_INSN ("shrnb", 0x45201000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5089 | SVE2_INSN ("shrnt", 0x45201400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5090 | SVE2_INSNC ("shsub", 0x44128000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5091 | SVE2_INSNC ("shsubr", 0x44168000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5092 | SVE2_INSN ("sli", 0x4500f400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
91802f3c JB |
5093 | SVE2_INSNC ("smaxp", 0x4414a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), |
5094 | SVE2_INSNC ("sminp", 0x4416a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
42e6288f MM |
5095 | SVE2_INSNC ("smlalb", 0x44a08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5096 | SVE2_INSNC ("smlalb", 0x44e08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5097 | SVE2_INSNC ("smlalb", 0x44004000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5098 | SVE2_INSNC ("smlalt", 0x44a08400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5099 | SVE2_INSNC ("smlalt", 0x44e08400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5100 | SVE2_INSNC ("smlalt", 0x44004400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5101 | SVE2_INSNC ("smlslb", 0x44a0a000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5102 | SVE2_INSNC ("smlslb", 0x44e0a000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5103 | SVE2_INSNC ("smlslb", 0x44005000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5104 | SVE2_INSNC ("smlslt", 0x44a0a400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5105 | SVE2_INSNC ("smlslt", 0x44e0a400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5106 | SVE2_INSNC ("smlslt", 0x44005400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5107 | SVE2_INSN ("smulh", 0x04206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5108 | SVE2_INSN ("smullb", 0x44a0c000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5109 | SVE2_INSN ("smullb", 0x44e0c000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5110 | SVE2_INSN ("smullb", 0x45007000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5111 | SVE2_INSN ("smullt", 0x44a0c400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5112 | SVE2_INSN ("smullt", 0x44e0c400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5113 | SVE2_INSN ("smullt", 0x45007400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5114 | SVE2_INSN ("splice", 0x052d8000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_ZnxN), OP_SVE_VUV_BHSD, F_OD(2), 0), | |
5115 | SVE2_INSNC ("sqabs", 0x4408a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5116 | SVE2_INSNC ("sqadd", 0x44188000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5117 | SVE2_INSNC ("sqcadd", 0x4501d800, 0xff3ff800, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_IMM_ROT3), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
5118 | SVE2_INSNC ("sqdmlalb", 0x44a02000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5119 | SVE2_INSNC ("sqdmlalb", 0x44e02000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5120 | SVE2_INSNC ("sqdmlalb", 0x44006000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5121 | SVE2_INSNC ("sqdmlalbt", 0x44000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5122 | SVE2_INSNC ("sqdmlalt", 0x44a02400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5123 | SVE2_INSNC ("sqdmlalt", 0x44e02400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5124 | SVE2_INSNC ("sqdmlalt", 0x44006400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5125 | SVE2_INSNC ("sqdmlslb", 0x44a03000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5126 | SVE2_INSNC ("sqdmlslb", 0x44e03000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5127 | SVE2_INSNC ("sqdmlslb", 0x44006800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5128 | SVE2_INSNC ("sqdmlslbt", 0x44000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5129 | SVE2_INSNC ("sqdmlslt", 0x44a03400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5130 | SVE2_INSNC ("sqdmlslt", 0x44e03400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5131 | SVE2_INSNC ("sqdmlslt", 0x44006c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5132 | SVE2_INSN ("sqdmulh", 0x4420f000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0), | |
5133 | SVE2_INSN ("sqdmulh", 0x44a0f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0), | |
5134 | SVE2_INSN ("sqdmulh", 0x44e0f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0), | |
5135 | SVE2_INSN ("sqdmulh", 0x04207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5136 | SVE2_INSN ("sqdmullb", 0x44a0e000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5137 | SVE2_INSN ("sqdmullb", 0x44e0e000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5138 | SVE2_INSN ("sqdmullb", 0x45006000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5139 | SVE2_INSN ("sqdmullt", 0x44a0e400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5140 | SVE2_INSN ("sqdmullt", 0x44e0e400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5141 | SVE2_INSN ("sqdmullt", 0x45006400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5142 | SVE2_INSNC ("sqneg", 0x4409a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5143 | SVE2_INSNC ("sqrdcmlah", 0x44a07000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_HHHU, 0, C_SCAN_MOVPRFX, 0), | |
5144 | SVE2_INSNC ("sqrdcmlah", 0x44e07000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_SSSU, 0, C_SCAN_MOVPRFX, 0), | |
5145 | SVE2_INSNC ("sqrdcmlah", 0x44003000, 0xff20f000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5146 | SVE2_INSNC ("sqrdmlah", 0x44201000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), | |
5147 | SVE2_INSNC ("sqrdmlah", 0x44a01000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0), | |
5148 | SVE2_INSNC ("sqrdmlah", 0x44e01000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0), | |
5149 | SVE2_INSNC ("sqrdmlah", 0x44007000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5150 | SVE2_INSNC ("sqrdmlsh", 0x44201400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), | |
5151 | SVE2_INSNC ("sqrdmlsh", 0x44a01400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0), | |
5152 | SVE2_INSNC ("sqrdmlsh", 0x44e01400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0), | |
5153 | SVE2_INSNC ("sqrdmlsh", 0x44007400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5154 | SVE2_INSN ("sqrdmulh", 0x4420f400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0), | |
5155 | SVE2_INSN ("sqrdmulh", 0x44a0f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0), | |
5156 | SVE2_INSN ("sqrdmulh", 0x44e0f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0), | |
5157 | SVE2_INSN ("sqrdmulh", 0x04207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5158 | SVE2_INSNC ("sqrshl", 0x440a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5159 | SVE2_INSNC ("sqrshlr", 0x440e8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5160 | SVE2_INSN ("sqrshrnb", 0x45202800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5161 | SVE2_INSN ("sqrshrnt", 0x45202c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5162 | SVE2_INSN ("sqrshrunb", 0x45200800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5163 | SVE2_INSN ("sqrshrunt", 0x45200c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5164 | SVE2_INSNC ("sqshl", 0x04068000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5165 | SVE2_INSNC ("sqshl", 0x44088000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5166 | SVE2_INSNC ("sqshlr", 0x440c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5167 | SVE2_INSNC ("sqshlu", 0x040f8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5168 | SVE2_INSN ("sqshrnb", 0x45202000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5169 | SVE2_INSN ("sqshrnt", 0x45202400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5170 | SVE2_INSN ("sqshrunb", 0x45200000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5171 | SVE2_INSN ("sqshrunt", 0x45200400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5172 | SVE2_INSNC ("sqsub", 0x441a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5173 | SVE2_INSNC ("sqsubr", 0x441e8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5174 | SVE2_INSN ("sqxtnb", 0x45204000, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5175 | SVE2_INSN ("sqxtnt", 0x45204400, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5176 | SVE2_INSN ("sqxtunb", 0x45205000, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5177 | SVE2_INSN ("sqxtunt", 0x45205400, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5178 | SVE2_INSNC ("srhadd", 0x44148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5179 | SVE2_INSN ("sri", 0x4500f000, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), | |
5180 | SVE2_INSNC ("srshl", 0x44028000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5181 | SVE2_INSNC ("srshlr", 0x44068000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5182 | SVE2_INSNC ("srshr", 0x040c8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5183 | SVE2_INSNC ("srsra", 0x4500e800, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5184 | SVE2_INSN ("sshllb", 0x4500a000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0), | |
5185 | SVE2_INSN ("sshllt", 0x4500a400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0), | |
5186 | SVE2_INSNC ("ssra", 0x4500e000, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5187 | SVE2_INSN ("ssublb", 0x45001000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5188 | SVE2_INSN ("ssublbt", 0x45008800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5189 | SVE2_INSN ("ssublt", 0x45001400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5190 | SVE2_INSN ("ssubltb", 0x45008c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5191 | SVE2_INSN ("ssubwb", 0x45005000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5192 | SVE2_INSN ("ssubwt", 0x45005400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5193 | SVE2_INSN ("stnt1b", 0xe4402000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0), | |
5194 | SVE2_INSN ("stnt1b", 0xe4002000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0), | |
5195 | SVE2_INSN ("stnt1d", 0xe5802000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0), | |
5196 | SVE2_INSN ("stnt1h", 0xe4c02000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0), | |
5197 | SVE2_INSN ("stnt1h", 0xe4802000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0), | |
5198 | SVE2_INSN ("stnt1w", 0xe5402000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0), | |
5199 | SVE2_INSN ("stnt1w", 0xe5002000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0), | |
5200 | SVE2_INSN ("subhnb", 0x45207000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5201 | SVE2_INSN ("subhnt", 0x45207400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0), | |
5202 | SVE2_INSNC ("suqadd", 0x441c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5203 | SVE2_INSN ("tbl", 0x05202800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(2), 0), | |
5204 | SVE2_INSN ("tbx", 0x05202c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5205 | SVE2_INSNC ("uaba", 0x4500fc00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5206 | SVE2_INSNC ("uabalb", 0x4500c800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5207 | SVE2_INSNC ("uabalt", 0x4500cc00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5208 | SVE2_INSN ("uabdlb", 0x45003800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5209 | SVE2_INSN ("uabdlt", 0x45003c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5210 | SVE2_INSNC ("uadalp", 0x4405a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5211 | SVE2_INSN ("uaddlb", 0x45000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5212 | SVE2_INSN ("uaddlt", 0x45000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5213 | SVE2_INSN ("uaddwb", 0x45004800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5214 | SVE2_INSN ("uaddwt", 0x45004c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5215 | SVE2_INSNC ("uhadd", 0x44118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5216 | SVE2_INSNC ("uhsub", 0x44138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5217 | SVE2_INSNC ("uhsubr", 0x44178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5218 | SVE2_INSNC ("umaxp", 0x4415a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5219 | SVE2_INSNC ("uminp", 0x4417a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5220 | SVE2_INSNC ("umlalb", 0x44a09000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5221 | SVE2_INSNC ("umlalb", 0x44e09000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5222 | SVE2_INSNC ("umlalb", 0x44004800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5223 | SVE2_INSNC ("umlalt", 0x44a09400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5224 | SVE2_INSNC ("umlalt", 0x44e09400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5225 | SVE2_INSNC ("umlalt", 0x44004c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5226 | SVE2_INSNC ("umlslb", 0x44a0b000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5227 | SVE2_INSNC ("umlslb", 0x44e0b000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5228 | SVE2_INSNC ("umlslb", 0x44005800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5229 | SVE2_INSNC ("umlslt", 0x44a0b400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5230 | SVE2_INSNC ("umlslt", 0x44e0b400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), | |
5231 | SVE2_INSNC ("umlslt", 0x44005c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), | |
5232 | SVE2_INSN ("umulh", 0x04206c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5233 | SVE2_INSN ("umullb", 0x44a0d000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5234 | SVE2_INSN ("umullb", 0x44e0d000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5235 | SVE2_INSN ("umullb", 0x45007800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5236 | SVE2_INSN ("umullt", 0x44a0d400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0), | |
5237 | SVE2_INSN ("umullt", 0x44e0d400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0), | |
5238 | SVE2_INSN ("umullt", 0x45007c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5239 | SVE2_INSNC ("uqadd", 0x44198000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5240 | SVE2_INSNC ("uqrshl", 0x440b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5241 | SVE2_INSNC ("uqrshlr", 0x440f8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5242 | SVE2_INSN ("uqrshrnb", 0x45203800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5243 | SVE2_INSN ("uqrshrnt", 0x45203c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5244 | SVE2_INSNC ("uqshl", 0x04078000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5245 | SVE2_INSNC ("uqshl", 0x44098000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5246 | SVE2_INSNC ("uqshlr", 0x440d8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5247 | SVE2_INSN ("uqshrnb", 0x45203000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5248 | SVE2_INSN ("uqshrnt", 0x45203400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0), | |
5249 | SVE2_INSNC ("uqsub", 0x441b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5250 | SVE2_INSNC ("uqsubr", 0x441f8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5251 | SVE2_INSN ("uqxtnb", 0x45204800, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5252 | SVE2_INSN ("uqxtnt", 0x45204c00, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0), | |
5253 | SVE2_INSNC ("urecpe", 0x4480a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
5254 | SVE2_INSNC ("urhadd", 0x44158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5255 | SVE2_INSNC ("urshl", 0x44038000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5256 | SVE2_INSNC ("urshlr", 0x44078000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5257 | SVE2_INSNC ("urshr", 0x040d8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5258 | SVE2_INSNC ("ursqrte", 0x4481a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0), | |
5259 | SVE2_INSNC ("ursra", 0x4500ec00, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5260 | SVE2_INSN ("ushllb", 0x4500a800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0), | |
5261 | SVE2_INSN ("ushllt", 0x4500ac00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0), | |
5262 | SVE2_INSNC ("usqadd", 0x441d8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), | |
5263 | SVE2_INSNC ("usra", 0x4500e400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5264 | SVE2_INSN ("usublb", 0x45001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5265 | SVE2_INSN ("usublt", 0x45001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0), | |
5266 | SVE2_INSN ("usubwb", 0x45005800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5267 | SVE2_INSN ("usubwt", 0x45005c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0), | |
5268 | SVE2_INSN ("whilege", 0x25200000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
5269 | SVE2_INSN ("whilege", 0x25201000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5270 | SVE2_INSN ("whilegt", 0x25200010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
5271 | SVE2_INSN ("whilegt", 0x25201010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5272 | SVE2_INSN ("whilehi", 0x25200810, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
5273 | SVE2_INSN ("whilehi", 0x25201810, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5274 | SVE2_INSN ("whilehs", 0x25200800, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0), | |
5275 | SVE2_INSN ("whilehs", 0x25201800, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5276 | SVE2_INSN ("whilerw", 0x25203010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5277 | SVE2_INSN ("whilewr", 0x25203000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5278 | SVE2_INSNC ("xar", 0x04203400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1), | |
5279 | /* SVE2_SM4 instructions. */ | |
5280 | SVE2SM4_INSN ("sm4e", 0x4523e000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_SSS, 0, 1), | |
5281 | SVE2SM4_INSN ("sm4ekey", 0x4520f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SSS, 0, 0), | |
5282 | /* SVE2_AES instructions. */ | |
5283 | SVE2AES_INSN ("aesd", 0x4522e400, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_BBB, 0, 1), | |
5284 | SVE2AES_INSN ("aese", 0x4522e000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_BBB, 0, 1), | |
5285 | SVE2AES_INSN ("aesimc", 0x4520e400, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1), | |
5286 | SVE2AES_INSN ("aesmc", 0x4520e000, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1), | |
41be57ca MM |
5287 | SVE2AES_INSN ("pmullb", 0x45006800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0), |
5288 | SVE2AES_INSN ("pmullt", 0x45006c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0), | |
42e6288f MM |
5289 | /* SVE2_SHA3 instructions. */ |
5290 | SVE2SHA3_INSN ("rax1", 0x4520f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0), | |
5291 | /* SVE2_BITPERM instructions. */ | |
5292 | SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5293 | SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
5294 | SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
971eda73 | 5295 | /* SME instructions. */ |
56723f69 RS |
5296 | SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0), |
5297 | SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0), | |
27297937 RS |
5298 | SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), |
5299 | SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), | |
56723f69 RS |
5300 | SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_SMMS, 0, 0), |
5301 | SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SVE_DMMD, 0, 0), | |
5302 | SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
5303 | SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
5304 | SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0), | |
5305 | SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0), | |
5306 | SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
5307 | SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0), | |
5308 | SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMDD, 0, 0), | |
5309 | SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
27297937 | 5310 | SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), |
56723f69 RS |
5311 | SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), |
5312 | SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5313 | SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5314 | SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5315 | SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5316 | SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5317 | SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5318 | SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5319 | SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5320 | SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5321 | SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5322 | SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5323 | SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5324 | SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5325 | SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), | |
5326 | SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0), | |
5327 | ||
5328 | SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0), | |
5329 | SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0), | |
5330 | SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0), | |
5331 | SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0), | |
7bb5f07c | 5332 | |
1cad938d PW |
5333 | SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0), |
5334 | ||
01a4d082 PW |
5335 | SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), |
5336 | SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5337 | SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5338 | SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5339 | SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, 0), | |
5340 | ||
5341 | SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, 0, 0), | |
5342 | SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, 0, 0), | |
5343 | SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, 0, 0), | |
5344 | SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, 0, 0), | |
5345 | SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QZU, 0, 0), | |
5346 | ||
5347 | SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5348 | SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5349 | SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5350 | SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5351 | SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, 0), | |
5352 | ||
5353 | SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BUU, 0, 0), | |
5354 | SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HUU, 0, 0), | |
5355 | SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SUU, 0, 0), | |
5356 | SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DUU, 0, 0), | |
5357 | SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QUU, 0, 0), | |
5358 | ||
90cd80f8 RS |
5359 | SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1), |
5360 | SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1), | |
01a4d082 | 5361 | |
d3de0860 PW |
5362 | SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0), |
5363 | SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
5364 | SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), | |
a5791d58 | 5365 | SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), |
503fae12 | 5366 | SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), |
d3de0860 | 5367 | |
8ff42920 RS |
5368 | /* Added in SME2, but part of the prefetch hint space and available |
5369 | without special command-line flags. */ | |
5370 | CORE_INSN ("rprfm", 0xf8a04818, 0xffe04c18, sme_misc, 0, OP3 (RPRFMOP, Rm, SIMD_ADDR_SIMPLE), OP_SVE_UXU, 0), | |
5371 | ||
99e01a66 | 5372 | /* SME2 extensions to SVE2. */ |
6a245d99 RS |
5373 | SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5374 | SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5375 | SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5376 | SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
dfc12f9f RS |
5377 | SME2_INSNC ("fdot", 0x64204000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5378 | SME2_INSNC ("fdot", 0x64208000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
e4cf4736 | 5379 | SME2_INSNC ("fclamp", 0x64202400, 0xff20fc00, sme_size_22_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, C_SCAN_MOVPRFX, 0), |
dfc12f9f RS |
5380 | SME2_INSNC ("sdot", 0x4480c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5381 | SME2_INSNC ("sdot", 0x4400c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
d7829a28 RS |
5382 | SME2_INSN ("sqcvtn", 0x45314000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
5383 | SME2_INSN ("sqcvtun", 0x45315000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), | |
b368719a RS |
5384 | SME2_INSN ("sqrshrn", 0x45b02800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), |
5385 | SME2_INSN ("sqrshrun", 0x45b00800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), | |
dfc12f9f RS |
5386 | SME2_INSNC ("udot", 0x4480cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5387 | SME2_INSNC ("udot", 0x4400cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
d7829a28 | 5388 | SME2_INSN ("uqcvtn", 0x45314800, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
b368719a | 5389 | SME2_INSN ("uqrshrn", 0x45b03800, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), |
99e01a66 RS |
5390 | SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), |
5391 | SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5392 | SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5393 | SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5394 | SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5395 | SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5396 | SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5397 | SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), | |
5398 | ||
d8773a8a | 5399 | /* SME2 extensions to SME. */ |
e87ff672 RS |
5400 | SME2_INSN ("add", 0xc1a01c10, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), |
5401 | SME2_INSN ("add", 0xc1a11c10, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
5402 | SME2_INSN ("add", 0xc1201810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), | |
5403 | SME2_INSN ("add", 0xc1301810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), | |
5404 | SME2_INSN ("add", 0xc1a01810, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), | |
5405 | SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
5406 | SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5407 | SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
c04965ec RS |
5408 | SME2_INSN ("bfcvt", 0xc160e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
5409 | SME2_INSN ("bfcvtn", 0xc160e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), | |
57e727c7 RS |
5410 | SME2_INSN ("bfdot", 0xc1501018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
5411 | SME2_INSN ("bfdot", 0xc1509018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), | |
5412 | SME2_INSN ("bfdot", 0xc1201010, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5413 | SME2_INSN ("bfdot", 0xc1301010, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5414 | SME2_INSN ("bfdot", 0xc1a01010, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5415 | SME2_INSN ("bfdot", 0xc1a11010, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
ed429b33 RS |
5416 | SME2_INSN ("bfmlal", 0xc1801010, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5417 | SME2_INSN ("bfmlal", 0xc1901010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5418 | SME2_INSN ("bfmlal", 0xc1909010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5419 | SME2_INSN ("bfmlal", 0xc1200c10, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5420 | SME2_INSN ("bfmlal", 0xc1200810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5421 | SME2_INSN ("bfmlal", 0xc1300810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5422 | SME2_INSN ("bfmlal", 0xc1a00810, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5423 | SME2_INSN ("bfmlal", 0xc1a10810, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
5424 | SME2_INSN ("bfmlsl", 0xc1801018, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), | |
5425 | SME2_INSN ("bfmlsl", 0xc1901018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5426 | SME2_INSN ("bfmlsl", 0xc1909018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5427 | SME2_INSN ("bfmlsl", 0xc1200c18, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5428 | SME2_INSN ("bfmlsl", 0xc1200818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5429 | SME2_INSN ("bfmlsl", 0xc1300818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5430 | SME2_INSN ("bfmlsl", 0xc1a00818, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5431 | SME2_INSN ("bfmlsl", 0xc1a10818, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
a42de229 | 5432 | SME2_INSN ("bfvdot", 0xc1500018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
261f8708 RS |
5433 | SME2_INSN ("bmopa", 0x80800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0), |
5434 | SME2_INSN ("bmops", 0x80800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMSS, 0, 0), | |
99e01a66 | 5435 | SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), |
e87ff672 RS |
5436 | SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), |
5437 | SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
5f05951e RS |
5438 | SME2_INSN ("fclamp", 0xc120c000, 0xff20fc01, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), |
5439 | SME2_INSN ("fclamp", 0xc120c800, 0xff20fc03, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), | |
c04965ec RS |
5440 | SME2_INSN ("fcvt", 0xc120e000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
5441 | SME2_INSN ("fcvtn", 0xc120e020, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), | |
28ef4f20 RS |
5442 | SME2_INSN ("fcvtzs", 0xc121e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), |
5443 | SME2_INSN ("fcvtzs", 0xc131e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
5444 | SME2_INSN ("fcvtzu", 0xc121e020, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), | |
5445 | SME2_INSN ("fcvtzu", 0xc131e020, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
57e727c7 RS |
5446 | SME2_INSN ("fdot", 0xc1501008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
5447 | SME2_INSN ("fdot", 0xc1509008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), | |
5448 | SME2_INSN ("fdot", 0xc1201000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5449 | SME2_INSN ("fdot", 0xc1301000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5450 | SME2_INSN ("fdot", 0xc1a01000, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5451 | SME2_INSN ("fdot", 0xc1a11000, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
27f6a0bd RS |
5452 | SME2_INSN ("fmax", 0xc120a100, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1), |
5453 | SME2_INSN ("fmax", 0xc120a900, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5454 | SME2_INSN ("fmax", 0xc120b100, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1), | |
5455 | SME2_INSN ("fmax", 0xc120b900, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1), | |
5456 | SME2_INSN ("fmaxnm", 0xc120a120, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5457 | SME2_INSN ("fmaxnm", 0xc120a920, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5458 | SME2_INSN ("fmaxnm", 0xc120b120, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1), | |
5459 | SME2_INSN ("fmaxnm", 0xc120b920, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1), | |
5460 | SME2_INSN ("fmin", 0xc120a101, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5461 | SME2_INSN ("fmin", 0xc120a901, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5462 | SME2_INSN ("fmin", 0xc120b101, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1), | |
5463 | SME2_INSN ("fmin", 0xc120b901, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1), | |
5464 | SME2_INSN ("fminnm", 0xc120a121, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5465 | SME2_INSN ("fminnm", 0xc120a921, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1), | |
5466 | SME2_INSN ("fminnm", 0xc120b121, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1), | |
5467 | SME2_INSN ("fminnm", 0xc120b921, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1), | |
80752eb0 RS |
5468 | SME2_INSN ("fmla", 0xc1500000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0), |
5469 | SME2_INSN ("fmla", 0xc1508000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0), | |
5470 | SME2_INSN ("fmla", 0xc1201800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), | |
5471 | SME2_INSN ("fmla", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), | |
5472 | SME2_INSN ("fmla", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), | |
5473 | SME2_INSN ("fmla", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
ed429b33 RS |
5474 | SME2_INSN ("fmlal", 0xc1801000, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5475 | SME2_INSN ("fmlal", 0xc1901000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5476 | SME2_INSN ("fmlal", 0xc1909000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5477 | SME2_INSN ("fmlal", 0xc1200c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5478 | SME2_INSN ("fmlal", 0xc1200800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5479 | SME2_INSN ("fmlal", 0xc1300800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5480 | SME2_INSN ("fmlal", 0xc1a00800, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5481 | SME2_INSN ("fmlal", 0xc1a10800, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
80752eb0 RS |
5482 | SME2_INSN ("fmls", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0), |
5483 | SME2_INSN ("fmls", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0), | |
5484 | SME2_INSN ("fmls", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), | |
5485 | SME2_INSN ("fmls", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), | |
5486 | SME2_INSN ("fmls", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), | |
5487 | SME2_INSN ("fmls", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
ed429b33 RS |
5488 | SME2_INSN ("fmlsl", 0xc1801008, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5489 | SME2_INSN ("fmlsl", 0xc1901008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5490 | SME2_INSN ("fmlsl", 0xc1909008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5491 | SME2_INSN ("fmlsl", 0xc1200c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5492 | SME2_INSN ("fmlsl", 0xc1200808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5493 | SME2_INSN ("fmlsl", 0xc1300808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5494 | SME2_INSN ("fmlsl", 0xc1a00808, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5495 | SME2_INSN ("fmlsl", 0xc1a10808, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
28ef4f20 RS |
5496 | SME2_INSN ("frinta", 0xc1ace000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), |
5497 | SME2_INSN ("frinta", 0xc1bce000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
5498 | SME2_INSN ("frintm", 0xc1aae000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), | |
5499 | SME2_INSN ("frintm", 0xc1bae000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
5500 | SME2_INSN ("frintn", 0xc1a8e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), | |
5501 | SME2_INSN ("frintn", 0xc1b8e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
5502 | SME2_INSN ("frintp", 0xc1a9e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), | |
5503 | SME2_INSN ("frintp", 0xc1b9e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
e87ff672 RS |
5504 | SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), |
5505 | SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
a42de229 | 5506 | SME2_INSN ("fvdot", 0xc1500008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
b408ebbf RS |
5507 | SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), |
5508 | SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), | |
5509 | SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), | |
5510 | SME2_INSN ("ld1b", 0xa1408000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), | |
5511 | SME2_INSN ("ld1b", 0xa0000000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5512 | SME2_INSN ("ld1b", 0xa0008000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5513 | SME2_INSN ("ld1b", 0xa1000000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5514 | SME2_INSN ("ld1b", 0xa1008000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5515 | SME2_INSN ("ld1d", 0xa0406000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0), | |
5516 | SME2_INSN ("ld1d", 0xa040e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0), | |
5517 | SME2_INSN ("ld1d", 0xa1406000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0), | |
5518 | SME2_INSN ("ld1d", 0xa140e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0), | |
5519 | SME2_INSN ("ld1d", 0xa0006000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5520 | SME2_INSN ("ld1d", 0xa000e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5521 | SME2_INSN ("ld1d", 0xa1006000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5522 | SME2_INSN ("ld1d", 0xa100e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5523 | SME2_INSN ("ld1h", 0xa0402000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0), | |
5524 | SME2_INSN ("ld1h", 0xa040a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0), | |
5525 | SME2_INSN ("ld1h", 0xa1402000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0), | |
5526 | SME2_INSN ("ld1h", 0xa140a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0), | |
5527 | SME2_INSN ("ld1h", 0xa0002000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5528 | SME2_INSN ("ld1h", 0xa000a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5529 | SME2_INSN ("ld1h", 0xa1002000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5530 | SME2_INSN ("ld1h", 0xa100a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5531 | SME2_INSN ("ld1w", 0xa0404000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0), | |
5532 | SME2_INSN ("ld1w", 0xa040c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0), | |
5533 | SME2_INSN ("ld1w", 0xa1404000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0), | |
5534 | SME2_INSN ("ld1w", 0xa140c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0), | |
5535 | SME2_INSN ("ld1w", 0xa0004000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5536 | SME2_INSN ("ld1w", 0xa000c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5537 | SME2_INSN ("ld1w", 0xa1004000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5538 | SME2_INSN ("ld1w", 0xa100c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5539 | SME2_INSN ("ldnt1b", 0xa0400001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), | |
5540 | SME2_INSN ("ldnt1b", 0xa0408001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), | |
5541 | SME2_INSN ("ldnt1b", 0xa1400008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), | |
5542 | SME2_INSN ("ldnt1b", 0xa1408008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), | |
5543 | SME2_INSN ("ldnt1b", 0xa0000001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5544 | SME2_INSN ("ldnt1b", 0xa0008001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5545 | SME2_INSN ("ldnt1b", 0xa1000008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5546 | SME2_INSN ("ldnt1b", 0xa1008008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), | |
5547 | SME2_INSN ("ldnt1d", 0xa0406001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0), | |
5548 | SME2_INSN ("ldnt1d", 0xa040e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0), | |
5549 | SME2_INSN ("ldnt1d", 0xa1406008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0), | |
5550 | SME2_INSN ("ldnt1d", 0xa140e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0), | |
5551 | SME2_INSN ("ldnt1d", 0xa0006001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5552 | SME2_INSN ("ldnt1d", 0xa000e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5553 | SME2_INSN ("ldnt1d", 0xa1006008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5554 | SME2_INSN ("ldnt1d", 0xa100e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), | |
5555 | SME2_INSN ("ldnt1h", 0xa0402001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0), | |
5556 | SME2_INSN ("ldnt1h", 0xa040a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0), | |
5557 | SME2_INSN ("ldnt1h", 0xa1402008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0), | |
5558 | SME2_INSN ("ldnt1h", 0xa140a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0), | |
5559 | SME2_INSN ("ldnt1h", 0xa0002001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5560 | SME2_INSN ("ldnt1h", 0xa000a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5561 | SME2_INSN ("ldnt1h", 0xa1002008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5562 | SME2_INSN ("ldnt1h", 0xa100a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), | |
5563 | SME2_INSN ("ldnt1w", 0xa0404001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0), | |
5564 | SME2_INSN ("ldnt1w", 0xa040c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0), | |
5565 | SME2_INSN ("ldnt1w", 0xa1404008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0), | |
5566 | SME2_INSN ("ldnt1w", 0xa140c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0), | |
5567 | SME2_INSN ("ldnt1w", 0xa0004001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5568 | SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5569 | SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
5570 | SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), | |
cbd11b88 RS |
5571 | SME2_INSN ("ldr", 0xe11f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), |
5572 | SME2_INSN ("luti2", 0xc0cc0000, 0xfffc0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX4_14), OP_SVE_VUU_BHS, 0, 0), | |
5573 | SME2_INSN ("luti2", 0xc08c4000, 0xfffc4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX3_15), OP_SVE_VUU_BHS, 0, 0), | |
5574 | SME2_INSN ("luti2", 0xc08c8000, 0xfffccc03, sme_size_12_bhs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX2_16), OP_SVE_VUU_BHS, 0, 0), | |
5575 | SME2_INSN ("luti4", 0xc0ca0000, 0xfffe0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX3_14), OP_SVE_VUU_BHS, 0, 0), | |
5576 | SME2_INSN ("luti4", 0xc08a4000, 0xfffe4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BHS, 0, 0), | |
5577 | SME2_INSN ("luti4", 0xc08a8000, 0xfffecc03, sme_size_12_hs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_VUU_HS, 0, 0), | |
d8773a8a RS |
5578 | SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), |
5579 | SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), | |
5580 | SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), | |
5581 | SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0), | |
5582 | SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0), | |
5583 | SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), | |
5584 | SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), | |
5585 | SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), | |
5586 | SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), | |
5587 | SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), | |
5588 | SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), | |
5589 | SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0), | |
5590 | SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0), | |
5591 | SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), | |
5592 | SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), | |
5593 | SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), | |
cbd11b88 RS |
5594 | SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0), |
5595 | SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0), | |
99e01a66 RS |
5596 | SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0), |
5597 | SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0), | |
5598 | SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0), | |
5f05951e RS |
5599 | SME2_INSN ("sclamp", 0xc120c400, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
5600 | SME2_INSN ("sclamp", 0xc120cc00, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
28ef4f20 RS |
5601 | SME2_INSN ("scvtf", 0xc122e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), |
5602 | SME2_INSN ("scvtf", 0xc132e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
57e727c7 RS |
5603 | SME2_INSN ("sdot", 0xc1501000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
5604 | SME2_INSN ("sdot", 0xc1509000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), | |
5605 | SME2_INSN ("sdot", 0xc1601408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5606 | SME2_INSN ("sdot", 0xc1701408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5607 | SME2_INSN ("sdot", 0xc1e01408, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5608 | SME2_INSN ("sdot", 0xc1e11408, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
5609 | SME2_INSN ("sdot", 0xc1501020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0), | |
5610 | SME2_INSN ("sdot", 0xc1509020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
5611 | SME2_INSN ("sdot", 0xc1201400, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5612 | SME2_INSN ("sdot", 0xc1301400, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5613 | SME2_INSN ("sdot", 0xc1a01400, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5614 | SME2_INSN ("sdot", 0xc1a11400, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
99e01a66 RS |
5615 | SME2_INSN ("sel", 0xc1208000, 0xff21e021, sme_size_22, 0, OP4 (SME_Zdnx2, SME_PNg3, SME_Znx2, SME_Zmx2), OP_SVE_VUVV_BHSD, 0, 0), |
5616 | SME2_INSN ("sel", 0xc1218000, 0xff23e063, sme_size_22, 0, OP4 (SME_Zdnx4, SME_PNg3, SME_Znx4, SME_Zmx4), OP_SVE_VUVV_BHSD, 0, 0), | |
27f6a0bd RS |
5617 | SME2_INSN ("smax", 0xc120a000, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), |
5618 | SME2_INSN ("smax", 0xc120a800, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5619 | SME2_INSN ("smax", 0xc120b000, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5620 | SME2_INSN ("smax", 0xc120b800, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
5621 | SME2_INSN ("smin", 0xc120a020, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5622 | SME2_INSN ("smin", 0xc120a820, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5623 | SME2_INSN ("smin", 0xc120b020, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5624 | SME2_INSN ("smin", 0xc120b820, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
ed429b33 RS |
5625 | SME2_INSN ("smlal", 0xc1c01000, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5626 | SME2_INSN ("smlal", 0xc1d01000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5627 | SME2_INSN ("smlal", 0xc1d09000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5628 | SME2_INSN ("smlal", 0xc1600c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5629 | SME2_INSN ("smlal", 0xc1600800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5630 | SME2_INSN ("smlal", 0xc1700800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5631 | SME2_INSN ("smlal", 0xc1e00800, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5632 | SME2_INSN ("smlal", 0xc1e10800, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
a8cb21aa RS |
5633 | SME2_INSN ("smlall", 0xc1000000, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5634 | SME2_INSN ("smlall", 0xc1100000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5635 | SME2_INSN ("smlall", 0xc1108000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5636 | SME2_INSN ("smlall", 0xc1200400, 0xffb09c1c, sme_int_sd, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_SD_BH, 0, 0), | |
5637 | SME2_INSN ("smlall", 0xc1200000, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5638 | SME2_INSN ("smlall", 0xc1300000, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5639 | SME2_INSN ("smlall", 0xc1a00000, 0xffa19c3e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5640 | SME2_INSN ("smlall", 0xc1a10000, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
ed429b33 RS |
5641 | SME2_INSN ("smlsl", 0xc1c01008, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5642 | SME2_INSN ("smlsl", 0xc1d01008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5643 | SME2_INSN ("smlsl", 0xc1d09008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5644 | SME2_INSN ("smlsl", 0xc1600c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5645 | SME2_INSN ("smlsl", 0xc1600808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5646 | SME2_INSN ("smlsl", 0xc1700808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5647 | SME2_INSN ("smlsl", 0xc1e00808, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5648 | SME2_INSN ("smlsl", 0xc1e10808, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
a8cb21aa RS |
5649 | SME2_INSN ("smlsll", 0xc1000008, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5650 | SME2_INSN ("smlsll", 0xc1100008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5651 | SME2_INSN ("smlsll", 0xc1108008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5652 | SME2_INSN ("smlsll", 0xc1200408, 0xffb09c1c, sme_int_sd, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_SD_BH, 0, 0), | |
5653 | SME2_INSN ("smlsll", 0xc1200008, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5654 | SME2_INSN ("smlsll", 0xc1300008, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5655 | SME2_INSN ("smlsll", 0xc1a00008, 0xffa19c3e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5656 | SME2_INSN ("smlsll", 0xc1a10008, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
261f8708 RS |
5657 | SME2_INSN ("smopa", 0xa0800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), |
5658 | SME2_INSN ("smops", 0xa0800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
ce623e7a RS |
5659 | SME2_INSN ("sqcvt", 0xc123e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
5660 | SME2_INSN ("sqcvt", 0xc133e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
5661 | SME2_INSN ("sqcvtn", 0xc133e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
5662 | SME2_INSN ("sqcvtu", 0xc163e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), | |
5663 | SME2_INSN ("sqcvtu", 0xc173e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
5664 | SME2_INSN ("sqcvtun", 0xc173e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
27f6a0bd RS |
5665 | SME2_INSN ("sqdmulh", 0xc120a400, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), |
5666 | SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5667 | SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5668 | SME2_INSN ("sqdmulh", 0xc120bc00, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
6efa6601 RS |
5669 | SME2_INSN ("sqrshr", 0xc1e0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), |
5670 | SME2_INSN ("sqrshr", 0xc120d800, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
5671 | SME2_INSN ("sqrshrn", 0xc120dc00, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
5672 | SME2_INSN ("sqrshru", 0xc1f0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), | |
5673 | SME2_INSN ("sqrshru", 0xc120d840, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
5674 | SME2_INSN ("sqrshrun", 0xc120dc40, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
27f6a0bd RS |
5675 | SME2_INSN ("srshl", 0xc120a220, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), |
5676 | SME2_INSN ("srshl", 0xc120aa20, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5677 | SME2_INSN ("srshl", 0xc120b220, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5678 | SME2_INSN ("srshl", 0xc120ba20, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
b408ebbf RS |
5679 | SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), |
5680 | SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0), | |
5681 | SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), | |
5682 | SME2_INSN ("st1b", 0xa1608000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0), | |
5683 | SME2_INSN ("st1b", 0xa0200000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5684 | SME2_INSN ("st1b", 0xa0208000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5685 | SME2_INSN ("st1b", 0xa1200000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5686 | SME2_INSN ("st1b", 0xa1208000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5687 | SME2_INSN ("st1d", 0xa0606000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0), | |
5688 | SME2_INSN ("st1d", 0xa060e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0), | |
5689 | SME2_INSN ("st1d", 0xa1606000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0), | |
5690 | SME2_INSN ("st1d", 0xa160e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0), | |
5691 | SME2_INSN ("st1d", 0xa0206000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5692 | SME2_INSN ("st1d", 0xa020e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5693 | SME2_INSN ("st1d", 0xa1206000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5694 | SME2_INSN ("st1d", 0xa120e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5695 | SME2_INSN ("st1h", 0xa0602000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0), | |
5696 | SME2_INSN ("st1h", 0xa060a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0), | |
5697 | SME2_INSN ("st1h", 0xa1602000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0), | |
5698 | SME2_INSN ("st1h", 0xa160a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0), | |
5699 | SME2_INSN ("st1h", 0xa0202000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5700 | SME2_INSN ("st1h", 0xa020a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5701 | SME2_INSN ("st1h", 0xa1202000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5702 | SME2_INSN ("st1h", 0xa120a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5703 | SME2_INSN ("st1w", 0xa0604000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0), | |
5704 | SME2_INSN ("st1w", 0xa060c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0), | |
5705 | SME2_INSN ("st1w", 0xa1604000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0), | |
5706 | SME2_INSN ("st1w", 0xa160c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0), | |
5707 | SME2_INSN ("st1w", 0xa0204000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5708 | SME2_INSN ("st1w", 0xa020c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5709 | SME2_INSN ("st1w", 0xa1204000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5710 | SME2_INSN ("st1w", 0xa120c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5711 | SME2_INSN ("stnt1b", 0xa0600001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), | |
5712 | SME2_INSN ("stnt1b", 0xa0608001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0), | |
5713 | SME2_INSN ("stnt1b", 0xa1600008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0), | |
5714 | SME2_INSN ("stnt1b", 0xa1608008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0), | |
5715 | SME2_INSN ("stnt1b", 0xa0200001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5716 | SME2_INSN ("stnt1b", 0xa0208001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5717 | SME2_INSN ("stnt1b", 0xa1200008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5718 | SME2_INSN ("stnt1b", 0xa1208008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), | |
5719 | SME2_INSN ("stnt1d", 0xa0606001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0), | |
5720 | SME2_INSN ("stnt1d", 0xa060e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0), | |
5721 | SME2_INSN ("stnt1d", 0xa1606008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0), | |
5722 | SME2_INSN ("stnt1d", 0xa160e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0), | |
5723 | SME2_INSN ("stnt1d", 0xa0206001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5724 | SME2_INSN ("stnt1d", 0xa020e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5725 | SME2_INSN ("stnt1d", 0xa1206008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5726 | SME2_INSN ("stnt1d", 0xa120e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), | |
5727 | SME2_INSN ("stnt1h", 0xa0602001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0), | |
5728 | SME2_INSN ("stnt1h", 0xa060a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0), | |
5729 | SME2_INSN ("stnt1h", 0xa1602008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0), | |
5730 | SME2_INSN ("stnt1h", 0xa160a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0), | |
5731 | SME2_INSN ("stnt1h", 0xa0202001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5732 | SME2_INSN ("stnt1h", 0xa020a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5733 | SME2_INSN ("stnt1h", 0xa1202008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5734 | SME2_INSN ("stnt1h", 0xa120a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), | |
5735 | SME2_INSN ("stnt1w", 0xa0604001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0), | |
5736 | SME2_INSN ("stnt1w", 0xa060c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0), | |
5737 | SME2_INSN ("stnt1w", 0xa1604008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0), | |
5738 | SME2_INSN ("stnt1w", 0xa160c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0), | |
5739 | SME2_INSN ("stnt1w", 0xa0204001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5740 | SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5741 | SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
5742 | SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), | |
cbd11b88 | 5743 | SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), |
e87ff672 RS |
5744 | SME2_INSN ("sub", 0xc1a01c18, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), |
5745 | SME2_INSN ("sub", 0xc1a11c18, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
5746 | SME2_INSN ("sub", 0xc1201818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), | |
5747 | SME2_INSN ("sub", 0xc1301818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), | |
5748 | SME2_INSN ("sub", 0xc1a01818, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), | |
5749 | SME2_INSN ("sub", 0xc1a11818, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), | |
57e727c7 RS |
5750 | SME2_INSN ("sudot", 0xc1501038, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0), |
5751 | SME2_INSN ("sudot", 0xc1509038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
5752 | SME2_INSN ("sudot", 0xc1201418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0), | |
5753 | SME2_INSN ("sudot", 0xc1301418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0), | |
a8cb21aa RS |
5754 | SME2_INSN ("sumlall", 0xc1000014, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5755 | SME2_INSN ("sumlall", 0xc1100030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5756 | SME2_INSN ("sumlall", 0xc1108030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5757 | SME2_INSN ("sumlall", 0xc1200014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0), | |
5758 | SME2_INSN ("sumlall", 0xc1300014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0), | |
fa64dc80 RS |
5759 | SME2_INSN ("sunpk", 0xc125e000, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
5760 | SME2_INSN ("sunpk", 0xc135e000, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0), | |
a42de229 RS |
5761 | SME2_INSN ("suvdot", 0xc1508038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), |
5762 | SME2_INSN ("svdot", 0xc1500020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), | |
5763 | SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
5f05951e RS |
5764 | SME2_INSN ("uclamp", 0xc120c401, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
5765 | SME2_INSN ("uclamp", 0xc120cc01, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), | |
28ef4f20 RS |
5766 | SME2_INSN ("ucvtf", 0xc122e020, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0), |
5767 | SME2_INSN ("ucvtf", 0xc132e020, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0), | |
57e727c7 RS |
5768 | SME2_INSN ("udot", 0xc1501010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
5769 | SME2_INSN ("udot", 0xc1509010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), | |
5770 | SME2_INSN ("udot", 0xc1601418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5771 | SME2_INSN ("udot", 0xc1701418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5772 | SME2_INSN ("udot", 0xc1e01418, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5773 | SME2_INSN ("udot", 0xc1e11418, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
5774 | SME2_INSN ("udot", 0xc1501030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0), | |
5775 | SME2_INSN ("udot", 0xc1509030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
5776 | SME2_INSN ("udot", 0xc1201410, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5777 | SME2_INSN ("udot", 0xc1301410, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5778 | SME2_INSN ("udot", 0xc1a01410, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5779 | SME2_INSN ("udot", 0xc1a11410, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
27f6a0bd RS |
5780 | SME2_INSN ("umax", 0xc120a001, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), |
5781 | SME2_INSN ("umax", 0xc120a801, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5782 | SME2_INSN ("umax", 0xc120b001, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5783 | SME2_INSN ("umax", 0xc120b801, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
5784 | SME2_INSN ("umin", 0xc120a021, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5785 | SME2_INSN ("umin", 0xc120a821, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5786 | SME2_INSN ("umin", 0xc120b021, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5787 | SME2_INSN ("umin", 0xc120b821, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
ed429b33 RS |
5788 | SME2_INSN ("umlal", 0xc1c01010, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5789 | SME2_INSN ("umlal", 0xc1d01010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5790 | SME2_INSN ("umlal", 0xc1d09010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5791 | SME2_INSN ("umlal", 0xc1600c10, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5792 | SME2_INSN ("umlal", 0xc1600810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5793 | SME2_INSN ("umlal", 0xc1700810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5794 | SME2_INSN ("umlal", 0xc1e00810, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5795 | SME2_INSN ("umlal", 0xc1e10810, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
a8cb21aa RS |
5796 | SME2_INSN ("umlall", 0xc1000010, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5797 | SME2_INSN ("umlall", 0xc1100010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5798 | SME2_INSN ("umlall", 0xc1108010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5799 | SME2_INSN ("umlall", 0xc1200410, 0xffb09c1c, sme_int_sd, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_SD_BH, 0, 0), | |
5800 | SME2_INSN ("umlall", 0xc1200010, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5801 | SME2_INSN ("umlall", 0xc1300010, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5802 | SME2_INSN ("umlall", 0xc1a00010, 0xffa19c3e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5803 | SME2_INSN ("umlall", 0xc1a10010, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
ed429b33 RS |
5804 | SME2_INSN ("umlsl", 0xc1c01018, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), |
5805 | SME2_INSN ("umlsl", 0xc1d01018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), | |
5806 | SME2_INSN ("umlsl", 0xc1d09018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), | |
5807 | SME2_INSN ("umlsl", 0xc1600c18, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), | |
5808 | SME2_INSN ("umlsl", 0xc1600818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), | |
5809 | SME2_INSN ("umlsl", 0xc1700818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), | |
5810 | SME2_INSN ("umlsl", 0xc1e00818, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), | |
5811 | SME2_INSN ("umlsl", 0xc1e10818, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), | |
a8cb21aa RS |
5812 | SME2_INSN ("umlsll", 0xc1000018, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5813 | SME2_INSN ("umlsll", 0xc1100018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5814 | SME2_INSN ("umlsll", 0xc1108018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5815 | SME2_INSN ("umlsll", 0xc1200418, 0xffb09c1c, sme_int_sd, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_SD_BH, 0, 0), | |
5816 | SME2_INSN ("umlsll", 0xc1200018, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5817 | SME2_INSN ("umlsll", 0xc1300018, 0xffb09c1e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5818 | SME2_INSN ("umlsll", 0xc1a00018, 0xffa19c3e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5819 | SME2_INSN ("umlsll", 0xc1a10018, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
261f8708 RS |
5820 | SME2_INSN ("umopa", 0xa1800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), |
5821 | SME2_INSN ("umops", 0xa1800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), | |
ce623e7a RS |
5822 | SME2_INSN ("uqcvt", 0xc123e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), |
5823 | SME2_INSN ("uqcvt", 0xc133e020, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
5824 | SME2_INSN ("uqcvtn", 0xc133e060, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), | |
6efa6601 RS |
5825 | SME2_INSN ("uqrshr", 0xc1e0d420, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), |
5826 | SME2_INSN ("uqrshr", 0xc120d820, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
5827 | SME2_INSN ("uqrshrn", 0xc120dc20, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), | |
27f6a0bd RS |
5828 | SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), |
5829 | SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), | |
5830 | SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), | |
5831 | SME2_INSN ("urshl", 0xc120ba21, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), | |
57e727c7 RS |
5832 | SME2_INSN ("usdot", 0xc1501028, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (2), 0), |
5833 | SME2_INSN ("usdot", 0xc1509028, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
5834 | SME2_INSN ("usdot", 0xc1201408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0), | |
5835 | SME2_INSN ("usdot", 0xc1301408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0), | |
5836 | SME2_INSN ("usdot", 0xc1a01408, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_SBB, F_OD (2), 0), | |
5837 | SME2_INSN ("usdot", 0xc1a11408, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_SBB, F_OD (4), 0), | |
a8cb21aa RS |
5838 | SME2_INSN ("usmlall", 0xc1000004, 0xfff0001c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_SBB, 0, 0), |
5839 | SME2_INSN ("usmlall", 0xc1100020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (2), 0), | |
5840 | SME2_INSN ("usmlall", 0xc1108020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), | |
5841 | SME2_INSN ("usmlall", 0xc1200404, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_SD_BH, 0, 0), | |
5842 | SME2_INSN ("usmlall", 0xc1200004, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (2), 0), | |
5843 | SME2_INSN ("usmlall", 0xc1300004, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD_BH, F_OD (4), 0), | |
5844 | SME2_INSN ("usmlall", 0xc1a00004, 0xffe19c3e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_SBB, F_OD (2), 0), | |
5845 | SME2_INSN ("usmlall", 0xc1a10004, 0xffe39c7e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_SBB, F_OD (4), 0), | |
a42de229 | 5846 | SME2_INSN ("usvdot", 0xc1508028, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), |
fa64dc80 RS |
5847 | SME2_INSN ("uunpk", 0xc125e001, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), |
5848 | SME2_INSN ("uunpk", 0xc135e001, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0), | |
a42de229 RS |
5849 | SME2_INSN ("uvdot", 0xc1500030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), |
5850 | SME2_INSN ("uvdot", 0xc1508030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), | |
7bd1d20e RS |
5851 | SME2_INSN ("uzp", 0xc120d001, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
5852 | SME2_INSN ("uzp", 0xc120d401, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
5853 | SME2_INSN ("uzp", 0xc136e002, 0xff3ffc63, sme_size_22, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_VV_BHSD, 0, 0), | |
5854 | SME2_INSN ("uzp", 0xc137e002, 0xfffffc63, sme_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_QQ, 0, 0), | |
99e01a66 RS |
5855 | SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), |
5856 | SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5857 | SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5858 | SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5859 | SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5860 | SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5861 | SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
5862 | SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), | |
cbd11b88 | 5863 | SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0), |
7bd1d20e RS |
5864 | SME2_INSN ("zip", 0xc120d000, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), |
5865 | SME2_INSN ("zip", 0xc120d400, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
5866 | SME2_INSN ("zip", 0xc136e000, 0xff3ffc63, sme_size_22, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_VV_BHSD, 0, 0), | |
5867 | SME2_INSN ("zip", 0xc137e000, 0xfffffc63, sme_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_QQ, 0, 0), | |
d8773a8a | 5868 | |
a8cb21aa | 5869 | /* SME2 I16I64 instructions. */ |
57e727c7 RS |
5870 | SME2_I16I64_INSN ("sdot", 0xc1d00008, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (2), 0), |
5871 | SME2_I16I64_INSN ("sdot", 0xc1d08008, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0), | |
a8cb21aa RS |
5872 | SME2_I16I64_INSN ("smlall", 0xc1800000, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0), |
5873 | SME2_I16I64_INSN ("smlall", 0xc1900000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0), | |
5874 | SME2_I16I64_INSN ("smlall", 0xc1908000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0), | |
5875 | SME2_I16I64_INSN ("smlsll", 0xc1800008, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0), | |
5876 | SME2_I16I64_INSN ("smlsll", 0xc1900008, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0), | |
5877 | SME2_I16I64_INSN ("smlsll", 0xc1908008, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0), | |
a42de229 | 5878 | SME2_I16I64_INSN ("svdot", 0xc1d08808, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0), |
57e727c7 RS |
5879 | SME2_I16I64_INSN ("udot", 0xc1d00018, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (2), 0), |
5880 | SME2_I16I64_INSN ("udot", 0xc1d08018, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0), | |
a8cb21aa RS |
5881 | SME2_I16I64_INSN ("umlall", 0xc1800010, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0), |
5882 | SME2_I16I64_INSN ("umlall", 0xc1900010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0), | |
5883 | SME2_I16I64_INSN ("umlall", 0xc1908010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0), | |
5884 | SME2_I16I64_INSN ("umlsll", 0xc1800018, 0xfff0101c, sme_misc, 0, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_DHH, 0, 0), | |
5885 | SME2_I16I64_INSN ("umlsll", 0xc1900018, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (2), 0), | |
5886 | SME2_I16I64_INSN ("umlsll", 0xc1908018, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX3_1), OP_SVE_DHH, F_OD (4), 0), | |
a42de229 | 5887 | SME2_I16I64_INSN ("uvdot", 0xc1d08818, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (4), 0), |
a8cb21aa | 5888 | |
80752eb0 RS |
5889 | /* SME2 F64F64 instructions. */ |
5890 | SME2_F64F64_INSN ("fmla", 0xc1d00000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0), | |
5891 | SME2_F64F64_INSN ("fmla", 0xc1d08000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0), | |
5892 | SME2_F64F64_INSN ("fmls", 0xc1d00010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0), | |
5893 | SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0), | |
5894 | ||
65a55fbb TC |
5895 | /* SIMD Dot Product (optional in v8.2-A). */ |
5896 | DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
5897 | DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), | |
ff329288 TC |
5898 | DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), |
5899 | DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), | |
e9dbdd80 TC |
5900 | /* Crypto SHA2 (optional in ARMv8.2-a). */ |
5901 | SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
5902 | SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), | |
5903 | SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0), | |
5904 | SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
5905 | /* Crypto SHA3 (optional in ARMv8.2-a). */ | |
5906 | SHA3_INSN ("eor3", 0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
5907 | SHA3_INSN ("rax1", 0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), | |
5908 | SHA3_INSN ("xar", 0xce800000, 0xffe00000, cryptosha3, OP4 (Vd, Vn, Vm, IMM), QL_XAR, 0), | |
5909 | SHA3_INSN ("bcax", 0xce200000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), | |
5910 | /* Crypto SM3 (optional in ARMv8.2-a). */ | |
5911 | SM4_INSN ("sm3ss1", 0xce400000, 0xffe08000, cryptosm3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME4S, 0), | |
5912 | SM4_INSN ("sm3tt1a", 0xce408000, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
5913 | SM4_INSN ("sm3tt1b", 0xce408400, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
5914 | SM4_INSN ("sm3tt2a", 0xce408800, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
5915 | SM4_INSN ("sm3tt2b", 0xce408c00, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0), | |
5916 | SM4_INSN ("sm3partw1", 0xce60c000, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
5917 | SM4_INSN ("sm3partw2", 0xce60c400, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
5918 | /* Crypto SM4 (optional in ARMv8.2-a). */ | |
5919 | SM4_INSN ("sm4e", 0xcec08400, 0xfffffc00, cryptosm4, OP2 (Vd, Vn), QL_V2SAME4S, 0), | |
5920 | SM4_INSN ("sm4ekey", 0xce60c800, 0xffe0fc00, cryptosm4, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), | |
5921 | /* Crypto FP16 (optional in ARMv8.2-a). */ | |
a4822788 VDN |
5922 | FP16_V8_2A_INSN ("fmlal", 0xe20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), |
5923 | FP16_V8_2A_INSN ("fmlsl", 0xea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
5924 | FP16_V8_2A_INSN ("fmlal2", 0x2e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
5925 | FP16_V8_2A_INSN ("fmlsl2", 0x2ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0), | |
5926 | ||
5927 | FP16_V8_2A_INSN ("fmlal", 0x4e20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
5928 | FP16_V8_2A_INSN ("fmlsl", 0x4ea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
5929 | FP16_V8_2A_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
5930 | FP16_V8_2A_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), | |
5931 | ||
5932 | FP16_V8_2A_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
5933 | FP16_V8_2A_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
5934 | FP16_V8_2A_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
5935 | FP16_V8_2A_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), | |
5936 | ||
5937 | FP16_V8_2A_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
5938 | FP16_V8_2A_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
5939 | FP16_V8_2A_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
5940 | FP16_V8_2A_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), | |
e9dbdd80 | 5941 | /* System extensions ARMv8.4-a. */ |
e64441b1 PW |
5942 | FLAGM_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0), |
5943 | FLAGM_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
5944 | FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0), | |
e9dbdd80 | 5945 | /* Memory access instructions ARMv8.4-a. */ |
a4822788 VDN |
5946 | V8_4A_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), |
5947 | V8_4A_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5948 | V8_4A_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5949 | V8_4A_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
5950 | V8_4A_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5951 | V8_4A_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5952 | V8_4A_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5953 | V8_4A_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
5954 | V8_4A_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5955 | V8_4A_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0), | |
5956 | V8_4A_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
5957 | V8_4A_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
5958 | V8_4A_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), | |
df678013 | 5959 | |
8382113f MM |
5960 | /* Matrix Multiply instructions. */ |
5961 | INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5962 | INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5963 | INT8MATMUL_SVE_INSNC ("usmmla", 0x45809800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5964 | INT8MATMUL_SVE_INSNC ("usdot", 0x44807800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5965 | INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5966 | INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), | |
5967 | F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), | |
f4950f76 | 5968 | F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), |
5437a02a JB |
5969 | F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), |
5970 | F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), | |
5971 | F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), | |
5972 | F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), | |
8382113f MM |
5973 | F64MATMUL_SVE_INSN ("ld1rob", 0xa4202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_BZU, F_OD(1), 0), |
5974 | F64MATMUL_SVE_INSN ("ld1roh", 0xa4a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_HZU, F_OD(1), 0), | |
5975 | F64MATMUL_SVE_INSN ("ld1row", 0xa5202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_SZU, F_OD(1), 0), | |
5976 | F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0), | |
5977 | F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
5978 | F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
8c45011a JB |
5979 | F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), |
5980 | F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
8382113f MM |
5981 | F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), |
5982 | F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), | |
5983 | /* Matrix Multiply advanced SIMD instructions. */ | |
5984 | INT8MATMUL_INSN ("smmla", 0x4e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), | |
5985 | INT8MATMUL_INSN ("ummla", 0x6e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), | |
5986 | INT8MATMUL_INSN ("usmmla", 0x4e80ac00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), | |
567dfba2 JB |
5987 | INT8MATMUL_INSN ("usdot", 0x0e809c00, 0xbfe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), |
5988 | INT8MATMUL_INSN ("usdot", 0x0f80f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), | |
5989 | INT8MATMUL_INSN ("sudot", 0x0f00f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), | |
8382113f | 5990 | |
df678013 MM |
5991 | /* BFloat instructions. */ |
5992 | BFLOAT16_SVE_INSNC ("bfdot", 0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5993 | BFLOAT16_SVE_INSNC ("bfdot", 0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5994 | BFLOAT16_SVE_INSNC ("bfmmla", 0x6460e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
c3036ed0 RS |
5995 | BFLOAT16_SVE_INSNC ("bfcvt", 0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0), |
5996 | BFLOAT16_SVE_INSNC ("bfcvtnt", 0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0, 0), | |
df678013 MM |
5997 | BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e08400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), |
5998 | BFLOAT16_SVE_INSNC ("bfmlalb", 0x64e08000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
5999 | BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e04400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
6000 | BFLOAT16_SVE_INSNC ("bfmlalb", 0x64e04000, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), | |
6001 | /* BFloat Advanced SIMD instructions. */ | |
6002 | BFLOAT16_INSN ("bfdot", 0x2e40fc00, 0xbfe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFDOT64, F_SIZEQ), | |
6003 | /* Using dotproduct as iclass to treat instruction similar to udot. */ | |
6004 | BFLOAT16_INSN ("bfdot", 0x0f40f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_BFDOT64I, F_SIZEQ), | |
6005 | BFLOAT16_INSN ("bfmmla", 0x6e40ec00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, F_SIZEQ), | |
6006 | BFLOAT16_INSN ("bfcvtn", 0x0ea16800, 0xfffffc00, bfloat16, OP2 (Vd, Vn), QL_BFCVTN64, 0), | |
6007 | BFLOAT16_INSN ("bfcvtn2", 0x4ea16800, 0xfffffc00, bfloat16, OP2 (Vd, Vn), QL_BFCVTN2_64, 0), | |
6008 | BFLOAT16_INSN ("bfcvt", 0x1e634000, 0xfffffc00, bfloat16, OP2 (Fd, Fn), QL_BFCVT64, 0), | |
6009 | BFLOAT16_INSN ("bfmlalt", 0x6ec0fc00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, 0), | |
6010 | BFLOAT16_INSN ("bfmlalb", 0x2ec0fc00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, 0), | |
6011 | BFLOAT16_INSN ("bfmlalt", 0x4fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0), | |
6012 | BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0), | |
6327658e RS |
6013 | |
6014 | /* cpyfp cpyfprn cpyfpwn cpyfpn | |
6015 | cpyfm cpyfmrn cpyfmwn cpyfmn | |
6016 | cpyfe cpyfern cpyfewn cpyfen | |
6017 | ||
6018 | cpyfprt cpyfprtrn cpyfprtwn cpyfprtn | |
6019 | cpyfmrt cpyfmrtrn cpyfmrtwn cpyfmrtn | |
6020 | cpyfert cpyfertrn cpyfertwn cpyfertn | |
6021 | ||
6022 | cpyfpwt cpyfpwtrn cpyfpwtwn cpyfpwtn | |
6023 | cpyfmwt cpyfmwtrn cpyfmwtwn cpyfmwtn | |
6024 | cpyfewt cpyfewtrn cpyfewtwn cpyfewtn | |
6025 | ||
6026 | cpyfpt cpyfptrn cpyfptwn cpyfptn | |
6027 | cpyfmt cpyfmtrn cpyfmtwn cpyfmtn | |
6028 | cpyfet cpyfetrn cpyfetwn cpyfetn. */ | |
6029 | MOPS_CPY_INSN ("cpyf", 0x19000400, 0xffe0fc00), | |
6030 | ||
6031 | /* cpyp cpyprn cpypwn cpypn | |
6032 | cpym cpymrn cpymwn cpymn | |
6033 | cpye cpyern cpyewn cpyen | |
6034 | ||
6035 | cpyprt cpyprtrn cpyprtwn cpyprtn | |
6036 | cpymrt cpymrtrn cpymrtwn cpymrtn | |
6037 | cpyert cpyertrn cpyertwn cpyertn | |
6038 | ||
6039 | cpypwt cpypwtrn cpypwtwn cpypwtn | |
6040 | cpymwt cpymwtrn cpymwtwn cpymwtn | |
6041 | cpyewt cpyewtrn cpyewtwn cpyewtn | |
6042 | ||
6043 | cpypt cpyptrn cpyptwn cpyptn | |
6044 | cpymt cpymtrn cpymtwn cpymtn | |
6045 | cpyet cpyetrn cpyetwn cpyetn. */ | |
6046 | MOPS_CPY_INSN ("cpy", 0x1d000400, 0xffe0fc00), | |
6047 | ||
6048 | /* setp setpt setpn setptn | |
6049 | setm setmt setmn setmtn | |
6050 | sete setet seten setetn */ | |
6051 | MOPS_SET_INSN ("set", 0x19c00400, 0xffe0fc00, MOPS_INSN), | |
6052 | ||
6053 | /* setgp setgpt setgpn setgptn | |
6054 | setgm setgmt setgmn setgmtn | |
6055 | setge setget setgen setgetn */ | |
6056 | MOPS_SET_INSN ("setg", 0x1dc00400, 0xffe0fc00, MOPS_MEMTAG_INSN), | |
6057 | ||
bcca550b RS |
6058 | HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND), |
6059 | ||
1f7b42d5 AV |
6060 | /* CSSC with immediates. */ |
6061 | CSSC_INSN ("smax", 0x11c00000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF), | |
6062 | CSSC_INSN ("umax", 0x11c40000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF), | |
6063 | CSSC_INSN ("smin", 0x11c80000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF), | |
6064 | CSSC_INSN ("umin", 0x11cc0000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF), | |
6065 | ||
6066 | /* CSSC with registers only. */ | |
6067 | CSSC_INSN ("abs", 0x5ac02000, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
6068 | CSSC_INSN ("cnt", 0x5ac01c00, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
6069 | CSSC_INSN ("ctz", 0x5ac01800, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF), | |
6070 | CSSC_INSN ("smax", 0x1ac06000, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
6071 | CSSC_INSN ("umax", 0x1ac06400, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
6072 | CSSC_INSN ("smin", 0x1ac06800, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
6073 | CSSC_INSN ("umin", 0x1ac06c00, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), | |
6074 | ||
eae424ae | 6075 | {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, |
a06ea964 NC |
6076 | }; |
6077 | ||
6078 | #ifdef AARCH64_OPERANDS | |
6079 | #undef AARCH64_OPERANDS | |
6080 | #endif | |
6081 | ||
6082 | /* Macro-based operand decription; this will be fed into aarch64-gen for it | |
6083 | to generate the structure aarch64_operands and the function | |
6084 | aarch64_insert_operand and aarch64_extract_operand. | |
6085 | ||
6086 | These inserters and extracters in the description execute the conversion | |
6087 | between the aarch64_opnd_info and value in the operand-related instruction | |
6088 | field(s). */ | |
6089 | ||
6090 | /* Y expects arguments (left to right) to be operand class, inserter/extractor | |
6091 | name suffix, operand name, flags, related bitfield(s) and description. | |
6092 | X only differs from Y by having the operand inserter and extractor names | |
6093 | listed separately. */ | |
6094 | ||
6095 | #define AARCH64_OPERANDS \ | |
6096 | Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ | |
6097 | Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ | |
6098 | Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ | |
6099 | Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ | |
6100 | Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ | |
8edca81e | 6101 | Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \ |
bd7ceb8d SD |
6102 | Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \ |
6103 | "an integer or stack pointer register") \ | |
a06ea964 NC |
6104 | Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ |
6105 | Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ | |
6106 | X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ | |
6107 | "an integer register") \ | |
6108 | Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ | |
6109 | "an integer or stack pointer register") \ | |
6110 | Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ | |
6111 | "an integer or stack pointer register") \ | |
c84364ec SN |
6112 | Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \ |
6113 | "an integer or stack pointer register") \ | |
ee804238 JW |
6114 | X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ |
6115 | "the second reg of a pair") \ | |
a06ea964 NC |
6116 | Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ |
6117 | "an integer register with optional extension") \ | |
6118 | Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ | |
6119 | "an integer register with optional shift") \ | |
6120 | Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ | |
6121 | Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ | |
6122 | Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ | |
6123 | Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ | |
6124 | Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ | |
6125 | Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ | |
6126 | Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ | |
6127 | Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ | |
6128 | Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ | |
f42f1a1d | 6129 | Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \ |
a06ea964 NC |
6130 | Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ |
6131 | Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ | |
6132 | Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ | |
6133 | Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ | |
6134 | "the top half of a 128-bit FP/SIMD register") \ | |
6135 | Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ | |
6136 | "the top half of a 128-bit FP/SIMD register") \ | |
6137 | Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ | |
6138 | "a SIMD vector element") \ | |
6139 | Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ | |
6140 | "a SIMD vector element") \ | |
6141 | Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ | |
6142 | "a SIMD vector element") \ | |
369c9167 TC |
6143 | Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ |
6144 | "a SIMD vector element limited to V0-V15") \ | |
a06ea964 NC |
6145 | Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ |
6146 | "a SIMD vector register list") \ | |
6147 | Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ | |
6148 | "a SIMD vector register list") \ | |
6149 | Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ | |
6150 | "a SIMD vector register list") \ | |
6151 | Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ | |
6152 | "a SIMD vector element list") \ | |
a6a51754 | 6153 | Y(IMMEDIATE, imm, "CRn", 0, F(FLD_CRn), \ |
a06ea964 | 6154 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
a6a51754 | 6155 | Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \ |
a06ea964 | 6156 | "a 4-bit opcode field named for historical reasons C0 - C15") \ |
1d106042 | 6157 | Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4_11), \ |
a06ea964 | 6158 | "an immediate as the index of the least significant byte") \ |
1d106042 | 6159 | Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_0), \ |
f42f1a1d | 6160 | "an immediate as the index of the least significant byte") \ |
a06ea964 NC |
6161 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ |
6162 | "a left shift amount for an AdvSIMD register") \ | |
6163 | Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \ | |
6164 | "a right shift amount for an AdvSIMD register") \ | |
6165 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \ | |
6166 | "an immediate") \ | |
6167 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \ | |
6168 | "an 8-bit unsigned immediate with optional shift") \ | |
6169 | Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \ | |
6170 | "an 8-bit floating-point constant") \ | |
6171 | X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \ | |
6172 | "an immediate shift amount of 8, 16 or 32") \ | |
6173 | X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ | |
6174 | X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ | |
aa2aa4c6 | 6175 | Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD_imm8), \ |
a06ea964 NC |
6176 | "an 8-bit floating-point constant") \ |
6177 | Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ | |
6178 | "the right rotate amount") \ | |
1d106042 | 6179 | Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6_10), \ |
a06ea964 | 6180 | "the leftmost bit number to be moved from the source") \ |
1d106042 | 6181 | Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6_10), \ |
a06ea964 | 6182 | "the width of the bit-field") \ |
1d106042 RS |
6183 | Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6_10), "an immediate") \ |
6184 | Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_15), "an immediate") \ | |
a06ea964 NC |
6185 | Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ |
6186 | "a 3-bit unsigned immediate") \ | |
6187 | Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ | |
6188 | "a 3-bit unsigned immediate") \ | |
6189 | Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ | |
6190 | "a 4-bit unsigned immediate") \ | |
1d106042 | 6191 | Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_10), \ |
193614f2 | 6192 | "a 4-bit unsigned Logical Address Tag modifier") \ |
a06ea964 NC |
6193 | Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ |
6194 | "a 7-bit unsigned immediate") \ | |
193614f2 SD |
6195 | Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \ |
6196 | "a 10-bit unsigned multiple of 16") \ | |
a06ea964 NC |
6197 | Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ |
6198 | "the bit number to be tested") \ | |
1d106042 | 6199 | Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16_5), \ |
a06ea964 | 6200 | "a 16-bit unsigned immediate") \ |
1d106042 | 6201 | Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_0), \ |
09c1e68a | 6202 | "a 16-bit unsigned immediate") \ |
a06ea964 NC |
6203 | Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ |
6204 | "a 5-bit unsigned immediate") \ | |
e950b345 RS |
6205 | Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ |
6206 | "a 5-bit signed immediate") \ | |
a06ea964 NC |
6207 | Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ |
6208 | "a flag bit specifier giving an alternative value for each flag") \ | |
6209 | Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ | |
6210 | "Logical immediate") \ | |
6211 | Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ | |
6212 | "a 12-bit unsigned immediate with optional left shift of 12 bits")\ | |
1d106042 | 6213 | Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16_5), \ |
a06ea964 NC |
6214 | "a 16-bit immediate with optional left shift") \ |
6215 | Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ | |
6216 | "the number of bits after the binary point in the fixed-point value")\ | |
6217 | X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ | |
582e12bf | 6218 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \ |
c2c4ff8d | 6219 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
582e12bf | 6220 | Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \ |
c2c4ff8d | 6221 | "a 2-bit rotation specifier for complex arithmetic operations") \ |
582e12bf | 6222 | Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \ |
c2c4ff8d | 6223 | "a 1-bit rotation specifier for complex arithmetic operations") \ |
68a64283 YZ |
6224 | Y(COND, cond, "COND", 0, F(), "a condition") \ |
6225 | Y(COND, cond, "COND1", 0, F(), \ | |
6226 | "one of the standard conditions, excluding AL and NV.") \ | |
a06ea964 NC |
6227 | X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ |
6228 | "21-bit PC-relative address of a 4KB page") \ | |
6229 | Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
6230 | F(FLD_imm14), "14-bit PC-relative address") \ | |
6231 | Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
6232 | F(FLD_imm19), "19-bit PC-relative address") \ | |
6233 | Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ | |
6234 | "21-bit PC-relative address") \ | |
6235 | Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ | |
6236 | F(FLD_imm26), "26-bit PC-relative address") \ | |
6237 | Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ | |
6238 | "an address with base register (no offset)") \ | |
6239 | Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ | |
6240 | "an address with register offset") \ | |
6241 | Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ | |
6242 | "an address with 7-bit signed immediate offset") \ | |
6243 | Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ | |
6244 | "an address with 9-bit signed immediate offset") \ | |
6245 | Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ | |
6246 | "an address with 9-bit negative or unaligned immediate offset") \ | |
3f06e550 | 6247 | Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\ |
1820262b | 6248 | "an address with an optional 10-bit scaled, signed immediate offset") \ |
fb3265b3 SD |
6249 | Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\ |
6250 | "an address with 11-bit signed immediate (multiple of 16) offset")\ | |
a06ea964 NC |
6251 | Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ |
6252 | "an address with scaled, unsigned immediate offset") \ | |
fb3265b3 SD |
6253 | Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\ |
6254 | "an address with 13-bit signed immediate (multiple of 16) offset")\ | |
a06ea964 NC |
6255 | Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ |
6256 | "an address with base register (no offset)") \ | |
f42f1a1d TC |
6257 | Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\ |
6258 | "an address with an optional 8-bit signed immediate offset") \ | |
a06ea964 NC |
6259 | Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ |
6260 | "a post-indexed address with immediate or register increment") \ | |
6261 | Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \ | |
6262 | Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \ | |
6263 | "a PSTATE field name") \ | |
6264 | Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \ | |
6265 | "an address translation operation specifier") \ | |
6266 | Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \ | |
6267 | "a data cache maintenance operation specifier") \ | |
6268 | Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \ | |
9ed608f9 | 6269 | "an instruction cache maintenance operation specifier") \ |
a06ea964 NC |
6270 | Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ |
6271 | "a TBL invalidation operation specifier") \ | |
2ac435d4 SD |
6272 | Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ |
6273 | "a Speculation Restriction option name (RCTX)") \ | |
a06ea964 NC |
6274 | Y(SYSTEM, barrier, "BARRIER", 0, F(), \ |
6275 | "a barrier option name") \ | |
fd195909 PW |
6276 | Y(SYSTEM, barrier_dsb_nxs, "BARRIER_DSB_NXS", 0, F(), \ |
6277 | "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate") \ | |
a06ea964 NC |
6278 | Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ |
6279 | "the ISB option name SY or an optional 4-bit unsigned immediate") \ | |
6280 | Y(SYSTEM, prfop, "PRFOP", 0, F(), \ | |
1e6f4800 | 6281 | "a prefetch operation specifier") \ |
8ff42920 RS |
6282 | Y(SYSTEM, imm, "RPRFMOP", 0, \ |
6283 | F(FLD_imm1_15, FLD_imm2_12, FLD_imm3_0), \ | |
6284 | "a range prefetch operation specifier") \ | |
c2e5c986 SD |
6285 | Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \ |
6286 | "the PSB/TSB option name CSYNC") \ | |
ff605452 SD |
6287 | Y(SYSTEM, hint, "BTI", 0, F (), \ |
6288 | "BTI targets j/c/jc") \ | |
582e12bf RS |
6289 | Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ |
6290 | 4 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6291 | "an address with a 4-bit signed offset, multiplied by 16") \ | |
8382113f MM |
6292 | Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x32", \ |
6293 | 5 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6294 | "an address with a 4-bit signed offset, multiplied by 32") \ | |
98907a70 RS |
6295 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \ |
6296 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6297 | "an address with a 4-bit signed offset, multiplied by VL") \ | |
6298 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x2xVL", \ | |
6299 | 1 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6300 | "an address with a 4-bit signed offset, multiplied by 2*VL") \ | |
6301 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x3xVL", \ | |
6302 | 2 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6303 | "an address with a 4-bit signed offset, multiplied by 3*VL") \ | |
6304 | Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x4xVL", \ | |
6305 | 3 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6306 | "an address with a 4-bit signed offset, multiplied by 4*VL") \ | |
6307 | Y(ADDRESS, sve_addr_ri_s6xvl, "SVE_ADDR_RI_S6xVL", \ | |
6308 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6309 | "an address with a 6-bit signed offset, multiplied by VL") \ | |
6310 | Y(ADDRESS, sve_addr_ri_s9xvl, "SVE_ADDR_RI_S9xVL", \ | |
6311 | 0 << OPD_F_OD_LSB, F(FLD_Rn), \ | |
6312 | "an address with a 9-bit signed offset, multiplied by VL") \ | |
4df068de RS |
6313 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6", 0 << OPD_F_OD_LSB, \ |
6314 | F(FLD_Rn), "an address with a 6-bit unsigned offset") \ | |
6315 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB, \ | |
6316 | F(FLD_Rn), \ | |
6317 | "an address with a 6-bit unsigned offset, multiplied by 2") \ | |
6318 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB, \ | |
6319 | F(FLD_Rn), \ | |
6320 | "an address with a 6-bit unsigned offset, multiplied by 4") \ | |
6321 | Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \ | |
6322 | F(FLD_Rn), \ | |
6323 | "an address with a 6-bit unsigned offset, multiplied by 8") \ | |
c8d59609 NC |
6324 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_R", 0 << OPD_F_OD_LSB, \ |
6325 | F(FLD_Rn,FLD_Rm), "an address with an optional scalar register offset") \ | |
4df068de RS |
6326 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \ |
6327 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
6328 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \ | |
6329 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
6330 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB, \ | |
6331 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
6332 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \ | |
6333 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
01a4d082 PW |
6334 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB, \ |
6335 | F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ | |
4df068de RS |
6336 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \ |
6337 | (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
6338 | "an address with a scalar register offset") \ | |
6339 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL1", \ | |
6340 | (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
6341 | "an address with a scalar register offset") \ | |
6342 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL2", \ | |
6343 | (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
6344 | "an address with a scalar register offset") \ | |
6345 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ | |
6346 | (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ | |
6347 | "an address with a scalar register offset") \ | |
c469c864 MM |
6348 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \ |
6349 | 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \ | |
6350 | "vector of address with a scalar register offset") \ | |
4df068de RS |
6351 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \ |
6352 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
6353 | "an address with a vector register offset") \ | |
6354 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB, \ | |
6355 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
6356 | "an address with a vector register offset") \ | |
6357 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB, \ | |
6358 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
6359 | "an address with a vector register offset") \ | |
6360 | Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB, \ | |
6361 | F(FLD_Rn,FLD_SVE_Zm_16), \ | |
6362 | "an address with a vector register offset") \ | |
6363 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_14", \ | |
6364 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
6365 | "an address with a vector register offset") \ | |
6366 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_22", \ | |
6367 | 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
6368 | "an address with a vector register offset") \ | |
6369 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_14", \ | |
6370 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
6371 | "an address with a vector register offset") \ | |
6372 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_22", \ | |
6373 | 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
6374 | "an address with a vector register offset") \ | |
6375 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_14", \ | |
6376 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
6377 | "an address with a vector register offset") \ | |
6378 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_22", \ | |
6379 | 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
6380 | "an address with a vector register offset") \ | |
6381 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_14", \ | |
6382 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ | |
6383 | "an address with a vector register offset") \ | |
6384 | Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_22", \ | |
6385 | 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ | |
6386 | "an address with a vector register offset") \ | |
6387 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5", 0 << OPD_F_OD_LSB, \ | |
6388 | F(FLD_SVE_Zn), "an address with a 5-bit unsigned offset") \ | |
6389 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB, \ | |
6390 | F(FLD_SVE_Zn), \ | |
6391 | "an address with a 5-bit unsigned offset, multiplied by 2") \ | |
6392 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB, \ | |
6393 | F(FLD_SVE_Zn), \ | |
6394 | "an address with a 5-bit unsigned offset, multiplied by 4") \ | |
6395 | Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB, \ | |
6396 | F(FLD_SVE_Zn), \ | |
6397 | "an address with a 5-bit unsigned offset, multiplied by 8") \ | |
6398 | Y(ADDRESS, sve_addr_zz_lsl, "SVE_ADDR_ZZ_LSL", 0, \ | |
6399 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
6400 | "an address with a vector register offset") \ | |
6401 | Y(ADDRESS, sve_addr_zz_sxtw, "SVE_ADDR_ZZ_SXTW", 0, \ | |
6402 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
6403 | "an address with a vector register offset") \ | |
6404 | Y(ADDRESS, sve_addr_zz_uxtw, "SVE_ADDR_ZZ_UXTW", 0, \ | |
6405 | F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ | |
6406 | "an address with a vector register offset") \ | |
e950b345 RS |
6407 | Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD_SVE_imm9), \ |
6408 | "a 9-bit unsigned arithmetic operand") \ | |
6409 | Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD_SVE_imm9), \ | |
6410 | "a 9-bit signed arithmetic operand") \ | |
165d4950 RS |
6411 | Y(IMMEDIATE, fpimm, "SVE_FPIMM8", 0, F(FLD_SVE_imm8), \ |
6412 | "an 8-bit floating-point immediate") \ | |
6413 | Y(IMMEDIATE, sve_float_half_one, "SVE_I1_HALF_ONE", 0, \ | |
6414 | F(FLD_SVE_i1), "either 0.5 or 1.0") \ | |
6415 | Y(IMMEDIATE, sve_float_half_two, "SVE_I1_HALF_TWO", 0, \ | |
6416 | F(FLD_SVE_i1), "either 0.5 or 2.0") \ | |
6417 | Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \ | |
6418 | F(FLD_SVE_i1), "either 0.0 or 1.0") \ | |
582e12bf RS |
6419 | Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \ |
6420 | "a 1-bit rotation specifier for complex arithmetic operations") \ | |
6421 | Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \ | |
6422 | "a 2-bit rotation specifier for complex arithmetic operations") \ | |
adccc507 MM |
6423 | Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \ |
6424 | "a 1-bit rotation specifier for complex arithmetic operations") \ | |
e950b345 RS |
6425 | Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \ |
6426 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
6427 | "an inverted 13-bit logical immediate") \ | |
6428 | Y(IMMEDIATE, limm, "SVE_LIMM", 0, \ | |
6429 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
6430 | "a 13-bit logical immediate") \ | |
6431 | Y(IMMEDIATE, sve_limm_mov, "SVE_LIMM_MOV", 0, \ | |
6432 | F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ | |
6433 | "a 13-bit logical move immediate") \ | |
245d2e3f RS |
6434 | Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD_SVE_pattern), \ |
6435 | "an enumeration value such as POW2") \ | |
2442d846 RS |
6436 | Y(IMMEDIATE, sve_scale, "SVE_PATTERN_SCALED", 0, \ |
6437 | F(FLD_SVE_pattern), "an enumeration value such as POW2") \ | |
245d2e3f RS |
6438 | Y(IMMEDIATE, imm, "SVE_PRFOP", 0, F(FLD_SVE_prfop), \ |
6439 | "an enumeration value such as PLDL1KEEP") \ | |
f11ad6bc RS |
6440 | Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \ |
6441 | "an SVE predicate register") \ | |
503fae12 RS |
6442 | Y(PRED_REG, regno, "SVE_PNd", 0, F(FLD_SVE_Pd), \ |
6443 | "an SVE predicate-as-counter register") \ | |
f11ad6bc RS |
6444 | Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \ |
6445 | "an SVE predicate register") \ | |
6446 | Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \ | |
6447 | "an SVE predicate register") \ | |
6448 | Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \ | |
6449 | "an SVE predicate register") \ | |
503fae12 RS |
6450 | Y(PRED_REG, regno, "SVE_PNg4_10", 0, F(FLD_SVE_Pg4_10), \ |
6451 | "an SVE predicate-as-counter register") \ | |
f11ad6bc RS |
6452 | Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \ |
6453 | "an SVE predicate register") \ | |
6454 | Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \ | |
6455 | "an SVE predicate register") \ | |
6456 | Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \ | |
6457 | "an SVE predicate register") \ | |
503fae12 RS |
6458 | Y(PRED_REG, regno, "SVE_PNn", 0, F(FLD_SVE_Pn), \ |
6459 | "an SVE predicate register") \ | |
f11ad6bc RS |
6460 | Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ |
6461 | "an SVE predicate register") \ | |
503fae12 RS |
6462 | Y(PRED_REG, regno, "SVE_PNt", 0, F(FLD_SVE_Pt), \ |
6463 | "an SVE predicate register") \ | |
047cd301 RS |
6464 | Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \ |
6465 | "an integer register or zero") \ | |
6466 | Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \ | |
6467 | "an integer register or SP") \ | |
e950b345 RS |
6468 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ |
6469 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ | |
6470 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ | |
6471 | F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ | |
28ed815a MM |
6472 | Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0, \ |
6473 | F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ | |
6474 | "a shift-left immediate operand") \ | |
3c17238b | 6475 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \ |
e950b345 | 6476 | F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ |
3c17238b | 6477 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \ |
e950b345 | 6478 | F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ |
3c17238b MM |
6479 | Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB, \ |
6480 | F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ | |
6481 | "a shift-right immediate operand") \ | |
e950b345 RS |
6482 | Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ |
6483 | "a 5-bit signed immediate") \ | |
6484 | Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ | |
6485 | "a 5-bit signed immediate") \ | |
6486 | Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD_SVE_imms), \ | |
6487 | "a 6-bit signed immediate") \ | |
6488 | Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD_SVE_imm8), \ | |
6489 | "an 8-bit signed immediate") \ | |
6490 | Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD_SVE_imm3), \ | |
6491 | "a 3-bit unsigned immediate") \ | |
6492 | Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD_SVE_imm7), \ | |
6493 | "a 7-bit unsigned immediate") \ | |
6494 | Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ | |
6495 | "an 8-bit unsigned immediate") \ | |
abd542a2 | 6496 | Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \ |
e950b345 | 6497 | "an 8-bit unsigned immediate") \ |
047cd301 RS |
6498 | Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ |
6499 | Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ | |
6500 | Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \ | |
6501 | Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \ | |
f11ad6bc RS |
6502 | Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ |
6503 | "an SVE vector register") \ | |
6504 | Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ | |
6505 | "an SVE vector register") \ | |
6506 | Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD_SVE_Zd), \ | |
6507 | "an SVE vector register") \ | |
6508 | Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD_SVE_Zm_5), \ | |
6509 | "an SVE vector register") \ | |
6510 | Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ | |
6511 | "an SVE vector register") \ | |
582e12bf RS |
6512 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ |
6513 | 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
6514 | "an indexed SVE vector register") \ | |
116adc27 MM |
6515 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \ |
6516 | 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \ | |
6517 | "an indexed SVE vector register") \ | |
dfc12f9f RS |
6518 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \ |
6519 | 3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \ | |
6520 | "an indexed SVE vector register") \ | |
6521 | Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ | |
6522 | 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ | |
6523 | "an indexed SVE vector register") \ | |
31e36ab3 MM |
6524 | Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ |
6525 | 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ | |
6526 | "an indexed SVE vector register") \ | |
582e12bf RS |
6527 | Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ |
6528 | 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ | |
6529 | "an indexed SVE vector register") \ | |
f11ad6bc RS |
6530 | Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ |
6531 | "an SVE vector register") \ | |
6532 | Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ | |
6533 | "an indexed SVE vector register") \ | |
db3c06bf | 6534 | Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ |
f11ad6bc RS |
6535 | "a list of SVE vector registers") \ |
6536 | Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ | |
6537 | "an SVE vector register") \ | |
db3c06bf | 6538 | Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ |
f42f1a1d | 6539 | "a list of SVE vector registers") \ |
d8773a8a RS |
6540 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB, \ |
6541 | F(FLD_SME_Zdn2), "a list of SVE vector registers") \ | |
6542 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ | |
6543 | F(FLD_SME_Zdn4), "a list of SVE vector registers") \ | |
e87ff672 RS |
6544 | Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \ |
6545 | "an SVE vector register") \ | |
99e01a66 RS |
6546 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \ |
6547 | F(FLD_SME_Zm2), "a list of SVE vector registers") \ | |
6548 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \ | |
6549 | F(FLD_SME_Zm4), "a list of SVE vector registers") \ | |
d8773a8a RS |
6550 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \ |
6551 | F(FLD_SME_Zn2), "a list of SVE vector registers") \ | |
6552 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \ | |
6553 | F(FLD_SME_Zn4), "a list of SVE vector registers") \ | |
b408ebbf RS |
6554 | Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \ |
6555 | 2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \ | |
6556 | "a list of SVE vector registers") \ | |
6557 | Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \ | |
6558 | 4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \ | |
6559 | "a list of SVE vector registers") \ | |
971eda73 | 6560 | Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ |
ff60bcbf | 6561 | "an SME ZA tile ZA0-ZA3") \ |
971eda73 | 6562 | Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ |
ff60bcbf RS |
6563 | "an SME ZA tile ZA0-ZA7") \ |
6564 | Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ | |
1d106042 | 6565 | F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ |
ff60bcbf | 6566 | "an SME horizontal or vertical vector access register") \ |
d8773a8a RS |
6567 | Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_srcxN", 0, \ |
6568 | F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_5), \ | |
6569 | "an SME horizontal or vertical vector access register") \ | |
ff60bcbf | 6570 | Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ |
1d106042 | 6571 | F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ |
ff60bcbf | 6572 | "an SME horizontal or vertical vector access register") \ |
d8773a8a RS |
6573 | Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \ |
6574 | F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \ | |
6575 | "an SME horizontal or vertical vector access register") \ | |
99e01a66 RS |
6576 | Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \ |
6577 | F(FLD_SME_Pdx2), "a list of SVE predicate registers") \ | |
6578 | Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd), \ | |
6579 | "a list of SVE predicate registers") \ | |
971eda73 PW |
6580 | Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ |
6581 | "an SVE predicate register") \ | |
99e01a66 RS |
6582 | Y(PRED_REG, regno, "SME_PNd3", 8 << OPD_F_OD_LSB, F(FLD_SME_PNd3), \ |
6583 | "an SVE predicate-as-counter register") \ | |
b408ebbf RS |
6584 | Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \ |
6585 | "an SVE predicate-as-counter register") \ | |
99e01a66 RS |
6586 | Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \ |
6587 | "an SVE predicate-as-counter register") \ | |
6588 | Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB, \ | |
6589 | F(FLD_SME_PNn3, FLD_imm1_8), \ | |
6590 | "an indexed SVE predicate-as-counter register") \ | |
6591 | Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB, \ | |
6592 | F(FLD_SME_PNn3, FLD_imm2_8), \ | |
6593 | "an indexed SVE predicate-as-counter register") \ | |
ff60bcbf RS |
6594 | Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ |
6595 | F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ | |
6596 | Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ | |
1d106042 | 6597 | F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ |
ff60bcbf | 6598 | "an SME horizontal or vertical vector access register") \ |
a8cb21aa RS |
6599 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off1x4", \ |
6600 | 4 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm1_0), "ZA array") \ | |
ed429b33 RS |
6601 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off2x2", \ |
6602 | 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm2_0), "ZA array") \ | |
a8cb21aa RS |
6603 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off2x4", \ |
6604 | 4 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm2_0), "ZA array") \ | |
d8773a8a RS |
6605 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \ |
6606 | F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ | |
6607 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \ | |
6608 | F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \ | |
ed429b33 RS |
6609 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3x2", \ |
6610 | 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ | |
90cd80f8 | 6611 | Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \ |
1d106042 | 6612 | F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ |
01a4d082 | 6613 | Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ |
1d106042 | 6614 | F(FLD_Rn,FLD_imm4_0), "memory offset") \ |
ff60bcbf RS |
6615 | Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ |
6616 | F(FLD_CRm), "streaming mode") \ | |
6617 | Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ | |
d3de0860 PW |
6618 | F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ |
6619 | "Source scalable predicate register with index ") \ | |
6efa6601 RS |
6620 | Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \ |
6621 | "a shift-right immediate operand") \ | |
6622 | Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \ | |
6623 | F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \ | |
80752eb0 RS |
6624 | Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \ |
6625 | F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \ | |
6626 | Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ | |
6627 | F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \ | |
a8cb21aa RS |
6628 | Y(SVE_REG, simple_index, "SME_Zm_INDEX3_1", 0, \ |
6629 | F(FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1), \ | |
6630 | "an indexed SVE vector register") \ | |
ed429b33 RS |
6631 | Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \ |
6632 | F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2), \ | |
6633 | "an indexed SVE vector register") \ | |
6634 | Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \ | |
6635 | F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10), \ | |
6636 | "an indexed SVE vector register") \ | |
a8cb21aa RS |
6637 | Y(SVE_REG, simple_index, "SME_Zm_INDEX4_1", 0, \ |
6638 | F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1), \ | |
6639 | "an indexed SVE vector register") \ | |
6640 | Y(SVE_REG, simple_index, "SME_Zm_INDEX4_10", 0, \ | |
6641 | F(FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10), \ | |
6642 | "an indexed SVE vector register") \ | |
cbd11b88 RS |
6643 | Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ |
6644 | F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ | |
6645 | Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ | |
6646 | F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \ | |
6647 | Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ | |
6648 | F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \ | |
6649 | Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ | |
6650 | F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \ | |
6651 | Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ | |
6652 | F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \ | |
6653 | Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ | |
6654 | F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \ | |
99e01a66 RS |
6655 | Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ |
6656 | "VLx2 or VLx4") \ | |
6657 | Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ | |
6658 | "VLx2 or VLx4") \ | |
cbd11b88 RS |
6659 | Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \ |
6660 | Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \ | |
6661 | F (FLD_imm3_12), "a ZT0 index") \ | |
6662 | Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \ | |
1d106042 | 6663 | Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ |
b83b4b13 | 6664 | "a 16-bit unsigned immediate for TME tcancel") \ |
f42f1a1d | 6665 | Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ |
6327658e RS |
6666 | "an indexed SM3 vector immediate") \ |
6667 | /* These next two are really register fields; the [...] notation \ | |
6668 | is just syntactic sugar. */ \ | |
6669 | Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd), \ | |
6670 | "a register destination address with writeback") \ | |
6671 | Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \ | |
6672 | "a register source address with writeback") \ | |
6673 | Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn), \ | |
1f7b42d5 AV |
6674 | "an integer register with writeback") \ |
6675 | Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ | |
6676 | "an 8-bit signed immediate") \ | |
6677 | Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ | |
6678 | "an 8-bit unsigned immediate") |