2022-01-02 |
Alan Modra | Update year range in copyright notice of binutils files |
tree | commitdiff |
2021-12-24 |
Vineet Gupta | RISC-V: Hypervisor ext: support Privileged Spec 1.12 |
tree | commitdiff |
2021-12-24 |
Vineet Gupta | RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1... |
tree | commitdiff |
2021-12-16 |
Richard Sandiford | arm: Add support for Armv9.1-A to Armv9.3-A |
tree | commitdiff |
2021-12-16 |
Richard Sandiford | arm: Add support for Armv8.7-A and Armv8.8-A |
tree | commitdiff |
2021-12-16 |
Richard Sandiford | aarch64: Add support for Armv9.1-A to Armv9.3-A |
tree | commitdiff |
2021-12-16 |
Nelson Chu | RISC-V: Support svinval extension with frozen version... |
tree | commitdiff |
2021-12-02 |
Richard Sandiford | aarch64: Add BC instruction |
tree | commitdiff |
2021-12-02 |
Richard Sandiford | aarch64: Enforce P/M/E order for MOPS instructions |
tree | commitdiff |
2021-12-02 |
Richard Sandiford | aarch64: Add support for +mops |
tree | commitdiff |
2021-12-02 |
Richard Sandiford | aarch64: Add support for Armv8.8-A |
tree | commitdiff |
2021-12-02 |
Richard Sandiford | aarch64: Tweak insn sequence code |
tree | commitdiff |
2021-11-30 |
Nelson Chu | RISC-V: The vtype immediate with more than the defined... |
tree | commitdiff |
2021-11-18 |
jiawei | RISC-V: Add instructions and operand set for z[fdq]inx |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] SVE2 instructions added to support SME |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add SME mode selection and state access... |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add ZERO instruction |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add MOV and MOVA instructions |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add SME instructions |
tree | commitdiff |
2021-11-17 |
Przemyslaw Wirkus | aarch64: [SME] Add +sme option to -march |
tree | commitdiff |
2021-11-17 |
Nelson Chu | RISC-V: Support rvv extension with released version... |
tree | commitdiff |
2021-11-16 |
jiawei | RISC-V: Scalar crypto instructions and operand set. |
tree | commitdiff |
2021-11-01 |
Przemyslaw Wirkus | arm: add armv9-a architecture to -march |
tree | commitdiff |
2021-10-24 |
liuzhensong | LoongArch opcodes support |
tree | commitdiff |
2021-10-07 |
Philipp Tomsich | RISC-V: Add support for Zbs instructions |
tree | commitdiff |
2021-09-30 |
Przemyslaw Wirkus | aarch64: add armv9-a architecture to -march |
tree | commitdiff |
2021-08-30 |
Nelson Chu | RISC-V: PR27916, Support mapping symbols. |
tree | commitdiff |
2021-07-26 |
Andrea Corallo | PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti... |
tree | commitdiff |
2021-07-26 |
Andrea Corallo | PATCH [5/10] arm: Extend again arm_feature_set struct... |
tree | commitdiff |
2021-07-01 |
Mike Frysinger | opcodes: constify aarch64_opcode_tables |
tree | commitdiff |
2021-07-01 |
Richard Earnshaw | arm: don't treat XScale features as part of the FPU... |
tree | commitdiff |
2021-05-29 |
Maciej W. Rozycki | MIPS/opcodes: Properly handle ISA exclusion |
tree | commitdiff |
2021-05-29 |
Maciej W. Rozycki | MIPS/opcodes: Factor out ISA matching against flags |
tree | commitdiff |
2021-05-29 |
Maciej W. Rozycki | MIPS/opcodes: Do not use CP0 register names for control... |
tree | commitdiff |
2021-05-29 |
Maciej W. Rozycki | MIPS/opcodes: Free up redundant `g' operand code |
tree | commitdiff |
2021-04-01 |
Martin Liska | Remove strneq macro and use startswith. |
tree | commitdiff |
2021-03-31 |
Alan Modra | Use bool in include |
tree | commitdiff |
2021-03-31 |
Alan Modra | Remove bfd_stdint.h |
tree | commitdiff |
2021-03-29 |
Alan Modra | TRUE/FALSE simplification |
tree | commitdiff |
2021-03-29 |
Alan Modra | opcodes int vs bfd_boolean fixes |
tree | commitdiff |
2021-03-16 |
Kuan-Lin Chen | RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions |
tree | commitdiff |
2021-02-19 |
Nelson Chu | RISC-V: PR27158, fixed UJ/SB types and added CSS/CL... |
tree | commitdiff |
2021-02-18 |
Nelson Chu | RISC-V: Add bfd/cpu-riscv.h to support all spec version... |
tree | commitdiff |
2021-02-15 |
Andreas Krebbel | IBM Z: Implement instruction set extensions |
tree | commitdiff |
2021-02-08 |
Mike Frysinger | opcodes: tic54x: namespace exported variables |
tree | commitdiff |
2021-02-05 |
Nelson Chu | RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM. |
tree | commitdiff |
2021-02-05 |
Nelson Chu | RISC-V: PR27348, Remove obsolete Xcustom support. |
tree | commitdiff |
2021-02-04 |
Nelson Chu | RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct... |
tree | commitdiff |
2021-01-15 |
Nelson Chu | RISC-V: Indent and GNU coding standards tidy, also... |
tree | commitdiff |
2021-01-15 |
Nelson Chu | RISC-V: Comments tidy and improvement. |
tree | commitdiff |
2021-01-11 |
Kyrylo Tkachov | aarch64: Remove support for CSRE |
tree | commitdiff |
2021-01-07 |
Philipp Tomsich | RISC-V: Add pause hint instruction. |
tree | commitdiff |
2021-01-07 |
Claire Xenia Wolf | RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr... |
tree | commitdiff |
2021-01-01 |
Alan Modra | PR27116, Spelling errors found by Debian style checker |
tree | commitdiff |
2021-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
tree | commitdiff |
2020-12-18 |
Alan Modra | Constify more arrays |
tree | commitdiff |
2020-12-10 |
Nelson Chu | RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. |
tree | commitdiff |
2020-12-10 |
Nelson Chu | RISC-V: Control fence.i and csr instructions by zifence... |
tree | commitdiff |
2020-12-01 |
Nelson Chu | RISC-V: Support to add implicit extensions for G. |
tree | commitdiff |
2020-12-01 |
Nelson Chu | RISC-V: Improve the version parsing for arch string. |
tree | commitdiff |
2020-11-16 |
Przemyslaw Wirkus | aarch64: Extract Condition flag manipulation feature... |
tree | commitdiff |
2020-11-09 |
Spencer E. Olson | Add support for the LMBD (left-most bit detect) instruc... |
tree | commitdiff |
2020-11-09 |
Przemyslaw Wirkus | aarch64: Limit Rt register number for LS64 load/store... |
tree | commitdiff |
2020-11-06 |
Przemyslaw Wirkus | aarch64: Extract Pointer Authentication feature from... |
tree | commitdiff |
2020-11-04 |
Przemyslaw Wirkus | aarch64: Update feature RAS system registers |
tree | commitdiff |
2020-11-03 |
Przemyslaw Wirkus | [PATCH][GAS] aarch64: Add atomic 64-byte load/store... |
tree | commitdiff |
2020-10-28 |
Przemyslaw Wirkus | aarch64: Add CSR PDEC instruction |
tree | commitdiff |
2020-10-28 |
Przemyslaw Wirkus | aarch64: Add DSB instruction Armv8.7-a variant |
tree | commitdiff |
2020-10-28 |
Przemyslaw Wirkus | aarch64: Add basic support for armv8.7-a architecture |
tree | commitdiff |
2020-10-26 |
Cooper Qu | CSKY: Add version flag in eflag and fix bug in disassem... |
tree | commitdiff |
2020-09-11 |
Cooper Qu | CSKY: Change ISA flag's type to bfd_uint64_t and fix... |
tree | commitdiff |
2020-09-10 |
Nick Clifton | Fix compile time warnings when building for the CSKY... |
tree | commitdiff |
2020-09-09 |
Cooper Qu | CSKY: Change mvtc and mulsw's ISA flag. |
tree | commitdiff |
2020-09-09 |
Cooper Qu | CSKY: Add FPUV3 instructions, which supported by ck860f. |
tree | commitdiff |
2020-09-08 |
Alex Coplan | aarch64: Add support for Armv8-R system registers |
tree | commitdiff |
2020-09-08 |
Alex Coplan | aarch64: Add base support for Armv8-R |
tree | commitdiff |
2020-09-02 |
Alan Modra | ubsan: v850-opc.c:412 left shift cannot be represented |
tree | commitdiff |
2020-09-02 |
Cooper Qu | CSKY: Add CPU CK803r3. |
tree | commitdiff |
2020-08-31 |
Alan Modra | PR26493 UBSAN: elfnn-riscv.c left shift of negative... |
tree | commitdiff |
2020-08-28 |
Cooper Qu | CSKY: Support attribute section. |
tree | commitdiff |
2020-08-24 |
Cooper Qu | CSKY: Add new arch CK860. |
tree | commitdiff |
2020-08-24 |
Cooper Qu | CSKY: Add ck803r2 series cpu. |
tree | commitdiff |
2020-08-10 |
Alex Coplan | aarch64: Don't assert on long sysreg names |
tree | commitdiff |
2020-08-10 |
Przemyslaw Wirkus | [aarch64] GAS doesn't validate the architecture version... |
tree | commitdiff |
2020-06-30 |
Nelson Chu | RISC-V: Support debug and float CSR as the unprivileged... |
tree | commitdiff |
2020-06-30 |
Nelson Chu | RISC-V: Cleanup the include/opcode/riscv-opc.h. |
tree | commitdiff |
2020-06-22 |
Alex Coplan | aarch64: Normalize and sort feature bit macros |
tree | commitdiff |
2020-06-22 |
Nelson Chu | RISC-V: Report warning when linking the objects with... |
tree | commitdiff |
2020-06-12 |
Nelson Chu | RISC-V: Drop the privileged spec v1.9 support. |
tree | commitdiff |
2020-06-11 |
Alex Coplan | [PATCH]: aarch64: Refactor representation of system... |
tree | commitdiff |
2020-06-04 |
Jose E. Marchesi | opcodes: discriminate endianness and insn-endianness... |
tree | commitdiff |
2020-06-04 |
Jose E. Marchesi | opcodes: support insn endianness in cgen_cpu_open |
tree | commitdiff |
2020-06-03 |
Nelson Chu | RISC-V: Fix the error when building RISC-V linux native... |
tree | commitdiff |
2020-05-28 |
Alan Modra | PR26044, Some targets can't be compiled with GCC 10... |
tree | commitdiff |
2020-05-20 |
Nelson Chu | [PATCH v2 0/9] RISC-V: Support version controling for... |
tree | commitdiff |
2020-05-19 |
Alexander Fedotov | Fix the ARM assembler to generate a Realtime profile... |
tree | commitdiff |
2020-05-11 |
Alan Modra | Power10 Reduced precision outer product operations |
tree | commitdiff |
2020-05-11 |
Alan Modra | PowerPC Rename powerxx to power10 |
tree | commitdiff |
2020-04-30 |
Alex Coplan | AArch64: add GAS support for UDF instruction |
tree | commitdiff |
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