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[thirdparty/binutils-gdb.git] / opcodes / riscv-dis.c

2025-05-09	Chao-ying Fu	RISC-V: Added vendor extensions, xmipscbop, xmipscmov...	blob \| commitdiff \| raw
2025-04-15	Marek Pikuła	RISC-V: Add missing disassembler option `max`	blob \| commitdiff \| raw \| diff to current
2025-03-28	Marek Pikuła	RISC-V: Don't show support for 1.9.1 priv spec	blob \| commitdiff \| raw \| diff to current
2025-03-18	Nelson Chu	RISC-V: Avoid parsing arch string repeatedly for dis...	blob \| commitdiff \| raw \| diff to current
2025-03-03	Andrew Oates	RISC-V: Re-define mapping symbol $x to the file elf...	blob \| commitdiff \| raw \| diff to current
2025-02-26	Charlie Jenkins	RISC-V: Fix abort when displaying data and partial...	blob \| commitdiff \| raw \| diff to current
2025-02-15	Alan Modra	riscv disassembler leak	blob \| commitdiff \| raw \| diff to current
2025-02-11	Nelson Chu	RISC-V: Move all global static target stuff into privat...	blob \| commitdiff \| raw \| diff to current
2025-01-09	Charlie Jenkins	RISC-V: Fix display of partial instructions	blob \| commitdiff \| raw \| diff to current
2025-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2024-11-24	Tom de Vries	opcodes: fix Werror=format build breaker in opcodes...	blob \| commitdiff \| raw \| diff to current
2024-11-20	Jiawei	RISC-V: Add Zcmt instructions and csr.	blob \| commitdiff \| raw \| diff to current
2024-10-31	Nelson Chu	RISC-V: Dump instruction without checking architecture...	blob \| commitdiff \| raw \| diff to current
2024-09-27	Jan Beulich	RISC-V: correct alignment directive handling for text...	blob \| commitdiff \| raw \| diff to current
2024-09-03	Mary Bennett	RISC-V: Add support for XCVsimd extension in CV32E40P	blob \| commitdiff \| raw \| diff to current
2024-08-27	Jiawei	RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01...	blob \| commitdiff \| raw \| diff to current
2024-08-06	Mary Bennett	RISC-V: Add support for XCvBitmanip extension in CV32E40P	blob \| commitdiff \| raw \| diff to current
2024-06-06	Andrew Burgess	opcodes/riscv: prevent future use of disassemble_info...	blob \| commitdiff \| raw \| diff to current
2024-06-06	Andrew Burgess	opcodes/riscv: add styling support to print_reg_list	blob \| commitdiff \| raw \| diff to current
2024-06-05	Mary Bennett	RISC-V: Add support for XCVbi extension in CV32E40P	blob \| commitdiff \| raw \| diff to current
2024-05-14	Joseph Faulls	RISC-V: Search for mapping symbols from the last one...	blob \| commitdiff \| raw \| diff to current
2024-04-09	Jiawei	RISC-V: Support Zcmp push/pop instructions.	blob \| commitdiff \| raw \| diff to current
2024-01-05	Jin Ma	RISC-V: T-HEAD: Fix wrong instruction encoding for...	blob \| commitdiff \| raw \| diff to current
2024-01-04	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2023-12-01	Patrick O'Neill	RISC-V: Make riscv_is_mapping_symbol stricter	blob \| commitdiff \| raw \| diff to current
2023-12-01	Nelson Chu	RISC-V: Add SiFive custom vector coprocessor interface...	blob \| commitdiff \| raw \| diff to current
2023-11-30	Patrick O'Neill	RISC-V: Avoid updating state until symbol is found	blob \| commitdiff \| raw \| diff to current
2023-11-24	Jan Beulich	RISC-V: disallow x0 with certain macro-insns	blob \| commitdiff \| raw \| diff to current
2023-11-23	Jin Ma	RISC-V: Add CSRs for T-Head VECTOR vendor extension	blob \| commitdiff \| raw \| diff to current
2023-11-07	Mary Bennett	RISC-V: Add support for XCValu extension in CV32E40P	blob \| commitdiff \| raw \| diff to current
2023-11-07	Mary Bennett	RISC-V: Add support for XCVmac extension in CV32E40P	blob \| commitdiff \| raw \| diff to current
2023-10-13	Joseph Faulls	RISC-V: Add support for numbered ISA mapping strings	blob \| commitdiff \| raw \| diff to current
2023-09-07	Nelson Chu	RISC-V: Clarify the naming rules of vendor operands.	blob \| commitdiff \| raw \| diff to current
2023-08-15	Jan Beulich	RISC-V: remove indirection from register tables	blob \| commitdiff \| raw \| diff to current
2023-08-02	Sam James	Revert "2.41 Release sources"	blob \| commitdiff \| raw \| diff to current
2023-08-02	Nick Clifton	2.41 Release sources binutils-2_41-release	blob \| commitdiff \| raw \| diff to current
2023-07-28	Tsukasa OI	Fix typo in riscv-dis.c comment	blob \| commitdiff \| raw \| diff to current
2023-07-18	Jiawei	RISC-V: Supports Zcb extension.	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvbb ISA extension	blob \| commitdiff \| raw \| diff to current
2023-06-30	Christoph Müllner	RISC-V: Add support for the Zfa extension	blob \| commitdiff \| raw \| diff to current
2023-05-19	Nelson Chu	RISC-V: Minor improvements for dis-assembler.	blob \| commitdiff \| raw \| diff to current
2023-04-18	Kito Cheng	RISC-V: Cache the latest mapping symbol and its boundary.	blob \| commitdiff \| raw \| diff to current
2023-03-31	Tsukasa OI	RISC-V: Allocate "various" operand type	blob \| commitdiff \| raw \| diff to current
2023-03-21	Jiawei	RISC-V: Fix disassemble fetch fail return value.	blob \| commitdiff \| raw \| diff to current
2023-02-03	Jan Beulich	RISC-V: don't disassemble unrecognized insns as .byte	blob \| commitdiff \| raw \| diff to current
2023-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2022-11-28	Tsukasa OI	RISC-V: Better support for long instructions (disassembler)	blob \| commitdiff \| raw \| diff to current
2022-10-28	Nelson Chu	RISC-V: Output mapping symbols with ISA string.	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	opcodes/riscv-dis.c: Remove last_map_state	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	opcodes/riscv-dis.c: Make XLEN variable static	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	opcodes/riscv-dis.c: Use bool type whenever possible	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	opcodes/riscv-dis.c: Tidying with spacing	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	opcodes/riscv-dis.c: Tidying with comments/clarity	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Print XTheadMemPair literal as "immediate"	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Fix T-Head immediate types on printing	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Print comma and tabs as the "text" style	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Optimize riscv_disassemble_data printf	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Fix printf argument types corresponding %x	blob \| commitdiff \| raw \| diff to current
2022-10-06	Tsukasa OI	RISC-V: Fix immediates to have "immediate" style	blob \| commitdiff \| raw \| diff to current
2022-10-04	Tsukasa OI	RISC-V: Fix buffer overflow on print_insn_riscv	blob \| commitdiff \| raw \| diff to current
2022-10-04	Andrew Burgess	opcodes/riscv: style csr names as registers	blob \| commitdiff \| raw \| diff to current
2022-09-30	Jan Beulich	RISC-V: fix build after "Add support for arbitrary...	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add support for literal instruction arguments	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add support for arbitrary immediate encoding...	blob \| commitdiff \| raw \| diff to current
2022-09-22	Tsukasa OI	RISC-V: Remove "b" operand type from disassembler	blob \| commitdiff \| raw \| diff to current
2022-09-06	Tsukasa OI	opcodes: Add non-enum disassembler options	blob \| commitdiff \| raw \| diff to current
2022-09-02	Tsukasa OI	RISC-V: Print highest address (-1) on the disassembler	blob \| commitdiff \| raw \| diff to current
2022-09-02	Tsukasa OI	RISC-V: PR29342, Fix RV32 disassembler address computation	blob \| commitdiff \| raw \| diff to current
2022-07-07	Tsukasa OI	RISC-V: Fix disassembling Zfinx with -M numeric	blob \| commitdiff \| raw \| diff to current
2022-04-30	Thomas Hebb	opcodes: don't assume ELF in riscv, csky, rl78, mep...	blob \| commitdiff \| raw \| diff to current
2022-04-04	Andrew Burgess	opcodes/riscv: implement style support in the disassembler	blob \| commitdiff \| raw \| diff to current
2022-03-18	Tsukasa OI	RISC-V: Prefetch hint instructions and operand set	blob \| commitdiff \| raw \| diff to current
2022-01-02	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2021-11-30	Nelson Chu	RISC-V: The vtype immediate with more than the defined...	blob \| commitdiff \| raw \| diff to current
2021-11-30	Nelson Chu	RISC-V: Dump vset[i]vli immediate as numbers once vsew...	blob \| commitdiff \| raw \| diff to current
2021-11-26	Andrew Burgess	opcodes/riscv: add disassembler options support to...	blob \| commitdiff \| raw \| diff to current
2021-11-18	jiawei	RISC-V: Add instructions and operand set for z[fdq]inx	blob \| commitdiff \| raw \| diff to current
2021-11-17	Nelson Chu	RISC-V: Support rvv extension with released version...	blob \| commitdiff \| raw \| diff to current
2021-11-16	jiawei	RISC-V: Scalar crypto instructions and operand set.	blob \| commitdiff \| raw \| diff to current
2021-11-11	Nelson Chu	RISC-V: Dump objects according to the elf architecture...	blob \| commitdiff \| raw \| diff to current
2021-10-27	Nelson Chu	RISC-V: Tidy riscv assembler and disassembler.	blob \| commitdiff \| raw \| diff to current
2021-09-20	Andrew Burgess	riscv: print .2byte or .4byte before an unknown instruc...	blob \| commitdiff \| raw \| diff to current
2021-09-09	Jim Wilson	RISC-V: Pretty print values formed with lui and addiw.	blob \| commitdiff \| raw \| diff to current
2021-08-30	Nelson Chu	RISC-V: PR28291, Fix the gdb fails that PR27916 caused.	blob \| commitdiff \| raw \| diff to current
2021-08-30	Nelson Chu	RISC-V: PR27916, Support mapping symbols.	blob \| commitdiff \| raw \| diff to current
2021-05-18	Job Noorman	RISC-V: PR27814, Objdump crashes when disassembling...	blob \| commitdiff \| raw \| diff to current
2021-03-31	Alan Modra	Use bool in opcodes	blob \| commitdiff \| raw \| diff to current
2021-03-31	Alan Modra	Remove bfd_stdint.h	blob \| commitdiff \| raw \| diff to current
2021-02-19	Nelson Chu	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL...	blob \| commitdiff \| raw \| diff to current
2021-02-18	Nelson Chu	RISC-V: Add bfd/cpu-riscv.h to support all spec version...	blob \| commitdiff \| raw \| diff to current
2021-01-15	Nelson Chu	RISC-V: Error and warning messages tidy.	blob \| commitdiff \| raw \| diff to current
2021-01-15	Nelson Chu	RISC-V: Comments tidy and improvement.	blob \| commitdiff \| raw \| diff to current
2021-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2020-12-10	Nelson Chu	RISC-V: Dump CSR according to the elf privileged spec...	blob \| commitdiff \| raw \| diff to current
2020-06-30	Nelson Chu	RISC-V: Support debug and float CSR as the unprivileged...	blob \| commitdiff \| raw \| diff to current
2020-06-22	Nelson Chu	RISC-V: Report warning when linking the objects with...	blob \| commitdiff \| raw \| diff to current
2020-05-20	Nelson Chu	[PATCH v2 0/9] RISC-V: Support version controling for...	blob \| commitdiff \| raw \| diff to current
2020-02-21	Nelson Chu	RISC-V: Support the ISA-dependent CSR checking.	blob \| commitdiff \| raw \| diff to current
2020-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2019-06-27	Jim Wilson	RISC-V: Make objdump disassembly work right for binary...	blob \| commitdiff \| raw \| diff to current
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