]>
Commit | Line | Data |
---|---|---|
23608e23 JL |
1 | /* |
2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
5 | */ |
6 | ||
7 | #include <common.h> | |
5a660169 | 8 | #include <div64.h> |
23608e23 JL |
9 | #include <asm/io.h> |
10 | #include <asm/errno.h> | |
11 | #include <asm/arch/imx-regs.h> | |
6a376046 | 12 | #include <asm/arch/crm_regs.h> |
23608e23 | 13 | #include <asm/arch/clock.h> |
6a376046 | 14 | #include <asm/arch/sys_proto.h> |
23608e23 JL |
15 | |
16 | enum pll_clocks { | |
17 | PLL_SYS, /* System PLL */ | |
18 | PLL_BUS, /* System Bus PLL*/ | |
19 | PLL_USBOTG, /* OTG USB PLL */ | |
20 | PLL_ENET, /* ENET PLL */ | |
21 | }; | |
22 | ||
6a376046 | 23 | struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
23608e23 | 24 | |
112fd2ec BT |
25 | #ifdef CONFIG_MXC_OCOTP |
26 | void enable_ocotp_clk(unsigned char enable) | |
27 | { | |
28 | u32 reg; | |
29 | ||
30 | reg = __raw_readl(&imx_ccm->CCGR2); | |
31 | if (enable) | |
32 | reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
33 | else | |
34 | reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
35 | __raw_writel(reg, &imx_ccm->CCGR2); | |
36 | } | |
37 | #endif | |
38 | ||
224beb83 NK |
39 | #ifdef CONFIG_NAND_MXS |
40 | void setup_gpmi_io_clk(u32 cfg) | |
41 | { | |
42 | /* Disable clocks per ERR007177 from MX6 errata */ | |
43 | clrbits_le32(&imx_ccm->CCGR4, | |
44 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
45 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
46 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
47 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
48 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
49 | ||
50 | clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
51 | ||
52 | clrsetbits_le32(&imx_ccm->cs2cdr, | |
53 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
54 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
55 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
56 | cfg); | |
57 | ||
58 | setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
59 | setbits_le32(&imx_ccm->CCGR4, | |
60 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
62 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
63 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
64 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
65 | } | |
66 | #endif | |
67 | ||
3f467529 WG |
68 | void enable_usboh3_clk(unsigned char enable) |
69 | { | |
70 | u32 reg; | |
71 | ||
72 | reg = __raw_readl(&imx_ccm->CCGR6); | |
73 | if (enable) | |
0bb7e316 | 74 | reg |= MXC_CCM_CCGR6_USBOH3_MASK; |
3f467529 | 75 | else |
0bb7e316 | 76 | reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); |
3f467529 WG |
77 | __raw_writel(reg, &imx_ccm->CCGR6); |
78 | ||
79 | } | |
80 | ||
3d8f1798 | 81 | #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX) |
224beb83 NK |
82 | void enable_enet_clk(unsigned char enable) |
83 | { | |
43cb127b PF |
84 | u32 mask, *addr; |
85 | ||
86 | if (is_cpu_type(MXC_CPU_MX6UL)) { | |
87 | mask = MXC_CCM_CCGR3_ENET_MASK; | |
88 | addr = &imx_ccm->CCGR3; | |
89 | } else { | |
90 | mask = MXC_CCM_CCGR1_ENET_MASK; | |
91 | addr = &imx_ccm->CCGR1; | |
92 | } | |
224beb83 NK |
93 | |
94 | if (enable) | |
43cb127b | 95 | setbits_le32(addr, mask); |
224beb83 | 96 | else |
43cb127b | 97 | clrbits_le32(addr, mask); |
224beb83 NK |
98 | } |
99 | #endif | |
100 | ||
101 | #ifdef CONFIG_MXC_UART | |
102 | void enable_uart_clk(unsigned char enable) | |
103 | { | |
43cb127b PF |
104 | u32 mask; |
105 | ||
106 | if (is_cpu_type(MXC_CPU_MX6UL)) | |
107 | mask = MXC_CCM_CCGR5_UART_MASK; | |
108 | else | |
109 | mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; | |
224beb83 NK |
110 | |
111 | if (enable) | |
112 | setbits_le32(&imx_ccm->CCGR5, mask); | |
113 | else | |
114 | clrbits_le32(&imx_ccm->CCGR5, mask); | |
115 | } | |
116 | #endif | |
117 | ||
224beb83 NK |
118 | #ifdef CONFIG_MMC |
119 | int enable_usdhc_clk(unsigned char enable, unsigned bus_num) | |
120 | { | |
121 | u32 mask; | |
122 | ||
123 | if (bus_num > 3) | |
124 | return -EINVAL; | |
125 | ||
126 | mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); | |
127 | if (enable) | |
128 | setbits_le32(&imx_ccm->CCGR6, mask); | |
129 | else | |
130 | clrbits_le32(&imx_ccm->CCGR6, mask); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | #endif | |
135 | ||
fac96408 | 136 | #ifdef CONFIG_SYS_I2C_MXC |
21a26940 | 137 | /* i2c_num can be from 0 - 3 */ |
cc54a0f7 TK |
138 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) |
139 | { | |
140 | u32 reg; | |
141 | u32 mask; | |
19c6ec70 | 142 | u32 *addr; |
cc54a0f7 | 143 | |
21a26940 | 144 | if (i2c_num > 3) |
cc54a0f7 | 145 | return -EINVAL; |
21a26940 HS |
146 | if (i2c_num < 3) { |
147 | mask = MXC_CCM_CCGR_CG_MASK | |
148 | << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET | |
149 | + (i2c_num << 1)); | |
150 | reg = __raw_readl(&imx_ccm->CCGR2); | |
151 | if (enable) | |
152 | reg |= mask; | |
153 | else | |
154 | reg &= ~mask; | |
155 | __raw_writel(reg, &imx_ccm->CCGR2); | |
156 | } else { | |
43cb127b | 157 | if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { |
19c6ec70 PF |
158 | mask = MXC_CCM_CCGR6_I2C4_MASK; |
159 | addr = &imx_ccm->CCGR6; | |
160 | } else { | |
161 | mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK; | |
162 | addr = &imx_ccm->CCGR1; | |
163 | } | |
164 | reg = __raw_readl(addr); | |
21a26940 HS |
165 | if (enable) |
166 | reg |= mask; | |
167 | else | |
168 | reg &= ~mask; | |
19c6ec70 | 169 | __raw_writel(reg, addr); |
21a26940 | 170 | } |
cc54a0f7 TK |
171 | return 0; |
172 | } | |
173 | #endif | |
174 | ||
a0ae0091 HS |
175 | /* spi_num can be from 0 - SPI_MAX_NUM */ |
176 | int enable_spi_clk(unsigned char enable, unsigned spi_num) | |
177 | { | |
178 | u32 reg; | |
179 | u32 mask; | |
180 | ||
181 | if (spi_num > SPI_MAX_NUM) | |
182 | return -EINVAL; | |
183 | ||
184 | mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1); | |
185 | reg = __raw_readl(&imx_ccm->CCGR1); | |
186 | if (enable) | |
187 | reg |= mask; | |
188 | else | |
189 | reg &= ~mask; | |
190 | __raw_writel(reg, &imx_ccm->CCGR1); | |
191 | return 0; | |
192 | } | |
23608e23 JL |
193 | static u32 decode_pll(enum pll_clocks pll, u32 infreq) |
194 | { | |
195 | u32 div; | |
196 | ||
197 | switch (pll) { | |
198 | case PLL_SYS: | |
199 | div = __raw_readl(&imx_ccm->analog_pll_sys); | |
200 | div &= BM_ANADIG_PLL_SYS_DIV_SELECT; | |
201 | ||
2eb268f6 | 202 | return (infreq * div) >> 1; |
23608e23 JL |
203 | case PLL_BUS: |
204 | div = __raw_readl(&imx_ccm->analog_pll_528); | |
205 | div &= BM_ANADIG_PLL_528_DIV_SELECT; | |
206 | ||
207 | return infreq * (20 + (div << 1)); | |
208 | case PLL_USBOTG: | |
209 | div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); | |
210 | div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; | |
211 | ||
212 | return infreq * (20 + (div << 1)); | |
213 | case PLL_ENET: | |
214 | div = __raw_readl(&imx_ccm->analog_pll_enet); | |
215 | div &= BM_ANADIG_PLL_ENET_DIV_SELECT; | |
216 | ||
89cfd0f5 | 217 | return 25000000 * (div + (div >> 1) + 1); |
23608e23 JL |
218 | default: |
219 | return 0; | |
220 | } | |
221 | /* NOTREACHED */ | |
222 | } | |
762a88cc PA |
223 | static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) |
224 | { | |
225 | u32 div; | |
226 | u64 freq; | |
227 | ||
228 | switch (pll) { | |
229 | case PLL_BUS: | |
43cb127b PF |
230 | if (!is_cpu_type(MXC_CPU_MX6UL)) { |
231 | if (pfd_num == 3) { | |
232 | /* No PFD3 on PPL2 */ | |
233 | return 0; | |
234 | } | |
762a88cc PA |
235 | } |
236 | div = __raw_readl(&imx_ccm->analog_pfd_528); | |
237 | freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); | |
238 | break; | |
239 | case PLL_USBOTG: | |
240 | div = __raw_readl(&imx_ccm->analog_pfd_480); | |
241 | freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); | |
242 | break; | |
243 | default: | |
244 | /* No PFD on other PLL */ | |
245 | return 0; | |
246 | } | |
247 | ||
5a660169 | 248 | return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> |
762a88cc PA |
249 | ANATOP_PFD_FRAC_SHIFT(pfd_num)); |
250 | } | |
23608e23 JL |
251 | |
252 | static u32 get_mcu_main_clk(void) | |
253 | { | |
254 | u32 reg, freq; | |
255 | ||
256 | reg = __raw_readl(&imx_ccm->cacrr); | |
257 | reg &= MXC_CCM_CACRR_ARM_PODF_MASK; | |
258 | reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; | |
833b6435 | 259 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 JL |
260 | |
261 | return freq / (reg + 1); | |
262 | } | |
263 | ||
6a376046 | 264 | u32 get_periph_clk(void) |
23608e23 | 265 | { |
43cb127b | 266 | u32 reg, div = 0, freq = 0; |
23608e23 JL |
267 | |
268 | reg = __raw_readl(&imx_ccm->cbcdr); | |
269 | if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { | |
43cb127b PF |
270 | div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> |
271 | MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET; | |
23608e23 JL |
272 | reg = __raw_readl(&imx_ccm->cbcmr); |
273 | reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; | |
274 | reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; | |
275 | ||
276 | switch (reg) { | |
277 | case 0: | |
833b6435 | 278 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
279 | break; |
280 | case 1: | |
281 | case 2: | |
833b6435 | 282 | freq = MXC_HCLK; |
23608e23 JL |
283 | break; |
284 | default: | |
285 | break; | |
286 | } | |
287 | } else { | |
288 | reg = __raw_readl(&imx_ccm->cbcmr); | |
289 | reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; | |
290 | reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; | |
291 | ||
292 | switch (reg) { | |
293 | case 0: | |
833b6435 | 294 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 JL |
295 | break; |
296 | case 1: | |
762a88cc | 297 | freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
298 | break; |
299 | case 2: | |
762a88cc | 300 | freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
301 | break; |
302 | case 3: | |
762a88cc PA |
303 | /* static / 2 divider */ |
304 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
23608e23 JL |
305 | break; |
306 | default: | |
307 | break; | |
308 | } | |
309 | } | |
310 | ||
43cb127b | 311 | return freq / (div + 1); |
23608e23 JL |
312 | } |
313 | ||
23608e23 JL |
314 | static u32 get_ipg_clk(void) |
315 | { | |
316 | u32 reg, ipg_podf; | |
317 | ||
318 | reg = __raw_readl(&imx_ccm->cbcdr); | |
319 | reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; | |
320 | ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; | |
321 | ||
322 | return get_ahb_clk() / (ipg_podf + 1); | |
323 | } | |
324 | ||
325 | static u32 get_ipg_per_clk(void) | |
326 | { | |
327 | u32 reg, perclk_podf; | |
328 | ||
329 | reg = __raw_readl(&imx_ccm->cscmr1); | |
e1c2d68b | 330 | if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || |
43cb127b | 331 | is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { |
e1c2d68b PF |
332 | if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) |
333 | return MXC_HCLK; /* OSC 24Mhz */ | |
334 | } | |
335 | ||
23608e23 JL |
336 | perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; |
337 | ||
338 | return get_ipg_clk() / (perclk_podf + 1); | |
339 | } | |
340 | ||
341 | static u32 get_uart_clk(void) | |
342 | { | |
343 | u32 reg, uart_podf; | |
762a88cc | 344 | u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ |
23608e23 | 345 | reg = __raw_readl(&imx_ccm->cscdr1); |
e1c2d68b PF |
346 | |
347 | if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || | |
43cb127b | 348 | is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { |
e1c2d68b PF |
349 | if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) |
350 | freq = MXC_HCLK; | |
351 | } | |
352 | ||
23608e23 JL |
353 | reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; |
354 | uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; | |
355 | ||
25b4aa14 | 356 | return freq / (uart_podf + 1); |
23608e23 JL |
357 | } |
358 | ||
359 | static u32 get_cspi_clk(void) | |
360 | { | |
361 | u32 reg, cspi_podf; | |
362 | ||
363 | reg = __raw_readl(&imx_ccm->cscdr2); | |
e1c2d68b PF |
364 | cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> |
365 | MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; | |
366 | ||
43cb127b PF |
367 | if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) || |
368 | is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { | |
e1c2d68b PF |
369 | if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) |
370 | return MXC_HCLK / (cspi_podf + 1); | |
371 | } | |
23608e23 | 372 | |
762a88cc | 373 | return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); |
23608e23 JL |
374 | } |
375 | ||
376 | static u32 get_axi_clk(void) | |
377 | { | |
378 | u32 root_freq, axi_podf; | |
379 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
380 | ||
381 | axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; | |
382 | axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; | |
383 | ||
384 | if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { | |
385 | if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) | |
762a88cc | 386 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 | 387 | else |
762a88cc | 388 | root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); |
23608e23 JL |
389 | } else |
390 | root_freq = get_periph_clk(); | |
391 | ||
392 | return root_freq / (axi_podf + 1); | |
393 | } | |
394 | ||
395 | static u32 get_emi_slow_clk(void) | |
396 | { | |
d55e0dab | 397 | u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; |
23608e23 JL |
398 | |
399 | cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
400 | emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; | |
401 | emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; | |
d55e0dab AG |
402 | emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; |
403 | emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; | |
23608e23 JL |
404 | |
405 | switch (emi_clk_sel) { | |
406 | case 0: | |
407 | root_freq = get_axi_clk(); | |
408 | break; | |
409 | case 1: | |
833b6435 | 410 | root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
411 | break; |
412 | case 2: | |
762a88cc | 413 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
414 | break; |
415 | case 3: | |
762a88cc | 416 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
417 | break; |
418 | } | |
419 | ||
d55e0dab | 420 | return root_freq / (emi_slow_podf + 1); |
23608e23 JL |
421 | } |
422 | ||
25b4aa14 FE |
423 | static u32 get_mmdc_ch0_clk(void) |
424 | { | |
425 | u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); | |
426 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
25b4aa14 | 427 | |
43cb127b PF |
428 | u32 freq, podf, per2_clk2_podf; |
429 | ||
430 | if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || | |
431 | is_cpu_type(MXC_CPU_MX6SL)) { | |
432 | podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> | |
433 | MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; | |
434 | if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { | |
435 | per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >> | |
436 | MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET; | |
437 | if (is_cpu_type(MXC_CPU_MX6SL)) { | |
438 | if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL) | |
439 | freq = MXC_HCLK; | |
440 | else | |
441 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); | |
442 | } else { | |
443 | if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL) | |
444 | freq = decode_pll(PLL_BUS, MXC_HCLK); | |
445 | else | |
446 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); | |
447 | } | |
448 | } else { | |
449 | per2_clk2_podf = 0; | |
450 | switch ((cbcmr & | |
451 | MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> | |
452 | MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { | |
453 | case 0: | |
454 | freq = decode_pll(PLL_BUS, MXC_HCLK); | |
455 | break; | |
456 | case 1: | |
457 | freq = mxc_get_pll_pfd(PLL_BUS, 2); | |
458 | break; | |
459 | case 2: | |
460 | freq = mxc_get_pll_pfd(PLL_BUS, 0); | |
461 | break; | |
462 | case 3: | |
463 | /* static / 2 divider */ | |
464 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
465 | break; | |
466 | } | |
467 | } | |
468 | return freq / (podf + 1) / (per2_clk2_podf + 1); | |
469 | } else { | |
470 | podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> | |
471 | MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; | |
472 | return get_periph_clk() / (podf + 1); | |
25b4aa14 | 473 | } |
25b4aa14 | 474 | } |
c655b816 | 475 | |
43cb127b | 476 | #ifdef CONFIG_FSL_QSPI |
b93ab2ee PF |
477 | /* qspi_num can be from 0 - 1 */ |
478 | void enable_qspi_clk(int qspi_num) | |
479 | { | |
480 | u32 reg = 0; | |
481 | /* Enable QuadSPI clock */ | |
482 | switch (qspi_num) { | |
483 | case 0: | |
484 | /* disable the clock gate */ | |
485 | clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); | |
486 | ||
487 | /* set 50M : (50 = 396 / 2 / 4) */ | |
488 | reg = readl(&imx_ccm->cscmr1); | |
489 | reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | | |
490 | MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); | |
491 | reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | | |
492 | (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); | |
493 | writel(reg, &imx_ccm->cscmr1); | |
494 | ||
495 | /* enable the clock gate */ | |
496 | setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); | |
497 | break; | |
498 | case 1: | |
499 | /* | |
500 | * disable the clock gate | |
501 | * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, | |
502 | * disable both of them. | |
503 | */ | |
504 | clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | | |
505 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); | |
506 | ||
507 | /* set 50M : (50 = 396 / 2 / 4) */ | |
508 | reg = readl(&imx_ccm->cs2cdr); | |
509 | reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | | |
510 | MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | | |
511 | MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); | |
512 | reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | | |
513 | MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); | |
514 | writel(reg, &imx_ccm->cs2cdr); | |
515 | ||
516 | /*enable the clock gate*/ | |
517 | setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | | |
518 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); | |
519 | break; | |
520 | default: | |
521 | break; | |
522 | } | |
523 | } | |
524 | #endif | |
525 | ||
c655b816 | 526 | #ifdef CONFIG_FEC_MXC |
6d97dc10 | 527 | int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) |
31f07964 FE |
528 | { |
529 | u32 reg = 0; | |
530 | s32 timeout = 100000; | |
531 | ||
532 | struct anatop_regs __iomem *anatop = | |
533 | (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | |
534 | ||
7731745c | 535 | if (freq < ENET_25MHZ || freq > ENET_125MHZ) |
5f98d0b5 FE |
536 | return -EINVAL; |
537 | ||
e2748b41 PF |
538 | reg = readl(&anatop->pll_enet); |
539 | ||
6d97dc10 PF |
540 | if (fec_id == 0) { |
541 | reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; | |
542 | reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); | |
543 | } else if (fec_id == 1) { | |
544 | /* Only i.MX6SX/UL support ENET2 */ | |
545 | if (!(is_cpu_type(MXC_CPU_MX6SX) || | |
546 | is_cpu_type(MXC_CPU_MX6UL))) | |
547 | return -EINVAL; | |
548 | reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; | |
549 | reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); | |
550 | } else { | |
551 | return -EINVAL; | |
552 | } | |
5f98d0b5 | 553 | |
31f07964 FE |
554 | if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || |
555 | (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { | |
556 | reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; | |
557 | writel(reg, &anatop->pll_enet); | |
558 | while (timeout--) { | |
559 | if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) | |
560 | break; | |
561 | } | |
562 | if (timeout < 0) | |
563 | return -ETIMEDOUT; | |
564 | } | |
565 | ||
566 | /* Enable FEC clock */ | |
6d97dc10 PF |
567 | if (fec_id == 0) |
568 | reg |= BM_ANADIG_PLL_ENET_ENABLE; | |
569 | else | |
570 | reg |= BM_ANADIG_PLL_ENET2_ENABLE; | |
31f07964 FE |
571 | reg &= ~BM_ANADIG_PLL_ENET_BYPASS; |
572 | writel(reg, &anatop->pll_enet); | |
573 | ||
5c045cdd FE |
574 | #ifdef CONFIG_MX6SX |
575 | /* | |
576 | * Set enet ahb clock to 200MHz | |
577 | * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB | |
578 | */ | |
579 | reg = readl(&imx_ccm->chsccdr); | |
580 | reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK | |
581 | | MXC_CCM_CHSCCDR_ENET_PODF_MASK | |
582 | | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); | |
583 | /* PLL2 PFD2 */ | |
584 | reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); | |
585 | /* Div = 2*/ | |
586 | reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); | |
587 | reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); | |
588 | writel(reg, &imx_ccm->chsccdr); | |
589 | ||
590 | /* Enable enet system clock */ | |
591 | reg = readl(&imx_ccm->CCGR3); | |
592 | reg |= MXC_CCM_CCGR3_ENET_MASK; | |
593 | writel(reg, &imx_ccm->CCGR3); | |
594 | #endif | |
31f07964 FE |
595 | return 0; |
596 | } | |
25b4aa14 | 597 | #endif |
23608e23 JL |
598 | |
599 | static u32 get_usdhc_clk(u32 port) | |
600 | { | |
601 | u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; | |
602 | u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
603 | u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); | |
604 | ||
605 | switch (port) { | |
606 | case 0: | |
607 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> | |
608 | MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; | |
609 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; | |
610 | ||
611 | break; | |
612 | case 1: | |
613 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> | |
614 | MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; | |
615 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; | |
616 | ||
617 | break; | |
618 | case 2: | |
619 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> | |
620 | MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; | |
621 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; | |
622 | ||
623 | break; | |
624 | case 3: | |
625 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> | |
626 | MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; | |
627 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; | |
628 | ||
629 | break; | |
630 | default: | |
631 | break; | |
632 | } | |
633 | ||
634 | if (clk_sel) | |
762a88cc | 635 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 | 636 | else |
762a88cc | 637 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
638 | |
639 | return root_freq / (usdhc_podf + 1); | |
640 | } | |
641 | ||
642 | u32 imx_get_uartclk(void) | |
643 | { | |
644 | return get_uart_clk(); | |
645 | } | |
646 | ||
ff167df5 JL |
647 | u32 imx_get_fecclk(void) |
648 | { | |
adadc915 | 649 | return mxc_get_clock(MXC_IPG_CLK); |
ff167df5 JL |
650 | } |
651 | ||
43cb127b | 652 | #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX) |
79814492 | 653 | static int enable_enet_pll(uint32_t en) |
64e7cdb5 | 654 | { |
64e7cdb5 EN |
655 | struct mxc_ccm_reg *const imx_ccm |
656 | = (struct mxc_ccm_reg *) CCM_BASE_ADDR; | |
79814492 MV |
657 | s32 timeout = 100000; |
658 | u32 reg = 0; | |
64e7cdb5 EN |
659 | |
660 | /* Enable PLLs */ | |
661 | reg = readl(&imx_ccm->analog_pll_enet); | |
662 | reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; | |
663 | writel(reg, &imx_ccm->analog_pll_enet); | |
664 | reg |= BM_ANADIG_PLL_SYS_ENABLE; | |
665 | while (timeout--) { | |
666 | if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) | |
667 | break; | |
668 | } | |
669 | if (timeout <= 0) | |
670 | return -EIO; | |
671 | reg &= ~BM_ANADIG_PLL_SYS_BYPASS; | |
672 | writel(reg, &imx_ccm->analog_pll_enet); | |
79814492 | 673 | reg |= en; |
64e7cdb5 | 674 | writel(reg, &imx_ccm->analog_pll_enet); |
79814492 MV |
675 | return 0; |
676 | } | |
43cb127b | 677 | #endif |
64e7cdb5 | 678 | |
43cb127b | 679 | #ifdef CONFIG_CMD_SATA |
79814492 MV |
680 | static void ungate_sata_clock(void) |
681 | { | |
682 | struct mxc_ccm_reg *const imx_ccm = | |
683 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
684 | ||
685 | /* Enable SATA clock. */ | |
686 | setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); | |
687 | } | |
688 | ||
79814492 MV |
689 | int enable_sata_clock(void) |
690 | { | |
691 | ungate_sata_clock(); | |
692 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); | |
693 | } | |
8d29cef5 NK |
694 | |
695 | void disable_sata_clock(void) | |
696 | { | |
697 | struct mxc_ccm_reg *const imx_ccm = | |
698 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
699 | ||
700 | clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); | |
701 | } | |
d95b6ab8 | 702 | #endif |
79814492 | 703 | |
43cb127b PF |
704 | #ifdef CONFIG_PCIE_IMX |
705 | static void ungate_pcie_clock(void) | |
706 | { | |
707 | struct mxc_ccm_reg *const imx_ccm = | |
708 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
709 | ||
710 | /* Enable PCIe clock. */ | |
711 | setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); | |
712 | } | |
713 | ||
79814492 MV |
714 | int enable_pcie_clock(void) |
715 | { | |
716 | struct anatop_regs *anatop_regs = | |
717 | (struct anatop_regs *)ANATOP_BASE_ADDR; | |
718 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
1b8ad74a | 719 | u32 lvds1_clk_sel; |
79814492 MV |
720 | |
721 | /* | |
722 | * Here be dragons! | |
723 | * | |
724 | * The register ANATOP_MISC1 is not documented in the Freescale | |
725 | * MX6RM. The register that is mapped in the ANATOP space and | |
726 | * marked as ANATOP_MISC1 is actually documented in the PMU section | |
727 | * of the datasheet as PMU_MISC1. | |
728 | * | |
1b8ad74a FE |
729 | * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on |
730 | * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important | |
731 | * for PCI express link that is clocked from the i.MX6. | |
79814492 MV |
732 | */ |
733 | #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) | |
734 | #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) | |
735 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F | |
1b8ad74a FE |
736 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa |
737 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb | |
738 | ||
739 | if (is_cpu_type(MXC_CPU_MX6SX)) | |
740 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; | |
741 | else | |
742 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; | |
743 | ||
79814492 MV |
744 | clrsetbits_le32(&anatop_regs->ana_misc1, |
745 | ANADIG_ANA_MISC1_LVDSCLK1_IBEN | | |
746 | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, | |
1b8ad74a | 747 | ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); |
79814492 MV |
748 | |
749 | /* PCIe reference clock sourced from AXI. */ | |
750 | clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); | |
751 | ||
752 | /* Party time! Ungate the clock to the PCIe. */ | |
43cb127b | 753 | #ifdef CONFIG_CMD_SATA |
79814492 | 754 | ungate_sata_clock(); |
d95b6ab8 | 755 | #endif |
79814492 MV |
756 | ungate_pcie_clock(); |
757 | ||
758 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | | |
759 | BM_ANADIG_PLL_ENET_ENABLE_PCIE); | |
64e7cdb5 | 760 | } |
43cb127b | 761 | #endif |
64e7cdb5 | 762 | |
36c1ca4d NG |
763 | #ifdef CONFIG_SECURE_BOOT |
764 | void hab_caam_clock_enable(unsigned char enable) | |
765 | { | |
766 | u32 reg; | |
767 | ||
768 | /* CG4 ~ CG6, CAAM clocks */ | |
769 | reg = __raw_readl(&imx_ccm->CCGR0); | |
770 | if (enable) | |
771 | reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
772 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
773 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
774 | else | |
775 | reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
776 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
777 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
778 | __raw_writel(reg, &imx_ccm->CCGR0); | |
779 | ||
780 | /* EMI slow clk */ | |
781 | reg = __raw_readl(&imx_ccm->CCGR6); | |
782 | if (enable) | |
783 | reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
784 | else | |
785 | reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
786 | __raw_writel(reg, &imx_ccm->CCGR6); | |
787 | } | |
788 | #endif | |
789 | ||
cf202d26 NG |
790 | static void enable_pll3(void) |
791 | { | |
792 | struct anatop_regs __iomem *anatop = | |
793 | (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | |
794 | ||
795 | /* make sure pll3 is enabled */ | |
796 | if ((readl(&anatop->usb1_pll_480_ctrl) & | |
797 | BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { | |
798 | /* enable pll's power */ | |
799 | writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, | |
800 | &anatop->usb1_pll_480_ctrl_set); | |
801 | writel(0x80, &anatop->ana_misc2_clr); | |
802 | /* wait for pll lock */ | |
803 | while ((readl(&anatop->usb1_pll_480_ctrl) & | |
804 | BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) | |
805 | ; | |
806 | /* disable bypass */ | |
807 | writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, | |
808 | &anatop->usb1_pll_480_ctrl_clr); | |
809 | /* enable pll output */ | |
810 | writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, | |
811 | &anatop->usb1_pll_480_ctrl_set); | |
812 | } | |
813 | } | |
814 | ||
815 | void enable_thermal_clk(void) | |
816 | { | |
817 | enable_pll3(); | |
818 | } | |
819 | ||
23608e23 JL |
820 | unsigned int mxc_get_clock(enum mxc_clock clk) |
821 | { | |
822 | switch (clk) { | |
823 | case MXC_ARM_CLK: | |
824 | return get_mcu_main_clk(); | |
825 | case MXC_PER_CLK: | |
826 | return get_periph_clk(); | |
827 | case MXC_AHB_CLK: | |
828 | return get_ahb_clk(); | |
829 | case MXC_IPG_CLK: | |
830 | return get_ipg_clk(); | |
831 | case MXC_IPG_PERCLK: | |
e7bed5c2 | 832 | case MXC_I2C_CLK: |
23608e23 JL |
833 | return get_ipg_per_clk(); |
834 | case MXC_UART_CLK: | |
835 | return get_uart_clk(); | |
836 | case MXC_CSPI_CLK: | |
837 | return get_cspi_clk(); | |
838 | case MXC_AXI_CLK: | |
839 | return get_axi_clk(); | |
840 | case MXC_EMI_SLOW_CLK: | |
841 | return get_emi_slow_clk(); | |
842 | case MXC_DDR_CLK: | |
843 | return get_mmdc_ch0_clk(); | |
844 | case MXC_ESDHC_CLK: | |
845 | return get_usdhc_clk(0); | |
846 | case MXC_ESDHC2_CLK: | |
847 | return get_usdhc_clk(1); | |
848 | case MXC_ESDHC3_CLK: | |
849 | return get_usdhc_clk(2); | |
850 | case MXC_ESDHC4_CLK: | |
851 | return get_usdhc_clk(3); | |
852 | case MXC_SATA_CLK: | |
853 | return get_ahb_clk(); | |
854 | default: | |
eb412d79 | 855 | printf("Unsupported MXC CLK: %d\n", clk); |
23608e23 JL |
856 | break; |
857 | } | |
858 | ||
eb412d79 | 859 | return 0; |
23608e23 JL |
860 | } |
861 | ||
862 | /* | |
863 | * Dump some core clockes. | |
864 | */ | |
865 | int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
866 | { | |
867 | u32 freq; | |
833b6435 | 868 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 | 869 | printf("PLL_SYS %8d MHz\n", freq / 1000000); |
833b6435 | 870 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 | 871 | printf("PLL_BUS %8d MHz\n", freq / 1000000); |
833b6435 | 872 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 | 873 | printf("PLL_OTG %8d MHz\n", freq / 1000000); |
833b6435 | 874 | freq = decode_pll(PLL_ENET, MXC_HCLK); |
23608e23 JL |
875 | printf("PLL_NET %8d MHz\n", freq / 1000000); |
876 | ||
877 | printf("\n"); | |
878 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | |
879 | printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); | |
cc446726 | 880 | #ifdef CONFIG_MXC_SPI |
23608e23 | 881 | printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); |
cc446726 | 882 | #endif |
23608e23 JL |
883 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); |
884 | printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); | |
885 | printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); | |
886 | printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); | |
887 | printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); | |
888 | printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); | |
889 | printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); | |
890 | printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); | |
891 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
d95b6ab8 | 896 | #ifndef CONFIG_MX6SX |
5ea7f0e3 PKS |
897 | void enable_ipu_clock(void) |
898 | { | |
899 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
900 | int reg; | |
901 | reg = readl(&mxc_ccm->CCGR3); | |
a0a0dacf | 902 | reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; |
5ea7f0e3 | 903 | writel(reg, &mxc_ccm->CCGR3); |
8d779461 PF |
904 | |
905 | if (is_mx6dqp()) { | |
906 | setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); | |
907 | setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); | |
908 | } | |
5ea7f0e3 | 909 | } |
d95b6ab8 | 910 | #endif |
23608e23 JL |
911 | /***************************************************/ |
912 | ||
913 | U_BOOT_CMD( | |
914 | clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, | |
915 | "display clocks", | |
916 | "" | |
917 | ); |