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4a9cbbe8 | 1 | /* |
dbbd1257 | 2 | * (C) Copyright 2000-2007 |
4a9cbbe8 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
b36df561 | 26 | #include <asm/ppc4xx-emac.h> |
4a9cbbe8 | 27 | #include <asm/processor.h> |
09887762 | 28 | #include <asm/ppc4xx-gpio.h> |
b36df561 | 29 | #include <asm/ppc4xx.h> |
4a9cbbe8 | 30 | |
d87080b7 WD |
31 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
32 | DECLARE_GLOBAL_DATA_PTR; | |
33 | #endif | |
34 | ||
6d0f6bcf JCPV |
35 | #ifndef CONFIG_SYS_PLL_RECONFIG |
36 | #define CONFIG_SYS_PLL_RECONFIG 0 | |
f66e2c8b MN |
37 | #endif |
38 | ||
fe7cca71 SR |
39 | #if defined(CONFIG_440EPX) || \ |
40 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
41 | static void reset_with_rli(void) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | /* | |
46 | * Set reload inhibit so configuration will persist across | |
47 | * processor resets | |
48 | */ | |
49 | mfcpr(CPR0_ICFG, reg); | |
50 | reg |= CPR0_ICFG_RLI_MASK; | |
51 | mtcpr(CPR0_ICFG, reg); | |
52 | ||
53 | /* Reset processor if configuration changed */ | |
54 | __asm__ __volatile__ ("sync; isync"); | |
55 | mtspr(SPRN_DBCR0, 0x20000000); | |
56 | } | |
57 | #endif | |
58 | ||
f66e2c8b MN |
59 | void reconfigure_pll(u32 new_cpu_freq) |
60 | { | |
61 | #if defined(CONFIG_440EPX) | |
62 | int reset_needed = 0; | |
63 | u32 reg, temp; | |
64 | u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ | |
65 | fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ | |
66 | fbdv, target_fbdv, lfbdv, target_lfbdv, | |
67 | perdv0, target_perdv0, /* CLK_PERD */ | |
68 | spcid0, target_spcid0; /* CLK_SPCID */ | |
69 | ||
70 | /* Reconfigure clocks if necessary. | |
71 | * See PPC440EPx User's Manual, sections 8.2 and 14 */ | |
72 | if (new_cpu_freq == 667) { | |
73 | target_prbdv0 = 2; | |
74 | target_fwdva = 2; | |
75 | target_fwdvb = 4; | |
76 | target_fbdv = 20; | |
77 | target_lfbdv = 1; | |
78 | target_perdv0 = 4; | |
79 | target_spcid0 = 4; | |
80 | ||
ddc922ff | 81 | mfcpr(CPR0_PRIMBD0, reg); |
f66e2c8b MN |
82 | temp = (reg & PRBDV_MASK) >> 24; |
83 | prbdv0 = temp ? temp : 8; | |
84 | if (prbdv0 != target_prbdv0) { | |
85 | reg &= ~PRBDV_MASK; | |
86 | reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); | |
ddc922ff | 87 | mtcpr(CPR0_PRIMBD0, reg); |
f66e2c8b MN |
88 | reset_needed = 1; |
89 | } | |
90 | ||
d1c3b275 | 91 | mfcpr(CPR0_PLLD, reg); |
f66e2c8b MN |
92 | |
93 | temp = (reg & PLLD_FWDVA_MASK) >> 16; | |
94 | fwdva = temp ? temp : 16; | |
95 | ||
96 | temp = (reg & PLLD_FWDVB_MASK) >> 8; | |
97 | fwdvb = temp ? temp : 8; | |
98 | ||
99 | temp = (reg & PLLD_FBDV_MASK) >> 24; | |
100 | fbdv = temp ? temp : 32; | |
101 | ||
102 | temp = (reg & PLLD_LFBDV_MASK); | |
103 | lfbdv = temp ? temp : 64; | |
104 | ||
105 | if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { | |
106 | reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | | |
107 | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); | |
108 | reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | | |
109 | ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | | |
110 | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | | |
111 | (target_lfbdv == 64 ? 0 : target_lfbdv); | |
d1c3b275 | 112 | mtcpr(CPR0_PLLD, reg); |
f66e2c8b MN |
113 | reset_needed = 1; |
114 | } | |
115 | ||
d1c3b275 | 116 | mfcpr(CPR0_PERD, reg); |
f66e2c8b MN |
117 | perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; |
118 | if (perdv0 != target_perdv0) { | |
119 | reg &= ~CPR0_PERD_PERDV0_MASK; | |
120 | reg |= (target_perdv0 << 24); | |
d1c3b275 | 121 | mtcpr(CPR0_PERD, reg); |
f66e2c8b MN |
122 | reset_needed = 1; |
123 | } | |
124 | ||
d1c3b275 | 125 | mfcpr(CPR0_SPCID, reg); |
f66e2c8b MN |
126 | temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; |
127 | spcid0 = temp ? temp : 4; | |
128 | if (spcid0 != target_spcid0) { | |
129 | reg &= ~CPR0_SPCID_SPCIDV0_MASK; | |
130 | reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); | |
d1c3b275 | 131 | mtcpr(CPR0_SPCID, reg); |
f66e2c8b MN |
132 | reset_needed = 1; |
133 | } | |
c550afad RS |
134 | } |
135 | ||
136 | /* Get current value of FWDVA.*/ | |
137 | mfcpr(CPR0_PLLD, reg); | |
138 | temp = (reg & PLLD_FWDVA_MASK) >> 16; | |
f66e2c8b | 139 | |
c550afad RS |
140 | /* |
141 | * Check to see if FWDVA has been set to value of 1. if it has we must | |
142 | * modify it. | |
143 | */ | |
144 | if (temp == 1) { | |
c550afad RS |
145 | /* |
146 | * Load register that contains current boot strapping option. | |
147 | */ | |
148 | mfcpr(CPR0_ICFG, reg); | |
c1ab75c7 SR |
149 | /* |
150 | * Strapping option bits (ICS) are already in correct position, | |
151 | * only masking needed. | |
152 | */ | |
153 | reg &= CPR0_ICFG_ICS_MASK; | |
c550afad RS |
154 | |
155 | if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || | |
156 | (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { | |
c1ab75c7 SR |
157 | mfcpr(CPR0_PLLD, reg); |
158 | ||
159 | /* Get current value of fbdv. */ | |
160 | temp = (reg & PLLD_FBDV_MASK) >> 24; | |
161 | fbdv = temp ? temp : 32; | |
162 | ||
163 | /* Get current value of lfbdv. */ | |
164 | temp = (reg & PLLD_LFBDV_MASK); | |
165 | lfbdv = temp ? temp : 64; | |
166 | ||
c550afad RS |
167 | /* |
168 | * Get current value of FWDVA. Assign current FWDVA to | |
169 | * new FWDVB. | |
170 | */ | |
171 | mfcpr(CPR0_PLLD, reg); | |
172 | target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; | |
173 | fwdvb = target_fwdvb ? target_fwdvb : 8; | |
c1ab75c7 | 174 | |
c550afad RS |
175 | /* |
176 | * Get current value of FWDVB. Assign current FWDVB to | |
177 | * new FWDVA. | |
178 | */ | |
179 | target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; | |
180 | fwdva = target_fwdva ? target_fwdva : 16; | |
c1ab75c7 | 181 | |
c550afad RS |
182 | /* |
183 | * Update CPR0_PLLD with switched FWDVA and FWDVB. | |
184 | */ | |
185 | reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | | |
186 | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); | |
187 | reg |= ((fwdva == 16 ? 0 : fwdva) << 16) | | |
188 | ((fwdvb == 8 ? 0 : fwdvb) << 8) | | |
189 | ((fbdv == 32 ? 0 : fbdv) << 24) | | |
190 | (lfbdv == 64 ? 0 : lfbdv); | |
191 | mtcpr(CPR0_PLLD, reg); | |
c1ab75c7 | 192 | |
c550afad RS |
193 | /* Acknowledge that a reset is required. */ |
194 | reset_needed = 1; | |
195 | } | |
196 | } | |
197 | ||
fe7cca71 SR |
198 | /* Now reset the CPU if needed */ |
199 | if (reset_needed) | |
200 | reset_with_rli(); | |
201 | #endif | |
202 | ||
203 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
204 | u32 reg; | |
205 | ||
206 | /* | |
207 | * See "9.2.1.1 Booting with Option E" in the 460EX/GT | |
208 | * users manual | |
209 | */ | |
210 | mfcpr(CPR0_PLLC, reg); | |
211 | if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) { | |
c550afad | 212 | /* |
fe7cca71 | 213 | * Set engage bit |
c550afad | 214 | */ |
fe7cca71 SR |
215 | reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG; |
216 | mtcpr(CPR0_PLLC, reg); | |
f66e2c8b | 217 | |
fe7cca71 SR |
218 | /* Now reset the CPU */ |
219 | reset_with_rli(); | |
f66e2c8b MN |
220 | } |
221 | #endif | |
222 | } | |
223 | ||
4a9cbbe8 WD |
224 | /* |
225 | * Breath some life into the CPU... | |
226 | * | |
f66e2c8b MN |
227 | * Reconfigure PLL if necessary, |
228 | * set up the memory map, | |
4a9cbbe8 WD |
229 | * initialize a bunch of registers |
230 | */ | |
231 | void | |
232 | cpu_init_f (void) | |
233 | { | |
f5564837 | 234 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) |
745d8a0d | 235 | u32 val; |
f11033e7 | 236 | #endif |
5de85140 | 237 | |
6d0f6bcf | 238 | reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); |
f11033e7 | 239 | |
6d0f6bcf | 240 | #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) |
b867d705 SR |
241 | /* |
242 | * GPIO0 setup (select GPIO or alternate function) | |
243 | */ | |
6d0f6bcf JCPV |
244 | #if defined(CONFIG_SYS_GPIO0_OR) |
245 | out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ | |
e0a46554 | 246 | #endif |
6d0f6bcf JCPV |
247 | #if defined(CONFIG_SYS_GPIO0_ODR) |
248 | out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ | |
e0a46554 | 249 | #endif |
6d0f6bcf JCPV |
250 | out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ |
251 | out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); | |
252 | out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ | |
253 | out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); | |
254 | out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ | |
255 | out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); | |
256 | #if defined(CONFIG_SYS_GPIO0_ISR2H) | |
257 | out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); | |
258 | out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); | |
dbbd1257 | 259 | #endif |
6d0f6bcf JCPV |
260 | #if defined (CONFIG_SYS_GPIO0_TCR) |
261 | out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ | |
dbbd1257 | 262 | #endif |
6d0f6bcf | 263 | #endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ |
b867d705 | 264 | |
bec92646 | 265 | #if defined (CONFIG_405EP) |
b867d705 SR |
266 | /* |
267 | * Set EMAC noise filter bits | |
268 | */ | |
afabb498 | 269 | mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); |
b867d705 SR |
270 | #endif /* CONFIG_405EP */ |
271 | ||
6d0f6bcf | 272 | #if defined(CONFIG_SYS_4xx_GPIO_TABLE) |
0d974d52 | 273 | gpio_set_chip_configuration(); |
6d0f6bcf | 274 | #endif /* CONFIG_SYS_4xx_GPIO_TABLE */ |
a4c8d138 | 275 | |
4a9cbbe8 WD |
276 | /* |
277 | * External Bus Controller (EBC) Setup | |
278 | */ | |
6d0f6bcf | 279 | #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
a4c8d138 | 280 | #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
e01bd218 | 281 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ |
dbbd1257 | 282 | defined(CONFIG_405EX) || defined(CONFIG_405)) |
4a9cbbe8 WD |
283 | /* |
284 | * Move the next instructions into icache, since these modify the flash | |
285 | * we are running from! | |
286 | */ | |
287 | asm volatile(" bl 0f" ::: "lr"); | |
288 | asm volatile("0: mflr 3" ::: "r3"); | |
1636d1c8 | 289 | asm volatile(" addi 4, 0, 14" ::: "r4"); |
4a9cbbe8 WD |
290 | asm volatile(" mtctr 4" ::: "ctr"); |
291 | asm volatile("1: icbt 0, 3"); | |
292 | asm volatile(" addi 3, 3, 32" ::: "r3"); | |
293 | asm volatile(" bdnz 1b" ::: "ctr", "cr0"); | |
294 | asm volatile(" addis 3, 0, 0x0" ::: "r3"); | |
295 | asm volatile(" ori 3, 3, 0xA000" ::: "r3"); | |
296 | asm volatile(" mtctr 3" ::: "ctr"); | |
297 | asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); | |
a4c8d138 | 298 | #endif |
4a9cbbe8 | 299 | |
d1c3b275 SR |
300 | mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); |
301 | mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); | |
4a9cbbe8 WD |
302 | #endif |
303 | ||
6d0f6bcf | 304 | #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) |
d1c3b275 SR |
305 | mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); |
306 | mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); | |
4a9cbbe8 WD |
307 | #endif |
308 | ||
6d0f6bcf | 309 | #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) |
d1c3b275 SR |
310 | mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); |
311 | mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); | |
4a9cbbe8 WD |
312 | #endif |
313 | ||
6d0f6bcf | 314 | #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) |
d1c3b275 SR |
315 | mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); |
316 | mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); | |
4a9cbbe8 WD |
317 | #endif |
318 | ||
6d0f6bcf | 319 | #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) |
d1c3b275 SR |
320 | mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); |
321 | mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); | |
4a9cbbe8 WD |
322 | #endif |
323 | ||
6d0f6bcf | 324 | #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) |
d1c3b275 SR |
325 | mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); |
326 | mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); | |
4a9cbbe8 WD |
327 | #endif |
328 | ||
6d0f6bcf | 329 | #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) |
d1c3b275 SR |
330 | mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); |
331 | mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); | |
4a9cbbe8 WD |
332 | #endif |
333 | ||
6d0f6bcf | 334 | #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) |
d1c3b275 SR |
335 | mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); |
336 | mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); | |
4a9cbbe8 WD |
337 | #endif |
338 | ||
6d0f6bcf JCPV |
339 | #if defined (CONFIG_SYS_EBC_CFG) |
340 | mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); | |
ca43ba18 | 341 | #endif |
4a9cbbe8 | 342 | |
f11033e7 | 343 | #if defined(CONFIG_WATCHDOG) |
4a9cbbe8 | 344 | val = mfspr(tcr); |
846b0dd2 | 345 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 | 346 | val |= 0xb8000000; /* generate system reset after 1.34 seconds */ |
a11e0696 IL |
347 | #elif defined(CONFIG_440EPX) |
348 | val |= 0xb0000000; /* generate system reset after 1.34 seconds */ | |
c157d8e2 | 349 | #else |
4a9cbbe8 | 350 | val |= 0xf0000000; /* generate system reset after 2.684 seconds */ |
1c2ce226 | 351 | #endif |
6d0f6bcf | 352 | #if defined(CONFIG_SYS_4xx_RESET_TYPE) |
1c2ce226 | 353 | val &= ~0x30000000; /* clear WRC bits */ |
6d0f6bcf | 354 | val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ |
c157d8e2 | 355 | #endif |
4a9cbbe8 WD |
356 | mtspr(tcr, val); |
357 | ||
358 | val = mfspr(tsr); | |
359 | val |= 0x80000000; /* enable watchdog timer */ | |
360 | mtspr(tsr, val); | |
361 | ||
362 | reset_4xx_watchdog(); | |
363 | #endif /* CONFIG_WATCHDOG */ | |
745d8a0d | 364 | |
5de85140 SR |
365 | #if defined(CONFIG_440GX) |
366 | /* Take the GX out of compatibility mode | |
367 | * Travis Sawyer, 9 Mar 2004 | |
368 | * NOTE: 440gx user manual inconsistency here | |
369 | * Compatibility mode and Ethernet Clock select are not | |
370 | * correct in the manual | |
371 | */ | |
d1c3b275 | 372 | mfsdr(SDR0_MFR, val); |
5de85140 | 373 | val &= ~0x10000000; |
d1c3b275 | 374 | mtsdr(SDR0_MFR,val); |
5de85140 SR |
375 | #endif /* CONFIG_440GX */ |
376 | ||
745d8a0d SR |
377 | #if defined(CONFIG_460EX) |
378 | /* | |
379 | * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and | |
380 | * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata | |
381 | * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA | |
382 | */ | |
383 | mfsdr(SDR0_AHB_CFG, val); | |
384 | val |= 0x80; | |
385 | val &= ~0x40; | |
386 | mtsdr(SDR0_AHB_CFG, val); | |
387 | mfsdr(SDR0_USB2HOST_CFG, val); | |
388 | val &= ~0xf00; | |
389 | val |= 0x400; | |
390 | mtsdr(SDR0_USB2HOST_CFG, val); | |
391 | #endif /* CONFIG_460EX */ | |
079589bc | 392 | |
f5564837 SR |
393 | #if defined(CONFIG_405EX) || \ |
394 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
079589bc | 395 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
f5564837 | 396 | defined(CONFIG_460SX) |
079589bc PH |
397 | /* |
398 | * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read | |
399 | */ | |
5e7abce9 SR |
400 | mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) | |
401 | PLB4Ax_ACR_RDP_4DEEP); | |
402 | mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | | |
403 | PLB4Ax_ACR_RDP_4DEEP); | |
079589bc | 404 | #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ |
4a9cbbe8 WD |
405 | } |
406 | ||
407 | /* | |
408 | * initialize higher level parts of CPU like time base and timers | |
409 | */ | |
410 | int cpu_init_r (void) | |
411 | { | |
b867d705 | 412 | #if defined(CONFIG_405GP) |
38daa27d | 413 | uint pvr = get_pvr(); |
38daa27d SR |
414 | |
415 | /* | |
416 | * Set edge conditioning circuitry on PPC405GPr | |
417 | * for compatibility to existing PPC405GP designs. | |
418 | */ | |
baa3d528 | 419 | if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { |
d1c3b275 | 420 | mtdcr(CPC0_ECR, 0x60606000); |
38daa27d | 421 | } |
b867d705 | 422 | #endif /* defined(CONFIG_405GP) */ |
2801b2d2 | 423 | |
9cd69016 | 424 | return 0; |
4a9cbbe8 | 425 | } |
5e47f953 SR |
426 | |
427 | #if defined(CONFIG_PCI) && \ | |
428 | (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ | |
429 | defined(CONFIG_440GR) || defined(CONFIG_440GRX)) | |
430 | /* | |
431 | * 440EP(x)/GR(x) PCI async/sync clocking restriction: | |
432 | * | |
433 | * In asynchronous PCI mode, the synchronous PCI clock must meet | |
434 | * certain requirements. The following equation describes the | |
435 | * relationship that must be maintained between the asynchronous PCI | |
436 | * clock and synchronous PCI clock. Select an appropriate PCI:PLB | |
437 | * ratio to maintain the relationship: | |
438 | * | |
439 | * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz | |
440 | */ | |
441 | static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async) | |
442 | { | |
443 | if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000))) | |
444 | return 0; | |
445 | else | |
446 | return 1; | |
447 | } | |
448 | ||
449 | int ppc4xx_pci_sync_clock_config(u32 async) | |
450 | { | |
451 | sys_info_t sys_info; | |
452 | u32 sync; | |
453 | int div; | |
454 | u32 reg; | |
455 | u32 spcid_val[] = { | |
456 | CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2, | |
457 | CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 }; | |
458 | ||
459 | get_sys_info(&sys_info); | |
460 | sync = sys_info.freqPCI; | |
461 | ||
462 | /* | |
463 | * First check if the equation above is met | |
464 | */ | |
465 | if (!ppc4xx_pci_sync_clock_ok(sync, async)) { | |
466 | /* | |
467 | * Reconfigure PCI sync clock to meet the equation. | |
468 | * Start with highest possible PCI sync frequency | |
469 | * (divider 1). | |
470 | */ | |
471 | for (div = 1; div <= 4; div++) { | |
472 | sync = sys_info.freqPLB / div; | |
473 | if (ppc4xx_pci_sync_clock_ok(sync, async)) | |
474 | break; | |
475 | } | |
476 | ||
477 | if (div <= 4) { | |
478 | mtcpr(CPR0_SPCID, spcid_val[div]); | |
479 | ||
480 | mfcpr(CPR0_ICFG, reg); | |
481 | reg |= CPR0_ICFG_RLI_MASK; | |
482 | mtcpr(CPR0_ICFG, reg); | |
483 | ||
484 | /* do chip reset */ | |
485 | mtspr(SPRN_DBCR0, 0x20000000); | |
486 | } else { | |
487 | /* Impossible to configure the PCI sync clock */ | |
488 | return -1; | |
489 | } | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | #endif |