[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / gpio.c

/*
 * (C) Copyright 2007-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>

/* Only compile this file for boards with GPIO support */
#if defined(GPIO0_BASE)

#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
#endif

#if defined(GPIO0_OSRL)
/* Only some 4xx variants support alternate funtions on the GPIO's */
void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
{
	u32 mask;
	u32 mask2;
	u32 val;
	u32 offs = 0;
	u32 offs2 = 0;
	int pin2 = pin << 1;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (pin >= GPIO_MAX/2) {
		offs2 = 0x4;
		pin2 = (pin - GPIO_MAX/2) << 1;
	}

	mask = 0x80000000 >> pin;
	mask2 = 0xc0000000 >> pin2;

	/* first set TCR to 0 */
	out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);

	if (in_out == GPIO_OUT) {
		val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
		switch (gpio_alt) {
		case GPIO_ALT1:
			val |= GPIO_ALT1_SEL >> pin2;
			break;
		case GPIO_ALT2:
			val |= GPIO_ALT2_SEL >> pin2;
			break;
		case GPIO_ALT3:
			val |= GPIO_ALT3_SEL >> pin2;
			break;
		}
		out_be32((void *)GPIO0_OSRL + offs + offs2, val);

		/* setup requested output value */
		if (out_val == GPIO_OUT_0)
			out_be32((void *)GPIO0_OR + offs,
				 in_be32((void *)GPIO0_OR + offs) & ~mask);
		else if (out_val == GPIO_OUT_1)
			out_be32((void *)GPIO0_OR + offs,
				 in_be32((void *)GPIO0_OR + offs) | mask);

		/* now configure TCR to drive output if selected */
		out_be32((void *)GPIO0_TCR + offs,
			 in_be32((void *)GPIO0_TCR + offs) | mask);
	} else {
		val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
		val |= GPIO_IN_SEL >> pin2;
		out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
	}
}
#endif /* GPIO_OSRL */

void gpio_write_bit(int pin, int val)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	if (val)
		out_be32((void *)GPIO0_OR + offs,
			 in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
	else
		out_be32((void *)GPIO0_OR + offs,
			 in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
}

int gpio_read_out_bit(int pin)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}

int gpio_read_in_bit(int pin)
{
	u32 offs = 0;

	if (pin >= GPIO_MAX) {
		offs = 0x100;
		pin -= GPIO_MAX;
	}

	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
}

#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
	unsigned char i=0, j=0, offs=0, gpio_core;
	unsigned long reg, core_add;

	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
		j = 0;
		offs = 0;
		/* GPIO config of the GPIOs 0 to 31 */
		for (i=0; i<GPIO_MAX; i++, j++) {
			if (i == GPIO_MAX/2) {
				offs = 4;
				j = i-16;
			}

			core_add = gpio_tab[gpio_core][i].add;

			if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					break;

				case GPIO_ALT1:
					reg = in_be32((void *)GPIO_IS1(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS1(core_add+offs), reg);
					break;

				case GPIO_ALT2:
					reg = in_be32((void *)GPIO_IS2(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS2(core_add+offs), reg);
					break;

				case GPIO_ALT3:
					reg = in_be32((void *)GPIO_IS3(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (GPIO_IN_SEL >> (j*2));
					out_be32((void *)GPIO_IS3(core_add+offs), reg);
					break;
				}
			}

			if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
			    (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {

				u32 gpio_alt_sel = 0;

				switch (gpio_tab[gpio_core][i].alt_nb) {
				case GPIO_SEL:
					/*
					 * Setup output value
					 * 1 -> high level
					 * 0 -> low level
					 * else -> don't touch
					 */
					reg = in_be32((void *)GPIO_OR(core_add));
					if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
						reg |= (0x80000000 >> (i));
					else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
						reg &= ~(0x80000000 >> (i));
					out_be32((void *)GPIO_OR(core_add), reg);

					reg = in_be32((void *)GPIO_TCR(core_add)) |
						(0x80000000 >> (i));
					out_be32((void *)GPIO_TCR(core_add), reg);

					reg = in_be32((void *)GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out_be32((void *)GPIO_OS(core_add+offs), reg);
					reg = in_be32((void *)GPIO_TS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					out_be32((void *)GPIO_TS(core_add+offs), reg);
					break;

				case GPIO_ALT1:
					gpio_alt_sel = GPIO_ALT1_SEL;
					break;

				case GPIO_ALT2:
					gpio_alt_sel = GPIO_ALT2_SEL;
					break;

				case GPIO_ALT3:
					gpio_alt_sel = GPIO_ALT3_SEL;
					break;
				}

				if (0 != gpio_alt_sel) {
					reg = in_be32((void *)GPIO_OS(core_add+offs))
						& ~(GPIO_MASK >> (j*2));
					reg = reg | (gpio_alt_sel >> (j*2));
					out_be32((void *)GPIO_OS(core_add+offs), reg);

					if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
						reg = in_be32((void *)GPIO_TCR(core_add))
							| (0x80000000 >> (i));
						out_be32((void *)GPIO_TCR(core_add), reg);
						reg = in_be32((void *)GPIO_TS(core_add+offs))
							& ~(GPIO_MASK >> (j*2));
						out_be32((void *)GPIO_TS(core_add+offs), reg);
					} else {
						reg = in_be32((void *)GPIO_TCR(core_add))
							& ~(0x80000000 >> (i));
						out_be32((void *)GPIO_TCR(core_add), reg);
						reg = in_be32((void *)GPIO_TS(core_add+offs))
							& ~(GPIO_MASK >> (j*2));
						reg = reg | (gpio_alt_sel >> (j*2));
						out_be32((void *)GPIO_TS(core_add+offs), reg);
					}
				}
			}
		}
	}
}

#endif /* GPIO0_BASE */
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
Commit	Line	Data
3cb86f3e	1	/*
aac7a509	2	* (C) Copyright 2007-2008
3cb86f3e SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
09887762	27	#include <asm/ppc4xx-gpio.h>
3cb86f3e	28
afabb498 SR	29	/* Only compile this file for boards with GPIO support */
	30	#if defined(GPIO0_BASE)
	31
6d0f6bcf JCPV	32	#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
6d0f6bcf JCPV	33	gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
3cb86f3e SR	34	#endif
	35
	36	#if defined(GPIO0_OSRL)
	37	/* Only some 4xx variants support alternate funtions on the GPIO's */
	38	void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
	39	{
	40	u32 mask;
	41	u32 mask2;
	42	u32 val;
	43	u32 offs = 0;
	44	u32 offs2 = 0;
	45	int pin2 = pin << 1;
	46
	47	if (pin >= GPIO_MAX) {
	48	offs = 0x100;
	49	pin -= GPIO_MAX;
	50	}
	51
	52	if (pin >= GPIO_MAX/2) {
3b9abdc4	53	offs2 = 0x4;
3cb86f3e SR	54	pin2 = (pin - GPIO_MAX/2) << 1;
	55	}
	56
	57	mask = 0x80000000 >> pin;
aac7a509	58	mask2 = 0xc0000000 >> pin2;
3cb86f3e SR	59
3cb86f3e SR	60	/* first set TCR to 0 */
aee747f1	61	out_be32((void )GPIO0_TCR + offs, in_be32((void )GPIO0_TCR + offs) & ~mask);
3cb86f3e SR	62
3cb86f3e SR	63	if (in_out == GPIO_OUT) {
aee747f1	64	val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
3cb86f3e SR	65	switch (gpio_alt) {
	66	case GPIO_ALT1:
	67	val \|= GPIO_ALT1_SEL >> pin2;
	68	break;
	69	case GPIO_ALT2:
	70	val \|= GPIO_ALT2_SEL >> pin2;
	71	break;
	72	case GPIO_ALT3:
	73	val \|= GPIO_ALT3_SEL >> pin2;
	74	break;
	75	}
aee747f1	76	out_be32((void *)GPIO0_OSRL + offs + offs2, val);
3cb86f3e SR	77
	78	/* setup requested output value */
	79	if (out_val == GPIO_OUT_0)
aee747f1 SR	80	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	81	in_be32((void *)GPIO0_OR + offs) & ~mask);
3cb86f3e	82	else if (out_val == GPIO_OUT_1)
aee747f1 SR	83	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	84	in_be32((void *)GPIO0_OR + offs) \| mask);
3cb86f3e SR	85
3cb86f3e SR	86	/* now configure TCR to drive output if selected */
aee747f1 SR	87	out_be32((void *)GPIO0_TCR + offs,
aee747f1 SR	88	in_be32((void *)GPIO0_TCR + offs) \| mask);
3cb86f3e	89	} else {
aee747f1	90	val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
3cb86f3e	91	val \|= GPIO_IN_SEL >> pin2;
aee747f1	92	out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
3cb86f3e SR	93	}
	94	}
	95	#endif /* GPIO_OSRL */
	96
	97	void gpio_write_bit(int pin, int val)
	98	{
	99	u32 offs = 0;
	100
	101	if (pin >= GPIO_MAX) {
	102	offs = 0x100;
	103	pin -= GPIO_MAX;
	104	}
	105
	106	if (val)
aee747f1 SR	107	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	108	in_be32((void *)GPIO0_OR + offs) \| GPIO_VAL(pin));
3cb86f3e	109	else
aee747f1 SR	110	out_be32((void *)GPIO0_OR + offs,
aee747f1 SR	111	in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
3cb86f3e SR	112	}
3cb86f3e SR	113
85f73737 SR	114	int gpio_read_out_bit(int pin)
	115	{
	116	u32 offs = 0;
	117
	118	if (pin >= GPIO_MAX) {
	119	offs = 0x100;
	120	pin -= GPIO_MAX;
	121	}
	122
aee747f1	123	return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
85f73737 SR	124	}
85f73737 SR	125
5ab884b2 LJ	126	int gpio_read_in_bit(int pin)
	127	{
	128	u32 offs = 0;
	129
	130	if (pin >= GPIO_MAX) {
	131	offs = 0x100;
	132	pin -= GPIO_MAX;
	133	}
	134
	135	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
	136	}
	137
6d0f6bcf	138	#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
3cb86f3e SR	139	void gpio_set_chip_configuration(void)
	140	{
	141	unsigned char i=0, j=0, offs=0, gpio_core;
	142	unsigned long reg, core_add;
	143
	144	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
	145	j = 0;
	146	offs = 0;
	147	/* GPIO config of the GPIOs 0 to 31 */
	148	for (i=0; i<GPIO_MAX; i++, j++) {
	149	if (i == GPIO_MAX/2) {
	150	offs = 4;
	151	j = i-16;
	152	}
	153
	154	core_add = gpio_tab[gpio_core][i].add;
	155
	156	if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) \|\|
	157	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	158
	159	switch (gpio_tab[gpio_core][i].alt_nb) {
	160	case GPIO_SEL:
	161	break;
	162
	163	case GPIO_ALT1:
aee747f1	164	reg = in_be32((void *)GPIO_IS1(core_add+offs))
3cb86f3e SR	165	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	166	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	167	out_be32((void *)GPIO_IS1(core_add+offs), reg);
3cb86f3e SR	168	break;
	169
	170	case GPIO_ALT2:
aee747f1	171	reg = in_be32((void *)GPIO_IS2(core_add+offs))
3cb86f3e SR	172	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	173	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	174	out_be32((void *)GPIO_IS2(core_add+offs), reg);
3cb86f3e SR	175	break;
	176
	177	case GPIO_ALT3:
aee747f1	178	reg = in_be32((void *)GPIO_IS3(core_add+offs))
3cb86f3e SR	179	& ~(GPIO_MASK >> (j*2));
3cb86f3e SR	180	reg = reg \| (GPIO_IN_SEL >> (j*2));
aee747f1	181	out_be32((void *)GPIO_IS3(core_add+offs), reg);
3cb86f3e SR	182	break;
	183	}
	184	}
	185
	186	if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) \|\|
	187	(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
	188
5ab884b2 LJ	189	u32 gpio_alt_sel = 0;
5ab884b2 LJ	190
3cb86f3e SR	191	switch (gpio_tab[gpio_core][i].alt_nb) {
3cb86f3e SR	192	case GPIO_SEL:
aee747f1 SR	193	/*
	194	* Setup output value
	195	* 1 -> high level
	196	* 0 -> low level
	197	* else -> don't touch
	198	*/
	199	reg = in_be32((void *)GPIO_OR(core_add));
	200	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
	201	reg \|= (0x80000000 >> (i));
	202	else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
	203	reg &= ~(0x80000000 >> (i));
	204	out_be32((void *)GPIO_OR(core_add), reg);
	205
	206	reg = in_be32((void *)GPIO_TCR(core_add)) \|
	207	(0x80000000 >> (i));
	208	out_be32((void *)GPIO_TCR(core_add), reg);
	209
	210	reg = in_be32((void *)GPIO_OS(core_add+offs))
3cb86f3e	211	& ~(GPIO_MASK >> (j*2));
aee747f1 SR	212	out_be32((void *)GPIO_OS(core_add+offs), reg);
aee747f1 SR	213	reg = in_be32((void *)GPIO_TS(core_add+offs))
3cb86f3e	214	& ~(GPIO_MASK >> (j*2));
aee747f1	215	out_be32((void *)GPIO_TS(core_add+offs), reg);
3cb86f3e SR	216	break;
	217
	218	case GPIO_ALT1:
5ab884b2	219	gpio_alt_sel = GPIO_ALT1_SEL;
3cb86f3e SR	220	break;
	221
	222	case GPIO_ALT2:
5ab884b2	223	gpio_alt_sel = GPIO_ALT2_SEL;
3cb86f3e SR	224	break;
	225
	226	case GPIO_ALT3:
5ab884b2 LJ	227	gpio_alt_sel = GPIO_ALT3_SEL;
	228	break;
	229	}
	230
	231	if (0 != gpio_alt_sel) {
aee747f1	232	reg = in_be32((void *)GPIO_OS(core_add+offs))
3cb86f3e	233	& ~(GPIO_MASK >> (j*2));
5ab884b2	234	reg = reg \| (gpio_alt_sel >> (j*2));
aee747f1	235	out_be32((void *)GPIO_OS(core_add+offs), reg);
5ab884b2 LJ	236
	237	if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
	238	reg = in_be32((void *)GPIO_TCR(core_add))
	239	\| (0x80000000 >> (i));
	240	out_be32((void *)GPIO_TCR(core_add), reg);
	241	reg = in_be32((void *)GPIO_TS(core_add+offs))
	242	& ~(GPIO_MASK >> (j*2));
	243	out_be32((void *)GPIO_TS(core_add+offs), reg);
	244	} else {
	245	reg = in_be32((void *)GPIO_TCR(core_add))
	246	& ~(0x80000000 >> (i));
	247	out_be32((void *)GPIO_TCR(core_add), reg);
	248	reg = in_be32((void *)GPIO_TS(core_add+offs))
	249	& ~(GPIO_MASK >> (j*2));
	250	reg = reg \| (gpio_alt_sel >> (j*2));
	251	out_be32((void *)GPIO_TS(core_add+offs), reg);
	252	}
3cb86f3e SR	253	}
	254	}
	255	}
	256	}
	257	}
afabb498 SR	258
afabb498 SR	259	#endif /* GPIO0_BASE */
6d0f6bcf	260	#endif /* CONFIG_SYS_4xx_GPIO_TABLE */