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drivers/serial: Move conditional compilation to Makefile for CONFIG_* macros
[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c
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887e2ec9 1/*
5a5958b7 2 * (C) Copyright 2006-2007
887e2ec9
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
865f0f97 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR		 26#include <libfdt.h>
27#include <fdt_support.h>
28#include <ppc440.h>
b05e8bf5 29#include <asm/gpio.h>
887e2ec9 30#include <asm/processor.h>
5a5958b7 31#include <asm/io.h>
83a49c8d 32#include <asm/bitops.h>
1f84021a 33#include <asm/ppc4xx-intvec.h>
887e2ec9
SR		 34
35DECLARE_GLOBAL_DATA_PTR;
36
83a49c8d 37extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
887e2ec9 38
1b3c360c
SR		 39ulong flash_get_size (ulong base, int banknum);
40
887e2ec9
SR		 41int board_early_init_f(void)
42{
a78bc443
SR		 43 u32 sdr0_cust0;
44 u32 sdr0_pfc1, sdr0_pfc2;
45 u32 reg;
887e2ec9
SR		 46
47 mtdcr(ebccfga, xbcfg);
48 mtdcr(ebccfgd, 0xb8400000);
49
83a49c8d 50 /*
887e2ec9 51 * Setup the interrupt controller polarities, triggers, etc.
83a49c8d 52 */
887e2ec9
SR		 53 mtdcr(uic0sr, 0xffffffff); /* clear all */
54 mtdcr(uic0er, 0x00000000); /* disable all */
55 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
56 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
57 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
58 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
59 mtdcr(uic0sr, 0xffffffff); /* clear all */
60
61 mtdcr(uic1sr, 0xffffffff); /* clear all */
62 mtdcr(uic1er, 0x00000000); /* disable all */
63 mtdcr(uic1cr, 0x00000000); /* all non-critical */
64 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
65 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
66 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
67 mtdcr(uic1sr, 0xffffffff); /* clear all */
68
69 mtdcr(uic2sr, 0xffffffff); /* clear all */
70 mtdcr(uic2er, 0x00000000); /* disable all */
71 mtdcr(uic2cr, 0x00000000); /* all non-critical */
72 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
73 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
74 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
75 mtdcr(uic2sr, 0xffffffff); /* clear all */
76
77 /* 50MHz tmrclk */
d3471173 78 out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR		 79
80 /* clear write protects */
d3471173 81 out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR		 82
83 /* enable Ethernet */
d3471173 84 out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR		 85
86 /* enable USB device */
d3471173 87 out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
887e2ec9 88
b738654d 89 /* select Ethernet (and optionally IIC1) pins */
887e2ec9 90 mfsdr(SDR0_PFC1, sdr0_pfc1);
83a49c8d
MF		 91 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
92 SDR0_PFC1_SELECT_CONFIG_4;
b738654d
MN		 93#ifdef CONFIG_I2C_MULTI_BUS
94 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
95#endif
887e2ec9 96 mfsdr(SDR0_PFC2, sdr0_pfc2);
83a49c8d
MF		 97 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
98 SDR0_PFC2_SELECT_CONFIG_4;
887e2ec9
SR		 99 mtsdr(SDR0_PFC2, sdr0_pfc2);
100 mtsdr(SDR0_PFC1, sdr0_pfc1);
101
102 /* PCI arbiter enabled */
103 mfsdr(sdr_pci0, reg);
104 mtsdr(sdr_pci0, 0x80000000 | reg);
105
106 /* setup NAND FLASH */
107 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 108 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR		 109 SDR0_CUST0_NDFC_ENABLE |
110 SDR0_CUST0_NDFC_BW_8_BIT |
111 SDR0_CUST0_NDFC_ARE_MASK |
112 (0x80000000 >> (28 + CFG_NAND_CS));
511d0c72 113 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR		 114
115 return 0;
116}
117
887e2ec9
SR		 118int misc_init_r(void)
119{
120 uint pbcr;
121 int size_val = 0;
a78bc443 122 u32 reg;
854bc8da 123#ifdef CONFIG_440EPX
887e2ec9
SR		 124 unsigned long usb2d0cr = 0;
125 unsigned long usb2phy0cr, usb2h0cr = 0;
126 unsigned long sdr0_pfc1;
127 char *act = getenv("usbact");
854bc8da 128#endif
887e2ec9 129
83a49c8d 130 /* Re-do flash sizing to get full correct info */
1b3c360c
SR		 131
132 /* adjust flash start and offset */
133 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
134 gd->bd->bi_flashoffset = 0;
135
887e2ec9
SR		 136#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
137 mtdcr(ebccfga, pb3cr);
138#else
139 mtdcr(ebccfga, pb0cr);
140#endif
141 pbcr = mfdcr(ebccfgd);
865f0f97 142 size_val = ffs(gd->bd->bi_flashsize) - 21;
887e2ec9
SR		 143 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
144#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
145 mtdcr(ebccfga, pb3cr);
146#else
147 mtdcr(ebccfga, pb0cr);
148#endif
149 mtdcr(ebccfgd, pbcr);
150
1b3c360c
SR		 151 /*
152 * Re-check to get correct base address
153 */
154 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9
SR		 155
156#ifdef CFG_ENV_IS_IN_FLASH
157 /* Monitor protection ON by default */
158 (void)flash_protect(FLAG_PROTECT_SET,
159 -CFG_MONITOR_LEN,
160 0xffffffff,
161 &flash_info[0]);
162
163 /* Env protection ON by default */
164 (void)flash_protect(FLAG_PROTECT_SET,
165 CFG_ENV_ADDR_REDUND,
166 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
167 &flash_info[0]);
168#endif
169
170 /*
171 * USB suff...
172 */
854bc8da 173#ifdef CONFIG_440EPX
83a49c8d 174 if (act == NULL || strcmp(act, "hostdev") == 0) {
887e2ec9 175 /* SDR Setting */
511d0c72 176 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 177 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 178 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
179 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 180
181 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 182 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 183 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 184 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
887e2ec9 185 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 186 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 187 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 188 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 189 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 190 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9 191
83a49c8d
MF		 192 /*
193 * An 8-bit/60MHz interface is the only possible alternative
194 * when connecting the Device to the PHY
195 */
511d0c72 196 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 197 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
887e2ec9 198
83a49c8d
MF		 199 /*
200 * To enable the USB 2.0 Device function
201 * through the UTMI interface
202 */
511d0c72 203 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 204 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
887e2ec9 205
511d0c72 206 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 207 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
887e2ec9 208
511d0c72 209 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 210 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 211 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
212 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 213
214 /*clear resets*/
215 udelay (1000);
216 mtsdr(SDR0_SRST1, 0x00000000);
217 udelay (1000);
218 mtsdr(SDR0_SRST0, 0x00000000);
219
220 printf("USB: Host(int phy) Device(ext phy)\n");
221
222 } else if (strcmp(act, "dev") == 0) {
223 /*-------------------PATCH-------------------------------*/
224 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225
226 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 227 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
887e2ec9 228 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 229 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 230 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 231 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 232 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 233 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9
SR		 234 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
235
236 udelay (1000);
237 mtsdr(SDR0_SRST1, 0x672c6000);
238
239 udelay (1000);
240 mtsdr(SDR0_SRST0, 0x00000080);
241
242 udelay (1000);
243 mtsdr(SDR0_SRST1, 0x60206000);
244
245 *(unsigned int *)(0xe0000350) = 0x00000001;
246
247 udelay (1000);
248 mtsdr(SDR0_SRST1, 0x60306000);
249 /*-------------------PATCH-------------------------------*/
250
251 /* SDR Setting */
511d0c72 252 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 253 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 254 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 255 mfsdr(SDR0_PFC1, sdr0_pfc1);
256
257 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 258 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 259 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 260 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
887e2ec9 261 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 262 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
887e2ec9 263 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 264 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
887e2ec9 265 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 266 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
887e2ec9
SR		 267
268 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 269 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
887e2ec9
SR		 270
271 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 272 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
887e2ec9
SR		 273
274 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 275 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
887e2ec9 276
511d0c72
WD		 277 mtsdr(SDR0_USB2H0CR, usb2h0cr);
278 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 279 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 280 mtsdr(SDR0_PFC1, sdr0_pfc1);
281
83a49c8d 282 /* clear resets */
887e2ec9
SR		 283 udelay (1000);
284 mtsdr(SDR0_SRST1, 0x00000000);
285 udelay (1000);
286 mtsdr(SDR0_SRST0, 0x00000000);
287
288 printf("USB: Device(int phy)\n");
289 }
854bc8da 290#endif /* CONFIG_440EPX */
887e2ec9 291
8ce16f55
JO		 292 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
293 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
294 mtsdr(SDR0_SRST1, reg);
295
a78bc443
SR		 296 /*
297 * Clear PLB4A0_ACR[WRP]
298 * This fix will make the MAL burst disabling patch for the Linux
299 * EMAC driver obsolete.
300 */
301 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
302 mtdcr(plb4_acr, reg);
303
887e2ec9
SR		 304 return 0;
305}
306
307int checkboard(void)
308{
309 char *s = getenv("serial#");
e0b9ea8c
SR		 310 u8 rev;
311 u8 val;
887e2ec9 312
854bc8da 313#ifdef CONFIG_440EPX
887e2ec9 314 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR		 315#else
316 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
317#endif
e0b9ea8c 318
5a5958b7
SR		 319 rev = in_8((void *)(CFG_BCSR_BASE + 0));
320 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
e0b9ea8c
SR		 321 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
322
887e2ec9
SR		 323 if (s != NULL) {
324 puts(", serial# ");
325 puts(s);
326 }
327 putc('\n');
328
329 return (0);
330}
331
1f84021a
MF		 332#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
333/*
334 * Assign interrupts to PCI devices.
335 */
336void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
337{
338 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
339}
340#endif
341
83a49c8d
MF		 342/*
343 * pci_pre_init
887e2ec9 344 *
83a49c8d
MF		 345 * This routine is called just prior to registering the hose and gives
346 * the board the opportunity to check things. Returning a value of zero
347 * indicates that things are bad & PCI initialization should be aborted.
887e2ec9 348 *
83a49c8d
MF		 349 * Different boards may wish to customize the pci controller structure
350 * (add regions, override default access routines, etc) or perform
351 * certain pre-initialization actions.
352 */
466fff1a 353#if defined(CONFIG_PCI)
887e2ec9
SR		 354int pci_pre_init(struct pci_controller *hose)
355{
356 unsigned long addr;
887e2ec9 357
83a49c8d
MF		 358 /*
359 * Set priority for all PLB3 devices to 0.
360 * Set PLB3 arbiter to fair mode.
361 */
887e2ec9
SR		 362 mfsdr(sdr_amp1, addr);
363 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
364 addr = mfdcr(plb3_acr);
365 mtdcr(plb3_acr, addr | 0x80000000);
366
83a49c8d
MF		 367 /*
368 * Set priority for all PLB4 devices to 0.
369 */
887e2ec9
SR		 370 mfsdr(sdr_amp0, addr);
371 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
372 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
373 mtdcr(plb4_acr, addr);
374
83a49c8d
MF		 375 /*
376 * Set Nebula PLB4 arbiter to fair mode.
377 */
887e2ec9
SR		 378 /* Segment0 */
379 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
380 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
381 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
382 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
383 mtdcr(plb0_acr, addr);
384
385 /* Segment1 */
386 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
387 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
388 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
389 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
390 mtdcr(plb1_acr, addr);
391
1f84021a
MF		 392#ifdef CONFIG_PCI_PNP
393 hose->fixup_irq = sequoia_pci_fixup_irq;
394#endif
887e2ec9
SR		 395 return 1;
396}
466fff1a 397#endif /* defined(CONFIG_PCI) */
887e2ec9 398
83a49c8d
MF		 399/*
400 * pci_target_init
887e2ec9 401 *
83a49c8d
MF		 402 * The bootstrap configuration provides default settings for the pci
403 * inbound map (PIM). But the bootstrap config choices are limited and
404 * may not be sufficient for a given board.
405 */
887e2ec9
SR		 406#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
407void pci_target_init(struct pci_controller *hose)
408{
83a49c8d 409 /*
887e2ec9 410 * Set up Direct MMIO registers
83a49c8d
MF		 411 */
412 /*
413 * PowerPC440EPX PCI Master configuration.
414 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
415 * PLB address 0xA0000000-0xDFFFFFFF
416 * ==> PCI address 0xA0000000-0xDFFFFFFF
417 * Use byte reversed out routines to handle endianess.
418 * Make this region non-prefetchable.
419 */
420 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
421 /* - disabled b4 setting */
887e2ec9 422 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
83a49c8d 423 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
887e2ec9 424 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF		 425 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
426 /* and enable region */
887e2ec9 427
83a49c8d
MF		 428 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
429 /* - disabled b4 setting */
887e2ec9 430 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
83a49c8d 431 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
887e2ec9 432 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF		 433 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
434 /* and enable region */
887e2ec9
SR		 435
436 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
83a49c8d
MF		 437 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
438 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
439 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
887e2ec9 440
83a49c8d 441 /*
887e2ec9 442 * Set up Configuration registers
83a49c8d 443 */
887e2ec9
SR		 444
445 /* Program the board's subsystem id/vendor id */
446 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
447 CFG_PCI_SUBSYS_VENDORID);
448 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
449
450 /* Configure command register as bus master */
451 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
452
453 /* 240nS PCI clock */
454 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
455
456 /* No error reporting */
457 pci_write_config_word(0, PCI_ERREN, 0);
458
459 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
460
461}
83a49c8d 462#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
887e2ec9 463
887e2ec9
SR		 464#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
465void pci_master_init(struct pci_controller *hose)
466{
467 unsigned short temp_short;
468
83a49c8d
MF		 469 /*
470 * Write the PowerPC440 EP PCI Configuration regs.
471 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
472 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
473 */
887e2ec9
SR		 474 pci_read_config_word(0, PCI_COMMAND, &temp_short);
475 pci_write_config_word(0, PCI_COMMAND,
476 temp_short | PCI_COMMAND_MASTER |
477 PCI_COMMAND_MEMORY);
478}
83a49c8d 479#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
887e2ec9 480
83a49c8d
MF		 481/*
482 * is_pci_host
887e2ec9 483 *
83a49c8d
MF		 484 * This routine is called to determine if a pci scan should be
485 * performed. With various hardware environments (especially cPCI and
486 * PPMC) it's insufficient to depend on the state of the arbiter enable
487 * bit in the strap register, or generic host/adapter assumptions.
887e2ec9 488 *
83a49c8d
MF		 489 * Rather than hard-code a bad assumption in the general 440 code, the
490 * 440 pci code requires the board to decide at runtime.
887e2ec9 491 *
83a49c8d
MF		 492 * Return 0 for adapter mode, non-zero for host (monarch) mode.
493 */
887e2ec9
SR		 494#if defined(CONFIG_PCI)
495int is_pci_host(struct pci_controller *hose)
496{
497 /* Cactus is always configured as host. */
498 return (1);
499}
83a49c8d
MF		 500#endif /* defined(CONFIG_PCI) */
501
a11e0696
IL		 502#if defined(CONFIG_POST)
503/*
504 * Returns 1 if keys pressed to start the power-on long-running tests
505 * Called from board_init_f().
506 */
507int post_hotkeys_pressed(void)
508{
509 return 0; /* No hotkeys supported */
510}
511#endif /* CONFIG_POST */
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