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board: am335x: Introduce scale_vcores
[people/ms/u-boot.git] / board / ti / am335x / board.c
CommitLineData
e363426e
PK		 1/*
2 * board.c
3 *
4 * Board functions for TI AM335X based boards
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
e363426e
PK		 9 */
10
11#include <common.h>
4548bc8d 12#include <dm.h>
e363426e
PK		 13#include <errno.h>
14#include <spl.h>
3d16389c 15#include <serial.h>
e363426e
PK		 16#include <asm/arch/cpu.h>
17#include <asm/arch/hardware.h>
18#include <asm/arch/omap.h>
19#include <asm/arch/ddr_defs.h>
20#include <asm/arch/clock.h>
97f3a178 21#include <asm/arch/clk_synthesizer.h>
e363426e
PK		 22#include <asm/arch/gpio.h>
23#include <asm/arch/mmc_host_def.h>
24#include <asm/arch/sys_proto.h>
cd8845d7 25#include <asm/arch/mem.h>
e363426e
PK		 26#include <asm/io.h>
27#include <asm/emif.h>
28#include <asm/gpio.h>
b0a4eea1 29#include <asm/omap_sec_common.h>
4548bc8d 30#include <asm/omap_mmc.h>
e363426e
PK		 31#include <i2c.h>
32#include <miiphy.h>
33#include <cpsw.h>
9721027a
TR		 34#include <power/tps65217.h>
35#include <power/tps65910.h>
6843918e
TR		 36#include <environment.h>
37#include <watchdog.h>
ba9a6708 38#include <environment.h>
770e68c0 39#include "../common/board_detect.h"
e363426e
PK		 40#include "board.h"
41
42DECLARE_GLOBAL_DATA_PTR;
43
e363426e 44/* GPIO that controls power to DDR on EVM-SK */
97f3a178
LV		 45#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
46#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
47#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
48#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
49#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
50#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
51#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
e607ec99
RQ		 52#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
53#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
e363426e
PK		 54
55static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
56
e607ec99
RQ		 57#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
58#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
59
60#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
61#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
62
63#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
64#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
65
e363426e
PK		 66/*
67 * Read header information from EEPROM into global structure.
68 */
140d76a9
LV		 69#ifdef CONFIG_TI_I2C_BOARD_DETECT
70void do_board_detect(void)
e363426e 71{
140d76a9
LV		 72 enable_i2c0_pin_mux();
73 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
74
75 if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
76 printf("ti_i2c_eeprom_init failed\n");
e363426e 77}
140d76a9 78#endif
e363426e 79
3d16389c
LV		 80#ifndef CONFIG_DM_SERIAL
81struct serial_device *default_serial_console(void)
82{
83 if (board_is_icev2())
84 return &eserial4_device;
85 else
86 return &eserial1_device;
87}
88#endif
89
d0e6d34d 90#ifndef CONFIG_SKIP_LOWLEVEL_INIT
c00f69db 91static const struct ddr_data ddr2_data = {
c4f80f50
TR		 92 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
93 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
94 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
c00f69db 95};
e363426e 96
c00f69db 97static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef 98 .cmd0csratio = MT47H128M16RT25E_RATIO,
c00f69db 99
c7d35bef 100 .cmd1csratio = MT47H128M16RT25E_RATIO,
c00f69db 101
c7d35bef 102 .cmd2csratio = MT47H128M16RT25E_RATIO,
c00f69db
PK		 103};
104
105static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef
PK		 106 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
107 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
108 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
109 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
110 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
111 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db
PK		 112};
113
8c17cbdf
JS		 114static const struct emif_regs ddr2_evm_emif_reg_data = {
115 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
116 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
117 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
118 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
119 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
120 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
121 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
122};
123
c00f69db 124static const struct ddr_data ddr3_data = {
c7d35bef
PK		 125 .datardsratio0 = MT41J128MJT125_RD_DQS,
126 .datawdsratio0 = MT41J128MJT125_WR_DQS,
127 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
128 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db
PK		 129};
130
c7ba18ad
TR		 131static const struct ddr_data ddr3_beagleblack_data = {
132 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
133 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
134 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
135 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
c7ba18ad
TR		 136};
137
13526f71
JL		 138static const struct ddr_data ddr3_evm_data = {
139 .datardsratio0 = MT41J512M8RH125_RD_DQS,
140 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
141 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
142 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
13526f71
JL		 143};
144
d8ff4fdb
LV		 145static const struct ddr_data ddr3_icev2_data = {
146 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
147 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
148 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
149 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
150};
151
c00f69db 152static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef 153 .cmd0csratio = MT41J128MJT125_RATIO,
c7d35bef 154 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db 155
c7d35bef 156 .cmd1csratio = MT41J128MJT125_RATIO,
c7d35bef 157 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db 158
c7d35bef 159 .cmd2csratio = MT41J128MJT125_RATIO,
c7d35bef 160 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db
PK		 161};
162
c7ba18ad
TR		 163static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
164 .cmd0csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 165 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
166
167 .cmd1csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 168 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
169
170 .cmd2csratio = MT41K256M16HA125E_RATIO,
c7ba18ad
TR		 171 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
172};
173
13526f71
JL		 174static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
175 .cmd0csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 176 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
177
178 .cmd1csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 179 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
180
181 .cmd2csratio = MT41J512M8RH125_RATIO,
13526f71
JL		 182 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
183};
184
d8ff4fdb
LV		 185static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
186 .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
187 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
188
189 .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
190 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
191
192 .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
193 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
194};
195
c00f69db 196static struct emif_regs ddr3_emif_reg_data = {
c7d35bef
PK		 197 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
198 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
199 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
200 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
201 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
202 .zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970
VH		 203 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
204 PHY_EN_DYN_PWRDN,
c00f69db 205};
13526f71 206
c7ba18ad
TR		 207static struct emif_regs ddr3_beagleblack_emif_reg_data = {
208 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
209 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
210 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
211 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
212 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
8c17cbdf 213 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
c7ba18ad
TR		 214 .zq_config = MT41K256M16HA125E_ZQ_CFG,
215 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
216};
217
13526f71
JL		 218static struct emif_regs ddr3_evm_emif_reg_data = {
219 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
220 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
221 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
222 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
223 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
8c17cbdf 224 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
13526f71 225 .zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970
VH		 226 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
227 PHY_EN_DYN_PWRDN,
13526f71 228};
12d7a474 229
d8ff4fdb
LV		 230static struct emif_regs ddr3_icev2_emif_reg_data = {
231 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
232 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
233 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
234 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
235 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
236 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
237 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
238 PHY_EN_DYN_PWRDN,
239};
240
12d7a474
PK		 241#ifdef CONFIG_SPL_OS_BOOT
242int spl_start_uboot(void)
243{
244 /* break into full u-boot on 'c' */
ba9a6708
TR		 245 if (serial_tstc() && serial_getc() == 'c')
246 return 1;
247
248#ifdef CONFIG_SPL_ENV_SUPPORT
249 env_init();
250 env_relocate_spec();
251 if (getenv_yesno("boot_os") != 1)
252 return 1;
253#endif
254
255 return 0;
12d7a474
PK		 256}
257#endif
258
94d77fb6
LV		 259#define OSC (V_OSCK/1000000)
260const struct dpll_params dpll_ddr = {
261 266, OSC-1, 1, -1, -1, -1, -1};
262const struct dpll_params dpll_ddr_evm_sk = {
263 303, OSC-1, 1, -1, -1, -1, -1};
264const struct dpll_params dpll_ddr_bone_black = {
265 400, OSC-1, 1, -1, -1, -1, -1};
266
06507988 267const struct dpll_params *get_dpll_ddr_params(void)
9721027a 268{
06507988
LV		 269 if (board_is_evm_sk())
270 return &dpll_ddr_evm_sk;
271 else if (board_is_bone_lt() || board_is_icev2())
272 return &dpll_ddr_bone_black;
273 else if (board_is_evm_15_or_later())
274 return &dpll_ddr_evm_sk;
275 else
276 return &dpll_ddr;
277}
9721027a 278
06507988
LV		 279static void scale_vcores_bone(int freq)
280{
281 int usb_cur_lim, mpu_vdd;
282
283 /*
284 * Only perform PMIC configurations if board rev > A1
285 * on Beaglebone White
286 */
287 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
288 return;
289
290 if (i2c_probe(TPS65217_CHIP_PM))
291 return;
292
293 /*
294 * On Beaglebone White we need to ensure we have AC power
295 * before increasing the frequency.
296 */
297 if (board_is_bone()) {
298 uchar pmic_status_reg;
299 if (tps65217_reg_read(TPS65217_STATUS,
300 &pmic_status_reg))
9721027a 301 return;
06507988
LV		 302 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
303 puts("No AC power, switching to default OPP\n");
304 freq = MPUPLL_M_600;
9721027a 305 }
06507988 306 }
9721027a 307
06507988
LV		 308 /*
309 * Override what we have detected since we know if we have
310 * a Beaglebone Black it supports 1GHz.
311 */
312 if (board_is_bone_lt())
313 freq = MPUPLL_M_1000;
9721027a 314
06507988
LV		 315 if (freq == MPUPLL_M_1000) {
316 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
317 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
318 } else {
319 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
320 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
321 }
52f7d844 322
06507988
LV		 323 switch (freq) {
324 case MPUPLL_M_1000:
325 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
326 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
327 break;
328 case MPUPLL_M_800:
329 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
330 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
331 break;
332 case MPUPLL_M_720:
333 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
334 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
335 break;
336 case MPUPLL_M_600:
337 case MPUPLL_M_500:
338 case MPUPLL_M_300:
339 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
340 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
341 break;
342 }
9721027a 343
06507988
LV		 344 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
345 TPS65217_POWER_PATH,
346 usb_cur_lim,
347 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
348 puts("tps65217_reg_write failure\n");
349
350 /* Set DCDC3 (CORE) voltage to 1.10V */
351 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
352 TPS65217_DCDC_VOLT_SEL_1100MV)) {
353 puts("tps65217_voltage_update failure\n");
354 return;
355 }
9721027a 356
06507988
LV		 357 /* Set DCDC2 (MPU) voltage */
358 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
359 puts("tps65217_voltage_update failure\n");
360 return;
361 }
9721027a 362
06507988
LV		 363 /*
364 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
365 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
366 */
367 if (board_is_bone()) {
9721027a 368 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
06507988 369 TPS65217_DEFLS1,
9721027a
TR		 370 TPS65217_LDO_VOLTAGE_OUT_3_3,
371 TPS65217_LDO_MASK))
372 puts("tps65217_reg_write failure\n");
373 } else {
06507988
LV		 374 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
375 TPS65217_DEFLS1,
376 TPS65217_LDO_VOLTAGE_OUT_1_8,
377 TPS65217_LDO_MASK))
378 puts("tps65217_reg_write failure\n");
379 }
9721027a 380
06507988
LV		 381 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
382 TPS65217_DEFLS2,
383 TPS65217_LDO_VOLTAGE_OUT_3_3,
384 TPS65217_LDO_MASK))
385 puts("tps65217_reg_write failure\n");
386}
9721027a 387
06507988
LV		 388void scale_vcores_generic(int freq)
389{
390 int sil_rev, mpu_vdd;
391
392 /*
393 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
394 * MPU frequencies we support we use a CORE voltage of
395 * 1.10V. For MPU voltage we need to switch based on
396 * the frequency we are running at.
397 */
398 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
399 return;
400
401 /*
402 * Depending on MPU clock and PG we will need a different
403 * VDD to drive at that speed.
404 */
405 sil_rev = readl(&cdev->deviceid) >> 28;
406 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
407
408 /* Tell the TPS65910 to use i2c */
409 tps65910_set_i2c_control();
410
411 /* First update MPU voltage. */
412 if (tps65910_voltage_update(MPU, mpu_vdd))
413 return;
414
415 /* Second, update the CORE voltage. */
416 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
417 return;
9721027a 418
06507988 419}
52f7d844 420
06507988
LV		 421void gpi2c_init(void)
422{
423 /* When needed to be invoked prior to BSS initialization */
424 static bool first_time = true;
425
426 if (first_time) {
427 enable_i2c0_pin_mux();
428 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
429 CONFIG_SYS_OMAP24_I2C_SLAVE);
430 first_time = false;
9721027a 431 }
9721027a
TR		 432}
433
06507988 434void scale_vcores(void)
94d77fb6 435{
06507988
LV		 436 int freq;
437
438 gpi2c_init();
439 freq = am335x_get_efuse_mpu_max_freq(cdev);
440
441 if (board_is_bone())
442 scale_vcores_bone(freq);
94d77fb6 443 else
06507988 444 scale_vcores_generic(freq);
94d77fb6
LV		 445}
446
0660481a 447void set_uart_mux_conf(void)
e363426e 448{
1286b7f6 449#if CONFIG_CONS_INDEX == 1
e363426e 450 enable_uart0_pin_mux();
1286b7f6 451#elif CONFIG_CONS_INDEX == 2
6422b70b 452 enable_uart1_pin_mux();
1286b7f6 453#elif CONFIG_CONS_INDEX == 3
6422b70b 454 enable_uart2_pin_mux();
1286b7f6 455#elif CONFIG_CONS_INDEX == 4
6422b70b 456 enable_uart3_pin_mux();
1286b7f6 457#elif CONFIG_CONS_INDEX == 5
6422b70b 458 enable_uart4_pin_mux();
1286b7f6 459#elif CONFIG_CONS_INDEX == 6
6422b70b 460 enable_uart5_pin_mux();
1286b7f6 461#endif
0660481a 462}
e363426e 463
0660481a
HS		 464void set_mux_conf_regs(void)
465{
770e68c0 466 enable_board_pin_mux();
0660481a 467}
e363426e 468
965de8b9
LV		 469const struct ctrl_ioregs ioregs_evmsk = {
470 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
471 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
472 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
473 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
474 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
475};
476
477const struct ctrl_ioregs ioregs_bonelt = {
478 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
479 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
480 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
481 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
482 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
483};
484
485const struct ctrl_ioregs ioregs_evm15 = {
486 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
487 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
488 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
489 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
490 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
491};
492
493const struct ctrl_ioregs ioregs = {
494 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
495 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
496 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
497 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
498 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
499};
500
0660481a
HS		 501void sdram_init(void)
502{
770e68c0 503 if (board_is_evm_sk()) {
e363426e
PK		 504 /*
505 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
506 * This is safe enough to do on older revs.
507 */
508 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
509 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
510 }
511
d8ff4fdb
LV		 512 if (board_is_icev2()) {
513 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
514 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
515 }
516
770e68c0 517 if (board_is_evm_sk())
965de8b9 518 config_ddr(303, &ioregs_evmsk, &ddr3_data,
3ba65f97 519 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
770e68c0 520 else if (board_is_bone_lt())
965de8b9 521 config_ddr(400, &ioregs_bonelt,
c7ba18ad
TR		 522 &ddr3_beagleblack_data,
523 &ddr3_beagleblack_cmd_ctrl_data,
524 &ddr3_beagleblack_emif_reg_data, 0);
770e68c0 525 else if (board_is_evm_15_or_later())
965de8b9 526 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
3ba65f97 527 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
d8ff4fdb
LV		 528 else if (board_is_icev2())
529 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
530 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
531 0);
8c17cbdf
JS		 532 else if (board_is_gp_evm())
533 config_ddr(266, &ioregs, &ddr2_data,
534 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
c00f69db 535 else
965de8b9 536 config_ddr(266, &ioregs, &ddr2_data,
3ba65f97 537 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
e363426e 538}
0660481a 539#endif
e363426e 540
e607ec99 541#if !defined(CONFIG_SPL_BUILD) || \
97f3a178 542 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e607ec99 543static void request_and_set_gpio(int gpio, char *name, int val)
97f3a178
LV		 544{
545 int ret;
546
547 ret = gpio_request(gpio, name);
548 if (ret < 0) {
549 printf("%s: Unable to request %s\n", __func__, name);
550 return;
551 }
552
553 ret = gpio_direction_output(gpio, 0);
554 if (ret < 0) {
555 printf("%s: Unable to set %s as output\n", __func__, name);
556 goto err_free_gpio;
557 }
558
e607ec99 559 gpio_set_value(gpio, val);
97f3a178
LV		 560
561 return;
562
563err_free_gpio:
564 gpio_free(gpio);
565}
566
e607ec99
RQ		 567#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
568#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
97f3a178
LV		 569
570/**
571 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
572 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
573 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
574 * give 50MHz output for Eth0 and 1.
575 */
576static struct clk_synth cdce913_data = {
577 .id = 0x81,
578 .capacitor = 0x90,
579 .mux = 0x6d,
580 .pdiv2 = 0x2,
581 .pdiv3 = 0x2,
582};
583#endif
584
e363426e
PK		 585/*
586 * Basic board specific setup. Pinmux has been handled already.
587 */
588int board_init(void)
589{
6843918e
TR		 590#if defined(CONFIG_HW_WATCHDOG)
591 hw_watchdog_init();
592#endif
593
73feefdc 594 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
2c17e6d1 595#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
98b5c269 596 gpmc_init();
cd8845d7 597#endif
97f3a178 598
e607ec99
RQ		 599#if !defined(CONFIG_SPL_BUILD) || \
600 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
97f3a178 601 if (board_is_icev2()) {
e607ec99
RQ		 602 int rv;
603 u32 reg;
604
97f3a178 605 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
e607ec99
RQ		 606 /* Make J19 status available on GPIO1_26 */
607 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
608
97f3a178 609 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
e607ec99
RQ		 610 /*
611 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
612 * jumpers near the port. Read the jumper value and set
613 * the pinmux, external mux and PHY clock accordingly.
614 * As jumper line is overridden by PHY RX_DV pin immediately
615 * after bootstrap (power-up/reset), we need to sample
616 * it during PHY reset using GPIO rising edge detection.
617 */
97f3a178 618 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
e607ec99
RQ		 619 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
620 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
621 writel(reg, GPIO0_RISINGDETECT);
622 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
623 writel(reg, GPIO1_RISINGDETECT);
624 /* Reset PHYs to capture the Jumper setting */
625 gpio_set_value(GPIO_PHY_RESET, 0);
626 udelay(2); /* PHY datasheet states 1uS min. */
627 gpio_set_value(GPIO_PHY_RESET, 1);
628
629 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
630 if (reg) {
631 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
632 /* RMII mode */
633 printf("ETH0, CPSW\n");
634 } else {
635 /* MII mode */
636 printf("ETH0, PRU\n");
637 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
638 }
639
640 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
641 if (reg) {
642 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
643 /* RMII mode */
644 printf("ETH1, CPSW\n");
645 gpio_set_value(GPIO_MUX_MII_CTRL, 1);
646 } else {
647 /* MII mode */
648 printf("ETH1, PRU\n");
649 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
650 }
651
652 /* disable rising edge IRQs */
653 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
654 writel(reg, GPIO0_RISINGDETECT);
655 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
656 writel(reg, GPIO1_RISINGDETECT);
97f3a178
LV		 657
658 rv = setup_clock_synthesizer(&cdce913_data);
659 if (rv) {
660 printf("Clock synthesizer setup failed %d\n", rv);
661 return rv;
662 }
e607ec99
RQ		 663
664 /* reset PHYs */
665 gpio_set_value(GPIO_PHY_RESET, 0);
666 udelay(2); /* PHY datasheet states 1uS min. */
667 gpio_set_value(GPIO_PHY_RESET, 1);
97f3a178
LV		 668 }
669#endif
670
e363426e
PK		 671 return 0;
672}
673
044fc14b
TR		 674#ifdef CONFIG_BOARD_LATE_INIT
675int board_late_init(void)
676{
f411b5cc
RQ		 677#if !defined(CONFIG_SPL_BUILD)
678 uint8_t mac_addr[6];
679 uint32_t mac_hi, mac_lo;
680#endif
681
044fc14b 682#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
770e68c0 683 char *name = NULL;
ace4275e 684
4015949f 685 if (board_is_bone_lt()) {
686 /* BeagleBoard.org BeagleBone Black Wireless: */
687 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
688 name = "BBBW";
2b79fba6 689 }
690 /* SeeedStudio BeagleBone Green Wireless */
691 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
692 name = "BBGW";
52609d75 693 }
694 /* BeagleBoard.org BeagleBone Blue */
695 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
696 name = "BBBL";
4015949f 697 }
698 }
699
770e68c0
NM		 700 if (board_is_bbg1())
701 name = "BBG1";
702 set_board_info_env(name);
5d4d436c
LV		 703
704 /*
705 * Default FIT boot on HS devices. Non FIT images are not allowed
706 * on HS devices.
707 */
708 if (get_device_type() == HS_DEVICE)
709 setenv("boot_fit", "1");
044fc14b
TR		 710#endif
711
f411b5cc
RQ		 712#if !defined(CONFIG_SPL_BUILD)
713 /* try reading mac address from efuse */
714 mac_lo = readl(&cdev->macid0l);
715 mac_hi = readl(&cdev->macid0h);
716 mac_addr[0] = mac_hi & 0xFF;
717 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
718 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
719 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
720 mac_addr[4] = mac_lo & 0xFF;
721 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
722
723 if (!getenv("ethaddr")) {
724 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
725
726 if (is_valid_ethaddr(mac_addr))
727 eth_setenv_enetaddr("ethaddr", mac_addr);
728 }
729
730 mac_lo = readl(&cdev->macid1l);
731 mac_hi = readl(&cdev->macid1h);
732 mac_addr[0] = mac_hi & 0xFF;
733 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
734 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
735 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
736 mac_addr[4] = mac_lo & 0xFF;
737 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
738
739 if (!getenv("eth1addr")) {
740 if (is_valid_ethaddr(mac_addr))
741 eth_setenv_enetaddr("eth1addr", mac_addr);
742 }
743#endif
744
044fc14b
TR		 745 return 0;
746}
747#endif
748
bd83e3df
M		 749#ifndef CONFIG_DM_ETH
750
c0e66793
IY		 751#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
752 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e
PK		 753static void cpsw_control(int enabled)
754{
755 /* VTP can be added here */
756
757 return;
758}
759
760static struct cpsw_slave_data cpsw_slaves[] = {
761 {
762 .slave_reg_ofs = 0x208,
763 .sliver_reg_ofs = 0xd80,
9c653aad 764 .phy_addr = 0,
e363426e
PK		 765 },
766 {
767 .slave_reg_ofs = 0x308,
768 .sliver_reg_ofs = 0xdc0,
9c653aad 769 .phy_addr = 1,
e363426e
PK		 770 },
771};
772
773static struct cpsw_platform_data cpsw_data = {
81df2bab
MP		 774 .mdio_base = CPSW_MDIO_BASE,
775 .cpsw_base = CPSW_BASE,
e363426e
PK		 776 .mdio_div = 0xff,
777 .channels = 8,
778 .cpdma_reg_ofs = 0x800,
779 .slaves = 1,
780 .slave_data = cpsw_slaves,
781 .ale_reg_ofs = 0xd00,
782 .ale_entries = 1024,
783 .host_port_reg_ofs = 0x108,
784 .hw_stats_reg_ofs = 0x900,
2bf36ac6 785 .bd_ram_ofs = 0x2000,
e363426e
PK		 786 .mac_control = (1 << 5),
787 .control = cpsw_control,
788 .host_port_num = 0,
789 .version = CPSW_CTRL_VERSION_2,
790};
d2aa1154 791#endif
e363426e 792
97f3a178
LV		 793#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
794 defined(CONFIG_SPL_BUILD)) || \
795 ((defined(CONFIG_DRIVER_TI_CPSW) || \
796 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
797 !defined(CONFIG_SPL_BUILD))
798
68996b84
TR		 799/*
800 * This function will:
801 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
802 * in the environment
803 * Perform fixups to the PHY present on certain boards. We only need this
804 * function in:
805 * - SPL with either CPSW or USB ethernet support
806 * - Full U-Boot, with either CPSW or USB ethernet
807 * Build in only these cases to avoid warnings about unused variables
808 * when we build an SPL that has neither option but full U-Boot will.
809 */
e363426e
PK		 810int board_eth_init(bd_t *bis)
811{
d2aa1154 812 int rv, n = 0;
f411b5cc
RQ		 813#if defined(CONFIG_USB_ETHER) && \
814 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
e363426e
PK		 815 uint8_t mac_addr[6];
816 uint32_t mac_hi, mac_lo;
817
f411b5cc
RQ		 818 /*
819 * use efuse mac address for USB ethernet as we know that
820 * both CPSW and USB ethernet will never be active at the same time
821 */
c0e66793
IY		 822 mac_lo = readl(&cdev->macid0l);
823 mac_hi = readl(&cdev->macid0h);
824 mac_addr[0] = mac_hi & 0xFF;
825 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
826 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
827 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
828 mac_addr[4] = mac_lo & 0xFF;
829 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
f411b5cc
RQ		 830#endif
831
c0e66793
IY		 832
833#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
834 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e 835
a662e0c3 836#ifdef CONFIG_DRIVER_TI_CPSW
770e68c0
NM		 837 if (board_is_bone() || board_is_bone_lt() ||
838 board_is_idk()) {
e363426e
PK		 839 writel(MII_MODE_ENABLE, &cdev->miisel);
840 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
841 PHY_INTERFACE_MODE_MII;
97f3a178
LV		 842 } else if (board_is_icev2()) {
843 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
844 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
845 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
846 cpsw_slaves[0].phy_addr = 1;
847 cpsw_slaves[1].phy_addr = 3;
e363426e 848 } else {
dafd4db3 849 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
e363426e
PK		 850 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
851 PHY_INTERFACE_MODE_RGMII;
852 }
853
d2aa1154
IY		 854 rv = cpsw_register(&cpsw_data);
855 if (rv < 0)
856 printf("Error %d registering CPSW switch\n", rv);
857 else
858 n += rv;
a662e0c3 859#endif
1634e969
TR		 860
861 /*
862 *
863 * CPSW RGMII Internal Delay Mode is not supported in all PVT
864 * operating points. So we must set the TX clock delay feature
865 * in the AR8051 PHY. Since we only support a single ethernet
866 * device in U-Boot, we only do this for the first instance.
867 */
868#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
869#define AR8051_PHY_DEBUG_DATA_REG 0x1e
870#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
871#define AR8051_RGMII_TX_CLK_DLY 0x100
872
770e68c0 873 if (board_is_evm_sk() || board_is_gp_evm()) {
1634e969
TR		 874 const char *devname;
875 devname = miiphy_get_current_dev();
876
877 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
878 AR8051_DEBUG_RGMII_CLK_DLY_REG);
879 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
880 AR8051_RGMII_TX_CLK_DLY);
881 }
d2aa1154 882#endif
c0e66793
IY		 883#if defined(CONFIG_USB_ETHER) && \
884 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
0adb5b76 885 if (is_valid_ethaddr(mac_addr))
c0e66793
IY		 886 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
887
d2aa1154
IY		 888 rv = usb_eth_initialize(bis);
889 if (rv < 0)
890 printf("Error %d registering USB_ETHER\n", rv);
891 else
892 n += rv;
893#endif
894 return n;
e363426e
PK		 895}
896#endif
bd83e3df
M		 897
898#endif /* CONFIG_DM_ETH */
505ea6e8
LV		 899
900#ifdef CONFIG_SPL_LOAD_FIT
901int board_fit_config_name_match(const char *name)
902{
903 if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
904 return 0;
905 else if (board_is_bone() && !strcmp(name, "am335x-bone"))
906 return 0;
907 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
908 return 0;
3819ea70
LV		 909 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
910 return 0;
da9d9599
LV		 911 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
912 return 0;
73ec6960
LV		 913 else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
914 return 0;
505ea6e8
LV		 915 else
916 return -1;
917}
918#endif
b0a4eea1
AD		 919
920#ifdef CONFIG_TI_SECURE_DEVICE
921void board_fit_image_post_process(void **p_image, size_t *p_size)
922{
923 secure_boot_verify_image(p_image, p_size);
924}
925#endif
4548bc8d
LV		 926
927#if !CONFIG_IS_ENABLED(OF_CONTROL)
928static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
929 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
930 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
931 .cfg.f_min = 400000,
932 .cfg.f_max = 52000000,
933 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
934 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
935};
936
937U_BOOT_DEVICE(am335x_mmc0) = {
938 .name = "omap_hsmmc",
939 .platdata = &am335x_mmc0_platdata,
940};
941
942static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
943 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
944 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
945 .cfg.f_min = 400000,
946 .cfg.f_max = 52000000,
947 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
948 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
949};
950
951U_BOOT_DEVICE(am335x_mmc1) = {
952 .name = "omap_hsmmc",
953 .platdata = &am335x_mmc1_platdata,
954};
955#endif
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