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Commit | Line | Data |
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dc7c9a1a WD |
1 | /* |
2 | * Driver for NAND support, Rick Bronson | |
3 | * borrowed heavily from: | |
4 | * (c) 1999 Machine Vision Holdings, Inc. | |
5 | * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> | |
dc7c9a1a WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
dc7c9a1a WD |
9 | #include <command.h> |
10 | #include <malloc.h> | |
11 | #include <asm/io.h> | |
a3d991bd | 12 | #include <watchdog.h> |
dc7c9a1a WD |
13 | |
14 | #ifdef CONFIG_SHOW_BOOT_PROGRESS | |
15 | # include <status_led.h> | |
16 | # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) | |
17 | #else | |
18 | # define SHOW_BOOT_PROGRESS(arg) | |
19 | #endif | |
20 | ||
21 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) | |
22 | ||
8b07a110 WD |
23 | #ifdef CONFIG_AT91RM9200DK |
24 | #include <asm/arch/hardware.h> | |
25 | #endif | |
26 | ||
dc7c9a1a WD |
27 | #include <linux/mtd/nand.h> |
28 | #include <linux/mtd/nand_ids.h> | |
7a8e9bed | 29 | #include <jffs2/jffs2.h> |
dc7c9a1a | 30 | |
1f4bb37d WD |
31 | #ifdef CONFIG_OMAP1510 |
32 | void archflashwp(void *archdata, int wp); | |
33 | #endif | |
34 | ||
35 | #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) | |
36 | ||
dc7c9a1a WD |
37 | /* |
38 | * Definition of the out of band configuration structure | |
39 | */ | |
40 | struct nand_oob_config { | |
41 | int ecc_pos[6]; /* position of ECC bytes inside oob */ | |
42 | int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ | |
43 | int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ | |
44 | } oob_config = { {0}, 0, 0}; | |
45 | ||
a43278a4 | 46 | #undef NAND_DEBUG |
dc7c9a1a | 47 | #undef PSYCHO_DEBUG |
7a8e9bed WD |
48 | |
49 | /* ****************** WARNING ********************* | |
50 | * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will | |
51 | * erase (or at least attempt to erase) blocks that are marked | |
52 | * bad. This can be very handy if you are _sure_ that the block | |
53 | * is OK, say because you marked a good block bad to test bad | |
54 | * block handling and you are done testing, or if you have | |
55 | * accidentally marked blocks bad. | |
56 | * | |
57 | * Erasing factory marked bad blocks is a _bad_ idea. If the | |
58 | * erase succeeds there is no reliable way to find them again, | |
59 | * and attempting to program or erase bad blocks can affect | |
60 | * the data in _other_ (good) blocks. | |
61 | */ | |
62 | #define ALLOW_ERASE_BAD_DEBUG 0 | |
dc7c9a1a WD |
63 | |
64 | #define CONFIG_MTD_NAND_ECC /* enable ECC */ | |
1f4bb37d | 65 | #define CONFIG_MTD_NAND_ECC_JFFS2 |
dc7c9a1a | 66 | |
7a8e9bed WD |
67 | /* bits for nand_rw() `cmd'; or together as needed */ |
68 | #define NANDRW_READ 0x01 | |
69 | #define NANDRW_WRITE 0x00 | |
70 | #define NANDRW_JFFS2 0x02 | |
a3d991bd | 71 | #define NANDRW_JFFS2_SKIP 0x04 |
7a8e9bed | 72 | |
dc7c9a1a WD |
73 | /* |
74 | * Function Prototypes | |
75 | */ | |
76 | static void nand_print(struct nand_chip *nand); | |
13a5695b | 77 | int nand_rw (struct nand_chip* nand, int cmd, |
dc7c9a1a WD |
78 | size_t start, size_t len, |
79 | size_t * retlen, u_char * buf); | |
13a5695b | 80 | int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); |
dc7c9a1a WD |
81 | static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, |
82 | size_t * retlen, u_char *buf, u_char *ecc_code); | |
83 | static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, | |
84 | size_t * retlen, const u_char * buf, u_char * ecc_code); | |
7a8e9bed WD |
85 | static void nand_print_bad(struct nand_chip *nand); |
86 | static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, | |
87 | size_t * retlen, u_char * buf); | |
88 | static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, | |
89 | size_t * retlen, const u_char * buf); | |
1f4bb37d | 90 | static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); |
dc7c9a1a WD |
91 | #ifdef CONFIG_MTD_NAND_ECC |
92 | static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); | |
93 | static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); | |
94 | #endif | |
95 | ||
7a8e9bed | 96 | struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; |
dc7c9a1a WD |
97 | |
98 | /* Current NAND Device */ | |
99 | static int curr_device = -1; | |
100 | ||
101 | /* ------------------------------------------------------------------------- */ | |
102 | ||
103 | int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
104 | { | |
105 | int rcode = 0; | |
106 | ||
107 | switch (argc) { | |
108 | case 0: | |
109 | case 1: | |
110 | printf ("Usage:\n%s\n", cmdtp->usage); | |
111 | return 1; | |
112 | case 2: | |
8bde7f77 | 113 | if (strcmp(argv[1],"info") == 0) { |
dc7c9a1a WD |
114 | int i; |
115 | ||
116 | putc ('\n'); | |
117 | ||
118 | for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) { | |
119 | if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) | |
120 | continue; /* list only known devices */ | |
121 | printf ("Device %d: ", i); | |
122 | nand_print(&nand_dev_desc[i]); | |
123 | } | |
124 | return 0; | |
125 | ||
126 | } else if (strcmp(argv[1],"device") == 0) { | |
127 | if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { | |
128 | puts ("\nno devices available\n"); | |
129 | return 1; | |
130 | } | |
131 | printf ("\nDevice %d: ", curr_device); | |
132 | nand_print(&nand_dev_desc[curr_device]); | |
133 | return 0; | |
7a8e9bed WD |
134 | |
135 | } else if (strcmp(argv[1],"bad") == 0) { | |
136 | if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { | |
137 | puts ("\nno devices available\n"); | |
138 | return 1; | |
139 | } | |
140 | printf ("\nDevice %d bad blocks:\n", curr_device); | |
141 | nand_print_bad(&nand_dev_desc[curr_device]); | |
142 | return 0; | |
143 | ||
dc7c9a1a WD |
144 | } |
145 | printf ("Usage:\n%s\n", cmdtp->usage); | |
146 | return 1; | |
147 | case 3: | |
148 | if (strcmp(argv[1],"device") == 0) { | |
149 | int dev = (int)simple_strtoul(argv[2], NULL, 10); | |
150 | ||
151 | printf ("\nDevice %d: ", dev); | |
152 | if (dev >= CFG_MAX_NAND_DEVICE) { | |
153 | puts ("unknown device\n"); | |
154 | return 1; | |
155 | } | |
156 | nand_print(&nand_dev_desc[dev]); | |
157 | /*nand_print (dev);*/ | |
158 | ||
159 | if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { | |
160 | return 1; | |
161 | } | |
162 | ||
163 | curr_device = dev; | |
164 | ||
165 | puts ("... is now current device\n"); | |
166 | ||
167 | return 0; | |
168 | } | |
7a8e9bed WD |
169 | else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { |
170 | struct nand_chip* nand = &nand_dev_desc[curr_device]; | |
171 | ulong off = 0; | |
172 | ulong size = nand->totlen; | |
173 | int ret; | |
174 | ||
175 | printf ("\nNAND erase: device %d offset %ld, size %ld ... ", | |
176 | curr_device, off, size); | |
177 | ||
178 | ret = nand_erase (nand, off, size, 1); | |
179 | ||
180 | printf("%s\n", ret ? "ERROR" : "OK"); | |
181 | ||
182 | return ret; | |
183 | } | |
dc7c9a1a WD |
184 | |
185 | printf ("Usage:\n%s\n", cmdtp->usage); | |
186 | return 1; | |
187 | default: | |
188 | /* at least 4 args */ | |
189 | ||
7a8e9bed WD |
190 | if (strncmp(argv[1], "read", 4) == 0 || |
191 | strncmp(argv[1], "write", 5) == 0) { | |
dc7c9a1a WD |
192 | ulong addr = simple_strtoul(argv[2], NULL, 16); |
193 | ulong off = simple_strtoul(argv[3], NULL, 16); | |
194 | ulong size = simple_strtoul(argv[4], NULL, 16); | |
7a8e9bed WD |
195 | int cmd = (strncmp(argv[1], "read", 4) == 0) ? |
196 | NANDRW_READ : NANDRW_WRITE; | |
dc7c9a1a | 197 | int ret, total; |
7a8e9bed WD |
198 | char* cmdtail = strchr(argv[1], '.'); |
199 | ||
200 | if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { | |
201 | /* read out-of-band data */ | |
202 | if (cmd & NANDRW_READ) { | |
203 | ret = nand_read_oob(nand_dev_desc + curr_device, | |
204 | off, size, &total, | |
205 | (u_char*)addr); | |
206 | } | |
207 | else { | |
208 | ret = nand_write_oob(nand_dev_desc + curr_device, | |
209 | off, size, &total, | |
210 | (u_char*)addr); | |
211 | } | |
212 | return ret; | |
213 | } | |
214 | else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) | |
215 | cmd |= NANDRW_JFFS2; /* skip bad blocks */ | |
a3d991bd WD |
216 | else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { |
217 | cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ | |
218 | if (cmd & NANDRW_READ) | |
219 | cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ | |
220 | } | |
7a8e9bed WD |
221 | #ifdef SXNI855T |
222 | /* need ".e" same as ".j" for compatibility with older units */ | |
223 | else if (cmdtail && !strcmp(cmdtail, ".e")) | |
224 | cmd |= NANDRW_JFFS2; /* skip bad blocks */ | |
225 | #endif | |
226 | else if (cmdtail) { | |
227 | printf ("Usage:\n%s\n", cmdtp->usage); | |
228 | return 1; | |
229 | } | |
dc7c9a1a WD |
230 | |
231 | printf ("\nNAND %s: device %d offset %ld, size %ld ... ", | |
7a8e9bed WD |
232 | (cmd & NANDRW_READ) ? "read" : "write", |
233 | curr_device, off, size); | |
dc7c9a1a WD |
234 | |
235 | ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size, | |
236 | &total, (u_char*)addr); | |
237 | ||
1f4bb37d | 238 | printf (" %d bytes %s: %s\n", total, |
998eaaec | 239 | (cmd & NANDRW_READ) ? "read" : "written", |
dc7c9a1a WD |
240 | ret ? "ERROR" : "OK"); |
241 | ||
242 | return ret; | |
7a8e9bed WD |
243 | } else if (strcmp(argv[1],"erase") == 0 && |
244 | (argc == 4 || strcmp("clean", argv[2]) == 0)) { | |
245 | int clean = argc == 5; | |
246 | ulong off = simple_strtoul(argv[2 + clean], NULL, 16); | |
247 | ulong size = simple_strtoul(argv[3 + clean], NULL, 16); | |
dc7c9a1a WD |
248 | int ret; |
249 | ||
250 | printf ("\nNAND erase: device %d offset %ld, size %ld ... ", | |
251 | curr_device, off, size); | |
252 | ||
7a8e9bed | 253 | ret = nand_erase (nand_dev_desc + curr_device, off, size, clean); |
dc7c9a1a WD |
254 | |
255 | printf("%s\n", ret ? "ERROR" : "OK"); | |
256 | ||
257 | return ret; | |
258 | } else { | |
259 | printf ("Usage:\n%s\n", cmdtp->usage); | |
260 | rcode = 1; | |
261 | } | |
262 | ||
263 | return rcode; | |
264 | } | |
265 | } | |
266 | ||
0d498393 WD |
267 | U_BOOT_CMD( |
268 | nand, 5, 1, do_nand, | |
b0fce99b WD |
269 | "nand - NAND sub-system\n", |
270 | "info - show available NAND devices\n" | |
271 | "nand device [dev] - show or set current device\n" | |
a3d991bd | 272 | "nand read[.jffs2[s]] addr off size\n" |
b0fce99b WD |
273 | "nand write[.jffs2] addr off size - read/write `size' bytes starting\n" |
274 | " at offset `off' to/from memory address `addr'\n" | |
275 | "nand erase [clean] [off size] - erase `size' bytes from\n" | |
276 | " offset `off' (entire device if not specified)\n" | |
277 | "nand bad - show bad blocks\n" | |
278 | "nand read.oob addr off size - read out-of-band data\n" | |
279 | "nand write.oob addr off size - read out-of-band data\n" | |
280 | ); | |
281 | ||
dc7c9a1a WD |
282 | int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
283 | { | |
284 | char *boot_device = NULL; | |
285 | char *ep; | |
286 | int dev; | |
287 | ulong cnt; | |
288 | ulong addr; | |
289 | ulong offset = 0; | |
290 | image_header_t *hdr; | |
291 | int rcode = 0; | |
292 | switch (argc) { | |
293 | case 1: | |
294 | addr = CFG_LOAD_ADDR; | |
295 | boot_device = getenv ("bootdevice"); | |
296 | break; | |
297 | case 2: | |
298 | addr = simple_strtoul(argv[1], NULL, 16); | |
299 | boot_device = getenv ("bootdevice"); | |
300 | break; | |
301 | case 3: | |
302 | addr = simple_strtoul(argv[1], NULL, 16); | |
303 | boot_device = argv[2]; | |
304 | break; | |
305 | case 4: | |
306 | addr = simple_strtoul(argv[1], NULL, 16); | |
307 | boot_device = argv[2]; | |
308 | offset = simple_strtoul(argv[3], NULL, 16); | |
309 | break; | |
310 | default: | |
311 | printf ("Usage:\n%s\n", cmdtp->usage); | |
312 | SHOW_BOOT_PROGRESS (-1); | |
313 | return 1; | |
314 | } | |
315 | ||
316 | if (!boot_device) { | |
317 | puts ("\n** No boot device **\n"); | |
318 | SHOW_BOOT_PROGRESS (-1); | |
319 | return 1; | |
320 | } | |
321 | ||
322 | dev = simple_strtoul(boot_device, &ep, 16); | |
323 | ||
324 | if ((dev >= CFG_MAX_NAND_DEVICE) || | |
325 | (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { | |
326 | printf ("\n** Device %d not available\n", dev); | |
327 | SHOW_BOOT_PROGRESS (-1); | |
328 | return 1; | |
329 | } | |
330 | ||
7a8e9bed | 331 | printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", |
dc7c9a1a WD |
332 | dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, |
333 | offset); | |
334 | ||
7a8e9bed | 335 | if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset, |
dc7c9a1a WD |
336 | SECTORSIZE, NULL, (u_char *)addr)) { |
337 | printf ("** Read error on %d\n", dev); | |
338 | SHOW_BOOT_PROGRESS (-1); | |
339 | return 1; | |
340 | } | |
341 | ||
342 | hdr = (image_header_t *)addr; | |
343 | ||
344 | if (ntohl(hdr->ih_magic) == IH_MAGIC) { | |
345 | ||
346 | print_image_hdr (hdr); | |
347 | ||
348 | cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); | |
349 | cnt -= SECTORSIZE; | |
350 | } else { | |
351 | printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); | |
352 | SHOW_BOOT_PROGRESS (-1); | |
353 | return 1; | |
354 | } | |
355 | ||
7a8e9bed | 356 | if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, |
dc7c9a1a WD |
357 | NULL, (u_char *)(addr+SECTORSIZE))) { |
358 | printf ("** Read error on %d\n", dev); | |
359 | SHOW_BOOT_PROGRESS (-1); | |
360 | return 1; | |
361 | } | |
362 | ||
363 | /* Loading ok, update default load address */ | |
364 | ||
365 | load_addr = addr; | |
366 | ||
367 | /* Check if we should attempt an auto-start */ | |
368 | if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { | |
369 | char *local_args[2]; | |
370 | extern int do_bootm (cmd_tbl_t *, int, int, char *[]); | |
371 | ||
372 | local_args[0] = argv[0]; | |
373 | local_args[1] = NULL; | |
374 | ||
7a8e9bed | 375 | printf ("Automatic boot of image at addr 0x%08lx ...\n", addr); |
dc7c9a1a WD |
376 | |
377 | do_bootm (cmdtp, 0, 1, local_args); | |
378 | rcode = 1; | |
379 | } | |
380 | return rcode; | |
381 | } | |
382 | ||
0d498393 WD |
383 | U_BOOT_CMD( |
384 | nboot, 4, 1, do_nandboot, | |
b0fce99b WD |
385 | "nboot - boot from NAND device\n", |
386 | "loadAddr dev\n" | |
387 | ); | |
388 | ||
7a8e9bed WD |
389 | /* returns 0 if block containing pos is OK: |
390 | * valid erase block and | |
391 | * not marked bad, or no bad mark position is specified | |
392 | * returns 1 if marked bad or otherwise invalid | |
393 | */ | |
394 | int check_block(struct nand_chip* nand, unsigned long pos) | |
395 | { | |
396 | int retlen; | |
397 | uint8_t oob_data; | |
398 | int page0 = pos & (-nand->erasesize); | |
399 | int page1 = page0 + nand->oobblock; | |
400 | int badpos = oob_config.badblock_pos; | |
401 | ||
402 | if (pos >= nand->totlen) | |
403 | return 1; | |
404 | ||
405 | if (badpos < 0) | |
406 | return 0; /* no way to check, assume OK */ | |
407 | ||
408 | /* Note - bad block marker can be on first or second page */ | |
409 | if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data) || | |
410 | oob_data != 0xff || | |
411 | nand_read_oob(nand, page1 + badpos, 1, &retlen, &oob_data) || | |
412 | oob_data != 0xff) | |
413 | return 1; | |
414 | ||
415 | return 0; | |
416 | } | |
8bde7f77 | 417 | |
7a8e9bed WD |
418 | /* print bad blocks in NAND flash */ |
419 | static void nand_print_bad(struct nand_chip* nand) | |
420 | { | |
421 | unsigned long pos; | |
422 | ||
423 | for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { | |
424 | if (check_block(nand, pos)) | |
425 | printf(" 0x%8.8lx\n", pos); | |
426 | } | |
427 | puts("\n"); | |
428 | } | |
429 | ||
430 | /* cmd: 0: NANDRW_WRITE write, fail on bad block | |
431 | * 1: NANDRW_READ read, fail on bad block | |
432 | * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks | |
433 | * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks | |
a3d991bd | 434 | * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks |
7a8e9bed | 435 | */ |
13a5695b | 436 | int nand_rw (struct nand_chip* nand, int cmd, |
dc7c9a1a WD |
437 | size_t start, size_t len, |
438 | size_t * retlen, u_char * buf) | |
439 | { | |
1f4bb37d | 440 | int ret = 0, n, total = 0; |
dc7c9a1a | 441 | char eccbuf[6]; |
7a8e9bed WD |
442 | /* eblk (once set) is the start of the erase block containing the |
443 | * data being processed. | |
444 | */ | |
445 | unsigned long eblk = ~0; /* force mismatch on first pass */ | |
446 | unsigned long erasesize = nand->erasesize; | |
447 | ||
448 | while (len) { | |
449 | if ((start & (-erasesize)) != eblk) { | |
450 | /* have crossed into new erase block, deal with | |
451 | * it if it is sure marked bad. | |
452 | */ | |
453 | eblk = start & (-erasesize); /* start of block */ | |
454 | if (check_block(nand, eblk)) { | |
455 | if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { | |
456 | while (len > 0 && | |
457 | start - eblk < erasesize) { | |
458 | *(buf++) = 0xff; | |
459 | ++start; | |
460 | ++total; | |
461 | --len; | |
462 | } | |
463 | continue; | |
464 | } | |
a3d991bd WD |
465 | else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { |
466 | start += erasesize; | |
467 | continue; | |
468 | } | |
7a8e9bed WD |
469 | else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { |
470 | /* skip bad block */ | |
471 | start += erasesize; | |
472 | continue; | |
473 | } | |
474 | else { | |
475 | ret = 1; | |
476 | break; | |
477 | } | |
478 | } | |
479 | } | |
dc7c9a1a WD |
480 | /* The ECC will not be calculated correctly if |
481 | less than 512 is written or read */ | |
1f4bb37d WD |
482 | /* Is request at least 512 bytes AND it starts on a proper boundry */ |
483 | if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) | |
484 | printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); | |
485 | ||
7a8e9bed WD |
486 | if (cmd & NANDRW_READ) |
487 | ret = nand_read_ecc(nand, start, | |
488 | min(len, eblk + erasesize - start), | |
1f4bb37d | 489 | &n, (u_char*)buf, eccbuf); |
dc7c9a1a | 490 | else |
7a8e9bed WD |
491 | ret = nand_write_ecc(nand, start, |
492 | min(len, eblk + erasesize - start), | |
1f4bb37d | 493 | &n, (u_char*)buf, eccbuf); |
dc7c9a1a WD |
494 | |
495 | if (ret) | |
496 | break; | |
497 | ||
498 | start += n; | |
499 | buf += n; | |
500 | total += n; | |
501 | len -= n; | |
502 | } | |
503 | if (retlen) | |
504 | *retlen = total; | |
505 | ||
506 | return ret; | |
507 | } | |
508 | ||
509 | static void nand_print(struct nand_chip *nand) | |
0db5bca8 | 510 | { |
7a8e9bed WD |
511 | if (nand->numchips > 1) { |
512 | printf("%s at 0x%lx,\n" | |
513 | "\t %d chips %s, size %d MB, \n" | |
514 | "\t total size %ld MB, sector size %ld kB\n", | |
515 | nand->name, nand->IO_ADDR, nand->numchips, | |
516 | nand->chips_name, 1 << (nand->chipshift - 20), | |
517 | nand->totlen >> 20, nand->erasesize >> 10); | |
518 | } | |
519 | else { | |
8bde7f77 | 520 | printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); |
7a8e9bed WD |
521 | print_size(nand->totlen, ", "); |
522 | print_size(nand->erasesize, " sector)\n"); | |
dc7c9a1a WD |
523 | } |
524 | } | |
525 | ||
526 | /* ------------------------------------------------------------------------- */ | |
527 | ||
1f4bb37d | 528 | static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) |
dc7c9a1a WD |
529 | { |
530 | /* This is inline, to optimise the common case, where it's ready instantly */ | |
531 | int ret = 0; | |
dc7c9a1a | 532 | |
1f4bb37d WD |
533 | #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ |
534 | if(ale_wait) | |
535 | NAND_WAIT_READY(nand); /* do the worst case 25us wait */ | |
536 | else | |
537 | udelay(10); | |
538 | #else /* has functional r/b signal */ | |
12f34241 | 539 | NAND_WAIT_READY(nand); |
1f4bb37d | 540 | #endif |
dc7c9a1a WD |
541 | return ret; |
542 | } | |
543 | ||
544 | /* NanD_Command: Send a flash command to the flash chip */ | |
545 | ||
546 | static inline int NanD_Command(struct nand_chip *nand, unsigned char command) | |
547 | { | |
548 | unsigned long nandptr = nand->IO_ADDR; | |
549 | ||
550 | /* Assert the CLE (Command Latch Enable) line to the flash chip */ | |
551 | NAND_CTL_SETCLE(nandptr); | |
552 | ||
553 | /* Send the command */ | |
554 | WRITE_NAND_COMMAND(command, nandptr); | |
555 | ||
556 | /* Lower the CLE line */ | |
557 | NAND_CTL_CLRCLE(nandptr); | |
558 | ||
1f4bb37d WD |
559 | #ifdef NAND_NO_RB |
560 | if(command == NAND_CMD_RESET){ | |
561 | u_char ret_val; | |
562 | NanD_Command(nand, NAND_CMD_STATUS); | |
563 | do{ | |
564 | ret_val = READ_NAND(nandptr);/* wait till ready */ | |
565 | } while((ret_val & 0x40) != 0x40); | |
566 | } | |
567 | #endif | |
568 | return NanD_WaitReady(nand, 0); | |
dc7c9a1a WD |
569 | } |
570 | ||
571 | /* NanD_Address: Set the current address for the flash chip */ | |
572 | ||
573 | static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) | |
0db5bca8 WD |
574 | { |
575 | unsigned long nandptr; | |
576 | int i; | |
dc7c9a1a | 577 | |
0db5bca8 | 578 | nandptr = nand->IO_ADDR; |
dc7c9a1a WD |
579 | |
580 | /* Assert the ALE (Address Latch Enable) line to the flash chip */ | |
0db5bca8 WD |
581 | NAND_CTL_SETALE(nandptr); |
582 | ||
583 | /* Send the address */ | |
584 | /* Devices with 256-byte page are addressed as: | |
585 | * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) | |
586 | * there is no device on the market with page256 | |
587 | * and more than 24 bits. | |
588 | * Devices with 512-byte page are addressed as: | |
589 | * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) | |
590 | * 25-31 is sent only if the chip support it. | |
591 | * bit 8 changes the read command to be sent | |
592 | * (NAND_CMD_READ0 or NAND_CMD_READ1). | |
dc7c9a1a WD |
593 | */ |
594 | ||
0db5bca8 WD |
595 | if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) |
596 | WRITE_NAND_ADDRESS(ofs, nandptr); | |
dc7c9a1a | 597 | |
0db5bca8 | 598 | ofs = ofs >> nand->page_shift; |
dc7c9a1a | 599 | |
0db5bca8 WD |
600 | if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) |
601 | for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) | |
602 | WRITE_NAND_ADDRESS(ofs, nandptr); | |
dc7c9a1a | 603 | |
0db5bca8 WD |
604 | /* Lower the ALE line */ |
605 | NAND_CTL_CLRALE(nandptr); | |
dc7c9a1a | 606 | |
0db5bca8 | 607 | /* Wait for the chip to respond */ |
1f4bb37d | 608 | return NanD_WaitReady(nand, 1); |
0db5bca8 | 609 | } |
dc7c9a1a WD |
610 | |
611 | /* NanD_SelectChip: Select a given flash chip within the current floor */ | |
612 | ||
613 | static inline int NanD_SelectChip(struct nand_chip *nand, int chip) | |
614 | { | |
615 | /* Wait for it to be ready */ | |
1f4bb37d | 616 | return NanD_WaitReady(nand, 0); |
dc7c9a1a WD |
617 | } |
618 | ||
619 | /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ | |
620 | ||
621 | static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) | |
622 | { | |
623 | int mfr, id, i; | |
624 | ||
0db5bca8 | 625 | NAND_ENABLE_CE(nand); /* set pin low */ |
dc7c9a1a WD |
626 | /* Reset the chip */ |
627 | if (NanD_Command(nand, NAND_CMD_RESET)) { | |
628 | #ifdef NAND_DEBUG | |
629 | printf("NanD_Command (reset) for %d,%d returned true\n", | |
630 | floor, chip); | |
631 | #endif | |
0db5bca8 | 632 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
633 | return 0; |
634 | } | |
635 | ||
636 | /* Read the NAND chip ID: 1. Send ReadID command */ | |
637 | if (NanD_Command(nand, NAND_CMD_READID)) { | |
638 | #ifdef NAND_DEBUG | |
639 | printf("NanD_Command (ReadID) for %d,%d returned true\n", | |
640 | floor, chip); | |
641 | #endif | |
0db5bca8 | 642 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
643 | return 0; |
644 | } | |
645 | ||
646 | /* Read the NAND chip ID: 2. Send address byte zero */ | |
647 | NanD_Address(nand, ADDR_COLUMN, 0); | |
648 | ||
649 | /* Read the manufacturer and device id codes from the device */ | |
650 | ||
651 | mfr = READ_NAND(nand->IO_ADDR); | |
652 | ||
653 | id = READ_NAND(nand->IO_ADDR); | |
654 | ||
8bde7f77 | 655 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a | 656 | /* No response - return failure */ |
0db5bca8 | 657 | if (mfr == 0xff || mfr == 0) { |
4d816774 | 658 | #ifdef NAND_DEBUG |
0db5bca8 | 659 | printf("NanD_Command (ReadID) got %d %d\n", mfr, id); |
4d816774 | 660 | #endif |
0db5bca8 WD |
661 | return 0; |
662 | } | |
dc7c9a1a WD |
663 | |
664 | /* Check it's the same as the first chip we identified. | |
665 | * M-Systems say that any given nand_chip device should only | |
666 | * contain _one_ type of flash part, although that's not a | |
667 | * hardware restriction. */ | |
668 | if (nand->mfr) { | |
669 | if (nand->mfr == mfr && nand->id == id) | |
670 | return 1; /* This is another the same the first */ | |
671 | else | |
672 | printf("Flash chip at floor %d, chip %d is different:\n", | |
673 | floor, chip); | |
674 | } | |
675 | ||
676 | /* Print and store the manufacturer and ID codes. */ | |
677 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { | |
678 | if (mfr == nand_flash_ids[i].manufacture_id && | |
679 | id == nand_flash_ids[i].model_id) { | |
680 | #ifdef NAND_DEBUG | |
681 | printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " | |
682 | "Chip ID: 0x%2.2X (%s)\n", mfr, id, | |
683 | nand_flash_ids[i].name); | |
684 | #endif | |
685 | if (!nand->mfr) { | |
686 | nand->mfr = mfr; | |
687 | nand->id = id; | |
688 | nand->chipshift = | |
689 | nand_flash_ids[i].chipshift; | |
690 | nand->page256 = nand_flash_ids[i].page256; | |
7a8e9bed | 691 | nand->eccsize = 256; |
dc7c9a1a WD |
692 | if (nand->page256) { |
693 | nand->oobblock = 256; | |
694 | nand->oobsize = 8; | |
695 | nand->page_shift = 8; | |
696 | } else { | |
697 | nand->oobblock = 512; | |
698 | nand->oobsize = 16; | |
699 | nand->page_shift = 9; | |
700 | } | |
701 | nand->pageadrlen = | |
702 | nand_flash_ids[i].pageadrlen; | |
703 | nand->erasesize = | |
704 | nand_flash_ids[i].erasesize; | |
705 | nand->chips_name = | |
706 | nand_flash_ids[i].name; | |
707 | return 1; | |
708 | } | |
709 | return 0; | |
710 | } | |
711 | } | |
712 | ||
713 | ||
714 | #ifdef NAND_DEBUG | |
715 | /* We haven't fully identified the chip. Print as much as we know. */ | |
716 | printf("Unknown flash chip found: %2.2X %2.2X\n", | |
717 | id, mfr); | |
718 | #endif | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ | |
724 | ||
725 | static void NanD_ScanChips(struct nand_chip *nand) | |
726 | { | |
727 | int floor, chip; | |
728 | int numchips[NAND_MAX_FLOORS]; | |
729 | int maxchips = NAND_MAX_CHIPS; | |
730 | int ret = 1; | |
731 | ||
732 | nand->numchips = 0; | |
733 | nand->mfr = 0; | |
734 | nand->id = 0; | |
735 | ||
736 | ||
737 | /* For each floor, find the number of valid chips it contains */ | |
738 | for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { | |
739 | ret = 1; | |
740 | numchips[floor] = 0; | |
741 | for (chip = 0; chip < maxchips && ret != 0; chip++) { | |
742 | ||
743 | ret = NanD_IdentChip(nand, floor, chip); | |
744 | if (ret) { | |
745 | numchips[floor]++; | |
746 | nand->numchips++; | |
747 | } | |
748 | } | |
749 | } | |
750 | ||
751 | /* If there are none at all that we recognise, bail */ | |
752 | if (!nand->numchips) { | |
a43278a4 | 753 | #ifdef NAND_DEBUG |
4d816774 | 754 | puts ("No NAND flash chips recognised.\n"); |
a43278a4 | 755 | #endif |
dc7c9a1a WD |
756 | return; |
757 | } | |
758 | ||
759 | /* Allocate an array to hold the information for each chip */ | |
760 | nand->chips = malloc(sizeof(struct Nand) * nand->numchips); | |
761 | if (!nand->chips) { | |
762 | puts ("No memory for allocating chip info structures\n"); | |
763 | return; | |
764 | } | |
765 | ||
766 | ret = 0; | |
767 | ||
768 | /* Fill out the chip array with {floor, chipno} for each | |
769 | * detected chip in the device. */ | |
770 | for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { | |
771 | for (chip = 0; chip < numchips[floor]; chip++) { | |
772 | nand->chips[ret].floor = floor; | |
773 | nand->chips[ret].chip = chip; | |
774 | nand->chips[ret].curadr = 0; | |
775 | nand->chips[ret].curmode = 0x50; | |
776 | ret++; | |
777 | } | |
778 | } | |
779 | ||
780 | /* Calculate and print the total size of the device */ | |
781 | nand->totlen = nand->numchips * (1 << nand->chipshift); | |
782 | ||
783 | #ifdef NAND_DEBUG | |
784 | printf("%d flash chips found. Total nand_chip size: %ld MB\n", | |
785 | nand->numchips, nand->totlen >> 20); | |
786 | #endif | |
787 | } | |
0db5bca8 | 788 | |
dc7c9a1a | 789 | /* we need to be fast here, 1 us per read translates to 1 second per meg */ |
7a8e9bed | 790 | static void NanD_ReadBuf(struct nand_chip *nand, u_char *data_buf, int cntr) |
0db5bca8 | 791 | { |
7a8e9bed | 792 | unsigned long nandptr = nand->IO_ADDR; |
0db5bca8 | 793 | |
7a8e9bed | 794 | while (cntr >= 16) { |
0db5bca8 WD |
795 | *data_buf++ = READ_NAND(nandptr); |
796 | *data_buf++ = READ_NAND(nandptr); | |
797 | *data_buf++ = READ_NAND(nandptr); | |
798 | *data_buf++ = READ_NAND(nandptr); | |
799 | *data_buf++ = READ_NAND(nandptr); | |
800 | *data_buf++ = READ_NAND(nandptr); | |
801 | *data_buf++ = READ_NAND(nandptr); | |
802 | *data_buf++ = READ_NAND(nandptr); | |
803 | *data_buf++ = READ_NAND(nandptr); | |
804 | *data_buf++ = READ_NAND(nandptr); | |
805 | *data_buf++ = READ_NAND(nandptr); | |
806 | *data_buf++ = READ_NAND(nandptr); | |
807 | *data_buf++ = READ_NAND(nandptr); | |
808 | *data_buf++ = READ_NAND(nandptr); | |
809 | *data_buf++ = READ_NAND(nandptr); | |
810 | *data_buf++ = READ_NAND(nandptr); | |
811 | cntr -= 16; | |
812 | } | |
813 | ||
814 | while (cntr > 0) { | |
815 | *data_buf++ = READ_NAND(nandptr); | |
816 | cntr--; | |
817 | } | |
818 | } | |
dc7c9a1a | 819 | |
dc7c9a1a WD |
820 | /* |
821 | * NAND read with ECC | |
822 | */ | |
823 | static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, | |
824 | size_t * retlen, u_char *buf, u_char *ecc_code) | |
825 | { | |
826 | int col, page; | |
827 | int ecc_status = 0; | |
828 | #ifdef CONFIG_MTD_NAND_ECC | |
829 | int j; | |
830 | int ecc_failed = 0; | |
831 | u_char *data_poi; | |
832 | u_char ecc_calc[6]; | |
833 | #endif | |
dc7c9a1a WD |
834 | |
835 | /* Do not allow reads past end of device */ | |
836 | if ((start + len) > nand->totlen) { | |
0db5bca8 | 837 | printf ("%s: Attempt read beyond end of device %x %x %x\n", __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); |
dc7c9a1a WD |
838 | *retlen = 0; |
839 | return -1; | |
840 | } | |
841 | ||
842 | /* First we calculate the starting page */ | |
0db5bca8 WD |
843 | /*page = shr(start, nand->page_shift);*/ |
844 | page = start >> nand->page_shift; | |
dc7c9a1a WD |
845 | |
846 | /* Get raw starting column */ | |
847 | col = start & (nand->oobblock - 1); | |
848 | ||
849 | /* Initialize return value */ | |
850 | *retlen = 0; | |
851 | ||
852 | /* Select the NAND device */ | |
853 | NAND_ENABLE_CE(nand); /* set pin low */ | |
854 | ||
855 | /* Loop until all data read */ | |
856 | while (*retlen < len) { | |
857 | ||
858 | ||
859 | #ifdef CONFIG_MTD_NAND_ECC | |
860 | ||
861 | /* Do we have this page in cache ? */ | |
862 | if (nand->cache_page == page) | |
863 | goto readdata; | |
864 | /* Send the read command */ | |
865 | NanD_Command(nand, NAND_CMD_READ0); | |
8bde7f77 | 866 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); |
dc7c9a1a | 867 | /* Read in a page + oob data */ |
7a8e9bed | 868 | NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); |
dc7c9a1a WD |
869 | |
870 | /* copy data into cache, for read out of cache and if ecc fails */ | |
871 | if (nand->data_cache) | |
872 | memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize); | |
873 | ||
874 | /* Pick the ECC bytes out of the oob data */ | |
875 | for (j = 0; j < 6; j++) | |
876 | ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; | |
877 | ||
878 | /* Calculate the ECC and verify it */ | |
879 | /* If block was not written with ECC, skip ECC */ | |
880 | if (oob_config.eccvalid_pos != -1 && | |
881 | (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { | |
882 | ||
883 | nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); | |
884 | switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { | |
885 | case -1: | |
0db5bca8 | 886 | printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); |
dc7c9a1a WD |
887 | ecc_failed++; |
888 | break; | |
889 | case 1: | |
890 | case 2: /* transfer ECC corrected data to cache */ | |
7a8e9bed WD |
891 | if (nand->data_cache) |
892 | memcpy (nand->data_cache, nand->data_buf, 256); | |
dc7c9a1a WD |
893 | break; |
894 | } | |
895 | } | |
896 | ||
897 | if (oob_config.eccvalid_pos != -1 && | |
898 | nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { | |
899 | ||
900 | nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); | |
901 | switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { | |
902 | case -1: | |
0db5bca8 | 903 | printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); |
dc7c9a1a WD |
904 | ecc_failed++; |
905 | break; | |
906 | case 1: | |
907 | case 2: /* transfer ECC corrected data to cache */ | |
908 | if (nand->data_cache) | |
909 | memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); | |
910 | break; | |
911 | } | |
912 | } | |
913 | readdata: | |
914 | /* Read the data from ECC data buffer into return buffer */ | |
915 | data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; | |
916 | data_poi += col; | |
917 | if ((*retlen + (nand->oobblock - col)) >= len) { | |
7a8e9bed | 918 | memcpy (buf + *retlen, data_poi, len - *retlen); |
dc7c9a1a WD |
919 | *retlen = len; |
920 | } else { | |
7a8e9bed | 921 | memcpy (buf + *retlen, data_poi, nand->oobblock - col); |
dc7c9a1a WD |
922 | *retlen += nand->oobblock - col; |
923 | } | |
924 | /* Set cache page address, invalidate, if ecc_failed */ | |
925 | nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; | |
926 | ||
927 | ecc_status += ecc_failed; | |
928 | ecc_failed = 0; | |
929 | ||
930 | #else | |
931 | /* Send the read command */ | |
932 | NanD_Command(nand, NAND_CMD_READ0); | |
8bde7f77 | 933 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); |
dc7c9a1a WD |
934 | /* Read the data directly into the return buffer */ |
935 | if ((*retlen + (nand->oobblock - col)) >= len) { | |
7a8e9bed | 936 | NanD_ReadBuf(nand, buf + *retlen, len - *retlen); |
dc7c9a1a WD |
937 | *retlen = len; |
938 | /* We're done */ | |
939 | continue; | |
940 | } else { | |
7a8e9bed | 941 | NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); |
dc7c9a1a WD |
942 | *retlen += nand->oobblock - col; |
943 | } | |
944 | #endif | |
945 | /* For subsequent reads align to page boundary. */ | |
946 | col = 0; | |
947 | /* Increment page address */ | |
948 | page++; | |
949 | } | |
950 | ||
951 | /* De-select the NAND device */ | |
0db5bca8 | 952 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
953 | |
954 | /* | |
955 | * Return success, if no ECC failures, else -EIO | |
956 | * fs driver will take care of that, because | |
957 | * retlen == desired len and result == -EIO | |
958 | */ | |
959 | return ecc_status ? -1 : 0; | |
960 | } | |
961 | ||
dc7c9a1a WD |
962 | /* |
963 | * Nand_page_program function is used for write and writev ! | |
964 | */ | |
965 | static int nand_write_page (struct nand_chip *nand, | |
966 | int page, int col, int last, u_char * ecc_code) | |
967 | { | |
968 | ||
969 | int i; | |
dc7c9a1a | 970 | unsigned long nandptr = nand->IO_ADDR; |
1f4bb37d | 971 | #ifdef CONFIG_MTD_NAND_ECC |
dc7c9a1a WD |
972 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE |
973 | int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; | |
974 | #endif | |
975 | #endif | |
976 | /* pad oob area */ | |
977 | for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) | |
978 | nand->data_buf[i] = 0xff; | |
979 | ||
980 | #ifdef CONFIG_MTD_NAND_ECC | |
981 | /* Zero out the ECC array */ | |
982 | for (i = 0; i < 6; i++) | |
983 | ecc_code[i] = 0x00; | |
984 | ||
985 | /* Read back previous written data, if col > 0 */ | |
986 | if (col) { | |
987 | NanD_Command(nand, NAND_CMD_READ0); | |
0db5bca8 | 988 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); |
dc7c9a1a WD |
989 | for (i = 0; i < col; i++) |
990 | nand->data_buf[i] = READ_NAND (nandptr); | |
991 | } | |
992 | ||
993 | /* Calculate and write the ECC if we have enough data */ | |
994 | if ((col < nand->eccsize) && (last >= nand->eccsize)) { | |
995 | nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); | |
996 | for (i = 0; i < 3; i++) | |
997 | nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i]; | |
998 | if (oob_config.eccvalid_pos != -1) | |
999 | nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] = 0xf0; | |
1000 | } | |
1001 | ||
1002 | /* Calculate and write the second ECC if we have enough data */ | |
1003 | if ((nand->oobblock == 512) && (last == nand->oobblock)) { | |
1004 | nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); | |
1005 | for (i = 3; i < 6; i++) | |
1006 | nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i]; | |
1007 | if (oob_config.eccvalid_pos != -1) | |
1008 | nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] &= 0x0f; | |
1009 | } | |
1010 | #endif | |
1011 | /* Prepad for partial page programming !!! */ | |
1012 | for (i = 0; i < col; i++) | |
1013 | nand->data_buf[i] = 0xff; | |
1014 | ||
1015 | /* Postpad for partial page programming !!! oob is already padded */ | |
1016 | for (i = last; i < nand->oobblock; i++) | |
1017 | nand->data_buf[i] = 0xff; | |
1018 | ||
1019 | /* Send command to begin auto page programming */ | |
7a8e9bed | 1020 | NanD_Command(nand, NAND_CMD_READ0); |
dc7c9a1a WD |
1021 | NanD_Command(nand, NAND_CMD_SEQIN); |
1022 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); | |
1023 | ||
1024 | /* Write out complete page of data */ | |
1025 | for (i = 0; i < (nand->oobblock + nand->oobsize); i++) | |
0db5bca8 | 1026 | WRITE_NAND(nand->data_buf[i], nand->IO_ADDR); |
dc7c9a1a WD |
1027 | |
1028 | /* Send command to actually program the data */ | |
0db5bca8 WD |
1029 | NanD_Command(nand, NAND_CMD_PAGEPROG); |
1030 | NanD_Command(nand, NAND_CMD_STATUS); | |
1f4bb37d WD |
1031 | #ifdef NAND_NO_RB |
1032 | { u_char ret_val; | |
dc7c9a1a | 1033 | |
1f4bb37d WD |
1034 | do{ |
1035 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1036 | } while((ret_val & 0x40) != 0x40); | |
1037 | } | |
1038 | #endif | |
dc7c9a1a WD |
1039 | /* See if device thinks it succeeded */ |
1040 | if (READ_NAND(nand->IO_ADDR) & 0x01) { | |
0db5bca8 | 1041 | printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page); |
dc7c9a1a WD |
1042 | return -1; |
1043 | } | |
1f4bb37d | 1044 | |
dc7c9a1a WD |
1045 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE |
1046 | /* | |
1047 | * The NAND device assumes that it is always writing to | |
1048 | * a cleanly erased page. Hence, it performs its internal | |
1049 | * write verification only on bits that transitioned from | |
1050 | * 1 to 0. The device does NOT verify the whole page on a | |
1051 | * byte by byte basis. It is possible that the page was | |
1052 | * not completely erased or the page is becoming unusable | |
1053 | * due to wear. The read with ECC would catch the error | |
1054 | * later when the ECC page check fails, but we would rather | |
1055 | * catch it early in the page write stage. Better to write | |
1056 | * no data than invalid data. | |
1057 | */ | |
1058 | ||
1059 | /* Send command to read back the page */ | |
1060 | if (col < nand->eccsize) | |
0db5bca8 | 1061 | NanD_Command(nand, NAND_CMD_READ0); |
dc7c9a1a | 1062 | else |
0db5bca8 WD |
1063 | NanD_Command(nand, NAND_CMD_READ1); |
1064 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); | |
dc7c9a1a WD |
1065 | |
1066 | /* Loop through and verify the data */ | |
1067 | for (i = col; i < last; i++) { | |
1068 | if (nand->data_buf[i] != readb (nand->IO_ADDR)) { | |
0db5bca8 | 1069 | printf ("%s: Failed write verify, page 0x%08x ", __FUNCTION__, page); |
dc7c9a1a WD |
1070 | return -1; |
1071 | } | |
1072 | } | |
1073 | ||
1074 | #ifdef CONFIG_MTD_NAND_ECC | |
1075 | /* | |
1076 | * We also want to check that the ECC bytes wrote | |
1077 | * correctly for the same reasons stated above. | |
1078 | */ | |
1079 | NanD_Command(nand, NAND_CMD_READOOB); | |
1080 | NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); | |
1081 | for (i = 0; i < nand->oobsize; i++) | |
1082 | nand->data_buf[i] = readb (nand->IO_ADDR); | |
1083 | for (i = 0; i < ecc_bytes; i++) { | |
1084 | if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { | |
0db5bca8 WD |
1085 | printf ("%s: Failed ECC write " |
1086 | "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); | |
dc7c9a1a WD |
1087 | return -1; |
1088 | } | |
1089 | } | |
1090 | #endif | |
1091 | #endif | |
1092 | return 0; | |
1093 | } | |
0db5bca8 | 1094 | |
dc7c9a1a WD |
1095 | static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, |
1096 | size_t * retlen, const u_char * buf, u_char * ecc_code) | |
1097 | { | |
1098 | int i, page, col, cnt, ret = 0; | |
1099 | ||
1100 | /* Do not allow write past end of device */ | |
1101 | if ((to + len) > nand->totlen) { | |
0db5bca8 | 1102 | printf ("%s: Attempt to write past end of page\n", __FUNCTION__); |
dc7c9a1a WD |
1103 | return -1; |
1104 | } | |
1105 | ||
1106 | /* Shift to get page */ | |
1107 | page = ((int) to) >> nand->page_shift; | |
1108 | ||
1109 | /* Get the starting column */ | |
1110 | col = to & (nand->oobblock - 1); | |
1111 | ||
1112 | /* Initialize return length value */ | |
1113 | *retlen = 0; | |
1114 | ||
1115 | /* Select the NAND device */ | |
1f4bb37d WD |
1116 | #ifdef CONFIG_OMAP1510 |
1117 | archflashwp(0,0); | |
1118 | #endif | |
1119 | NAND_ENABLE_CE(nand); /* set pin low */ | |
dc7c9a1a WD |
1120 | |
1121 | /* Check the WP bit */ | |
0db5bca8 | 1122 | NanD_Command(nand, NAND_CMD_STATUS); |
dc7c9a1a | 1123 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { |
0db5bca8 | 1124 | printf ("%s: Device is write protected!!!\n", __FUNCTION__); |
dc7c9a1a WD |
1125 | ret = -1; |
1126 | goto out; | |
1127 | } | |
1128 | ||
1129 | /* Loop until all data is written */ | |
1130 | while (*retlen < len) { | |
1131 | /* Invalidate cache, if we write to this page */ | |
1132 | if (nand->cache_page == page) | |
1133 | nand->cache_page = -1; | |
1134 | ||
1135 | /* Write data into buffer */ | |
1136 | if ((col + len) >= nand->oobblock) | |
1137 | for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) | |
1138 | nand->data_buf[i] = buf[(*retlen + cnt)]; | |
1139 | else | |
1140 | for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) | |
1141 | nand->data_buf[i] = buf[(*retlen + cnt)]; | |
1142 | /* We use the same function for write and writev !) */ | |
1143 | ret = nand_write_page (nand, page, col, i, ecc_code); | |
1144 | if (ret) | |
1145 | goto out; | |
1146 | ||
1147 | /* Next data start at page boundary */ | |
1148 | col = 0; | |
1149 | ||
1150 | /* Update written bytes count */ | |
1151 | *retlen += cnt; | |
1152 | ||
1153 | /* Increment page address */ | |
1154 | page++; | |
1155 | } | |
1156 | ||
1157 | /* Return happy */ | |
1158 | *retlen = len; | |
1159 | ||
1160 | out: | |
1161 | /* De-select the NAND device */ | |
0db5bca8 | 1162 | NAND_DISABLE_CE(nand); /* set pin high */ |
1f4bb37d WD |
1163 | #ifdef CONFIG_OMAP1510 |
1164 | archflashwp(0,1); | |
1165 | #endif | |
dc7c9a1a WD |
1166 | return ret; |
1167 | } | |
1168 | ||
7a8e9bed WD |
1169 | /* read from the 16 bytes of oob data that correspond to a 512 byte |
1170 | * page or 2 256-byte pages. | |
dc7c9a1a | 1171 | */ |
dc7c9a1a | 1172 | static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, |
7a8e9bed | 1173 | size_t * retlen, u_char * buf) |
dc7c9a1a | 1174 | { |
7a8e9bed | 1175 | int len256 = 0; |
dc7c9a1a | 1176 | struct Nand *mychip; |
0db5bca8 | 1177 | int ret = 0; |
dc7c9a1a | 1178 | |
7a8e9bed | 1179 | mychip = &nand->chips[ofs >> nand->chipshift]; |
dc7c9a1a WD |
1180 | |
1181 | /* update address for 2M x 8bit devices. OOB starts on the second */ | |
1182 | /* page to maintain compatibility with nand_read_ecc. */ | |
1183 | if (nand->page256) { | |
1184 | if (!(ofs & 0x8)) | |
1185 | ofs += 0x100; | |
1186 | else | |
1187 | ofs -= 0x8; | |
1188 | } | |
1189 | ||
7a8e9bed | 1190 | NAND_ENABLE_CE(nand); /* set pin low */ |
dc7c9a1a WD |
1191 | NanD_Command(nand, NAND_CMD_READOOB); |
1192 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1193 | ||
1194 | /* treat crossing 8-byte OOB data for 2M x 8bit devices */ | |
1195 | /* Note: datasheet says it should automaticaly wrap to the */ | |
1196 | /* next OOB block, but it didn't work here. mf. */ | |
1197 | if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { | |
1198 | len256 = (ofs | 0x7) + 1 - ofs; | |
1199 | NanD_ReadBuf(nand, buf, len256); | |
1200 | ||
1201 | NanD_Command(nand, NAND_CMD_READOOB); | |
1202 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); | |
1203 | } | |
1204 | ||
1205 | NanD_ReadBuf(nand, &buf[len256], len - len256); | |
1206 | ||
1207 | *retlen = len; | |
1208 | /* Reading the full OOB data drops us off of the end of the page, | |
8bde7f77 WD |
1209 | * causing the flash device to go into busy mode, so we need |
1210 | * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ | |
dc7c9a1a | 1211 | |
1f4bb37d | 1212 | ret = NanD_WaitReady(nand, 1); |
8bde7f77 | 1213 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1214 | |
1215 | return ret; | |
1216 | ||
1217 | } | |
7a8e9bed WD |
1218 | |
1219 | /* write to the 16 bytes of oob data that correspond to a 512 byte | |
1220 | * page or 2 256-byte pages. | |
1221 | */ | |
dc7c9a1a WD |
1222 | static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, |
1223 | size_t * retlen, const u_char * buf) | |
1224 | { | |
1225 | int len256 = 0; | |
7a8e9bed | 1226 | int i; |
dc7c9a1a WD |
1227 | unsigned long nandptr = nand->IO_ADDR; |
1228 | ||
1229 | #ifdef PSYCHO_DEBUG | |
1230 | printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", | |
1231 | (long)ofs, len, buf[0], buf[1], buf[2], buf[3], | |
1232 | buf[8], buf[9], buf[14],buf[15]); | |
1233 | #endif | |
1234 | ||
7a8e9bed WD |
1235 | NAND_ENABLE_CE(nand); /* set pin low to enable chip */ |
1236 | ||
dc7c9a1a WD |
1237 | /* Reset the chip */ |
1238 | NanD_Command(nand, NAND_CMD_RESET); | |
1239 | ||
1240 | /* issue the Read2 command to set the pointer to the Spare Data Area. */ | |
1241 | NanD_Command(nand, NAND_CMD_READOOB); | |
1242 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1243 | ||
1244 | /* update address for 2M x 8bit devices. OOB starts on the second */ | |
1245 | /* page to maintain compatibility with nand_read_ecc. */ | |
1246 | if (nand->page256) { | |
1247 | if (!(ofs & 0x8)) | |
1248 | ofs += 0x100; | |
1249 | else | |
1250 | ofs -= 0x8; | |
1251 | } | |
1252 | ||
1253 | /* issue the Serial Data In command to initial the Page Program process */ | |
1254 | NanD_Command(nand, NAND_CMD_SEQIN); | |
1255 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1256 | ||
1257 | /* treat crossing 8-byte OOB data for 2M x 8bit devices */ | |
1258 | /* Note: datasheet says it should automaticaly wrap to the */ | |
1259 | /* next OOB block, but it didn't work here. mf. */ | |
1260 | if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { | |
1261 | len256 = (ofs | 0x7) + 1 - ofs; | |
7a8e9bed WD |
1262 | for (i = 0; i < len256; i++) |
1263 | WRITE_NAND(buf[i], nandptr); | |
dc7c9a1a WD |
1264 | |
1265 | NanD_Command(nand, NAND_CMD_PAGEPROG); | |
1266 | NanD_Command(nand, NAND_CMD_STATUS); | |
1f4bb37d WD |
1267 | #ifdef NAND_NO_RB |
1268 | { u_char ret_val; | |
1269 | do{ | |
1270 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1271 | }while((ret_val & 0x40) != 0x40); | |
1272 | } | |
1273 | #endif | |
dc7c9a1a WD |
1274 | if (READ_NAND(nandptr) & 1) { |
1275 | puts ("Error programming oob data\n"); | |
1276 | /* There was an error */ | |
7a8e9bed | 1277 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1278 | *retlen = 0; |
1279 | return -1; | |
1280 | } | |
1281 | NanD_Command(nand, NAND_CMD_SEQIN); | |
1282 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); | |
1283 | } | |
1284 | ||
7a8e9bed WD |
1285 | for (i = len256; i < len; i++) |
1286 | WRITE_NAND(buf[i], nandptr); | |
dc7c9a1a WD |
1287 | |
1288 | NanD_Command(nand, NAND_CMD_PAGEPROG); | |
1289 | NanD_Command(nand, NAND_CMD_STATUS); | |
1f4bb37d WD |
1290 | #ifdef NAND_NO_RB |
1291 | { u_char ret_val; | |
1292 | do{ | |
1293 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1294 | } while((ret_val & 0x40) != 0x40); | |
1295 | } | |
1296 | #endif | |
dc7c9a1a WD |
1297 | if (READ_NAND(nandptr) & 1) { |
1298 | puts ("Error programming oob data\n"); | |
1299 | /* There was an error */ | |
7a8e9bed | 1300 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1301 | *retlen = 0; |
1302 | return -1; | |
1303 | } | |
1304 | ||
7a8e9bed | 1305 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1306 | *retlen = len; |
1307 | return 0; | |
1308 | ||
1309 | } | |
dc7c9a1a | 1310 | |
13a5695b | 1311 | int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) |
dc7c9a1a | 1312 | { |
7a8e9bed WD |
1313 | /* This is defined as a structure so it will work on any system |
1314 | * using native endian jffs2 (the default). | |
1315 | */ | |
1316 | static struct jffs2_unknown_node clean_marker = { | |
1317 | JFFS2_MAGIC_BITMASK, | |
1318 | JFFS2_NODETYPE_CLEANMARKER, | |
1319 | 8 /* 8 bytes in this node */ | |
1320 | }; | |
dc7c9a1a WD |
1321 | unsigned long nandptr; |
1322 | struct Nand *mychip; | |
85ec0bcc | 1323 | int ret = 0; |
dc7c9a1a WD |
1324 | |
1325 | if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { | |
1326 | printf ("Offset and size must be sector aligned, erasesize = %d\n", | |
8bde7f77 | 1327 | (int) nand->erasesize); |
dc7c9a1a WD |
1328 | return -1; |
1329 | } | |
1330 | ||
1331 | nandptr = nand->IO_ADDR; | |
1332 | ||
85ec0bcc | 1333 | /* Select the NAND device */ |
1f4bb37d WD |
1334 | #ifdef CONFIG_OMAP1510 |
1335 | archflashwp(0,0); | |
1336 | #endif | |
1337 | NAND_ENABLE_CE(nand); /* set pin low */ | |
85ec0bcc WD |
1338 | |
1339 | /* Check the WP bit */ | |
1340 | NanD_Command(nand, NAND_CMD_STATUS); | |
1341 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { | |
1342 | printf ("nand_write_ecc: Device is write protected!!!\n"); | |
1343 | ret = -1; | |
1344 | goto out; | |
1345 | } | |
1346 | ||
0db5bca8 WD |
1347 | /* Check the WP bit */ |
1348 | NanD_Command(nand, NAND_CMD_STATUS); | |
1349 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { | |
1350 | printf ("%s: Device is write protected!!!\n", __FUNCTION__); | |
1351 | ret = -1; | |
1352 | goto out; | |
1353 | } | |
1354 | ||
dc7c9a1a WD |
1355 | /* FIXME: Do nand in the background. Use timers or schedule_task() */ |
1356 | while(len) { | |
0db5bca8 WD |
1357 | /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ |
1358 | mychip = &nand->chips[ofs >> nand->chipshift]; | |
dc7c9a1a | 1359 | |
7a8e9bed WD |
1360 | /* always check for bad block first, genuine bad blocks |
1361 | * should _never_ be erased. | |
1362 | */ | |
1363 | if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { | |
1364 | /* Select the NAND device */ | |
1365 | NAND_ENABLE_CE(nand); /* set pin low */ | |
1366 | ||
1367 | NanD_Command(nand, NAND_CMD_ERASE1); | |
1368 | NanD_Address(nand, ADDR_PAGE, ofs); | |
1369 | NanD_Command(nand, NAND_CMD_ERASE2); | |
1370 | ||
1371 | NanD_Command(nand, NAND_CMD_STATUS); | |
1372 | ||
1f4bb37d WD |
1373 | #ifdef NAND_NO_RB |
1374 | { u_char ret_val; | |
1375 | do{ | |
1376 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1377 | } while((ret_val & 0x40) != 0x40); | |
1378 | } | |
1379 | #endif | |
7a8e9bed WD |
1380 | if (READ_NAND(nandptr) & 1) { |
1381 | printf ("%s: Error erasing at 0x%lx\n", | |
1382 | __FUNCTION__, (long)ofs); | |
1383 | /* There was an error */ | |
1384 | ret = -1; | |
1385 | goto out; | |
1386 | } | |
1387 | if (clean) { | |
1388 | int n; /* return value not used */ | |
1389 | int p, l; | |
1390 | ||
1391 | /* clean marker position and size depend | |
1392 | * on the page size, since 256 byte pages | |
1393 | * only have 8 bytes of oob data | |
1394 | */ | |
1395 | if (nand->page256) { | |
1396 | p = NAND_JFFS2_OOB8_FSDAPOS; | |
1397 | l = NAND_JFFS2_OOB8_FSDALEN; | |
1398 | } | |
1399 | else { | |
1400 | p = NAND_JFFS2_OOB16_FSDAPOS; | |
1401 | l = NAND_JFFS2_OOB16_FSDALEN; | |
1402 | } | |
dc7c9a1a | 1403 | |
7a8e9bed WD |
1404 | ret = nand_write_oob(nand, ofs + p, l, &n, |
1405 | (u_char *)&clean_marker); | |
1406 | /* quit here if write failed */ | |
1407 | if (ret) | |
1408 | goto out; | |
1409 | } | |
dc7c9a1a WD |
1410 | } |
1411 | ofs += nand->erasesize; | |
1412 | len -= nand->erasesize; | |
1413 | } | |
1414 | ||
85ec0bcc WD |
1415 | out: |
1416 | /* De-select the NAND device */ | |
1417 | NAND_DISABLE_CE(nand); /* set pin high */ | |
1f4bb37d WD |
1418 | #ifdef CONFIG_OMAP1510 |
1419 | archflashwp(0,1); | |
1420 | #endif | |
85ec0bcc | 1421 | return ret; |
dc7c9a1a WD |
1422 | } |
1423 | ||
1424 | static inline int nandcheck(unsigned long potential, unsigned long physadr) | |
1425 | { | |
dc7c9a1a WD |
1426 | return 0; |
1427 | } | |
1428 | ||
a43278a4 | 1429 | unsigned long nand_probe(unsigned long physadr) |
dc7c9a1a WD |
1430 | { |
1431 | struct nand_chip *nand = NULL; | |
1432 | int i = 0, ChipID = 1; | |
1433 | ||
1434 | #ifdef CONFIG_MTD_NAND_ECC_JFFS2 | |
1435 | oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; | |
1436 | oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; | |
1437 | oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; | |
1438 | oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; | |
1439 | oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; | |
1440 | oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; | |
dc7c9a1a WD |
1441 | oob_config.eccvalid_pos = 4; |
1442 | #else | |
1443 | oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; | |
1444 | oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; | |
1445 | oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; | |
1446 | oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; | |
1447 | oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; | |
1448 | oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; | |
dc7c9a1a WD |
1449 | oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; |
1450 | #endif | |
7a8e9bed | 1451 | oob_config.badblock_pos = 5; |
dc7c9a1a WD |
1452 | |
1453 | for (i=0; i<CFG_MAX_NAND_DEVICE; i++) { | |
1454 | if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) { | |
a43278a4 | 1455 | nand = &nand_dev_desc[i]; |
dc7c9a1a WD |
1456 | break; |
1457 | } | |
1458 | } | |
a43278a4 WD |
1459 | if (!nand) |
1460 | return (0); | |
dc7c9a1a | 1461 | |
0db5bca8 | 1462 | memset((char *)nand, 0, sizeof(struct nand_chip)); |
dc7c9a1a | 1463 | |
0db5bca8 | 1464 | nand->IO_ADDR = physadr; |
7a8e9bed | 1465 | nand->cache_page = -1; /* init the cache page */ |
0db5bca8 | 1466 | NanD_ScanChips(nand); |
7a8e9bed WD |
1467 | |
1468 | if (nand->totlen == 0) { | |
1469 | /* no chips found, clean up and quit */ | |
1470 | memset((char *)nand, 0, sizeof(struct nand_chip)); | |
1471 | nand->ChipID = NAND_ChipID_UNKNOWN; | |
a43278a4 | 1472 | return (0); |
7a8e9bed WD |
1473 | } |
1474 | ||
1475 | nand->ChipID = ChipID; | |
1476 | if (curr_device == -1) | |
1477 | curr_device = i; | |
1478 | ||
0db5bca8 WD |
1479 | nand->data_buf = malloc (nand->oobblock + nand->oobsize); |
1480 | if (!nand->data_buf) { | |
1481 | puts ("Cannot allocate memory for data structures.\n"); | |
a43278a4 | 1482 | return (0); |
0db5bca8 | 1483 | } |
a43278a4 WD |
1484 | |
1485 | return (nand->totlen); | |
dc7c9a1a WD |
1486 | } |
1487 | ||
1488 | #ifdef CONFIG_MTD_NAND_ECC | |
1489 | /* | |
1490 | * Pre-calculated 256-way 1 byte column parity | |
1491 | */ | |
1492 | static const u_char nand_ecc_precalc_table[] = { | |
1493 | 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, | |
1494 | 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, | |
1495 | 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, | |
1496 | 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, | |
1497 | 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, | |
1498 | 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, | |
1499 | 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, | |
1500 | 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, | |
1501 | 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, | |
1502 | 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, | |
1503 | 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, | |
1504 | 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, | |
1505 | 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, | |
1506 | 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, | |
1507 | 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, | |
1508 | 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 | |
1509 | }; | |
1510 | ||
1511 | ||
1512 | /* | |
1513 | * Creates non-inverted ECC code from line parity | |
1514 | */ | |
1515 | static void nand_trans_result(u_char reg2, u_char reg3, | |
1516 | u_char *ecc_code) | |
1517 | { | |
1518 | u_char a, b, i, tmp1, tmp2; | |
1519 | ||
1520 | /* Initialize variables */ | |
1521 | a = b = 0x80; | |
1522 | tmp1 = tmp2 = 0; | |
1523 | ||
1524 | /* Calculate first ECC byte */ | |
1525 | for (i = 0; i < 4; i++) { | |
1526 | if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ | |
1527 | tmp1 |= b; | |
1528 | b >>= 1; | |
1529 | if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ | |
1530 | tmp1 |= b; | |
1531 | b >>= 1; | |
1532 | a >>= 1; | |
1533 | } | |
1534 | ||
1535 | /* Calculate second ECC byte */ | |
1536 | b = 0x80; | |
1537 | for (i = 0; i < 4; i++) { | |
1538 | if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ | |
1539 | tmp2 |= b; | |
1540 | b >>= 1; | |
1541 | if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ | |
1542 | tmp2 |= b; | |
1543 | b >>= 1; | |
1544 | a >>= 1; | |
1545 | } | |
1546 | ||
1547 | /* Store two of the ECC bytes */ | |
1548 | ecc_code[0] = tmp1; | |
1549 | ecc_code[1] = tmp2; | |
1550 | } | |
1551 | ||
1552 | /* | |
1553 | * Calculate 3 byte ECC code for 256 byte block | |
1554 | */ | |
1555 | static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) | |
1556 | { | |
7a8e9bed | 1557 | u_char idx, reg1, reg3; |
dc7c9a1a WD |
1558 | int j; |
1559 | ||
1560 | /* Initialize variables */ | |
7a8e9bed | 1561 | reg1 = reg3 = 0; |
dc7c9a1a WD |
1562 | ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; |
1563 | ||
1564 | /* Build up column parity */ | |
1565 | for(j = 0; j < 256; j++) { | |
1566 | ||
1567 | /* Get CP0 - CP5 from table */ | |
1568 | idx = nand_ecc_precalc_table[dat[j]]; | |
7a8e9bed | 1569 | reg1 ^= idx; |
dc7c9a1a WD |
1570 | |
1571 | /* All bit XOR = 1 ? */ | |
1572 | if (idx & 0x40) { | |
1573 | reg3 ^= (u_char) j; | |
dc7c9a1a WD |
1574 | } |
1575 | } | |
1576 | ||
1577 | /* Create non-inverted ECC code from line parity */ | |
7a8e9bed | 1578 | nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); |
dc7c9a1a WD |
1579 | |
1580 | /* Calculate final ECC code */ | |
1581 | ecc_code[0] = ~ecc_code[0]; | |
1582 | ecc_code[1] = ~ecc_code[1]; | |
1583 | ecc_code[2] = ((~reg1) << 2) | 0x03; | |
1584 | } | |
1585 | ||
1586 | /* | |
1587 | * Detect and correct a 1 bit error for 256 byte block | |
1588 | */ | |
1589 | static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) | |
1590 | { | |
1591 | u_char a, b, c, d1, d2, d3, add, bit, i; | |
1592 | ||
1593 | /* Do error detection */ | |
1594 | d1 = calc_ecc[0] ^ read_ecc[0]; | |
1595 | d2 = calc_ecc[1] ^ read_ecc[1]; | |
1596 | d3 = calc_ecc[2] ^ read_ecc[2]; | |
1597 | ||
1598 | if ((d1 | d2 | d3) == 0) { | |
1599 | /* No errors */ | |
1600 | return 0; | |
1601 | } | |
1602 | else { | |
1603 | a = (d1 ^ (d1 >> 1)) & 0x55; | |
1604 | b = (d2 ^ (d2 >> 1)) & 0x55; | |
1605 | c = (d3 ^ (d3 >> 1)) & 0x54; | |
1606 | ||
1607 | /* Found and will correct single bit error in the data */ | |
1608 | if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { | |
1609 | c = 0x80; | |
1610 | add = 0; | |
1611 | a = 0x80; | |
1612 | for (i=0; i<4; i++) { | |
1613 | if (d1 & c) | |
1614 | add |= a; | |
1615 | c >>= 2; | |
1616 | a >>= 1; | |
1617 | } | |
1618 | c = 0x80; | |
1619 | for (i=0; i<4; i++) { | |
1620 | if (d2 & c) | |
1621 | add |= a; | |
1622 | c >>= 2; | |
1623 | a >>= 1; | |
1624 | } | |
1625 | bit = 0; | |
1626 | b = 0x04; | |
1627 | c = 0x80; | |
1628 | for (i=0; i<3; i++) { | |
1629 | if (d3 & c) | |
1630 | bit |= b; | |
1631 | c >>= 2; | |
1632 | b >>= 1; | |
1633 | } | |
1634 | b = 0x01; | |
1635 | a = dat[add]; | |
1636 | a ^= (b << bit); | |
1637 | dat[add] = a; | |
1638 | return 1; | |
1639 | } | |
1640 | else { | |
1641 | i = 0; | |
1642 | while (d1) { | |
1643 | if (d1 & 0x01) | |
1644 | ++i; | |
1645 | d1 >>= 1; | |
1646 | } | |
1647 | while (d2) { | |
1648 | if (d2 & 0x01) | |
1649 | ++i; | |
1650 | d2 >>= 1; | |
1651 | } | |
1652 | while (d3) { | |
1653 | if (d3 & 0x01) | |
1654 | ++i; | |
1655 | d3 >>= 1; | |
1656 | } | |
1657 | if (i == 1) { | |
1658 | /* ECC Code Error Correction */ | |
1659 | read_ecc[0] = calc_ecc[0]; | |
1660 | read_ecc[1] = calc_ecc[1]; | |
1661 | read_ecc[2] = calc_ecc[2]; | |
1662 | return 2; | |
1663 | } | |
1664 | else { | |
1665 | /* Uncorrectable Error */ | |
1666 | return -1; | |
1667 | } | |
1668 | } | |
1669 | } | |
1670 | ||
1671 | /* Should never happen */ | |
1672 | return -1; | |
1673 | } | |
1f4bb37d | 1674 | |
dc7c9a1a | 1675 | #endif |
998eaaec WD |
1676 | |
1677 | #ifdef CONFIG_JFFS2_NAND | |
1678 | ||
1679 | int read_jffs2_nand(size_t start, size_t len, | |
1680 | size_t * retlen, u_char * buf, int nanddev) | |
1681 | { | |
1682 | return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, | |
1683 | start, len, retlen, buf); | |
1684 | } | |
1685 | ||
1686 | #endif /* CONFIG_JFFS2_NAND */ | |
1687 | ||
1688 | ||
dc7c9a1a | 1689 | #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ |