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de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
de941241 SG |
34 | #include <asm/io.h> |
35 | #include <asm/arch/mmc_host_def.h> | |
3b68939f RQ |
36 | #if !defined(CONFIG_SOC_KEYSTONE) |
37 | #include <asm/gpio.h> | |
96e0e7b3 | 38 | #include <asm/arch/sys_proto.h> |
3b68939f | 39 | #endif |
de941241 | 40 | |
ab769f22 PA |
41 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
42 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
43 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
44 | #define OMAP_HSMMC_USE_GPIO | |
45 | #else | |
46 | #undef OMAP_HSMMC_USE_GPIO | |
47 | #endif | |
48 | ||
25c719e2 GI |
49 | /* common definitions for all OMAPs */ |
50 | #define SYSCTL_SRC (1 << 25) | |
51 | #define SYSCTL_SRD (1 << 26) | |
52 | ||
cc22b0c0 NK |
53 | struct omap_hsmmc_data { |
54 | struct hsmmc *base_addr; | |
93bfd616 | 55 | struct mmc_config cfg; |
ab769f22 | 56 | #ifdef OMAP_HSMMC_USE_GPIO |
e874d5b0 | 57 | int cd_gpio; |
e3913f56 | 58 | int wp_gpio; |
ab769f22 | 59 | #endif |
cc22b0c0 NK |
60 | }; |
61 | ||
eb9a28f6 NM |
62 | /* If we fail after 1 second wait, something is really bad */ |
63 | #define MAX_RETRY_MS 1000 | |
64 | ||
933efe64 S |
65 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
66 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
67 | unsigned int siz); | |
14fa2dd0 | 68 | |
ab769f22 | 69 | #ifdef OMAP_HSMMC_USE_GPIO |
e874d5b0 NK |
70 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
71 | { | |
5915a2ad | 72 | int ret; |
e874d5b0 | 73 | |
5915a2ad SG |
74 | #ifndef CONFIG_DM_GPIO |
75 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 76 | return -1; |
5915a2ad SG |
77 | #endif |
78 | ret = gpio_request(gpio, label); | |
79 | if (ret) | |
80 | return ret; | |
e874d5b0 | 81 | |
5915a2ad SG |
82 | ret = gpio_direction_input(gpio); |
83 | if (ret) | |
84 | return ret; | |
e874d5b0 NK |
85 | |
86 | return gpio; | |
87 | } | |
e874d5b0 NK |
88 | #endif |
89 | ||
14fa2dd0 B |
90 | #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) |
91 | static void omap4_vmmc_pbias_config(struct mmc *mmc) | |
92 | { | |
93 | u32 value = 0; | |
14fa2dd0 | 94 | |
c43c8339 | 95 | value = readl((*ctrl)->control_pbiaslite); |
14fa2dd0 | 96 | value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); |
c43c8339 | 97 | writel(value, (*ctrl)->control_pbiaslite); |
14fa2dd0 B |
98 | /* set VMMC to 3V */ |
99 | twl6030_power_mmc_init(); | |
c43c8339 | 100 | value = readl((*ctrl)->control_pbiaslite); |
14fa2dd0 | 101 | value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; |
c43c8339 | 102 | writel(value, (*ctrl)->control_pbiaslite); |
14fa2dd0 B |
103 | } |
104 | #endif | |
105 | ||
cb199102 | 106 | #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) |
dd23e59d B |
107 | static void omap5_pbias_config(struct mmc *mmc) |
108 | { | |
109 | u32 value = 0; | |
dd23e59d | 110 | |
c43c8339 | 111 | value = readl((*ctrl)->control_pbias); |
a5d439c2 B |
112 | value &= ~SDCARD_PWRDNZ; |
113 | writel(value, (*ctrl)->control_pbias); | |
114 | udelay(10); /* wait 10 us */ | |
115 | value &= ~SDCARD_BIAS_PWRDNZ; | |
c43c8339 | 116 | writel(value, (*ctrl)->control_pbias); |
dd23e59d | 117 | |
384bcae0 | 118 | palmas_mmc1_poweron_ldo(); |
dd23e59d | 119 | |
c43c8339 | 120 | value = readl((*ctrl)->control_pbias); |
a5d439c2 | 121 | value |= SDCARD_BIAS_PWRDNZ; |
c43c8339 | 122 | writel(value, (*ctrl)->control_pbias); |
a5d439c2 B |
123 | udelay(150); /* wait 150 us */ |
124 | value |= SDCARD_PWRDNZ; | |
125 | writel(value, (*ctrl)->control_pbias); | |
126 | udelay(150); /* wait 150 us */ | |
dd23e59d B |
127 | } |
128 | #endif | |
129 | ||
750121c3 | 130 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 131 | { |
de941241 SG |
132 | #if defined(CONFIG_OMAP34XX) |
133 | t2_t *t2_base = (t2_t *)T2_BASE; | |
134 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 135 | u32 pbias_lite; |
de941241 | 136 | |
b1e725f2 GI |
137 | pbias_lite = readl(&t2_base->pbias_lite); |
138 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
139 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
140 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
141 | pbias_lite &= ~PBIASLITEVMODE0; | |
142 | #endif | |
b1e725f2 | 143 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 144 | |
b1e725f2 | 145 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
146 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
147 | &t2_base->pbias_lite); | |
148 | ||
149 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, | |
150 | &t2_base->devconf0); | |
151 | ||
152 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
153 | &t2_base->devconf1); | |
154 | ||
bbbc1ae9 | 155 | /* Change from default of 52MHz to 26MHz if necessary */ |
93bfd616 | 156 | if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
157 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
158 | &t2_base->ctl_prog_io1); | |
159 | ||
de941241 SG |
160 | writel(readl(&prcm_base->fclken1_core) | |
161 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
162 | &prcm_base->fclken1_core); | |
163 | ||
164 | writel(readl(&prcm_base->iclken1_core) | | |
165 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
166 | &prcm_base->iclken1_core); | |
167 | #endif | |
168 | ||
14fa2dd0 B |
169 | #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) |
170 | /* PBIAS config needed for MMC1 only */ | |
171 | if (mmc->block_dev.dev == 0) | |
172 | omap4_vmmc_pbias_config(mmc); | |
173 | #endif | |
cb199102 | 174 | #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) |
dd23e59d B |
175 | if (mmc->block_dev.dev == 0) |
176 | omap5_pbias_config(mmc); | |
177 | #endif | |
de941241 SG |
178 | |
179 | return 0; | |
180 | } | |
181 | ||
933efe64 | 182 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 183 | { |
eb9a28f6 | 184 | ulong start; |
de941241 SG |
185 | |
186 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
187 | ||
188 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
189 | start = get_timer(0); |
190 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
191 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
192 | printf("%s: timedout waiting for cc!\n", __func__); | |
193 | return; | |
194 | } | |
195 | } | |
de941241 SG |
196 | writel(CC_MASK, &mmc_base->stat) |
197 | ; | |
198 | writel(MMC_CMD0, &mmc_base->cmd) | |
199 | ; | |
eb9a28f6 NM |
200 | start = get_timer(0); |
201 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
202 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
203 | printf("%s: timedout waiting for cc2!\n", __func__); | |
204 | return; | |
205 | } | |
206 | } | |
de941241 SG |
207 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
208 | } | |
209 | ||
210 | ||
ab769f22 | 211 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 212 | { |
cc22b0c0 | 213 | struct hsmmc *mmc_base; |
de941241 SG |
214 | unsigned int reg_val; |
215 | unsigned int dsor; | |
eb9a28f6 | 216 | ulong start; |
de941241 | 217 | |
cc22b0c0 | 218 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
14fa2dd0 | 219 | mmc_board_init(mmc); |
de941241 SG |
220 | |
221 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
222 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
223 | start = get_timer(0); |
224 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
225 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
226 | printf("%s: timedout waiting for cc2!\n", __func__); | |
227 | return TIMEOUT; | |
228 | } | |
229 | } | |
de941241 | 230 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
231 | start = get_timer(0); |
232 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
233 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
234 | printf("%s: timedout waiting for softresetall!\n", | |
235 | __func__); | |
236 | return TIMEOUT; | |
237 | } | |
238 | } | |
de941241 SG |
239 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
240 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
241 | &mmc_base->capa); | |
242 | ||
243 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
244 | ||
245 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
246 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
247 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
248 | ||
249 | dsor = 240; | |
250 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
251 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
252 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
253 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
254 | start = get_timer(0); |
255 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
256 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
257 | printf("%s: timedout waiting for ics!\n", __func__); | |
258 | return TIMEOUT; | |
259 | } | |
260 | } | |
de941241 SG |
261 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
262 | ||
263 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
264 | ||
265 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
266 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
267 | &mmc_base->ie); | |
268 | ||
269 | mmc_init_stream(mmc_base); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
25c719e2 GI |
274 | /* |
275 | * MMC controller internal finite state machine reset | |
276 | * | |
277 | * Used to reset command or data internal state machines, using respectively | |
278 | * SRC or SRD bit of SYSCTL register | |
279 | */ | |
280 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
281 | { | |
282 | ulong start; | |
283 | ||
284 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
285 | ||
61a6cc27 OT |
286 | /* |
287 | * CMD(DAT) lines reset procedures are slightly different | |
288 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
289 | * According to OMAP3 TRM: | |
290 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
291 | * returns to 0x0. | |
292 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
293 | * procedure steps must be as follows: | |
294 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
295 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
296 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
297 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
298 | * (reset procedure is completed). | |
299 | */ | |
300 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 301 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
302 | if (!(readl(&mmc_base->sysctl) & bit)) { |
303 | start = get_timer(0); | |
304 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
305 | if (get_timer(0) - start > MAX_RETRY_MS) | |
306 | return; | |
307 | } | |
308 | } | |
309 | #endif | |
25c719e2 GI |
310 | start = get_timer(0); |
311 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
312 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
313 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
314 | __func__, bit); | |
315 | return; | |
316 | } | |
317 | } | |
318 | } | |
de941241 | 319 | |
ab769f22 | 320 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
321 | struct mmc_data *data) |
322 | { | |
cc22b0c0 | 323 | struct hsmmc *mmc_base; |
de941241 | 324 | unsigned int flags, mmc_stat; |
eb9a28f6 | 325 | ulong start; |
de941241 | 326 | |
cc22b0c0 | 327 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
eb9a28f6 | 328 | start = get_timer(0); |
a7778f8f | 329 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 330 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
331 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
332 | __func__); | |
eb9a28f6 NM |
333 | return TIMEOUT; |
334 | } | |
335 | } | |
de941241 | 336 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
337 | start = get_timer(0); |
338 | while (readl(&mmc_base->stat)) { | |
339 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
340 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
341 | __func__, readl(&mmc_base->stat)); | |
eb9a28f6 NM |
342 | return TIMEOUT; |
343 | } | |
344 | } | |
de941241 SG |
345 | /* |
346 | * CMDREG | |
347 | * CMDIDX[13:8] : Command index | |
348 | * DATAPRNT[5] : Data Present Select | |
349 | * ENCMDIDX[4] : Command Index Check Enable | |
350 | * ENCMDCRC[3] : Command CRC Check Enable | |
351 | * RSPTYP[1:0] | |
352 | * 00 = No Response | |
353 | * 01 = Length 136 | |
354 | * 10 = Length 48 | |
355 | * 11 = Length 48 Check busy after response | |
356 | */ | |
357 | /* Delay added before checking the status of frq change | |
358 | * retry not supported by mmc.c(core file) | |
359 | */ | |
360 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
361 | udelay(50000); /* wait 50 ms */ | |
362 | ||
363 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
364 | flags = 0; | |
365 | else if (cmd->resp_type & MMC_RSP_136) | |
366 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
367 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
368 | flags = RSP_TYPE_LGHT48B; | |
369 | else | |
370 | flags = RSP_TYPE_LGHT48; | |
371 | ||
372 | /* enable default flags */ | |
373 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
374 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
375 | ||
376 | if (cmd->resp_type & MMC_RSP_CRC) | |
377 | flags |= CCCE_CHECK; | |
378 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
379 | flags |= CICE_CHECK; | |
380 | ||
381 | if (data) { | |
382 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
383 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
384 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
385 | data->blocksize = 512; | |
386 | writel(data->blocksize | (data->blocks << 16), | |
387 | &mmc_base->blk); | |
388 | } else | |
389 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
390 | ||
391 | if (data->flags & MMC_DATA_READ) | |
392 | flags |= (DP_DATA | DDIR_READ); | |
393 | else | |
394 | flags |= (DP_DATA | DDIR_WRITE); | |
395 | } | |
396 | ||
397 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 398 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
399 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
400 | ||
eb9a28f6 | 401 | start = get_timer(0); |
de941241 SG |
402 | do { |
403 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
404 | if (get_timer(0) - start > MAX_RETRY_MS) { |
405 | printf("%s : timeout: No status update\n", __func__); | |
406 | return TIMEOUT; | |
407 | } | |
408 | } while (!mmc_stat); | |
de941241 | 409 | |
25c719e2 GI |
410 | if ((mmc_stat & IE_CTO) != 0) { |
411 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
de941241 | 412 | return TIMEOUT; |
25c719e2 | 413 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
414 | return -1; |
415 | ||
416 | if (mmc_stat & CC_MASK) { | |
417 | writel(CC_MASK, &mmc_base->stat); | |
418 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
419 | if (cmd->resp_type & MMC_RSP_136) { | |
420 | /* response type 2 */ | |
421 | cmd->response[3] = readl(&mmc_base->rsp10); | |
422 | cmd->response[2] = readl(&mmc_base->rsp32); | |
423 | cmd->response[1] = readl(&mmc_base->rsp54); | |
424 | cmd->response[0] = readl(&mmc_base->rsp76); | |
425 | } else | |
426 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
427 | cmd->response[0] = readl(&mmc_base->rsp10); | |
428 | } | |
429 | } | |
430 | ||
431 | if (data && (data->flags & MMC_DATA_READ)) { | |
432 | mmc_read_data(mmc_base, data->dest, | |
433 | data->blocksize * data->blocks); | |
434 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
435 | mmc_write_data(mmc_base, data->src, | |
436 | data->blocksize * data->blocks); | |
437 | } | |
438 | return 0; | |
439 | } | |
440 | ||
933efe64 | 441 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
442 | { |
443 | unsigned int *output_buf = (unsigned int *)buf; | |
444 | unsigned int mmc_stat; | |
445 | unsigned int count; | |
446 | ||
447 | /* | |
448 | * Start Polled Read | |
449 | */ | |
450 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
451 | count /= 4; | |
452 | ||
453 | while (size) { | |
eb9a28f6 | 454 | ulong start = get_timer(0); |
de941241 SG |
455 | do { |
456 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
457 | if (get_timer(0) - start > MAX_RETRY_MS) { |
458 | printf("%s: timedout waiting for status!\n", | |
459 | __func__); | |
460 | return TIMEOUT; | |
461 | } | |
de941241 SG |
462 | } while (mmc_stat == 0); |
463 | ||
25c719e2 GI |
464 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
465 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
466 | ||
de941241 SG |
467 | if ((mmc_stat & ERRI_MASK) != 0) |
468 | return 1; | |
469 | ||
470 | if (mmc_stat & BRR_MASK) { | |
471 | unsigned int k; | |
472 | ||
473 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
474 | &mmc_base->stat); | |
475 | for (k = 0; k < count; k++) { | |
476 | *output_buf = readl(&mmc_base->data); | |
477 | output_buf++; | |
478 | } | |
479 | size -= (count*4); | |
480 | } | |
481 | ||
482 | if (mmc_stat & BWR_MASK) | |
483 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
484 | &mmc_base->stat); | |
485 | ||
486 | if (mmc_stat & TC_MASK) { | |
487 | writel(readl(&mmc_base->stat) | TC_MASK, | |
488 | &mmc_base->stat); | |
489 | break; | |
490 | } | |
491 | } | |
492 | return 0; | |
493 | } | |
494 | ||
933efe64 S |
495 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
496 | unsigned int size) | |
de941241 SG |
497 | { |
498 | unsigned int *input_buf = (unsigned int *)buf; | |
499 | unsigned int mmc_stat; | |
500 | unsigned int count; | |
501 | ||
502 | /* | |
152ba363 | 503 | * Start Polled Write |
de941241 SG |
504 | */ |
505 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
506 | count /= 4; | |
507 | ||
508 | while (size) { | |
eb9a28f6 | 509 | ulong start = get_timer(0); |
de941241 SG |
510 | do { |
511 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
512 | if (get_timer(0) - start > MAX_RETRY_MS) { |
513 | printf("%s: timedout waiting for status!\n", | |
514 | __func__); | |
515 | return TIMEOUT; | |
516 | } | |
de941241 SG |
517 | } while (mmc_stat == 0); |
518 | ||
25c719e2 GI |
519 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
520 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
521 | ||
de941241 SG |
522 | if ((mmc_stat & ERRI_MASK) != 0) |
523 | return 1; | |
524 | ||
525 | if (mmc_stat & BWR_MASK) { | |
526 | unsigned int k; | |
527 | ||
528 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
529 | &mmc_base->stat); | |
530 | for (k = 0; k < count; k++) { | |
531 | writel(*input_buf, &mmc_base->data); | |
532 | input_buf++; | |
533 | } | |
534 | size -= (count*4); | |
535 | } | |
536 | ||
537 | if (mmc_stat & BRR_MASK) | |
538 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
539 | &mmc_base->stat); | |
540 | ||
541 | if (mmc_stat & TC_MASK) { | |
542 | writel(readl(&mmc_base->stat) | TC_MASK, | |
543 | &mmc_base->stat); | |
544 | break; | |
545 | } | |
546 | } | |
547 | return 0; | |
548 | } | |
549 | ||
ab769f22 | 550 | static void omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 551 | { |
cc22b0c0 | 552 | struct hsmmc *mmc_base; |
de941241 | 553 | unsigned int dsor = 0; |
eb9a28f6 | 554 | ulong start; |
de941241 | 555 | |
cc22b0c0 | 556 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
de941241 SG |
557 | /* configue bus width */ |
558 | switch (mmc->bus_width) { | |
559 | case 8: | |
560 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
561 | &mmc_base->con); | |
562 | break; | |
563 | ||
564 | case 4: | |
565 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
566 | &mmc_base->con); | |
567 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
568 | &mmc_base->hctl); | |
569 | break; | |
570 | ||
571 | case 1: | |
572 | default: | |
573 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
574 | &mmc_base->con); | |
575 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
576 | &mmc_base->hctl); | |
577 | break; | |
578 | } | |
579 | ||
580 | /* configure clock with 96Mhz system clock. | |
581 | */ | |
582 | if (mmc->clock != 0) { | |
583 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
584 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
585 | dsor++; | |
586 | } | |
587 | ||
588 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
589 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
590 | ||
591 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
592 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
593 | ||
eb9a28f6 NM |
594 | start = get_timer(0); |
595 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
596 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
597 | printf("%s: timedout waiting for ics!\n", __func__); | |
598 | return; | |
599 | } | |
600 | } | |
de941241 SG |
601 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
602 | } | |
603 | ||
ab769f22 PA |
604 | #ifdef OMAP_HSMMC_USE_GPIO |
605 | static int omap_hsmmc_getcd(struct mmc *mmc) | |
606 | { | |
607 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
608 | int cd_gpio; | |
609 | ||
610 | /* if no CD return as 1 */ | |
611 | cd_gpio = priv_data->cd_gpio; | |
612 | if (cd_gpio < 0) | |
613 | return 1; | |
614 | ||
0b03a931 IG |
615 | /* NOTE: assumes card detect signal is active-low */ |
616 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
617 | } |
618 | ||
619 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
620 | { | |
621 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
622 | int wp_gpio; | |
623 | ||
624 | /* if no WP return as 0 */ | |
625 | wp_gpio = priv_data->wp_gpio; | |
626 | if (wp_gpio < 0) | |
627 | return 0; | |
628 | ||
0b03a931 | 629 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
630 | return gpio_get_value(wp_gpio); |
631 | } | |
632 | #endif | |
633 | ||
634 | static const struct mmc_ops omap_hsmmc_ops = { | |
635 | .send_cmd = omap_hsmmc_send_cmd, | |
636 | .set_ios = omap_hsmmc_set_ios, | |
637 | .init = omap_hsmmc_init_setup, | |
638 | #ifdef OMAP_HSMMC_USE_GPIO | |
639 | .getcd = omap_hsmmc_getcd, | |
640 | .getwp = omap_hsmmc_getwp, | |
641 | #endif | |
642 | }; | |
643 | ||
e3913f56 NK |
644 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
645 | int wp_gpio) | |
de941241 | 646 | { |
93bfd616 PA |
647 | struct mmc *mmc; |
648 | struct omap_hsmmc_data *priv_data; | |
649 | struct mmc_config *cfg; | |
650 | uint host_caps_val; | |
651 | ||
652 | priv_data = malloc(sizeof(*priv_data)); | |
653 | if (priv_data == NULL) | |
654 | return -1; | |
de941241 | 655 | |
5a20397b | 656 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
657 | |
658 | switch (dev_index) { | |
659 | case 0: | |
cc22b0c0 | 660 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 661 | break; |
1037d585 | 662 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 663 | case 1: |
cc22b0c0 | 664 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 665 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
9fbdca60 | 666 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \ |
3b68939f RQ |
667 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
668 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
669 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
670 | host_caps_val |= MMC_MODE_8BIT; | |
671 | #endif | |
de941241 | 672 | break; |
1037d585 TR |
673 | #endif |
674 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 675 | case 2: |
cc22b0c0 | 676 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
d11ac4b5 | 677 | #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
678 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
679 | host_caps_val |= MMC_MODE_8BIT; | |
680 | #endif | |
de941241 | 681 | break; |
1037d585 | 682 | #endif |
de941241 | 683 | default: |
cc22b0c0 | 684 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
685 | return 1; |
686 | } | |
ab769f22 PA |
687 | #ifdef OMAP_HSMMC_USE_GPIO |
688 | /* on error gpio values are set to -1, which is what we want */ | |
e874d5b0 | 689 | priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
e3913f56 | 690 | priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); |
ab769f22 | 691 | #endif |
173ddc5b | 692 | |
93bfd616 | 693 | cfg = &priv_data->cfg; |
de941241 | 694 | |
93bfd616 PA |
695 | cfg->name = "OMAP SD/MMC"; |
696 | cfg->ops = &omap_hsmmc_ops; | |
697 | ||
698 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
699 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
700 | ||
701 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
702 | |
703 | if (f_max != 0) | |
93bfd616 | 704 | cfg->f_max = f_max; |
bbbc1ae9 | 705 | else { |
93bfd616 PA |
706 | if (cfg->host_caps & MMC_MODE_HS) { |
707 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
708 | cfg->f_max = 52000000; | |
bbbc1ae9 | 709 | else |
93bfd616 | 710 | cfg->f_max = 26000000; |
bbbc1ae9 | 711 | } else |
93bfd616 | 712 | cfg->f_max = 20000000; |
bbbc1ae9 | 713 | } |
de941241 | 714 | |
93bfd616 | 715 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 716 | |
4ca9244d JR |
717 | #if defined(CONFIG_OMAP34XX) |
718 | /* | |
719 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
720 | */ | |
721 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 722 | cfg->b_max = 1; |
4ca9244d | 723 | #endif |
93bfd616 PA |
724 | mmc = mmc_create(cfg, priv_data); |
725 | if (mmc == NULL) | |
726 | return -1; | |
de941241 SG |
727 | |
728 | return 0; | |
729 | } |