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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 MK |
32 | #include <asm/byteorder.h> |
33 | ||
34 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 35 | # include <pci.h> |
477434c6 SP |
36 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
37 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
38 | #endif | |
ddf83a2f | 39 | #endif |
3e326ece MK |
40 | |
41 | #include <malloc.h> | |
42 | #include <usb.h> | |
2731b9a8 JCPV |
43 | |
44 | #include "ohci.h" | |
3e326ece | 45 | |
e8da58f2 WD |
46 | #ifdef CONFIG_AT91RM9200 |
47 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
48 | #endif | |
49 | ||
f2168440 | 50 | #if defined(CONFIG_CPU_ARM920T) || \ |
ac67804f | 51 | defined(CONFIG_S3C24X0) || \ |
ae3b770e | 52 | defined(CONFIG_440EP) || \ |
4dae14ce | 53 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 54 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 55 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
56 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
57 | #endif | |
58 | ||
3e326ece | 59 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
60 | #undef DEBUG |
61 | #undef SHOW_INFO | |
62 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
63 | |
64 | /* For initializing controller (mask in an HCFS mode too) */ | |
65 | #define OHCI_CONTROL_INIT \ | |
66 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
67 | ||
4dae14ce ZW |
68 | #ifdef CONFIG_PCI_OHCI |
69 | static struct pci_device_id ohci_pci_ids[] = { | |
70 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 71 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 72 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
73 | /* Please add supported PCI OHCI controller ids here */ |
74 | {0, 0} | |
75 | }; | |
76 | #endif | |
77 | ||
e90fb6af YT |
78 | #ifdef CONFIG_PCI_EHCI_DEVNO |
79 | static struct pci_device_id ehci_pci_ids[] = { | |
80 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
81 | /* Please add supported PCI EHCI controller ids here */ | |
82 | {0, 0} | |
83 | }; | |
84 | #endif | |
85 | ||
3e326ece MK |
86 | #ifdef DEBUG |
87 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
88 | #else | |
6f5794a6 | 89 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
90 | #endif /* DEBUG */ |
91 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
92 | #ifdef SHOW_INFO |
93 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
94 | #else | |
6f5794a6 | 95 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
96 | #endif |
97 | ||
6d0f6bcf | 98 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
99 | # define m16_swap(x) cpu_to_be16(x) |
100 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 101 | #else |
fc43be47 MK |
102 | # define m16_swap(x) cpu_to_le16(x) |
103 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 104 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece | 105 | |
8d005ef8 HG |
106 | #ifdef CONFIG_DM_USB |
107 | /* | |
108 | * We really should do proper cache flushing everywhere, but for now we only | |
109 | * do it for new (driver-model) usb code to avoid regressions. | |
110 | */ | |
111 | #define flush_dcache_buffer(addr, size) \ | |
112 | flush_dcache_range((unsigned long)(addr), \ | |
113 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
114 | #define invalidate_dcache_buffer(addr, size) \ | |
115 | invalidate_dcache_range((unsigned long)(addr), \ | |
116 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
117 | #else | |
118 | #define flush_dcache_buffer(addr, size) | |
119 | #define invalidate_dcache_buffer(addr, size) | |
120 | #endif | |
121 | ||
122 | /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ | |
123 | #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) | |
124 | #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) | |
125 | #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) | |
126 | #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) | |
127 | #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) | |
128 | #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) | |
129 | #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) | |
130 | #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) | |
131 | ||
3e326ece MK |
132 | /* global ohci_t */ |
133 | static ohci_t gohci; | |
134 | /* this must be aligned to a 256 byte boundary */ | |
135 | struct ohci_hcca ghcca[1]; | |
3e326ece | 136 | |
6651c140 HG |
137 | /* mapping of the OHCI CC status to error codes */ |
138 | static int cc_to_error[16] = { | |
139 | /* No Error */ 0, | |
140 | /* CRC Error */ USB_ST_CRC_ERR, | |
141 | /* Bit Stuff */ USB_ST_BIT_ERR, | |
142 | /* Data Togg */ USB_ST_CRC_ERR, | |
143 | /* Stall */ USB_ST_STALLED, | |
144 | /* DevNotResp */ -1, | |
145 | /* PIDCheck */ USB_ST_BIT_ERR, | |
146 | /* UnExpPID */ USB_ST_BIT_ERR, | |
147 | /* DataOver */ USB_ST_BUF_ERR, | |
148 | /* DataUnder */ USB_ST_BUF_ERR, | |
149 | /* reservd */ -1, | |
150 | /* reservd */ -1, | |
151 | /* BufferOver */ USB_ST_BUF_ERR, | |
152 | /* BuffUnder */ USB_ST_BUF_ERR, | |
153 | /* Not Access */ -1, | |
154 | /* Not Access */ -1 | |
155 | }; | |
156 | ||
157 | static const char *cc_to_string[16] = { | |
158 | "No Error", | |
159 | "CRC: Last data packet from endpoint contained a CRC error.", | |
160 | "BITSTUFFING: Last data packet from endpoint contained a bit " \ | |
161 | "stuffing violation", | |
162 | "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ | |
163 | "that did not match the expected value.", | |
164 | "STALL: TD was moved to the Done Queue because the endpoint returned" \ | |
165 | " a STALL PID", | |
166 | "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ | |
167 | "not provide a handshake (OUT)", | |
168 | "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ | |
169 | "(IN) or handshake (OUT)", | |
170 | "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ | |
171 | "value is not defined.", | |
172 | "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ | |
173 | "either the size of the maximum data packet allowed\n" \ | |
174 | "from the endpoint (found in MaximumPacketSize field\n" \ | |
175 | "of ED) or the remaining buffer size.", | |
176 | "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ | |
177 | "and that amount was not sufficient to fill the\n" \ | |
178 | "specified buffer", | |
179 | "reserved1", | |
180 | "reserved2", | |
181 | "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ | |
182 | "than it could be written to system memory", | |
183 | "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ | |
184 | "system memory fast enough to keep up with data USB " \ | |
185 | "data rate.", | |
186 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
187 | "on a list to be processed by the HC.(1)", | |
188 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
189 | "on a list to be processed by the HC.(2)", | |
190 | }; | |
191 | ||
6f5794a6 | 192 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 193 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 194 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 195 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 196 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 197 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 198 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 199 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 200 | |
3e326ece | 201 | /* forward declaration */ |
c5613df5 HG |
202 | static int hc_interrupt(ohci_t *ohci); |
203 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, | |
204 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
205 | struct devrequest *setup, urb_priv_t *urb, |
206 | int interval); | |
6651c140 HG |
207 | static int ep_link(ohci_t * ohci, ed_t * ed); |
208 | static int ep_unlink(ohci_t * ohci, ed_t * ed); | |
209 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, | |
210 | unsigned long pipe, int interval, int load); | |
211 | ||
212 | /*-------------------------------------------------------------------------*/ | |
213 | ||
214 | /* TDs ... */ | |
215 | static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) | |
216 | { | |
217 | int i; | |
218 | struct td *td; | |
219 | ||
220 | td = NULL; | |
221 | for (i = 0; i < NUM_TD; i++) | |
222 | { | |
223 | if (ohci_dev->tds[i].usb_dev == NULL) | |
224 | { | |
225 | td = &ohci_dev->tds[i]; | |
226 | td->usb_dev = usb_dev; | |
227 | break; | |
228 | } | |
229 | } | |
230 | ||
231 | return td; | |
232 | } | |
233 | ||
234 | static inline void ed_free(struct ed *ed) | |
235 | { | |
236 | ed->usb_dev = NULL; | |
237 | } | |
3e326ece MK |
238 | |
239 | /*-------------------------------------------------------------------------* | |
240 | * URB support functions | |
241 | *-------------------------------------------------------------------------*/ | |
242 | ||
243 | /* free HCD-private data associated with this URB */ | |
244 | ||
6f5794a6 | 245 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
246 | { |
247 | int i; | |
248 | int last; | |
6f5794a6 | 249 | struct td *td; |
3e326ece MK |
250 | |
251 | last = urb->length - 1; | |
252 | if (last >= 0) { | |
253 | for (i = 0; i <= last; i++) { | |
254 | td = urb->td[i]; | |
255 | if (td) { | |
256 | td->usb_dev = NULL; | |
257 | urb->td[i] = NULL; | |
258 | } | |
259 | } | |
260 | } | |
4dae14ce | 261 | free(urb); |
3e326ece MK |
262 | } |
263 | ||
264 | /*-------------------------------------------------------------------------*/ | |
265 | ||
266 | #ifdef DEBUG | |
c5613df5 | 267 | static int sohci_get_current_frame_number(ohci_t *ohci); |
3e326ece MK |
268 | |
269 | /* debug| print the main components of an URB | |
270 | * small: 0) header + data packets 1) just header */ | |
271 | ||
c5613df5 | 272 | static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, |
6f5794a6 RB |
273 | unsigned long pipe, void *buffer, int transfer_len, |
274 | struct devrequest *setup, char *str, int small) | |
3e326ece | 275 | { |
6f5794a6 | 276 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 277 | str, |
c5613df5 | 278 | sohci_get_current_frame_number(ohci), |
6f5794a6 RB |
279 | usb_pipedevice(pipe), |
280 | usb_pipeendpoint(pipe), | |
281 | usb_pipeout(pipe)? 'O': 'I', | |
282 | usb_pipetype(pipe) < 2 ? \ | |
283 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
284 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 285 | (purb ? purb->actual_length : 0), |
3e326ece MK |
286 | transfer_len, dev->status); |
287 | #ifdef OHCI_VERBOSE_DEBUG | |
288 | if (!small) { | |
289 | int i, len; | |
290 | ||
6f5794a6 RB |
291 | if (usb_pipecontrol(pipe)) { |
292 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 293 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
294 | printf(" %02x", ((__u8 *) setup) [i]); |
295 | printf("\n"); | |
3e326ece MK |
296 | } |
297 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 298 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 299 | (purb ? purb->actual_length : 0), |
3e326ece | 300 | transfer_len); |
6f5794a6 | 301 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 302 | (purb ? purb->actual_length : 0); |
3e326ece | 303 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
304 | printf(" %02x", ((__u8 *) buffer) [i]); |
305 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
306 | } |
307 | } | |
308 | #endif | |
309 | } | |
310 | ||
6f5794a6 RB |
311 | /* just for debugging; prints non-empty branches of the int ed tree |
312 | * inclusive iso eds */ | |
313 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
314 | { | |
3e326ece | 315 | int i, j; |
6f5794a6 RB |
316 | __u32 *ed_p; |
317 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
318 | j = 5; |
319 | ed_p = &(ohci->hcca->int_table [i]); | |
320 | if (*ed_p == 0) | |
321 | continue; | |
8d005ef8 | 322 | invalidate_dcache_ed(ed_p); |
6f5794a6 | 323 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
324 | while (*ed_p != 0 && j--) { |
325 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
8d005ef8 | 326 | invalidate_dcache_ed(ed); |
6f5794a6 | 327 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
328 | ed_p = &ed->hwNextED; |
329 | } | |
6f5794a6 | 330 | printf("\n"); |
3e326ece MK |
331 | } |
332 | } | |
333 | ||
6f5794a6 | 334 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 335 | { |
6f5794a6 | 336 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
337 | label, |
338 | mask, | |
339 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
340 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
341 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
342 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
343 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
344 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
345 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
346 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
347 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
348 | ); | |
349 | } | |
350 | ||
6f5794a6 | 351 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
352 | { |
353 | ed_t *edp = (ed_t *)value; | |
354 | ||
355 | if (value) { | |
6f5794a6 | 356 | dbg("%s %08x", label, value); |
8d005ef8 | 357 | invalidate_dcache_ed(edp); |
6f5794a6 RB |
358 | dbg("%08x", edp->hwINFO); |
359 | dbg("%08x", edp->hwTailP); | |
360 | dbg("%08x", edp->hwHeadP); | |
361 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
362 | } |
363 | } | |
364 | ||
6f5794a6 | 365 | static char *hcfs2string(int state) |
3e326ece MK |
366 | { |
367 | switch (state) { | |
6f5794a6 RB |
368 | case OHCI_USB_RESET: return "reset"; |
369 | case OHCI_USB_RESUME: return "resume"; | |
370 | case OHCI_USB_OPER: return "operational"; | |
371 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
372 | } |
373 | return "?"; | |
374 | } | |
375 | ||
376 | /* dump control and status registers */ | |
6f5794a6 | 377 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
378 | { |
379 | struct ohci_regs *regs = controller->regs; | |
380 | __u32 temp; | |
381 | ||
a5496a18 | 382 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 383 | if (temp != 0x10) |
6f5794a6 | 384 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 385 | |
a5496a18 | 386 | temp = ohci_readl(®s->control); |
6f5794a6 | 387 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
388 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
389 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
390 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 391 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
392 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
393 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
394 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
395 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
396 | temp & OHCI_CTRL_CBSR | |
397 | ); | |
398 | ||
a5496a18 | 399 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 400 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
401 | (temp & OHCI_SOC) >> 16, |
402 | (temp & OHCI_OCR) ? " OCR" : "", | |
403 | (temp & OHCI_BLF) ? " BLF" : "", | |
404 | (temp & OHCI_CLF) ? " CLF" : "", | |
405 | (temp & OHCI_HCR) ? " HCR" : "" | |
406 | ); | |
407 | ||
a5496a18 BB |
408 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
409 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 410 | |
a5496a18 BB |
411 | maybe_print_eds("ed_periodcurrent", |
412 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 413 | |
a5496a18 BB |
414 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
415 | maybe_print_eds("ed_controlcurrent", | |
416 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 417 | |
a5496a18 BB |
418 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
419 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 420 | |
a5496a18 | 421 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
422 | } |
423 | ||
6f5794a6 | 424 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
425 | { |
426 | __u32 temp, ndp, i; | |
427 | ||
6f5794a6 | 428 | temp = roothub_a(controller); |
3e326ece MK |
429 | ndp = (temp & RH_A_NDP); |
430 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
431 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
432 | #endif |
433 | if (verbose) { | |
6f5794a6 | 434 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
435 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
436 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
437 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
438 | (temp & RH_A_DT) ? " DT" : "", | |
439 | (temp & RH_A_NPS) ? " NPS" : "", | |
440 | (temp & RH_A_PSM) ? " PSM" : "", | |
441 | ndp | |
442 | ); | |
6f5794a6 RB |
443 | temp = roothub_b(controller); |
444 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
445 | temp, |
446 | (temp & RH_B_PPCM) >> 16, | |
447 | (temp & RH_B_DR) | |
448 | ); | |
6f5794a6 RB |
449 | temp = roothub_status(controller); |
450 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
451 | temp, |
452 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
453 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
454 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
455 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
456 | (temp & RH_HS_OCI) ? " OCI" : "", | |
457 | (temp & RH_HS_LPS) ? " LPS" : "" | |
458 | ); | |
459 | } | |
460 | ||
461 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
462 | temp = roothub_portstatus(controller, i); |
463 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
464 | i, |
465 | temp, | |
466 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
467 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
468 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
469 | (temp & RH_PS_PESC) ? " PESC" : "", | |
470 | (temp & RH_PS_CSC) ? " CSC" : "", | |
471 | ||
472 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
473 | (temp & RH_PS_PPS) ? " PPS" : "", | |
474 | (temp & RH_PS_PRS) ? " PRS" : "", | |
475 | (temp & RH_PS_POCI) ? " POCI" : "", | |
476 | (temp & RH_PS_PSS) ? " PSS" : "", | |
477 | ||
478 | (temp & RH_PS_PES) ? " PES" : "", | |
479 | (temp & RH_PS_CCS) ? " CCS" : "" | |
480 | ); | |
481 | } | |
482 | } | |
483 | ||
6f5794a6 | 484 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 485 | { |
6f5794a6 | 486 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
487 | |
488 | /* dumps some of the state we know about */ | |
6f5794a6 | 489 | ohci_dump_status(controller); |
3e326ece | 490 | if (verbose) |
6f5794a6 | 491 | ep_print_int_eds(controller, "hcca"); |
8d005ef8 | 492 | invalidate_dcache_hcca(controller->hcca); |
6f5794a6 RB |
493 | dbg("hcca frame #%04x", controller->hcca->frame_no); |
494 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 495 | } |
3e326ece MK |
496 | #endif /* DEBUG */ |
497 | ||
498 | /*-------------------------------------------------------------------------* | |
499 | * Interface functions (URB) | |
500 | *-------------------------------------------------------------------------*/ | |
501 | ||
502 | /* get a transfer request */ | |
503 | ||
19d95d57 HG |
504 | int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, |
505 | struct devrequest *setup) | |
3e326ece | 506 | { |
6f5794a6 | 507 | ed_t *ed; |
4dae14ce | 508 | urb_priv_t *purb_priv = urb; |
3e326ece | 509 | int i, size = 0; |
4dae14ce ZW |
510 | struct usb_device *dev = urb->dev; |
511 | unsigned long pipe = urb->pipe; | |
512 | void *buffer = urb->transfer_buffer; | |
513 | int transfer_len = urb->transfer_buffer_length; | |
514 | int interval = urb->interval; | |
3e326ece | 515 | |
3e326ece MK |
516 | /* when controller's hung, permit only roothub cleanup attempts |
517 | * such as powering down ports */ | |
518 | if (ohci->disabled) { | |
519 | err("sohci_submit_job: EPIPE"); | |
520 | return -1; | |
521 | } | |
ae79f606 | 522 | |
6f5794a6 RB |
523 | /* we're about to begin a new transaction here so mark the |
524 | * URB unfinished */ | |
4dae14ce | 525 | urb->finished = 0; |
3e326ece MK |
526 | |
527 | /* every endpoint has a ed, locate and fill it */ | |
19d95d57 | 528 | ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); |
6f5794a6 | 529 | if (!ed) { |
3e326ece MK |
530 | err("sohci_submit_job: ENOMEM"); |
531 | return -1; | |
532 | } | |
533 | ||
534 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
535 | switch (usb_pipetype(pipe)) { |
536 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
537 | size = (transfer_len - 1) / 4096 + 1; | |
538 | break; | |
539 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
540 | size = (transfer_len == 0)? 2: | |
541 | (transfer_len - 1) / 4096 + 3; | |
542 | break; | |
543 | case PIPE_INTERRUPT: /* 1 TD */ | |
544 | size = 1; | |
545 | break; | |
3e326ece MK |
546 | } |
547 | ||
4dae14ce ZW |
548 | ed->purb = urb; |
549 | ||
3e326ece MK |
550 | if (size >= (N_URB_TD - 1)) { |
551 | err("need %d TDs, only have %d", size, N_URB_TD); | |
552 | return -1; | |
553 | } | |
3e326ece MK |
554 | purb_priv->pipe = pipe; |
555 | ||
556 | /* fill the private part of the URB */ | |
557 | purb_priv->length = size; | |
558 | purb_priv->ed = ed; | |
559 | purb_priv->actual_length = 0; | |
560 | ||
561 | /* allocate the TDs */ | |
562 | /* note that td[0] was allocated in ep_add_ed */ | |
563 | for (i = 0; i < size; i++) { | |
3c5497d8 | 564 | purb_priv->td[i] = td_alloc(ohci_dev, dev); |
3e326ece MK |
565 | if (!purb_priv->td[i]) { |
566 | purb_priv->length = i; | |
6f5794a6 | 567 | urb_free_priv(purb_priv); |
3e326ece MK |
568 | err("sohci_submit_job: ENOMEM"); |
569 | return -1; | |
570 | } | |
571 | } | |
572 | ||
573 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 574 | urb_free_priv(purb_priv); |
3e326ece MK |
575 | err("sohci_submit_job: EINVAL"); |
576 | return -1; | |
577 | } | |
578 | ||
579 | /* link the ed into a chain if is not already */ | |
580 | if (ed->state != ED_OPER) | |
6f5794a6 | 581 | ep_link(ohci, ed); |
3e326ece MK |
582 | |
583 | /* fill the TDs and link it to the ed */ | |
c5613df5 | 584 | td_submit_job(ohci, dev, pipe, buffer, transfer_len, |
6f5794a6 | 585 | setup, purb_priv, interval); |
3e326ece MK |
586 | |
587 | return 0; | |
588 | } | |
589 | ||
4dae14ce ZW |
590 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
591 | { | |
592 | struct ohci_regs *regs = hc->regs; | |
593 | ||
6f5794a6 | 594 | switch (usb_pipetype(urb->pipe)) { |
4dae14ce ZW |
595 | case PIPE_INTERRUPT: |
596 | /* implicitly requeued */ | |
597 | if (urb->dev->irq_handle && | |
598 | (urb->dev->irq_act_len = urb->actual_length)) { | |
a5496a18 BB |
599 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
600 | ohci_readl(®s->intrenable); /* PCI posting flush */ | |
4dae14ce | 601 | urb->dev->irq_handle(urb->dev); |
a5496a18 BB |
602 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
603 | ohci_readl(®s->intrdisable); /* PCI posting flush */ | |
4dae14ce ZW |
604 | } |
605 | urb->actual_length = 0; | |
c5613df5 | 606 | td_submit_job( hc, |
4dae14ce ZW |
607 | urb->dev, |
608 | urb->pipe, | |
609 | urb->transfer_buffer, | |
610 | urb->transfer_buffer_length, | |
611 | NULL, | |
612 | urb, | |
613 | urb->interval); | |
614 | break; | |
615 | case PIPE_CONTROL: | |
616 | case PIPE_BULK: | |
617 | break; | |
618 | default: | |
619 | return 0; | |
620 | } | |
621 | return 1; | |
622 | } | |
623 | ||
3e326ece MK |
624 | /*-------------------------------------------------------------------------*/ |
625 | ||
626 | #ifdef DEBUG | |
627 | /* tell us the current USB frame number */ | |
c5613df5 | 628 | static int sohci_get_current_frame_number(ohci_t *ohci) |
3e326ece | 629 | { |
8d005ef8 | 630 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 631 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
632 | } |
633 | #endif | |
634 | ||
4dae14ce ZW |
635 | /*-------------------------------------------------------------------------* |
636 | * ED handling functions | |
637 | *-------------------------------------------------------------------------*/ | |
638 | ||
639 | /* search for the right branch to insert an interrupt ed into the int tree | |
640 | * do some load ballancing; | |
641 | * returns the branch and | |
642 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
643 | ||
6f5794a6 | 644 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
645 | { |
646 | int i, branch = 0; | |
647 | ||
648 | /* search for the least loaded interrupt endpoint | |
649 | * branch of all 32 branches | |
650 | */ | |
651 | for (i = 0; i < 32; i++) | |
652 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
653 | branch = i; | |
654 | ||
655 | branch = branch % interval; | |
656 | for (i = branch; i < 32; i += interval) | |
657 | ohci->ohci_int_load [i] += load; | |
658 | ||
659 | return branch; | |
660 | } | |
661 | ||
662 | /*-------------------------------------------------------------------------*/ | |
663 | ||
664 | /* 2^int( ld (inter)) */ | |
665 | ||
6f5794a6 | 666 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
667 | { |
668 | int i; | |
6f5794a6 | 669 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
670 | return 1 << i; |
671 | } | |
672 | ||
673 | /*-------------------------------------------------------------------------*/ | |
674 | ||
675 | /* the int tree is a binary tree | |
6f5794a6 RB |
676 | * in order to process it sequentially the indexes of the branches have to |
677 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
678 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
679 | { |
680 | int i, wout = 0; | |
681 | ||
682 | for (i = 0; i < num_bits; i++) | |
683 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
684 | return wout; | |
685 | } | |
686 | ||
3e326ece MK |
687 | /*-------------------------------------------------------------------------* |
688 | * ED handling functions | |
689 | *-------------------------------------------------------------------------*/ | |
690 | ||
691 | /* link an ed into one of the HC chains */ | |
692 | ||
6f5794a6 | 693 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
694 | { |
695 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
696 | int int_branch; |
697 | int i; | |
698 | int inter; | |
699 | int interval; | |
700 | int load; | |
6f5794a6 | 701 | __u32 *ed_p; |
3e326ece MK |
702 | |
703 | ed->state = ED_OPER; | |
4dae14ce | 704 | ed->int_interval = 0; |
3e326ece MK |
705 | |
706 | switch (ed->type) { | |
707 | case PIPE_CONTROL: | |
708 | ed->hwNextED = 0; | |
8d005ef8 | 709 | flush_dcache_ed(ed); |
6f5794a6 | 710 | if (ohci->ed_controltail == NULL) |
a5496a18 | 711 | ohci_writel(ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
712 | else |
713 | ohci->ed_controltail->hwNextED = | |
714 | m32_swap((unsigned long)ed); | |
715 | ||
3e326ece MK |
716 | ed->ed_prev = ohci->ed_controltail; |
717 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
718 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
719 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 720 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
721 | } |
722 | ohci->ed_controltail = edi; | |
723 | break; | |
724 | ||
725 | case PIPE_BULK: | |
726 | ed->hwNextED = 0; | |
8d005ef8 | 727 | flush_dcache_ed(ed); |
6f5794a6 | 728 | if (ohci->ed_bulktail == NULL) |
a5496a18 | 729 | ohci_writel(ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
730 | else |
731 | ohci->ed_bulktail->hwNextED = | |
732 | m32_swap((unsigned long)ed); | |
733 | ||
3e326ece MK |
734 | ed->ed_prev = ohci->ed_bulktail; |
735 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
736 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
737 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 738 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
739 | } |
740 | ohci->ed_bulktail = edi; | |
741 | break; | |
4dae14ce ZW |
742 | |
743 | case PIPE_INTERRUPT: | |
744 | load = ed->int_load; | |
6f5794a6 | 745 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 746 | ed->int_interval = interval; |
6f5794a6 | 747 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
748 | ed->int_branch = int_branch; |
749 | ||
6f5794a6 | 750 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 751 | inter = 1; |
6f5794a6 RB |
752 | for (ed_p = &(ohci->hcca->int_table[\ |
753 | ep_rev(5, i) + int_branch]); | |
754 | (*ed_p != 0) && | |
755 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 756 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
757 | inter = ep_rev(6, |
758 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 759 | ed->hwNextED = *ed_p; |
8d005ef8 | 760 | flush_dcache_ed(ed); |
4a8527ef | 761 | *ed_p = m32_swap((unsigned long)ed); |
8d005ef8 | 762 | flush_dcache_hcca(ohci->hcca); |
4dae14ce ZW |
763 | } |
764 | break; | |
3e326ece MK |
765 | } |
766 | return 0; | |
767 | } | |
768 | ||
769 | /*-------------------------------------------------------------------------*/ | |
770 | ||
4dae14ce | 771 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
772 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
773 | unsigned index, unsigned period) | |
4dae14ce | 774 | { |
8d005ef8 HG |
775 | __maybe_unused unsigned long aligned_ed_p; |
776 | ||
4dae14ce ZW |
777 | for (; index < NUM_INTS; index += period) { |
778 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
779 | ||
780 | /* ED might have been unlinked through another path */ | |
781 | while (*ed_p != 0) { | |
6f5794a6 RB |
782 | if (((struct ed *) |
783 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce | 784 | *ed_p = ed->hwNextED; |
8d005ef8 HG |
785 | #ifdef CONFIG_DM_USB |
786 | aligned_ed_p = (unsigned long)ed_p; | |
787 | aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); | |
788 | flush_dcache_range(aligned_ed_p, | |
789 | aligned_ed_p + ARCH_DMA_MINALIGN); | |
790 | #endif | |
4dae14ce ZW |
791 | break; |
792 | } | |
6f5794a6 RB |
793 | ed_p = &(((struct ed *) |
794 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
795 | } |
796 | } | |
797 | } | |
798 | ||
3e326ece MK |
799 | /* unlink an ed from one of the HC chains. |
800 | * just the link to the ed is unlinked. | |
801 | * the link from the ed still points to another operational ed or 0 | |
802 | * so the HC can eventually finish the processing of the unlinked ed */ | |
803 | ||
6f5794a6 | 804 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 805 | { |
53e336e9 | 806 | volatile ed_t *ed = edi; |
4dae14ce | 807 | int i; |
53e336e9 | 808 | |
6f5794a6 | 809 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
8d005ef8 | 810 | flush_dcache_ed(ed); |
3e326ece MK |
811 | |
812 | switch (ed->type) { | |
813 | case PIPE_CONTROL: | |
814 | if (ed->ed_prev == NULL) { | |
815 | if (!ed->hwNextED) { | |
816 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
817 | ohci_writel(ohci->hc_control, |
818 | &ohci->regs->control); | |
3e326ece | 819 | } |
a5496a18 | 820 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 821 | &ohci->regs->ed_controlhead); |
3e326ece MK |
822 | } else { |
823 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 824 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
825 | } |
826 | if (ohci->ed_controltail == ed) { | |
827 | ohci->ed_controltail = ed->ed_prev; | |
828 | } else { | |
6f5794a6 RB |
829 | ((ed_t *)m32_swap( |
830 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
831 | } |
832 | break; | |
833 | ||
834 | case PIPE_BULK: | |
835 | if (ed->ed_prev == NULL) { | |
836 | if (!ed->hwNextED) { | |
837 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
838 | ohci_writel(ohci->hc_control, |
839 | &ohci->regs->control); | |
3e326ece | 840 | } |
a5496a18 | 841 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 842 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
843 | } else { |
844 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 845 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
846 | } |
847 | if (ohci->ed_bulktail == ed) { | |
848 | ohci->ed_bulktail = ed->ed_prev; | |
849 | } else { | |
6f5794a6 RB |
850 | ((ed_t *)m32_swap( |
851 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
852 | } |
853 | break; | |
4dae14ce ZW |
854 | |
855 | case PIPE_INTERRUPT: | |
6f5794a6 | 856 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
857 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
858 | ohci->ohci_int_load[i] -= ed->int_load; | |
859 | break; | |
3e326ece MK |
860 | } |
861 | ed->state = ED_UNLINK; | |
862 | return 0; | |
863 | } | |
864 | ||
3e326ece MK |
865 | /*-------------------------------------------------------------------------*/ |
866 | ||
ddf83a2f MK |
867 | /* add/reinit an endpoint; this should be done once at the |
868 | * usb_set_configuration command, but the USB stack is a little bit | |
869 | * stateless so we do it at every transaction if the state of the ed | |
870 | * is ED_NEW then a dummy td is added and the state is changed to | |
871 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
872 | * info fields are setted anyway even though most of them should not | |
873 | * change | |
874 | */ | |
19d95d57 HG |
875 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, |
876 | unsigned long pipe, int interval, int load) | |
3e326ece MK |
877 | { |
878 | td_t *td; | |
879 | ed_t *ed_ret; | |
880 | volatile ed_t *ed; | |
881 | ||
19d95d57 | 882 | ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | |
6f5794a6 | 883 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; |
3e326ece MK |
884 | |
885 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
886 | err("ep_add_ed: pending delete"); | |
887 | /* pending delete request */ | |
888 | return NULL; | |
889 | } | |
890 | ||
891 | if (ed->state == ED_NEW) { | |
3e326ece | 892 | /* dummy td; end of td list for ed */ |
3c5497d8 | 893 | td = td_alloc(ohci_dev, usb_dev); |
6f5794a6 | 894 | ed->hwTailP = m32_swap((unsigned long)td); |
3e326ece MK |
895 | ed->hwHeadP = ed->hwTailP; |
896 | ed->state = ED_UNLINK; | |
6f5794a6 | 897 | ed->type = usb_pipetype(pipe); |
19d95d57 | 898 | ohci_dev->ed_cnt++; |
3e326ece MK |
899 | } |
900 | ||
6f5794a6 RB |
901 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
902 | | usb_pipeendpoint(pipe) << 7 | |
903 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
904 | | (usb_pipecontrol(pipe)? 0: \ | |
905 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 906 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 907 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 908 | |
4dae14ce ZW |
909 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
910 | ed->int_period = interval; | |
911 | ed->int_load = load; | |
912 | } | |
913 | ||
8d005ef8 HG |
914 | flush_dcache_ed(ed); |
915 | ||
3e326ece MK |
916 | return ed_ret; |
917 | } | |
918 | ||
919 | /*-------------------------------------------------------------------------* | |
920 | * TD handling functions | |
921 | *-------------------------------------------------------------------------*/ | |
922 | ||
923 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
924 | ||
6f5794a6 | 925 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
926 | void *data, int len, |
927 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
928 | { | |
929 | volatile td_t *td, *td_pt; | |
930 | #ifdef OHCI_FILL_TRACE | |
931 | int i; | |
932 | #endif | |
933 | ||
934 | if (index > urb_priv->length) { | |
935 | err("index > length"); | |
936 | return; | |
937 | } | |
938 | /* use this td as the next dummy */ | |
939 | td_pt = urb_priv->td [index]; | |
940 | td_pt->hwNextTD = 0; | |
8d005ef8 | 941 | flush_dcache_td(td_pt); |
3e326ece MK |
942 | |
943 | /* fill the old dummy TD */ | |
6f5794a6 RB |
944 | td = urb_priv->td [index] = |
945 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
946 | |
947 | td->ed = urb_priv->ed; | |
948 | td->next_dl_td = NULL; | |
949 | td->index = index; | |
950 | td->data = (__u32)data; | |
951 | #ifdef OHCI_FILL_TRACE | |
48867208 | 952 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 953 | for (i = 0; i < len; i++) |
6f5794a6 | 954 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
955 | printf("\n"); |
956 | } | |
957 | #endif | |
958 | if (!len) | |
959 | data = 0; | |
960 | ||
6f5794a6 RB |
961 | td->hwINFO = m32_swap(info); |
962 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 963 | if (data) |
6f5794a6 | 964 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
965 | else |
966 | td->hwBE = 0; | |
6f5794a6 RB |
967 | |
968 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
8d005ef8 | 969 | flush_dcache_td(td); |
3e326ece MK |
970 | |
971 | /* append to queue */ | |
972 | td->ed->hwTailP = td->hwNextTD; | |
8d005ef8 | 973 | flush_dcache_ed(td->ed); |
3e326ece MK |
974 | } |
975 | ||
976 | /*-------------------------------------------------------------------------*/ | |
977 | ||
978 | /* prepare all TDs of a transfer */ | |
979 | ||
c5613df5 HG |
980 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, |
981 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
982 | struct devrequest *setup, urb_priv_t *urb, |
983 | int interval) | |
3e326ece | 984 | { |
3e326ece MK |
985 | int data_len = transfer_len; |
986 | void *data; | |
987 | int cnt = 0; | |
988 | __u32 info = 0; | |
989 | unsigned int toggle = 0; | |
990 | ||
8d005ef8 HG |
991 | flush_dcache_buffer(buffer, data_len); |
992 | ||
6f5794a6 RB |
993 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
994 | * bits for reseting */ | |
995 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
996 | toggle = TD_T_TOGGLE; |
997 | } else { | |
998 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
999 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
1000 | usb_pipeout(pipe), 1); | |
3e326ece MK |
1001 | } |
1002 | urb->td_cnt = 0; | |
1003 | if (data_len) | |
1004 | data = buffer; | |
1005 | else | |
1006 | data = 0; | |
1007 | ||
6f5794a6 | 1008 | switch (usb_pipetype(pipe)) { |
3e326ece | 1009 | case PIPE_BULK: |
6f5794a6 | 1010 | info = usb_pipeout(pipe)? |
3e326ece | 1011 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
1012 | while (data_len > 4096) { |
1013 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
1014 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
1015 | data += 4096; data_len -= 4096; cnt++; |
1016 | } | |
6f5794a6 | 1017 | info = usb_pipeout(pipe)? |
3e326ece | 1018 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
1019 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
1020 | data_len, dev, cnt, urb); | |
3e326ece MK |
1021 | cnt++; |
1022 | ||
6f5794a6 RB |
1023 | if (!ohci->sleeping) { |
1024 | /* start bulk list */ | |
a5496a18 | 1025 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 1026 | } |
3e326ece MK |
1027 | break; |
1028 | ||
1029 | case PIPE_CONTROL: | |
6f5794a6 | 1030 | /* Setup phase */ |
3e326ece | 1031 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
8d005ef8 | 1032 | flush_dcache_buffer(setup, 8); |
6f5794a6 RB |
1033 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
1034 | ||
1035 | /* Optional Data phase */ | |
3e326ece | 1036 | if (data_len > 0) { |
6f5794a6 RB |
1037 | info = usb_pipeout(pipe)? |
1038 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
1039 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 1040 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
1041 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
1042 | } | |
1043 | ||
1044 | /* Status phase */ | |
cae01cb2 | 1045 | info = (usb_pipeout(pipe) || data_len == 0) ? |
6f5794a6 RB |
1046 | TD_CC | TD_DP_IN | TD_T_DATA1: |
1047 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
1048 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
1049 | ||
1050 | if (!ohci->sleeping) { | |
1051 | /* start Control list */ | |
a5496a18 | 1052 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 1053 | } |
3e326ece | 1054 | break; |
4dae14ce ZW |
1055 | |
1056 | case PIPE_INTERRUPT: | |
6f5794a6 | 1057 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
1058 | TD_CC | TD_DP_OUT | toggle: |
1059 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 1060 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 1061 | break; |
3e326ece MK |
1062 | } |
1063 | if (urb->length != cnt) | |
1064 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
1065 | } | |
1066 | ||
1067 | /*-------------------------------------------------------------------------* | |
1068 | * Done List handling functions | |
1069 | *-------------------------------------------------------------------------*/ | |
1070 | ||
3e326ece MK |
1071 | /* calculate the transfer length and update the urb */ |
1072 | ||
6f5794a6 | 1073 | static void dl_transfer_length(td_t *td) |
3e326ece | 1074 | { |
6bc52ef3 | 1075 | __u32 tdBE, tdCBP; |
4dae14ce | 1076 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 1077 | |
6f5794a6 RB |
1078 | tdBE = m32_swap(td->hwBE); |
1079 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 1080 | |
48867208 | 1081 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
1082 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
1083 | if (tdBE != 0) { | |
1084 | if (td->hwCBP == 0) | |
1085 | lurb_priv->actual_length += tdBE - td->data + 1; | |
1086 | else | |
1087 | lurb_priv->actual_length += tdCBP - td->data; | |
1088 | } | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
1093 | static void check_status(td_t *td_list) |
1094 | { | |
1095 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
1096 | int urb_len = lurb_priv->length; | |
1097 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
1098 | int cc; | |
1099 | ||
1100 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
1101 | if (cc) { | |
1102 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
1103 | ||
8d005ef8 | 1104 | invalidate_dcache_ed(td_list->ed); |
6f5794a6 RB |
1105 | if (*phwHeadP & m32_swap(0x1)) { |
1106 | if (lurb_priv && | |
1107 | ((td_list->index + 1) < urb_len)) { | |
1108 | *phwHeadP = | |
1109 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
1110 | m32_swap(0xfffffff0)) | | |
1111 | (*phwHeadP & m32_swap(0x2)); | |
1112 | ||
1113 | lurb_priv->td_cnt += urb_len - | |
1114 | td_list->index - 1; | |
1115 | } else | |
1116 | *phwHeadP &= m32_swap(0xfffffff2); | |
8d005ef8 | 1117 | flush_dcache_ed(td_list->ed); |
6f5794a6 RB |
1118 | } |
1119 | #ifdef CONFIG_MPC5200 | |
1120 | td_list->hwNextTD = 0; | |
8d005ef8 | 1121 | flush_dcache_td(td_list); |
6f5794a6 RB |
1122 | #endif |
1123 | } | |
1124 | } | |
3e326ece MK |
1125 | |
1126 | /* replies to the request have to be on a FIFO basis so | |
1127 | * we reverse the reversed done-list */ | |
6f5794a6 | 1128 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
1129 | { |
1130 | __u32 td_list_hc; | |
1131 | td_t *td_rev = NULL; | |
1132 | td_t *td_list = NULL; | |
3e326ece | 1133 | |
8d005ef8 | 1134 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 1135 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece | 1136 | ohci->hcca->done_head = 0; |
8d005ef8 | 1137 | flush_dcache_hcca(ohci->hcca); |
3e326ece MK |
1138 | |
1139 | while (td_list_hc) { | |
1140 | td_list = (td_t *)td_list_hc; | |
8d005ef8 | 1141 | invalidate_dcache_td(td_list); |
6f5794a6 | 1142 | check_status(td_list); |
3e326ece MK |
1143 | td_list->next_dl_td = td_rev; |
1144 | td_rev = td_list; | |
6f5794a6 | 1145 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1146 | } |
1147 | return td_list; | |
1148 | } | |
1149 | ||
6f5794a6 | 1150 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1151 | /*-------------------------------------------------------------------------*/ |
1152 | ||
6f5794a6 RB |
1153 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1154 | { | |
1155 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
1156 | urb->finished = sohci_return_job(ohci, urb); | |
1157 | else | |
1158 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1159 | } | |
1160 | ||
1161 | /* | |
1162 | * Used to take back a TD from the host controller. This would normally be | |
1163 | * called from within dl_done_list, however it may be called directly if the | |
1164 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1165 | * two frames). This bug has been observed on ZF Micro systems. | |
1166 | */ | |
1167 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1168 | { |
3e326ece | 1169 | ed_t *ed; |
6f5794a6 | 1170 | int cc; |
3e326ece MK |
1171 | int stat = 0; |
1172 | /* urb_t *urb; */ | |
1173 | urb_priv_t *lurb_priv; | |
1174 | __u32 tdINFO, edHeadP, edTailP; | |
1175 | ||
8d005ef8 | 1176 | invalidate_dcache_td(td_list); |
6f5794a6 | 1177 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1178 | |
6f5794a6 RB |
1179 | ed = td_list->ed; |
1180 | lurb_priv = ed->purb; | |
3e326ece | 1181 | |
6f5794a6 | 1182 | dl_transfer_length(td_list); |
3e326ece | 1183 | |
6f5794a6 | 1184 | lurb_priv->td_cnt++; |
3e326ece | 1185 | |
6f5794a6 RB |
1186 | /* error code of transfer */ |
1187 | cc = TD_CC_GET(tdINFO); | |
1188 | if (cc) { | |
1189 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1190 | stat = cc_to_error[cc]; | |
1191 | } | |
ae79f606 | 1192 | |
6f5794a6 RB |
1193 | /* see if this done list makes for all TD's of current URB, |
1194 | * and mark the URB finished if so */ | |
1195 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1196 | finish_urb(ohci, lurb_priv, ed->state); | |
1197 | ||
1198 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1199 | lurb_priv->td_cnt, lurb_priv->length); | |
1200 | ||
48867208 | 1201 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
8d005ef8 | 1202 | invalidate_dcache_ed(ed); |
6f5794a6 RB |
1203 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1204 | edTailP = m32_swap(ed->hwTailP); | |
1205 | ||
1206 | /* unlink eds if they are not busy */ | |
1207 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1208 | ep_unlink(ohci, ed); | |
1209 | } | |
1210 | return stat; | |
1211 | } | |
3e326ece | 1212 | |
6f5794a6 RB |
1213 | static int dl_done_list(ohci_t *ohci) |
1214 | { | |
1215 | int stat = 0; | |
1216 | td_t *td_list = dl_reverse_done_list(ohci); | |
1217 | ||
1218 | while (td_list) { | |
1219 | td_t *td_next = td_list->next_dl_td; | |
1220 | stat = takeback_td(ohci, td_list); | |
1221 | td_list = td_next; | |
3e326ece MK |
1222 | } |
1223 | return stat; | |
1224 | } | |
1225 | ||
1226 | /*-------------------------------------------------------------------------* | |
1227 | * Virtual Root Hub | |
1228 | *-------------------------------------------------------------------------*/ | |
1229 | ||
eb838e7d | 1230 | #include <usbroothubdes.h> |
3e326ece MK |
1231 | |
1232 | /* Hub class-specific descriptor is constructed dynamically */ | |
1233 | ||
3e326ece MK |
1234 | /*-------------------------------------------------------------------------*/ |
1235 | ||
1236 | #define OK(x) len = (x); break | |
1237 | #ifdef DEBUG | |
a5496a18 | 1238 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
c5613df5 | 1239 | &ohci->regs->roothub.status); } |
6f5794a6 | 1240 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ |
c5613df5 | 1241 | (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1242 | #else |
c5613df5 | 1243 | #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) |
a5496a18 | 1244 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ |
c5613df5 | 1245 | &ohci->regs->roothub.portstatus[wIndex-1]) |
3e326ece | 1246 | #endif |
c5613df5 HG |
1247 | #define RD_RH_STAT roothub_status(ohci) |
1248 | #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) | |
3e326ece MK |
1249 | |
1250 | /* request to virtual root hub */ | |
1251 | ||
1252 | int rh_check_port_status(ohci_t *controller) | |
1253 | { | |
1254 | __u32 temp, ndp, i; | |
1255 | int res; | |
1256 | ||
1257 | res = -1; | |
6f5794a6 | 1258 | temp = roothub_a(controller); |
3e326ece MK |
1259 | ndp = (temp & RH_A_NDP); |
1260 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1261 | ndp = (ndp == 2) ? 1:0; | |
1262 | #endif | |
1263 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1264 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1265 | /* check for a device disconnect */ |
1266 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1267 | (RH_PS_PESC | RH_PS_CSC)) && | |
1268 | ((temp & RH_PS_CCS) == 0)) { | |
1269 | res = i; | |
1270 | break; | |
1271 | } | |
1272 | } | |
1273 | return res; | |
1274 | } | |
1275 | ||
c5613df5 HG |
1276 | static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, |
1277 | unsigned long pipe, void *buffer, int transfer_len, | |
1278 | struct devrequest *cmd) | |
3e326ece | 1279 | { |
6f5794a6 | 1280 | void *data = buffer; |
3e326ece MK |
1281 | int leni = transfer_len; |
1282 | int len = 0; | |
1283 | int stat = 0; | |
3e326ece MK |
1284 | __u16 bmRType_bReq; |
1285 | __u16 wValue; | |
1286 | __u16 wIndex; | |
1287 | __u16 wLength; | |
f1273f11 | 1288 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1289 | |
3e326ece | 1290 | #ifdef DEBUG |
c5613df5 | 1291 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1292 | cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece | 1293 | #else |
5b84dd67 | 1294 | mdelay(1); |
3e326ece | 1295 | #endif |
48867208 | 1296 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1297 | info("Root-Hub submit IRQ: NOT implemented"); |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1302 | wValue = le16_to_cpu(cmd->value); |
1303 | wIndex = le16_to_cpu(cmd->index); | |
1304 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1305 | |
1306 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1307 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1308 | ||
1309 | switch (bmRType_bReq) { | |
1310 | /* Request Destination: | |
1311 | without flags: Device, | |
1312 | RH_INTERFACE: interface, | |
1313 | RH_ENDPOINT: endpoint, | |
1314 | RH_CLASS means HUB here, | |
1315 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1316 | */ | |
1317 | ||
1318 | case RH_GET_STATUS: | |
f1273f11 | 1319 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1320 | OK(2); |
3e326ece | 1321 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1322 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1323 | OK(2); |
3e326ece | 1324 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1325 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1326 | OK(2); |
3e326ece | 1327 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1328 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1329 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1330 | OK(4); |
3e326ece | 1331 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1332 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1333 | OK(4); |
3e326ece MK |
1334 | |
1335 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1336 | switch (wValue) { | |
6f5794a6 RB |
1337 | case (RH_ENDPOINT_STALL): |
1338 | OK(0); | |
3e326ece MK |
1339 | } |
1340 | break; | |
1341 | ||
1342 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1343 | switch (wValue) { | |
6f5794a6 RB |
1344 | case RH_C_HUB_LOCAL_POWER: |
1345 | OK(0); | |
1346 | case (RH_C_HUB_OVER_CURRENT): | |
1347 | WR_RH_STAT(RH_HS_OCIC); | |
1348 | OK(0); | |
3e326ece MK |
1349 | } |
1350 | break; | |
1351 | ||
1352 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1353 | switch (wValue) { | |
6f5794a6 RB |
1354 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1355 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1356 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1357 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1358 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1359 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1360 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1361 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1362 | } |
1363 | break; | |
1364 | ||
1365 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1366 | switch (wValue) { | |
6f5794a6 RB |
1367 | case (RH_PORT_SUSPEND): |
1368 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1369 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1370 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1371 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1372 | OK(0); | |
1373 | case (RH_PORT_POWER): | |
1374 | WR_RH_PORTSTAT(RH_PS_PPS); | |
5b84dd67 | 1375 | mdelay(100); |
6f5794a6 RB |
1376 | OK(0); |
1377 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1378 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1379 | WR_RH_PORTSTAT(RH_PS_PES); | |
1380 | OK(0); | |
3e326ece MK |
1381 | } |
1382 | break; | |
1383 | ||
6f5794a6 | 1384 | case RH_SET_ADDRESS: |
c5613df5 | 1385 | ohci->rh.devnum = wValue; |
6f5794a6 | 1386 | OK(0); |
3e326ece MK |
1387 | |
1388 | case RH_GET_DESCRIPTOR: | |
1389 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1390 | case (0x01): /* device descriptor */ |
1391 | len = min_t(unsigned int, | |
1392 | leni, | |
1393 | min_t(unsigned int, | |
1394 | sizeof(root_hub_dev_des), | |
1395 | wLength)); | |
f1273f11 | 1396 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1397 | case (0x02): /* configuration descriptor */ |
1398 | len = min_t(unsigned int, | |
1399 | leni, | |
1400 | min_t(unsigned int, | |
1401 | sizeof(root_hub_config_des), | |
1402 | wLength)); | |
f1273f11 | 1403 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1404 | case (0x03): /* string descriptors */ |
1405 | if (wValue == 0x0300) { | |
3e326ece | 1406 | len = min_t(unsigned int, |
6f5794a6 RB |
1407 | leni, |
1408 | min_t(unsigned int, | |
1409 | sizeof(root_hub_str_index0), | |
1410 | wLength)); | |
f1273f11 | 1411 | databuf = root_hub_str_index0; |
6f5794a6 | 1412 | OK(len); |
3e326ece | 1413 | } |
6f5794a6 RB |
1414 | if (wValue == 0x0301) { |
1415 | len = min_t(unsigned int, | |
1416 | leni, | |
1417 | min_t(unsigned int, | |
1418 | sizeof(root_hub_str_index1), | |
1419 | wLength)); | |
f1273f11 | 1420 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1421 | OK(len); |
1422 | } | |
1423 | default: | |
1424 | stat = USB_ST_STALLED; | |
3e326ece MK |
1425 | } |
1426 | break; | |
1427 | ||
1428 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1429 | { | |
c5613df5 | 1430 | __u32 temp = roothub_a(ohci); |
3e326ece | 1431 | |
f1273f11 TK |
1432 | databuf[0] = 9; /* min length; */ |
1433 | databuf[1] = 0x29; | |
1434 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1435 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1436 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1437 | #endif |
f1273f11 | 1438 | databuf[3] = 0; |
3e326ece | 1439 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1440 | databuf[3] |= 0x1; |
3e326ece | 1441 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1442 | databuf[3] |= 0x10; |
6f5794a6 | 1443 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1444 | databuf[3] |= 0x8; |
3e326ece | 1445 | |
f1273f11 TK |
1446 | databuf[4] = 0; |
1447 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1448 | databuf[6] = 0; | |
c5613df5 | 1449 | temp = roothub_b(ohci); |
f1273f11 TK |
1450 | databuf[7] = temp & RH_B_DR; |
1451 | if (databuf[2] < 7) { | |
1452 | databuf[8] = 0xff; | |
3e326ece | 1453 | } else { |
f1273f11 TK |
1454 | databuf[0] += 2; |
1455 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1456 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1457 | } |
1458 | ||
1459 | len = min_t(unsigned int, leni, | |
f1273f11 | 1460 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1461 | OK(len); |
3e326ece MK |
1462 | } |
1463 | ||
5f6aa03f | 1464 | case RH_GET_CONFIGURATION: |
f1273f11 | 1465 | databuf[0] = 0x01; |
5f6aa03f | 1466 | OK(1); |
3e326ece | 1467 | |
5f6aa03f MV |
1468 | case RH_SET_CONFIGURATION: |
1469 | WR_RH_STAT(0x10000); | |
1470 | OK(0); | |
3e326ece MK |
1471 | |
1472 | default: | |
6f5794a6 | 1473 | dbg("unsupported root hub command"); |
3e326ece MK |
1474 | stat = USB_ST_STALLED; |
1475 | } | |
1476 | ||
1477 | #ifdef DEBUG | |
c5613df5 | 1478 | ohci_dump_roothub(ohci, 1); |
3e326ece | 1479 | #else |
5b84dd67 | 1480 | mdelay(1); |
3e326ece MK |
1481 | #endif |
1482 | ||
1483 | len = min_t(int, len, leni); | |
f1273f11 TK |
1484 | if (data != databuf) |
1485 | memcpy(data, databuf, len); | |
3e326ece MK |
1486 | dev->act_len = len; |
1487 | dev->status = stat; | |
1488 | ||
1489 | #ifdef DEBUG | |
c5613df5 | 1490 | pkt_print(ohci, NULL, dev, pipe, buffer, |
6f5794a6 | 1491 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece | 1492 | #else |
5b84dd67 | 1493 | mdelay(1); |
3e326ece MK |
1494 | #endif |
1495 | ||
1496 | return stat; | |
1497 | } | |
1498 | ||
1499 | /*-------------------------------------------------------------------------*/ | |
1500 | ||
1501 | /* common code for handling submit messages - used for all but root hub */ | |
1502 | /* accesses. */ | |
c5613df5 HG |
1503 | static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, |
1504 | unsigned long pipe, void *buffer, int transfer_len, | |
1505 | struct devrequest *setup, int interval) | |
3e326ece MK |
1506 | { |
1507 | int stat = 0; | |
1508 | int maxsize = usb_maxpacket(dev, pipe); | |
1509 | int timeout; | |
4dae14ce ZW |
1510 | urb_priv_t *urb; |
1511 | ||
1512 | urb = malloc(sizeof(urb_priv_t)); | |
1513 | memset(urb, 0, sizeof(urb_priv_t)); | |
1514 | ||
1515 | urb->dev = dev; | |
1516 | urb->pipe = pipe; | |
1517 | urb->transfer_buffer = buffer; | |
1518 | urb->transfer_buffer_length = transfer_len; | |
1519 | urb->interval = interval; | |
3e326ece | 1520 | |
3e326ece | 1521 | #ifdef DEBUG |
4dae14ce | 1522 | urb->actual_length = 0; |
c5613df5 | 1523 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1524 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1525 | #else |
5b84dd67 | 1526 | mdelay(1); |
3e326ece MK |
1527 | #endif |
1528 | if (!maxsize) { | |
1529 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1530 | pipe); | |
1531 | return -1; | |
1532 | } | |
1533 | ||
19d95d57 | 1534 | if (sohci_submit_job(ohci, &ohci->ohci_dev, urb, setup) < 0) { |
3e326ece MK |
1535 | err("sohci_submit_job failed"); |
1536 | return -1; | |
1537 | } | |
1538 | ||
ae3b770e | 1539 | #if 0 |
5b84dd67 | 1540 | mdelay(10); |
c5613df5 | 1541 | /* ohci_dump_status(ohci); */ |
ae3b770e | 1542 | #endif |
3e326ece | 1543 | |
96820a35 | 1544 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1545 | |
1546 | /* wait for it to complete */ | |
1547 | for (;;) { | |
1548 | /* check whether the controller is done */ | |
c5613df5 | 1549 | stat = hc_interrupt(ohci); |
3e326ece MK |
1550 | if (stat < 0) { |
1551 | stat = USB_ST_CRC_ERR; | |
1552 | break; | |
1553 | } | |
ddf83a2f | 1554 | |
ddf83a2f MK |
1555 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1556 | * handle only one URB at a time, we cannot assume the | |
1557 | * transaction finished on the first successful return from | |
1558 | * hc_interrupt().. unless the flag for current URB is set, | |
1559 | * meaning that all TD's to/from device got actually | |
1560 | * transferred and processed. If the current URB is not | |
1561 | * finished we need to re-iterate this loop so as | |
1562 | * hc_interrupt() gets called again as there needs to be some | |
1563 | * more TD's to process still */ | |
4dae14ce | 1564 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1565 | /* 0xff is returned for an SF-interrupt */ |
1566 | break; | |
1567 | } | |
ddf83a2f | 1568 | |
3e326ece | 1569 | if (--timeout) { |
5b84dd67 | 1570 | mdelay(1); |
4dae14ce | 1571 | if (!urb->finished) |
6f5794a6 | 1572 | dbg("*"); |
4dae14ce | 1573 | |
3e326ece | 1574 | } else { |
fa5b9baa HG |
1575 | if (!usb_pipeint(pipe)) |
1576 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1577 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1578 | urb->finished = 1; |
3e326ece MK |
1579 | stat = USB_ST_CRC_ERR; |
1580 | break; | |
1581 | } | |
1582 | } | |
3e326ece MK |
1583 | |
1584 | dev->status = stat; | |
522c9564 | 1585 | dev->act_len = urb->actual_length; |
3e326ece | 1586 | |
8d005ef8 HG |
1587 | if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) |
1588 | invalidate_dcache_buffer(buffer, dev->act_len); | |
1589 | ||
3e326ece | 1590 | #ifdef DEBUG |
c5613df5 | 1591 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1592 | setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece | 1593 | #else |
5b84dd67 | 1594 | mdelay(1); |
3e326ece MK |
1595 | #endif |
1596 | ||
1597 | /* free TDs in urb_priv */ | |
48867208 | 1598 | if (!usb_pipeint(pipe)) |
6f5794a6 | 1599 | urb_free_priv(urb); |
3e326ece MK |
1600 | return 0; |
1601 | } | |
1602 | ||
1603 | /* submit routines called from usb.c */ | |
1604 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1605 | int transfer_len) | |
1606 | { | |
1607 | info("submit_bulk_msg"); | |
c5613df5 HG |
1608 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, |
1609 | NULL, 0); | |
1610 | } | |
1611 | ||
1612 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1613 | int transfer_len, int interval) | |
1614 | { | |
1615 | info("submit_int_msg"); | |
1616 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, | |
1617 | interval); | |
3e326ece MK |
1618 | } |
1619 | ||
c5613df5 HG |
1620 | static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, |
1621 | unsigned long pipe, void *buffer, int transfer_len, | |
1622 | struct devrequest *setup) | |
3e326ece MK |
1623 | { |
1624 | int maxsize = usb_maxpacket(dev, pipe); | |
1625 | ||
1626 | info("submit_control_msg"); | |
1627 | #ifdef DEBUG | |
c5613df5 | 1628 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1629 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1630 | #else |
5b84dd67 | 1631 | mdelay(1); |
3e326ece MK |
1632 | #endif |
1633 | if (!maxsize) { | |
1634 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1635 | pipe); | |
1636 | return -1; | |
1637 | } | |
c5613df5 HG |
1638 | if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { |
1639 | ohci->rh.dev = dev; | |
3e326ece | 1640 | /* root hub - redirect */ |
c5613df5 HG |
1641 | return ohci_submit_rh_msg(ohci, dev, pipe, buffer, |
1642 | transfer_len, setup); | |
3e326ece MK |
1643 | } |
1644 | ||
c5613df5 HG |
1645 | return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, |
1646 | setup, 0); | |
3e326ece MK |
1647 | } |
1648 | ||
1649 | /*-------------------------------------------------------------------------* | |
1650 | * HC functions | |
1651 | *-------------------------------------------------------------------------*/ | |
1652 | ||
1653 | /* reset the HC and BUS */ | |
1654 | ||
6f5794a6 | 1655 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1656 | { |
e90fb6af YT |
1657 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1658 | pci_dev_t pdev; | |
1659 | #endif | |
3e326ece MK |
1660 | int timeout = 30; |
1661 | int smm_timeout = 50; /* 0,5 sec */ | |
1662 | ||
1663 | dbg("%s\n", __FUNCTION__); | |
1664 | ||
e90fb6af YT |
1665 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1666 | /* | |
1667 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1668 | * resetting via EHCI registers only. | |
1669 | */ | |
1670 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1671 | if (pdev != -1) { | |
1672 | u32 base; | |
1673 | int timeout = 1000; | |
1674 | ||
1675 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1676 | base += EHCI_USBCMD_OFF; |
1677 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1678 | |
a5496a18 | 1679 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1680 | if (timeout-- <= 0) { |
1681 | printf("USB RootHub reset timed out!"); | |
1682 | break; | |
1683 | } | |
1684 | udelay(1); | |
1685 | } | |
1686 | } else | |
1687 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1688 | #endif | |
a5496a18 BB |
1689 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1690 | /* SMM owns the HC, request ownership */ | |
1691 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1692 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1693 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1694 | mdelay(10); |
3e326ece MK |
1695 | if (--smm_timeout == 0) { |
1696 | err("USB HC TakeOver failed!"); | |
1697 | return -1; | |
1698 | } | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | /* Disable HC interrupts */ | |
a5496a18 | 1703 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1704 | |
1705 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1706 | ohci->slot_name, | |
a5496a18 | 1707 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1708 | |
1709 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1710 | ohci->hc_control = 0; |
a5496a18 | 1711 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1712 | |
1713 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1714 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1715 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1716 | if (--timeout == 0) { |
1717 | err("USB HC reset timed out!"); | |
1718 | return -1; | |
1719 | } | |
6f5794a6 | 1720 | udelay(1); |
3e326ece MK |
1721 | } |
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | /*-------------------------------------------------------------------------*/ | |
1726 | ||
1727 | /* Start an OHCI controller, set the BUS operational | |
1728 | * enable interrupts | |
1729 | * connect the virtual root hub */ | |
1730 | ||
6f5794a6 | 1731 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1732 | { |
1733 | __u32 mask; | |
1734 | unsigned int fminterval; | |
1735 | ||
1736 | ohci->disabled = 1; | |
1737 | ||
1738 | /* Tell the controller where the control and bulk lists are | |
1739 | * The lists are empty now. */ | |
1740 | ||
a5496a18 BB |
1741 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1742 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1743 | |
a5496a18 BB |
1744 | ohci_writel((__u32)ohci->hcca, |
1745 | &ohci->regs->hcca); /* reset clears this */ | |
3e326ece MK |
1746 | |
1747 | fminterval = 0x2edf; | |
a5496a18 | 1748 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1749 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1750 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1751 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1752 | |
1753 | /* start controller operations */ | |
1754 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1755 | ohci->disabled = 0; | |
a5496a18 | 1756 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1757 | |
1758 | /* disable all interrupts */ | |
1759 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1760 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1761 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1762 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1763 | /* clear all interrupts */ |
1764 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1765 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1766 | /* Choose the interrupts we care about now - but w/o MIE */ |
1767 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1768 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1769 | |
1770 | #ifdef OHCI_USE_NPS | |
1771 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1772 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1773 | &ohci->regs->roothub.a); |
a5496a18 | 1774 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1775 | #endif /* OHCI_USE_NPS */ |
1776 | ||
3e326ece | 1777 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
6f5794a6 | 1778 | mdelay((roothub_a(ohci) >> 23) & 0x1fe); |
3e326ece MK |
1779 | |
1780 | /* connect the virtual root hub */ | |
1781 | ohci->rh.devnum = 0; | |
1782 | ||
1783 | return 0; | |
1784 | } | |
1785 | ||
1786 | /*-------------------------------------------------------------------------*/ | |
1787 | ||
1788 | /* an interrupt happens */ | |
1789 | ||
c5613df5 | 1790 | static int hc_interrupt(ohci_t *ohci) |
3e326ece | 1791 | { |
3e326ece MK |
1792 | struct ohci_regs *regs = ohci->regs; |
1793 | int ints; | |
1794 | int stat = -1; | |
1795 | ||
8d005ef8 HG |
1796 | invalidate_dcache_hcca(ohci->hcca); |
1797 | ||
ddf83a2f | 1798 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1799 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1800 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1801 | } else { |
a5496a18 | 1802 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1803 | if (ints == ~(u32)0) { |
1804 | ohci->disabled++; | |
1805 | err("%s device removed!", ohci->slot_name); | |
1806 | return -1; | |
1807 | } else { | |
a5496a18 | 1808 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1809 | if (ints == 0) { |
1810 | dbg("hc_interrupt: returning..\n"); | |
1811 | return 0xff; | |
1812 | } | |
1813 | } | |
ddf83a2f | 1814 | } |
ae79f606 | 1815 | |
6f5794a6 RB |
1816 | /* dbg("Interrupt: %x frame: %x", ints, |
1817 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1818 | |
6f5794a6 | 1819 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1820 | stat = 0xff; |
3e326ece MK |
1821 | |
1822 | if (ints & OHCI_INTR_UE) { | |
1823 | ohci->disabled++; | |
6f5794a6 | 1824 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1825 | ohci->slot_name); |
1826 | /* e.g. due to PCI Master/Target Abort */ | |
1827 | ||
1828 | #ifdef DEBUG | |
6f5794a6 | 1829 | ohci_dump(ohci, 1); |
3e326ece | 1830 | #else |
5b84dd67 | 1831 | mdelay(1); |
3e326ece MK |
1832 | #endif |
1833 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1834 | /* Make some non-interrupt context restart the controller. */ | |
1835 | /* Count and limit the retries though; either hardware or */ | |
1836 | /* software errors can go forever... */ | |
6f5794a6 | 1837 | hc_reset(ohci); |
3e326ece MK |
1838 | return -1; |
1839 | } | |
1840 | ||
1841 | if (ints & OHCI_INTR_WDH) { | |
5b84dd67 | 1842 | mdelay(1); |
a5496a18 BB |
1843 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1844 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
c5613df5 | 1845 | stat = dl_done_list(ohci); |
a5496a18 BB |
1846 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1847 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1848 | } |
1849 | ||
1850 | if (ints & OHCI_INTR_SO) { | |
1851 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1852 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1853 | stat = -1; |
1854 | } | |
1855 | ||
1856 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1857 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1858 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1859 | mdelay(1); |
a5496a18 | 1860 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1861 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1862 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1863 | stat = 0xff; |
1864 | } | |
1865 | ||
a5496a18 | 1866 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1867 | return stat; |
1868 | } | |
1869 | ||
1870 | /*-------------------------------------------------------------------------*/ | |
1871 | ||
1872 | /*-------------------------------------------------------------------------*/ | |
1873 | ||
1874 | /* De-allocate all resources.. */ | |
1875 | ||
6f5794a6 | 1876 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1877 | { |
6f5794a6 | 1878 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1879 | |
1880 | if (!ohci->disabled) | |
6f5794a6 | 1881 | hc_reset(ohci); |
3e326ece MK |
1882 | } |
1883 | ||
1884 | /*-------------------------------------------------------------------------*/ | |
1885 | ||
1886 | /* | |
1887 | * low level initalisation routine, called from usb.c | |
1888 | */ | |
1889 | static char ohci_inited = 0; | |
1890 | ||
06d513ec | 1891 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 1892 | { |
4dae14ce ZW |
1893 | #ifdef CONFIG_PCI_OHCI |
1894 | pci_dev_t pdev; | |
1895 | #endif | |
24e37645 | 1896 | |
6d0f6bcf | 1897 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1898 | /* cpu dependant init */ |
6f5794a6 | 1899 | if (usb_cpu_init()) |
3e326ece | 1900 | return -1; |
24e37645 | 1901 | #endif |
3e326ece | 1902 | |
6d0f6bcf | 1903 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1904 | /* board dependant init */ |
16297cfb | 1905 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
1906 | return -1; |
1907 | #endif | |
6f5794a6 | 1908 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1909 | |
1910 | /* align the storage */ | |
1911 | if ((__u32)&ghcca[0] & 0xff) { | |
1912 | err("HCCA not aligned!!"); | |
1913 | return -1; | |
1914 | } | |
26548bb2 HG |
1915 | gohci.hcca = &ghcca[0]; |
1916 | info("aligned ghcca %p", gohci.hcca); | |
1917 | memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); | |
3e326ece MK |
1918 | |
1919 | gohci.disabled = 1; | |
1920 | gohci.sleeping = 0; | |
1921 | gohci.irq = -1; | |
4dae14ce | 1922 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1923 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1924 | |
1925 | if (pdev != -1) { | |
1926 | u16 vid, did; | |
1927 | u32 base; | |
1928 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1929 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1930 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1931 | vid, did, (pdev >> 16) & 0xff, | |
1932 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1933 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1934 | printf("OHCI regs address 0x%08x\n", base); | |
1935 | gohci.regs = (struct ohci_regs *)base; | |
1936 | } else | |
1937 | return -1; | |
1938 | #else | |
6d0f6bcf | 1939 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1940 | #endif |
3e326ece MK |
1941 | |
1942 | gohci.flags = 0; | |
6d0f6bcf | 1943 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1944 | |
1945 | if (hc_reset (&gohci) < 0) { | |
1946 | hc_release_ohci (&gohci); | |
1947 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1948 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1949 | /* board dependant cleanup */ |
16297cfb | 1950 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
1951 | #endif |
1952 | ||
6d0f6bcf | 1953 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1954 | /* cpu dependant cleanup */ |
ddf83a2f | 1955 | usb_cpu_init_fail(); |
24e37645 | 1956 | #endif |
3e326ece MK |
1957 | return -1; |
1958 | } | |
1959 | ||
6f5794a6 RB |
1960 | if (hc_start(&gohci) < 0) { |
1961 | err("can't start usb-%s", gohci.slot_name); | |
1962 | hc_release_ohci(&gohci); | |
3e326ece | 1963 | /* Initialization failed */ |
6d0f6bcf | 1964 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1965 | /* board dependant cleanup */ |
1966 | usb_board_stop(); | |
1967 | #endif | |
1968 | ||
6d0f6bcf | 1969 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1970 | /* cpu dependant cleanup */ |
1971 | usb_cpu_stop(); | |
1972 | #endif | |
3e326ece MK |
1973 | return -1; |
1974 | } | |
1975 | ||
1976 | #ifdef DEBUG | |
6f5794a6 | 1977 | ohci_dump(&gohci, 1); |
3e326ece | 1978 | #else |
5b84dd67 | 1979 | mdelay(1); |
3e326ece MK |
1980 | #endif |
1981 | ohci_inited = 1; | |
1982 | return 0; | |
1983 | } | |
1984 | ||
c7e3b2b5 | 1985 | int usb_lowlevel_stop(int index) |
3e326ece MK |
1986 | { |
1987 | /* this gets called really early - before the controller has */ | |
1988 | /* even been initialized! */ | |
1989 | if (!ohci_inited) | |
1990 | return 0; | |
1991 | /* TODO release any interrupts, etc. */ | |
1992 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 1993 | hc_reset(&gohci); |
3e326ece | 1994 | |
6d0f6bcf | 1995 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 1996 | /* board dependant cleanup */ |
6f5794a6 | 1997 | if (usb_board_stop()) |
3e326ece | 1998 | return -1; |
24e37645 MK |
1999 | #endif |
2000 | ||
6d0f6bcf | 2001 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2002 | /* cpu dependant cleanup */ |
6f5794a6 | 2003 | if (usb_cpu_stop()) |
24e37645 MK |
2004 | return -1; |
2005 | #endif | |
eba1f2fc RB |
2006 | /* This driver is no longer initialised. It needs a new low-level |
2007 | * init (board/cpu) before it can be used again. */ | |
2008 | ohci_inited = 0; | |
3e326ece MK |
2009 | return 0; |
2010 | } | |
c5613df5 HG |
2011 | |
2012 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, | |
2013 | void *buffer, int transfer_len, struct devrequest *setup) | |
2014 | { | |
2015 | return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, | |
2016 | transfer_len, setup); | |
2017 | } |