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Commit | Line | Data |
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96b8a054 | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. |
96b8a054 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
96b8a054 SW |
5 | */ |
6 | /* | |
7 | * mpc8313epb board configuration file | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_E300 1 | |
0f898604 | 17 | #define CONFIG_MPC83xx 1 |
2c7920af | 18 | #define CONFIG_MPC831x 1 |
96b8a054 SW |
19 | #define CONFIG_MPC8313 1 |
20 | #define CONFIG_MPC8313ERDB 1 | |
21 | ||
22f4442d SW |
22 | #ifdef CONFIG_NAND |
23 | #define CONFIG_SPL | |
24 | #define CONFIG_SPL_INIT_MINIMAL | |
25 | #define CONFIG_SPL_SERIAL_SUPPORT | |
26 | #define CONFIG_SPL_NAND_SUPPORT | |
27 | #define CONFIG_SPL_NAND_MINIMAL | |
28 | #define CONFIG_SPL_FLUSH_IMAGE | |
29 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
30 | #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND | |
31 | ||
32 | #ifdef CONFIG_SPL_BUILD | |
33 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
34 | #endif | |
35 | ||
36 | #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ | |
37 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
38 | #define CONFIG_SPL_MAX_SIZE (4 * 1024) | |
6113d3f2 | 39 | #define CONFIG_SPL_PAD_TO 0x4000 |
22f4442d | 40 | |
f1c574d4 SW |
41 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
42 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
43 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
44 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
45 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
46 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) | |
47 | ||
22f4442d | 48 | #ifdef CONFIG_SPL_BUILD |
f1c574d4 | 49 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ |
22f4442d SW |
50 | #endif |
51 | ||
52 | #endif /* CONFIG_NAND */ | |
f1c574d4 | 53 | |
2ae18241 WD |
54 | #ifndef CONFIG_SYS_TEXT_BASE |
55 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
56 | #endif | |
57 | ||
f1c574d4 SW |
58 | #ifndef CONFIG_SYS_MONITOR_BASE |
59 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
60 | #endif | |
61 | ||
96b8a054 | 62 | #define CONFIG_PCI |
842033e6 | 63 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0914f483 | 64 | #define CONFIG_FSL_ELBC 1 |
96b8a054 | 65 | |
89c7784e TT |
66 | #define CONFIG_MISC_INIT_R |
67 | ||
68 | /* | |
69 | * On-board devices | |
4ce1e23b YS |
70 | * |
71 | * TSEC1 is VSC switch | |
72 | * TSEC2 is SoC TSEC | |
89c7784e TT |
73 | */ |
74 | #define CONFIG_VSC7385_ENET | |
4ce1e23b | 75 | #define CONFIG_TSEC2 |
89c7784e | 76 | |
6d0f6bcf | 77 | #ifdef CONFIG_SYS_66MHZ |
5c5d3242 | 78 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
6d0f6bcf | 79 | #elif defined(CONFIG_SYS_33MHZ) |
5c5d3242 | 80 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
81 | #else |
82 | #error Unknown oscillator frequency. | |
83 | #endif | |
84 | ||
85 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
86 | ||
0eaf8f9e JH |
87 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ |
88 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ | |
96b8a054 | 89 | |
6d0f6bcf | 90 | #define CONFIG_SYS_IMMR 0xE0000000 |
96b8a054 | 91 | |
22f4442d | 92 | #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 93 | #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR |
e4c09508 SW |
94 | #endif |
95 | ||
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_MEMTEST_START 0x00001000 |
97 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
96b8a054 SW |
98 | |
99 | /* Early revs of this board will lock up hard when attempting | |
100 | * to access the PMC registers, unless a JTAG debugger is | |
101 | * connected, or some resistor modifications are made. | |
102 | */ | |
6d0f6bcf | 103 | #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 |
96b8a054 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
106 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
96b8a054 | 107 | |
89c7784e TT |
108 | /* |
109 | * Device configurations | |
110 | */ | |
111 | ||
112 | /* Vitesse 7385 */ | |
113 | ||
114 | #ifdef CONFIG_VSC7385_ENET | |
115 | ||
4ce1e23b | 116 | #define CONFIG_TSEC1 |
89c7784e TT |
117 | |
118 | /* The flash address and size of the VSC7385 firmware image */ | |
119 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
120 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
121 | ||
122 | #endif | |
123 | ||
96b8a054 SW |
124 | /* |
125 | * DDR Setup | |
126 | */ | |
261c07bc | 127 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
129 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
96b8a054 SW |
130 | |
131 | /* | |
132 | * Manually set up DDR parameters, as this board does not | |
133 | * seem to have the SPD connected to I2C. | |
134 | */ | |
261c07bc | 135 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2e651b24 | 136 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
137 | | CSCONFIG_ODT_RD_NEVER \ |
138 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
261c07bc JH |
139 | | CSCONFIG_ROW_BIT_13 \ |
140 | | CSCONFIG_COL_BIT_10) | |
e1d8ed2c | 141 | /* 0x80010102 */ |
96b8a054 | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
261c07bc JH |
144 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
145 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
146 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
147 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
148 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
149 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
150 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
151 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
96b8a054 | 152 | /* 0x00220802 */ |
261c07bc JH |
153 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
154 | | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
155 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
156 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
157 | | (10 << TIMING_CFG1_REFREC_SHIFT) \ | |
158 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
159 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
160 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
e1d8ed2c | 161 | /* 0x3835a322 */ |
261c07bc JH |
162 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
163 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
164 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
165 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
166 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
167 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
168 | | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
e1d8ed2c | 169 | /* 0x129048c6 */ /* P9-45,may need tuning */ |
261c07bc JH |
170 | #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
171 | | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
e1d8ed2c | 172 | /* 0x05100500 */ |
96b8a054 | 173 | #if defined(CONFIG_DDR_2T_TIMING) |
261c07bc | 174 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
bbea46f7 | 175 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 JH |
176 | | SDRAM_CFG_DBW_32 \ |
177 | | SDRAM_CFG_2T_EN) | |
178 | /* 0x43088000 */ | |
96b8a054 | 179 | #else |
261c07bc | 180 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
bbea46f7 | 181 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 182 | | SDRAM_CFG_DBW_32) |
96b8a054 SW |
183 | /* 0x43080000 */ |
184 | #endif | |
6d0f6bcf | 185 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
96b8a054 | 186 | /* set burst length to 8 for 32-bit data path */ |
261c07bc JH |
187 | #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ |
188 | | (0x0632 << SDRAM_MODE_SD_SHIFT)) | |
e1d8ed2c | 189 | /* 0x44480632 */ |
261c07bc | 190 | #define CONFIG_SYS_DDR_MODE_2 0x8000C000 |
96b8a054 | 191 | |
6d0f6bcf | 192 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
96b8a054 | 193 | /*0x02000000*/ |
261c07bc | 194 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
96b8a054 SW |
195 | | DDRCDR_PZ_NOMZ \ |
196 | | DDRCDR_NZ_NOMZ \ | |
261c07bc | 197 | | DDRCDR_M_ODR) |
96b8a054 SW |
198 | |
199 | /* | |
200 | * FLASH on the Local Bus | |
201 | */ | |
261c07bc JH |
202 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
203 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
261c07bc JH |
205 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ |
206 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
207 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
208 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
209 | ||
210 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | |
7d6a0982 JH |
211 | | BR_PS_16 /* 16 bit port */ \ |
212 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
213 | | BR_V) /* valid */ | |
214 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
96b8a054 SW |
215 | | OR_GPCM_XACS \ |
216 | | OR_GPCM_SCY_9 \ | |
217 | | OR_GPCM_EHTR \ | |
261c07bc | 218 | | OR_GPCM_EAD) |
96b8a054 | 219 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ |
261c07bc JH |
220 | /* window base at flash base */ |
221 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 JH |
222 | /* 16 MB window size */ |
223 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) | |
96b8a054 | 224 | |
261c07bc JH |
225 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
226 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ | |
96b8a054 | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
229 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
96b8a054 | 230 | |
261c07bc | 231 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ |
22f4442d | 232 | !defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 233 | #define CONFIG_SYS_RAMBOOT |
96b8a054 SW |
234 | #endif |
235 | ||
6d0f6bcf | 236 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
261c07bc JH |
237 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
238 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
96b8a054 | 239 | |
261c07bc JH |
240 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
241 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 242 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
96b8a054 | 243 | |
6d0f6bcf | 244 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
261c07bc JH |
245 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
246 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
96b8a054 SW |
247 | |
248 | /* | |
249 | * Local Bus LCRR and LBCR regs | |
250 | */ | |
c7190f02 KP |
251 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 |
252 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
261c07bc JH |
253 | #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ |
254 | | (0xFF << LBCR_BMT_SHIFT) \ | |
255 | | 0xF) /* 0x0004ff0f */ | |
96b8a054 | 256 | |
261c07bc JH |
257 | /* LB refresh timer prescal, 266MHz/32 */ |
258 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ | |
96b8a054 | 259 | |
7817cb20 | 260 | /* drivers/mtd/nand/nand.c */ |
22f4442d | 261 | #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 262 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 |
e4c09508 | 263 | #else |
6d0f6bcf | 264 | #define CONFIG_SYS_NAND_BASE 0xE2800000 |
e4c09508 SW |
265 | #endif |
266 | ||
e8d3ca8b SW |
267 | #define CONFIG_MTD_DEVICE |
268 | #define CONFIG_MTD_PARTITION | |
269 | #define CONFIG_CMD_MTDPARTS | |
270 | #define MTDIDS_DEFAULT "nand0=e2800000.flash" | |
261c07bc | 271 | #define MTDPARTS_DEFAULT \ |
c947c12e | 272 | "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" |
e8d3ca8b | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
96b8a054 | 275 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
acdab5c3 SW |
276 | #define CONFIG_CMD_NAND 1 |
277 | #define CONFIG_NAND_FSL_ELBC 1 | |
6d0f6bcf | 278 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
7d6a0982 | 279 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) |
e4c09508 | 280 | |
96b8a054 | 281 | |
261c07bc | 282 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 283 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
261c07bc | 284 | | BR_PS_8 /* 8 bit port */ \ |
a7676ea7 | 285 | | BR_MS_FCM /* MSEL = FCM */ \ |
261c07bc | 286 | | BR_V) /* valid */ |
7d6a0982 JH |
287 | #define CONFIG_SYS_NAND_OR_PRELIM \ |
288 | (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | |
96b8a054 SW |
289 | | OR_FCM_CSCT \ |
290 | | OR_FCM_CST \ | |
291 | | OR_FCM_CHT \ | |
292 | | OR_FCM_SCY_1 \ | |
293 | | OR_FCM_TRLX \ | |
261c07bc | 294 | | OR_FCM_EHTR) |
96b8a054 | 295 | /* 0xFFFF8396 */ |
e4c09508 | 296 | |
22f4442d | 297 | #ifdef CONFIG_NAND |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM |
299 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
300 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM | |
301 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
e4c09508 | 302 | #else |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
304 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
305 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
306 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
e4c09508 SW |
307 | #endif |
308 | ||
6d0f6bcf | 309 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 310 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
96b8a054 | 311 | |
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
313 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
e4c09508 | 314 | |
7d6a0982 JH |
315 | /* local bus write LED / read status buffer (BCSR) mapping */ |
316 | #define CONFIG_SYS_BCSR_ADDR 0xFA000000 | |
317 | #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ | |
318 | /* map at 0xFA000000 on LCS3 */ | |
319 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ | |
320 | | BR_PS_8 /* 8 bit port */ \ | |
321 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
322 | | BR_V) /* valid */ | |
323 | /* 0xFA000801 */ | |
324 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ | |
325 | | OR_GPCM_CSNT \ | |
326 | | OR_GPCM_ACS_DIV2 \ | |
327 | | OR_GPCM_XACS \ | |
328 | | OR_GPCM_SCY_15 \ | |
329 | | OR_GPCM_TRLX_SET \ | |
330 | | OR_GPCM_EHTR_SET \ | |
331 | | OR_GPCM_EAD) | |
332 | /* 0xFFFF8FF7 */ | |
333 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR | |
334 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) | |
89c7784e TT |
335 | |
336 | /* Vitesse 7385 */ | |
337 | ||
89c7784e TT |
338 | #ifdef CONFIG_VSC7385_ENET |
339 | ||
7d6a0982 JH |
340 | /* VSC7385 Base address on LCS2 */ |
341 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 | |
342 | #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ | |
343 | ||
344 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ | |
345 | | BR_PS_8 /* 8 bit port */ \ | |
346 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
347 | | BR_V) /* valid */ | |
348 | #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ | |
349 | | OR_GPCM_CSNT \ | |
350 | | OR_GPCM_XACS \ | |
351 | | OR_GPCM_SCY_15 \ | |
352 | | OR_GPCM_SETA \ | |
353 | | OR_GPCM_TRLX_SET \ | |
354 | | OR_GPCM_EHTR_SET \ | |
355 | | OR_GPCM_EAD) | |
356 | /* 0xFFFE09FF */ | |
357 | ||
261c07bc JH |
358 | /* Access window base at VSC7385 base */ |
359 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 360 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
96b8a054 | 361 | |
89c7784e | 362 | #endif |
96b8a054 SW |
363 | |
364 | /* pass open firmware flat tree */ | |
35cc4e48 | 365 | #define CONFIG_OF_LIBFDT 1 |
96b8a054 | 366 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 367 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
96b8a054 | 368 | |
0eaf8f9e JH |
369 | #define CONFIG_MPC83XX_GPIO 1 |
370 | #define CONFIG_CMD_GPIO 1 | |
371 | ||
96b8a054 SW |
372 | /* |
373 | * Serial Port | |
374 | */ | |
375 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_NS16550 |
377 | #define CONFIG_SYS_NS16550_SERIAL | |
378 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
96b8a054 | 379 | |
6d0f6bcf | 380 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
96b8a054 SW |
381 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
382 | ||
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
384 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
96b8a054 SW |
385 | |
386 | /* Use the HUSH parser */ | |
6d0f6bcf | 387 | #define CONFIG_SYS_HUSH_PARSER |
96b8a054 SW |
388 | |
389 | /* I2C */ | |
390 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
391 | #define CONFIG_FSL_I2C | |
392 | #define CONFIG_I2C_MULTI_BUS | |
261c07bc JH |
393 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
394 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
395 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
396 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
397 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
96b8a054 | 398 | |
96b8a054 SW |
399 | /* |
400 | * General PCI | |
401 | * Addresses are mapped 1-1. | |
402 | */ | |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
404 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
405 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
406 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
407 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
408 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
409 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
410 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
411 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
96b8a054 SW |
412 | |
413 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
6d0f6bcf | 414 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
96b8a054 SW |
415 | |
416 | /* | |
89c7784e | 417 | * TSEC |
96b8a054 SW |
418 | */ |
419 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
420 | ||
89c7784e | 421 | #define CONFIG_GMII /* MII PHY management */ |
96b8a054 | 422 | |
89c7784e TT |
423 | #ifdef CONFIG_TSEC1 |
424 | #define CONFIG_HAS_ETH0 | |
255a3577 | 425 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 426 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
89c7784e TT |
427 | #define TSEC1_PHY_ADDR 0x1c |
428 | #define TSEC1_FLAGS TSEC_GIGABIT | |
429 | #define TSEC1_PHYIDX 0 | |
430 | #endif | |
431 | ||
432 | #ifdef CONFIG_TSEC2 | |
433 | #define CONFIG_HAS_ETH1 | |
255a3577 | 434 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 435 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
436 | #define TSEC2_PHY_ADDR 4 |
437 | #define TSEC2_FLAGS TSEC_GIGABIT | |
438 | #define TSEC2_PHYIDX 0 | |
439 | #endif | |
440 | ||
96b8a054 SW |
441 | |
442 | /* Options are: TSEC[0-1] */ | |
443 | #define CONFIG_ETHPRIME "TSEC1" | |
444 | ||
445 | /* | |
446 | * Configure on-board RTC | |
447 | */ | |
448 | #define CONFIG_RTC_DS1337 | |
6d0f6bcf | 449 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
96b8a054 SW |
450 | |
451 | /* | |
452 | * Environment | |
453 | */ | |
22f4442d | 454 | #if defined(CONFIG_NAND) |
51bfee19 | 455 | #define CONFIG_ENV_IS_IN_NAND 1 |
0e8d1586 | 456 | #define CONFIG_ENV_OFFSET (512 * 1024) |
6d0f6bcf | 457 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
0e8d1586 JCPV |
458 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
459 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
460 | #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) | |
261c07bc JH |
461 | #define CONFIG_ENV_OFFSET_REDUND \ |
462 | (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
6d0f6bcf | 463 | #elif !defined(CONFIG_SYS_RAMBOOT) |
5a1aceb0 | 464 | #define CONFIG_ENV_IS_IN_FLASH 1 |
261c07bc JH |
465 | #define CONFIG_ENV_ADDR \ |
466 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
467 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
468 | #define CONFIG_ENV_SIZE 0x2000 | |
96b8a054 SW |
469 | |
470 | /* Address and size of Redundant Environment Sector */ | |
471 | #else | |
93f6d725 | 472 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 473 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 474 | #define CONFIG_ENV_SIZE 0x2000 |
96b8a054 SW |
475 | #endif |
476 | ||
477 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 478 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
96b8a054 | 479 | |
079a136c JL |
480 | /* |
481 | * BOOTP options | |
482 | */ | |
483 | #define CONFIG_BOOTP_BOOTFILESIZE | |
484 | #define CONFIG_BOOTP_BOOTPATH | |
485 | #define CONFIG_BOOTP_GATEWAY | |
486 | #define CONFIG_BOOTP_HOSTNAME | |
487 | ||
488 | ||
8ea5499a JL |
489 | /* |
490 | * Command line configuration. | |
491 | */ | |
492 | #include <config_cmd_default.h> | |
96b8a054 | 493 | |
8ea5499a JL |
494 | #define CONFIG_CMD_PING |
495 | #define CONFIG_CMD_DHCP | |
496 | #define CONFIG_CMD_I2C | |
497 | #define CONFIG_CMD_MII | |
498 | #define CONFIG_CMD_DATE | |
499 | #define CONFIG_CMD_PCI | |
96b8a054 | 500 | |
22f4442d | 501 | #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND) |
bdab39d3 | 502 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 503 | #undef CONFIG_CMD_LOADS |
96b8a054 SW |
504 | #endif |
505 | ||
8ea5499a | 506 | #define CONFIG_CMDLINE_EDITING 1 |
a059e90e | 507 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
96b8a054 SW |
508 | |
509 | /* | |
510 | * Miscellaneous configurable options | |
511 | */ | |
6d0f6bcf JCPV |
512 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
513 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
514 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
515 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
96b8a054 | 516 | |
261c07bc JH |
517 | /* Print Buffer Size */ |
518 | #define CONFIG_SYS_PBSIZE \ | |
519 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
520 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
521 | /* Boot Argument Buffer Size */ | |
522 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
523 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
96b8a054 SW |
524 | |
525 | /* | |
526 | * For booting Linux, the board info and command line data | |
9f530d59 | 527 | * have to be in the first 256 MB of memory, since this is |
96b8a054 SW |
528 | * the maximum mapped by the Linux kernel during initialization. |
529 | */ | |
261c07bc JH |
530 | /* Initial Memory map for Linux*/ |
531 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
96b8a054 | 532 | |
6d0f6bcf | 533 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 | 534 | |
6d0f6bcf | 535 | #ifdef CONFIG_SYS_66MHZ |
96b8a054 SW |
536 | |
537 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
538 | /* 0x62040000 */ | |
6d0f6bcf | 539 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
540 | 0x20000000 /* reserved, must be set */ |\ |
541 | HRCWL_DDRCM |\ | |
542 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
543 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
544 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
545 | HRCWL_CORE_TO_CSB_2X1) | |
546 | ||
6d0f6bcf | 547 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
e4c09508 | 548 | |
6d0f6bcf | 549 | #elif defined(CONFIG_SYS_33MHZ) |
96b8a054 SW |
550 | |
551 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
552 | /* 0x65040000 */ | |
6d0f6bcf | 553 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
554 | 0x20000000 /* reserved, must be set */ |\ |
555 | HRCWL_DDRCM |\ | |
556 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
557 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
558 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
559 | HRCWL_CORE_TO_CSB_2X1) | |
560 | ||
6d0f6bcf | 561 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) |
e4c09508 | 562 | |
96b8a054 SW |
563 | #endif |
564 | ||
6d0f6bcf | 565 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
96b8a054 SW |
566 | HRCWH_PCI_HOST |\ |
567 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
568 | HRCWH_CORE_ENABLE |\ | |
96b8a054 SW |
569 | HRCWH_BOOTSEQ_DISABLE |\ |
570 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
96b8a054 SW |
571 | HRCWH_TSEC1M_IN_RGMII |\ |
572 | HRCWH_TSEC2M_IN_RGMII |\ | |
e4c09508 SW |
573 | HRCWH_BIG_ENDIAN) |
574 | ||
22f4442d | 575 | #ifdef CONFIG_NAND |
6d0f6bcf | 576 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
577 | HRCWH_FROM_0XFFF00100 |\ |
578 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
579 | HRCWH_RL_EXT_NAND) | |
e4c09508 | 580 | #else |
6d0f6bcf | 581 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
582 | HRCWH_FROM_0X00000100 |\ |
583 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
584 | HRCWH_RL_EXT_LEGACY) | |
e4c09508 | 585 | #endif |
96b8a054 SW |
586 | |
587 | /* System IO Config */ | |
6d0f6bcf | 588 | #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
0eaf8f9e JH |
589 | /* Enable Internal USB Phy and GPIO on LCD Connector */ |
590 | #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) | |
96b8a054 | 591 | |
6d0f6bcf JCPV |
592 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
593 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
1a2e203b KP |
594 | HID0_ENABLE_INSTRUCTION_CACHE | \ |
595 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
96b8a054 | 596 | |
6d0f6bcf | 597 | #define CONFIG_SYS_HID2 HID2_HBE |
96b8a054 | 598 | |
31d82672 BB |
599 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
600 | ||
96b8a054 | 601 | /* DDR @ 0x00000000 */ |
72cd4087 | 602 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) |
261c07bc JH |
603 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
604 | | BATU_BL_256M \ | |
605 | | BATU_VS \ | |
606 | | BATU_VP) | |
96b8a054 SW |
607 | |
608 | /* PCI @ 0x80000000 */ | |
72cd4087 | 609 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) |
261c07bc JH |
610 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ |
611 | | BATU_BL_256M \ | |
612 | | BATU_VS \ | |
613 | | BATU_VP) | |
614 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 615 | | BATL_PP_RW \ |
261c07bc JH |
616 | | BATL_CACHEINHIBIT \ |
617 | | BATL_GUARDEDSTORAGE) | |
618 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
619 | | BATU_BL_256M \ | |
620 | | BATU_VS \ | |
621 | | BATU_VP) | |
96b8a054 SW |
622 | |
623 | /* PCI2 not supported on 8313 */ | |
6d0f6bcf JCPV |
624 | #define CONFIG_SYS_IBAT3L (0) |
625 | #define CONFIG_SYS_IBAT3U (0) | |
626 | #define CONFIG_SYS_IBAT4L (0) | |
627 | #define CONFIG_SYS_IBAT4U (0) | |
96b8a054 SW |
628 | |
629 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
261c07bc | 630 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 631 | | BATL_PP_RW \ |
261c07bc JH |
632 | | BATL_CACHEINHIBIT \ |
633 | | BATL_GUARDEDSTORAGE) | |
634 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
635 | | BATU_BL_256M \ | |
636 | | BATU_VS \ | |
637 | | BATU_VP) | |
96b8a054 SW |
638 | |
639 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
72cd4087 | 640 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
641 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
642 | ||
643 | #define CONFIG_SYS_IBAT7L (0) | |
644 | #define CONFIG_SYS_IBAT7U (0) | |
645 | ||
646 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
647 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
648 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
649 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
650 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
651 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
652 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
653 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
654 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
655 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
656 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
657 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
658 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
659 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
660 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
661 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
96b8a054 | 662 | |
96b8a054 SW |
663 | /* |
664 | * Environment Configuration | |
665 | */ | |
666 | #define CONFIG_ENV_OVERWRITE | |
667 | ||
261c07bc | 668 | #define CONFIG_NETDEV "eth1" |
96b8a054 SW |
669 | |
670 | #define CONFIG_HOSTNAME mpc8313erdb | |
8b3637c6 | 671 | #define CONFIG_ROOTPATH "/nfs/root/path" |
b3f44c21 | 672 | #define CONFIG_BOOTFILE "uImage" |
261c07bc JH |
673 | /* U-Boot image on TFTP server */ |
674 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
675 | #define CONFIG_FDTFILE "mpc8313erdb.dtb" | |
96b8a054 | 676 | |
261c07bc JH |
677 | /* default location for tftp and bootm */ |
678 | #define CONFIG_LOADADDR 800000 | |
7fd0bea2 | 679 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
96b8a054 SW |
680 | #define CONFIG_BAUDRATE 115200 |
681 | ||
96b8a054 | 682 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
261c07bc | 683 | "netdev=" CONFIG_NETDEV "\0" \ |
96b8a054 | 684 | "ethprime=TSEC1\0" \ |
261c07bc | 685 | "uboot=" CONFIG_UBOOTPATH "\0" \ |
53677ef1 | 686 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
687 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
688 | " +$filesize; " \ | |
689 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
690 | " +$filesize; " \ | |
691 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
692 | " $filesize; " \ | |
693 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
694 | " +$filesize; " \ | |
695 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
696 | " $filesize\0" \ | |
79f516bc | 697 | "fdtaddr=780000\0" \ |
261c07bc | 698 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
96b8a054 SW |
699 | "console=ttyS0\0" \ |
700 | "setbootargs=setenv bootargs " \ | |
701 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
53677ef1 | 702 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ |
261c07bc JH |
703 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ |
704 | "$netdev:off " \ | |
96b8a054 SW |
705 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
706 | ||
707 | #define CONFIG_NFSBOOTCOMMAND \ | |
708 | "setenv rootdev /dev/nfs;" \ | |
53677ef1 WD |
709 | "run setbootargs;" \ |
710 | "run setipargs;" \ | |
96b8a054 SW |
711 | "tftp $loadaddr $bootfile;" \ |
712 | "tftp $fdtaddr $fdtfile;" \ | |
713 | "bootm $loadaddr - $fdtaddr" | |
714 | ||
715 | #define CONFIG_RAMBOOTCOMMAND \ | |
716 | "setenv rootdev /dev/ram;" \ | |
717 | "run setbootargs;" \ | |
718 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
719 | "tftp $loadaddr $bootfile;" \ | |
720 | "tftp $fdtaddr $fdtfile;" \ | |
721 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
722 | ||
96b8a054 | 723 | #endif /* __CONFIG_H */ |