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Commit | Line | Data |
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96b8a054 | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. |
96b8a054 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
96b8a054 SW |
5 | */ |
6 | /* | |
7 | * mpc8313epb board configuration file | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_E300 1 | |
2c7920af | 17 | #define CONFIG_MPC831x 1 |
96b8a054 SW |
18 | #define CONFIG_MPC8313 1 |
19 | #define CONFIG_MPC8313ERDB 1 | |
20 | ||
22f4442d | 21 | #ifdef CONFIG_NAND |
22f4442d | 22 | #define CONFIG_SPL_INIT_MINIMAL |
22f4442d SW |
23 | #define CONFIG_SPL_FLUSH_IMAGE |
24 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
25 | #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND | |
26 | ||
27 | #ifdef CONFIG_SPL_BUILD | |
28 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
29 | #endif | |
30 | ||
22f4442d SW |
31 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 |
32 | #define CONFIG_SPL_MAX_SIZE (4 * 1024) | |
6113d3f2 | 33 | #define CONFIG_SPL_PAD_TO 0x4000 |
22f4442d | 34 | |
f1c574d4 SW |
35 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
36 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
37 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
38 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
39 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
40 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) | |
41 | ||
22f4442d | 42 | #ifdef CONFIG_SPL_BUILD |
f1c574d4 | 43 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ |
22f4442d SW |
44 | #endif |
45 | ||
46 | #endif /* CONFIG_NAND */ | |
f1c574d4 | 47 | |
f1c574d4 SW |
48 | #ifndef CONFIG_SYS_MONITOR_BASE |
49 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
50 | #endif | |
51 | ||
842033e6 | 52 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0914f483 | 53 | #define CONFIG_FSL_ELBC 1 |
96b8a054 | 54 | |
89c7784e TT |
55 | #define CONFIG_MISC_INIT_R |
56 | ||
57 | /* | |
58 | * On-board devices | |
4ce1e23b YS |
59 | * |
60 | * TSEC1 is VSC switch | |
61 | * TSEC2 is SoC TSEC | |
89c7784e TT |
62 | */ |
63 | #define CONFIG_VSC7385_ENET | |
4ce1e23b | 64 | #define CONFIG_TSEC2 |
89c7784e | 65 | |
6d0f6bcf | 66 | #ifdef CONFIG_SYS_66MHZ |
5c5d3242 | 67 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
6d0f6bcf | 68 | #elif defined(CONFIG_SYS_33MHZ) |
5c5d3242 | 69 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
70 | #else |
71 | #error Unknown oscillator frequency. | |
72 | #endif | |
73 | ||
74 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
75 | ||
0eaf8f9e | 76 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ |
96b8a054 | 77 | |
6d0f6bcf | 78 | #define CONFIG_SYS_IMMR 0xE0000000 |
96b8a054 | 79 | |
22f4442d | 80 | #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 81 | #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR |
e4c09508 SW |
82 | #endif |
83 | ||
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_MEMTEST_START 0x00001000 |
85 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
96b8a054 SW |
86 | |
87 | /* Early revs of this board will lock up hard when attempting | |
88 | * to access the PMC registers, unless a JTAG debugger is | |
89 | * connected, or some resistor modifications are made. | |
90 | */ | |
6d0f6bcf | 91 | #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 |
96b8a054 | 92 | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
94 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
96b8a054 | 95 | |
89c7784e TT |
96 | /* |
97 | * Device configurations | |
98 | */ | |
99 | ||
100 | /* Vitesse 7385 */ | |
101 | ||
102 | #ifdef CONFIG_VSC7385_ENET | |
103 | ||
4ce1e23b | 104 | #define CONFIG_TSEC1 |
89c7784e TT |
105 | |
106 | /* The flash address and size of the VSC7385 firmware image */ | |
107 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
108 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
109 | ||
110 | #endif | |
111 | ||
96b8a054 SW |
112 | /* |
113 | * DDR Setup | |
114 | */ | |
261c07bc | 115 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
117 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
96b8a054 SW |
118 | |
119 | /* | |
120 | * Manually set up DDR parameters, as this board does not | |
121 | * seem to have the SPD connected to I2C. | |
122 | */ | |
261c07bc | 123 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2e651b24 | 124 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
125 | | CSCONFIG_ODT_RD_NEVER \ |
126 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
261c07bc JH |
127 | | CSCONFIG_ROW_BIT_13 \ |
128 | | CSCONFIG_COL_BIT_10) | |
e1d8ed2c | 129 | /* 0x80010102 */ |
96b8a054 | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
261c07bc JH |
132 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
133 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
134 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
135 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
136 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
137 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
138 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
139 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
96b8a054 | 140 | /* 0x00220802 */ |
261c07bc JH |
141 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
142 | | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
143 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
144 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
145 | | (10 << TIMING_CFG1_REFREC_SHIFT) \ | |
146 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
147 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
148 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
e1d8ed2c | 149 | /* 0x3835a322 */ |
261c07bc JH |
150 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
151 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
152 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
153 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
154 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
155 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
156 | | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
e1d8ed2c | 157 | /* 0x129048c6 */ /* P9-45,may need tuning */ |
261c07bc JH |
158 | #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
159 | | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
e1d8ed2c | 160 | /* 0x05100500 */ |
96b8a054 | 161 | #if defined(CONFIG_DDR_2T_TIMING) |
261c07bc | 162 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
bbea46f7 | 163 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 JH |
164 | | SDRAM_CFG_DBW_32 \ |
165 | | SDRAM_CFG_2T_EN) | |
166 | /* 0x43088000 */ | |
96b8a054 | 167 | #else |
261c07bc | 168 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ |
bbea46f7 | 169 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 170 | | SDRAM_CFG_DBW_32) |
96b8a054 SW |
171 | /* 0x43080000 */ |
172 | #endif | |
6d0f6bcf | 173 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
96b8a054 | 174 | /* set burst length to 8 for 32-bit data path */ |
261c07bc JH |
175 | #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ |
176 | | (0x0632 << SDRAM_MODE_SD_SHIFT)) | |
e1d8ed2c | 177 | /* 0x44480632 */ |
261c07bc | 178 | #define CONFIG_SYS_DDR_MODE_2 0x8000C000 |
96b8a054 | 179 | |
6d0f6bcf | 180 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
96b8a054 | 181 | /*0x02000000*/ |
261c07bc | 182 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
96b8a054 SW |
183 | | DDRCDR_PZ_NOMZ \ |
184 | | DDRCDR_NZ_NOMZ \ | |
261c07bc | 185 | | DDRCDR_M_ODR) |
96b8a054 SW |
186 | |
187 | /* | |
188 | * FLASH on the Local Bus | |
189 | */ | |
261c07bc JH |
190 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
191 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 192 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
261c07bc JH |
193 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ |
194 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
195 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
196 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
197 | ||
198 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | |
7d6a0982 JH |
199 | | BR_PS_16 /* 16 bit port */ \ |
200 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
201 | | BR_V) /* valid */ | |
202 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
96b8a054 SW |
203 | | OR_GPCM_XACS \ |
204 | | OR_GPCM_SCY_9 \ | |
205 | | OR_GPCM_EHTR \ | |
261c07bc | 206 | | OR_GPCM_EAD) |
96b8a054 | 207 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ |
261c07bc JH |
208 | /* window base at flash base */ |
209 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 JH |
210 | /* 16 MB window size */ |
211 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) | |
96b8a054 | 212 | |
261c07bc JH |
213 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
214 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ | |
96b8a054 | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
217 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
96b8a054 | 218 | |
261c07bc | 219 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ |
22f4442d | 220 | !defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 221 | #define CONFIG_SYS_RAMBOOT |
96b8a054 SW |
222 | #endif |
223 | ||
6d0f6bcf | 224 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
261c07bc JH |
225 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
226 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
96b8a054 | 227 | |
261c07bc JH |
228 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
229 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 230 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
96b8a054 | 231 | |
6d0f6bcf | 232 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
16c8c170 | 233 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
261c07bc | 234 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
96b8a054 SW |
235 | |
236 | /* | |
237 | * Local Bus LCRR and LBCR regs | |
238 | */ | |
c7190f02 KP |
239 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 |
240 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
261c07bc JH |
241 | #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ |
242 | | (0xFF << LBCR_BMT_SHIFT) \ | |
243 | | 0xF) /* 0x0004ff0f */ | |
96b8a054 | 244 | |
261c07bc JH |
245 | /* LB refresh timer prescal, 266MHz/32 */ |
246 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ | |
96b8a054 | 247 | |
7817cb20 | 248 | /* drivers/mtd/nand/nand.c */ |
22f4442d | 249 | #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) |
6d0f6bcf | 250 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 |
e4c09508 | 251 | #else |
6d0f6bcf | 252 | #define CONFIG_SYS_NAND_BASE 0xE2800000 |
e4c09508 SW |
253 | #endif |
254 | ||
e8d3ca8b SW |
255 | #define CONFIG_MTD_DEVICE |
256 | #define CONFIG_MTD_PARTITION | |
e8d3ca8b | 257 | |
6d0f6bcf | 258 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
acdab5c3 | 259 | #define CONFIG_NAND_FSL_ELBC 1 |
6d0f6bcf | 260 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
7d6a0982 | 261 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) |
e4c09508 | 262 | |
261c07bc | 263 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 264 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
261c07bc | 265 | | BR_PS_8 /* 8 bit port */ \ |
a7676ea7 | 266 | | BR_MS_FCM /* MSEL = FCM */ \ |
261c07bc | 267 | | BR_V) /* valid */ |
7d6a0982 JH |
268 | #define CONFIG_SYS_NAND_OR_PRELIM \ |
269 | (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | |
96b8a054 SW |
270 | | OR_FCM_CSCT \ |
271 | | OR_FCM_CST \ | |
272 | | OR_FCM_CHT \ | |
273 | | OR_FCM_SCY_1 \ | |
274 | | OR_FCM_TRLX \ | |
261c07bc | 275 | | OR_FCM_EHTR) |
96b8a054 | 276 | /* 0xFFFF8396 */ |
e4c09508 | 277 | |
22f4442d | 278 | #ifdef CONFIG_NAND |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM |
280 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
281 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM | |
282 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
e4c09508 | 283 | #else |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
285 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
286 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
287 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
e4c09508 SW |
288 | #endif |
289 | ||
6d0f6bcf | 290 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 291 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
96b8a054 | 292 | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
294 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
e4c09508 | 295 | |
7d6a0982 JH |
296 | /* local bus write LED / read status buffer (BCSR) mapping */ |
297 | #define CONFIG_SYS_BCSR_ADDR 0xFA000000 | |
298 | #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ | |
299 | /* map at 0xFA000000 on LCS3 */ | |
300 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ | |
301 | | BR_PS_8 /* 8 bit port */ \ | |
302 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
303 | | BR_V) /* valid */ | |
304 | /* 0xFA000801 */ | |
305 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ | |
306 | | OR_GPCM_CSNT \ | |
307 | | OR_GPCM_ACS_DIV2 \ | |
308 | | OR_GPCM_XACS \ | |
309 | | OR_GPCM_SCY_15 \ | |
310 | | OR_GPCM_TRLX_SET \ | |
311 | | OR_GPCM_EHTR_SET \ | |
312 | | OR_GPCM_EAD) | |
313 | /* 0xFFFF8FF7 */ | |
314 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR | |
315 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) | |
89c7784e TT |
316 | |
317 | /* Vitesse 7385 */ | |
318 | ||
89c7784e TT |
319 | #ifdef CONFIG_VSC7385_ENET |
320 | ||
7d6a0982 JH |
321 | /* VSC7385 Base address on LCS2 */ |
322 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 | |
323 | #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ | |
324 | ||
325 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ | |
326 | | BR_PS_8 /* 8 bit port */ \ | |
327 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
328 | | BR_V) /* valid */ | |
329 | #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ | |
330 | | OR_GPCM_CSNT \ | |
331 | | OR_GPCM_XACS \ | |
332 | | OR_GPCM_SCY_15 \ | |
333 | | OR_GPCM_SETA \ | |
334 | | OR_GPCM_TRLX_SET \ | |
335 | | OR_GPCM_EHTR_SET \ | |
336 | | OR_GPCM_EAD) | |
337 | /* 0xFFFE09FF */ | |
338 | ||
261c07bc JH |
339 | /* Access window base at VSC7385 base */ |
340 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 341 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
96b8a054 | 342 | |
89c7784e | 343 | #endif |
96b8a054 | 344 | |
0eaf8f9e | 345 | #define CONFIG_MPC83XX_GPIO 1 |
0eaf8f9e | 346 | |
96b8a054 SW |
347 | /* |
348 | * Serial Port | |
349 | */ | |
350 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_NS16550_SERIAL |
352 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
96b8a054 | 353 | |
6d0f6bcf | 354 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
96b8a054 SW |
355 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
356 | ||
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
358 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
96b8a054 | 359 | |
96b8a054 | 360 | /* I2C */ |
00f792e0 HS |
361 | #define CONFIG_SYS_I2C |
362 | #define CONFIG_SYS_I2C_FSL | |
363 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
364 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
365 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
366 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
367 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
368 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
369 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
96b8a054 | 370 | |
96b8a054 SW |
371 | /* |
372 | * General PCI | |
373 | * Addresses are mapped 1-1. | |
374 | */ | |
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
376 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
377 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
378 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
379 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
380 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
381 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
382 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
383 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
96b8a054 | 384 | |
6d0f6bcf | 385 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
96b8a054 SW |
386 | |
387 | /* | |
89c7784e | 388 | * TSEC |
96b8a054 SW |
389 | */ |
390 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
391 | ||
89c7784e | 392 | #define CONFIG_GMII /* MII PHY management */ |
96b8a054 | 393 | |
89c7784e TT |
394 | #ifdef CONFIG_TSEC1 |
395 | #define CONFIG_HAS_ETH0 | |
255a3577 | 396 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 397 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
89c7784e TT |
398 | #define TSEC1_PHY_ADDR 0x1c |
399 | #define TSEC1_FLAGS TSEC_GIGABIT | |
400 | #define TSEC1_PHYIDX 0 | |
401 | #endif | |
402 | ||
403 | #ifdef CONFIG_TSEC2 | |
404 | #define CONFIG_HAS_ETH1 | |
255a3577 | 405 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 406 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
407 | #define TSEC2_PHY_ADDR 4 |
408 | #define TSEC2_FLAGS TSEC_GIGABIT | |
409 | #define TSEC2_PHYIDX 0 | |
410 | #endif | |
411 | ||
96b8a054 SW |
412 | /* Options are: TSEC[0-1] */ |
413 | #define CONFIG_ETHPRIME "TSEC1" | |
414 | ||
415 | /* | |
416 | * Configure on-board RTC | |
417 | */ | |
418 | #define CONFIG_RTC_DS1337 | |
6d0f6bcf | 419 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
96b8a054 SW |
420 | |
421 | /* | |
422 | * Environment | |
423 | */ | |
22f4442d | 424 | #if defined(CONFIG_NAND) |
0e8d1586 | 425 | #define CONFIG_ENV_OFFSET (512 * 1024) |
6d0f6bcf | 426 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
0e8d1586 JCPV |
427 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
428 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
429 | #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) | |
261c07bc JH |
430 | #define CONFIG_ENV_OFFSET_REDUND \ |
431 | (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
6d0f6bcf | 432 | #elif !defined(CONFIG_SYS_RAMBOOT) |
261c07bc JH |
433 | #define CONFIG_ENV_ADDR \ |
434 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
435 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
436 | #define CONFIG_ENV_SIZE 0x2000 | |
96b8a054 SW |
437 | |
438 | /* Address and size of Redundant Environment Sector */ | |
439 | #else | |
6d0f6bcf | 440 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 441 | #define CONFIG_ENV_SIZE 0x2000 |
96b8a054 SW |
442 | #endif |
443 | ||
444 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 445 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
96b8a054 | 446 | |
079a136c JL |
447 | /* |
448 | * BOOTP options | |
449 | */ | |
450 | #define CONFIG_BOOTP_BOOTFILESIZE | |
079a136c | 451 | |
8ea5499a JL |
452 | /* |
453 | * Command line configuration. | |
454 | */ | |
96b8a054 | 455 | |
96b8a054 SW |
456 | /* |
457 | * Miscellaneous configurable options | |
458 | */ | |
6d0f6bcf | 459 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
6d0f6bcf | 460 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
96b8a054 | 461 | |
261c07bc JH |
462 | /* Boot Argument Buffer Size */ |
463 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
96b8a054 SW |
464 | |
465 | /* | |
466 | * For booting Linux, the board info and command line data | |
9f530d59 | 467 | * have to be in the first 256 MB of memory, since this is |
96b8a054 SW |
468 | * the maximum mapped by the Linux kernel during initialization. |
469 | */ | |
261c07bc JH |
470 | /* Initial Memory map for Linux*/ |
471 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
63865278 | 472 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
96b8a054 | 473 | |
6d0f6bcf | 474 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 | 475 | |
6d0f6bcf | 476 | #ifdef CONFIG_SYS_66MHZ |
96b8a054 SW |
477 | |
478 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
479 | /* 0x62040000 */ | |
6d0f6bcf | 480 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
481 | 0x20000000 /* reserved, must be set */ |\ |
482 | HRCWL_DDRCM |\ | |
483 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
484 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
485 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
486 | HRCWL_CORE_TO_CSB_2X1) | |
487 | ||
6d0f6bcf | 488 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
e4c09508 | 489 | |
6d0f6bcf | 490 | #elif defined(CONFIG_SYS_33MHZ) |
96b8a054 SW |
491 | |
492 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
493 | /* 0x65040000 */ | |
6d0f6bcf | 494 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
495 | 0x20000000 /* reserved, must be set */ |\ |
496 | HRCWL_DDRCM |\ | |
497 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
498 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
499 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
500 | HRCWL_CORE_TO_CSB_2X1) | |
501 | ||
6d0f6bcf | 502 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) |
e4c09508 | 503 | |
96b8a054 SW |
504 | #endif |
505 | ||
6d0f6bcf | 506 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
96b8a054 SW |
507 | HRCWH_PCI_HOST |\ |
508 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
509 | HRCWH_CORE_ENABLE |\ | |
96b8a054 SW |
510 | HRCWH_BOOTSEQ_DISABLE |\ |
511 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
96b8a054 SW |
512 | HRCWH_TSEC1M_IN_RGMII |\ |
513 | HRCWH_TSEC2M_IN_RGMII |\ | |
e4c09508 SW |
514 | HRCWH_BIG_ENDIAN) |
515 | ||
22f4442d | 516 | #ifdef CONFIG_NAND |
6d0f6bcf | 517 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
518 | HRCWH_FROM_0XFFF00100 |\ |
519 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
520 | HRCWH_RL_EXT_NAND) | |
e4c09508 | 521 | #else |
6d0f6bcf | 522 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
523 | HRCWH_FROM_0X00000100 |\ |
524 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
525 | HRCWH_RL_EXT_LEGACY) | |
e4c09508 | 526 | #endif |
96b8a054 SW |
527 | |
528 | /* System IO Config */ | |
6d0f6bcf | 529 | #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
0eaf8f9e JH |
530 | /* Enable Internal USB Phy and GPIO on LCD Connector */ |
531 | #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) | |
96b8a054 | 532 | |
6d0f6bcf JCPV |
533 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
534 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
1a2e203b KP |
535 | HID0_ENABLE_INSTRUCTION_CACHE | \ |
536 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
96b8a054 | 537 | |
6d0f6bcf | 538 | #define CONFIG_SYS_HID2 HID2_HBE |
96b8a054 | 539 | |
31d82672 BB |
540 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
541 | ||
96b8a054 | 542 | /* DDR @ 0x00000000 */ |
72cd4087 | 543 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) |
261c07bc JH |
544 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
545 | | BATU_BL_256M \ | |
546 | | BATU_VS \ | |
547 | | BATU_VP) | |
96b8a054 SW |
548 | |
549 | /* PCI @ 0x80000000 */ | |
72cd4087 | 550 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) |
261c07bc JH |
551 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ |
552 | | BATU_BL_256M \ | |
553 | | BATU_VS \ | |
554 | | BATU_VP) | |
555 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 556 | | BATL_PP_RW \ |
261c07bc JH |
557 | | BATL_CACHEINHIBIT \ |
558 | | BATL_GUARDEDSTORAGE) | |
559 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
560 | | BATU_BL_256M \ | |
561 | | BATU_VS \ | |
562 | | BATU_VP) | |
96b8a054 SW |
563 | |
564 | /* PCI2 not supported on 8313 */ | |
6d0f6bcf JCPV |
565 | #define CONFIG_SYS_IBAT3L (0) |
566 | #define CONFIG_SYS_IBAT3U (0) | |
567 | #define CONFIG_SYS_IBAT4L (0) | |
568 | #define CONFIG_SYS_IBAT4U (0) | |
96b8a054 SW |
569 | |
570 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
261c07bc | 571 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 572 | | BATL_PP_RW \ |
261c07bc JH |
573 | | BATL_CACHEINHIBIT \ |
574 | | BATL_GUARDEDSTORAGE) | |
575 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
576 | | BATU_BL_256M \ | |
577 | | BATU_VS \ | |
578 | | BATU_VP) | |
96b8a054 SW |
579 | |
580 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
72cd4087 | 581 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
582 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
583 | ||
584 | #define CONFIG_SYS_IBAT7L (0) | |
585 | #define CONFIG_SYS_IBAT7U (0) | |
586 | ||
587 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
588 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
589 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
590 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
591 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
592 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
593 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
594 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
595 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
596 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
597 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
598 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
599 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
600 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
601 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
602 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
96b8a054 | 603 | |
96b8a054 SW |
604 | /* |
605 | * Environment Configuration | |
606 | */ | |
607 | #define CONFIG_ENV_OVERWRITE | |
608 | ||
261c07bc | 609 | #define CONFIG_NETDEV "eth1" |
96b8a054 SW |
610 | |
611 | #define CONFIG_HOSTNAME mpc8313erdb | |
8b3637c6 | 612 | #define CONFIG_ROOTPATH "/nfs/root/path" |
b3f44c21 | 613 | #define CONFIG_BOOTFILE "uImage" |
261c07bc JH |
614 | /* U-Boot image on TFTP server */ |
615 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
616 | #define CONFIG_FDTFILE "mpc8313erdb.dtb" | |
96b8a054 | 617 | |
261c07bc JH |
618 | /* default location for tftp and bootm */ |
619 | #define CONFIG_LOADADDR 800000 | |
96b8a054 | 620 | |
96b8a054 | 621 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
261c07bc | 622 | "netdev=" CONFIG_NETDEV "\0" \ |
96b8a054 | 623 | "ethprime=TSEC1\0" \ |
261c07bc | 624 | "uboot=" CONFIG_UBOOTPATH "\0" \ |
53677ef1 | 625 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
626 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
627 | " +$filesize; " \ | |
628 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
629 | " +$filesize; " \ | |
630 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
631 | " $filesize; " \ | |
632 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
633 | " +$filesize; " \ | |
634 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
635 | " $filesize\0" \ | |
79f516bc | 636 | "fdtaddr=780000\0" \ |
261c07bc | 637 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
96b8a054 SW |
638 | "console=ttyS0\0" \ |
639 | "setbootargs=setenv bootargs " \ | |
640 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
53677ef1 | 641 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ |
261c07bc JH |
642 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ |
643 | "$netdev:off " \ | |
96b8a054 SW |
644 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
645 | ||
646 | #define CONFIG_NFSBOOTCOMMAND \ | |
647 | "setenv rootdev /dev/nfs;" \ | |
53677ef1 WD |
648 | "run setbootargs;" \ |
649 | "run setipargs;" \ | |
96b8a054 SW |
650 | "tftp $loadaddr $bootfile;" \ |
651 | "tftp $fdtaddr $fdtfile;" \ | |
652 | "bootm $loadaddr - $fdtaddr" | |
653 | ||
654 | #define CONFIG_RAMBOOTCOMMAND \ | |
655 | "setenv rootdev /dev/ram;" \ | |
656 | "run setbootargs;" \ | |
657 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
658 | "tftp $loadaddr $bootfile;" \ | |
659 | "tftp $fdtaddr $fdtfile;" \ | |
660 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
661 | ||
96b8a054 | 662 | #endif /* __CONFIG_H */ |