[people/ms/u-boot.git] / include / configs / MPC8568MDS.h

/*
 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8568mds board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568		1	/* MPC8568 specific */
#define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */

#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCI1		1	/* PCI controller */
#define CONFIG_PCIE1		1	/* PCIE controller */
#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_QE			/* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
#define CONFIG_BTB				/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1


#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */

#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */
#define CONFIG_SYS_BCSR_BASE		0xf8000000

#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */

/*Chip select 0 - Flash*/
#define CONFIG_SYS_BR0_PRELIM		0xfe001001
#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7

/*Chip slelect 1 - BCSR*/
#define CONFIG_SYS_BR1_PRELIM		0xf8000801
#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7

/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO


/*
 * SDRAM on the LocalBus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */


/*Chip select 2 - SDRAM*/
#define CONFIG_SYS_BR2_PRELIM      0xf0001861
#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The bcsr registers are connected to CS3 on MDS.
 * The new memory map places bcsr at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */
#define CONFIG_SYS_BCSR (0xf8000000)

/*Chip slelect 4 - PIB*/
#define CONFIG_SYS_BR4_PRELIM   0xf8008801
#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7

/*Chip select 5 - PIB*/
#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser*/
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES        {{0,0x69}}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

/*
 * General PCI
 * Memory Addresses are mapped 1-1. I/O is mapped from 0
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_PCIE1_NAME		"Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_QE
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME         "UEC0"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS

#ifdef CONFIG_eTSEC_MDIO_BUS
#define CONFIG_MIIM_ADDRESS	0xE0024520
#endif

#define CONFIG_UEC_ETH1         /* GETH1 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR       7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif

#define CONFIG_UEC_ETH2         /* GETH2 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR       1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
#endif /* CONFIG_QE */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  "/nfsroot"
#define CONFIG_BOOTFILE  your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"						\
   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs\0"			\
   "ramargs=setenv bootargs root=/dev/ram rw "				\
      "console=$consoledev,$baudrate $othbootargs\0"			\


#define CONFIG_NFSBOOTCOMMAND	                                        \
   "run nfsargs;"							\
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"


#define CONFIG_RAMBOOTCOMMAND \
   "run ramargs;"							\
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
67431059	1	/*
5f7bbd13	2	* Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
67431059 AF	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* mpc8568mds board configuration file
	25	*/
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/* High Level Configuration Options */
	30	#define CONFIG_BOOKE 1 /* BOOKE */
da9d4610	31	#define CONFIG_E500 1 /* BOOKE e500 family */
67431059 AF	32	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
	33	#define CONFIG_MPC8568 1 /* MPC8568 specific */
	34	#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
	35
2ae18241 WD	36	#define CONFIG_SYS_TEXT_BASE 0xfff80000
2ae18241 WD	37
5f7bbd13 KG	38	#define CONFIG_SYS_SRIO
	39	#define CONFIG_SRIO1 /* SRIO port 1 */
	40
1563f56e HW	41	#define CONFIG_PCI 1 /* Enable PCI/PCIE */
	42	#define CONFIG_PCI1 1 /* PCI controller */
	43	#define CONFIG_PCIE1 1 /* PCIE controller */
	44	#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
8ff3de61	45	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac	46	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	47	#define CONFIG_TSEC_ENET /* tsec ethernet support */
b96c83d4	48	#define CONFIG_QE /* Enable QE */
67431059	49	#define CONFIG_ENV_OVERWRITE
4d3521cc	50	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
67431059	51
67431059 AF	52	#ifndef __ASSEMBLY__
	53	extern unsigned long get_clock_freq(void);
	54	#endif /Replace a call to get_clock_freq (after it is implemented)/
	55	#define CONFIG_SYS_CLK_FREQ 66000000 /TODO: restore if wanting to read from BCSR: get_clock_freq()/ /* sysclk for MPC85xx */
	56
	57	/*
	58	* These can be toggled for performance analysis, otherwise use default.
	59	*/
53677ef1	60	#define CONFIG_L2_CACHE /* toggle L2 cache */
7a1ac419	61	#define CONFIG_BTB /* toggle branch predition */
67431059 AF	62
	63	/*
	64	* Only possible on E500 Version 2 or newer cores.
	65	*/
	66	#define CONFIG_ENABLE_36BIT_PHYS 1
	67
	68
	69	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	70
6d0f6bcf JCPV	71	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	72	#define CONFIG_SYS_MEMTEST_END 0x00400000
67431059	73
e46fedfe TT	74	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	75	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
67431059	76
e6f5b35b JL	77	/* DDR Setup */
	78	#define CONFIG_FSL_DDR2
	79	#undef CONFIG_FSL_DDR_INTERACTIVE
	80	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	81	#define CONFIG_DDR_SPD
9b0ad1b1	82	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
e6f5b35b JL	83
	84	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	85
6d0f6bcf JCPV	86	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	87	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67431059	88
e6f5b35b JL	89	#define CONFIG_NUM_DDR_CONTROLLERS 1
	90	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	91	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
67431059	92
e6f5b35b JL	93	/* I2C addresses of SPD EEPROMs */
	94	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	95
	96	/* Make sure required options are set */
67431059 AF	97	#ifndef CONFIG_SPD_EEPROM
	98	#error ("CONFIG_SPD_EEPROM is required")
	99	#endif
	100
	101	#undef CONFIG_CLOCKS_IN_MHZ
	102
67431059 AF	103	/*
	104	* Local Bus Definitions
	105	*/
	106
	107	/*
	108	* FLASH on the Local Bus
	109	* Two banks, 8M each, using the CFI driver.
	110	* Boot from BR0/OR0 bank at 0xff00_0000
	111	* Alternate BR1/OR1 bank at 0xff80_0000
	112	*
	113	* BR0, BR1:
	114	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	115	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	116	* Port Size = 16 bits = BRx[19:20] = 10
	117	* Use GPCM = BRx[24:26] = 000
	118	* Valid = BRx[31] = 1
	119	*
	120	* 0 4 8 12 16 20 24 28
	121	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	122	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	123	*
	124	* OR0, OR1:
	125	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	126	* Reserved ORx[17:18] = 11, confusion here?
	127	* CSNT = ORx[20] = 1
	128	* ACS = half cycle delay = ORx[21:22] = 11
	129	* SCY = 6 = ORx[24:27] = 0110
	130	* TRLX = use relaxed timing = ORx[29] = 1
	131	* EAD = use external address latch delay = OR[31] = 1
	132	*
	133	* 0 4 8 12 16 20 24 28
	134	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	135	*/
6d0f6bcf	136	#define CONFIG_SYS_BCSR_BASE 0xf8000000
67431059	137
6d0f6bcf	138	#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
67431059 AF	139
67431059 AF	140	/Chip select 0 - Flash/
6d0f6bcf JCPV	141	#define CONFIG_SYS_BR0_PRELIM 0xfe001001
6d0f6bcf JCPV	142	#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
67431059 AF	143
67431059 AF	144	/Chip slelect 1 - BCSR/
6d0f6bcf JCPV	145	#define CONFIG_SYS_BR1_PRELIM 0xf8000801
6d0f6bcf JCPV	146	#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
67431059	147
6d0f6bcf JCPV	148	/#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} /
	149	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	150	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	151	#undef CONFIG_SYS_FLASH_CHECKSUM
	152	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	153	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
67431059	154
14d0a02a	155	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
67431059	156
00b1883a	157	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	158	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_EMPTY_INFO
67431059 AF	160
	161
	162	/*
	163	* SDRAM on the LocalBus
	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	166	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
67431059 AF	167
	168
	169	/Chip select 2 - SDRAM/
6d0f6bcf JCPV	170	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
6d0f6bcf JCPV	171	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
67431059	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	174	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	175	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	176	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
67431059	177
67431059 AF	178	/*
	179	* Common settings for all Local Bus SDRAM commands.
	180	* At run time, either BSMA1516 (for CPU 1.1)
	181	* or BSMA1617 (for CPU 1.0) (old)
	182	* is OR'ed in too.
	183	*/
b0fe93ed KG	184	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	185	\| LSDMR_PRETOACT7 \
	186	\| LSDMR_ACTTORW7 \
	187	\| LSDMR_BL8 \
	188	\| LSDMR_WRC4 \
	189	\| LSDMR_CL3 \
	190	\| LSDMR_RFEN \
67431059 AF	191	)
	192
	193	/*
	194	* The bcsr registers are connected to CS3 on MDS.
	195	* The new memory map places bcsr at 0xf8000000.
	196	*
	197	* For BR3, need:
	198	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	199	* port-size = 8-bits = BR[19:20] = 01
	200	* no parity checking = BR[21:22] = 00
	201	* GPMC for MSEL = BR[24:26] = 000
	202	* Valid = BR[31] = 1
	203	*
	204	* 0 4 8 12 16 20 24 28
	205	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	206	*
	207	* For OR3, need:
	208	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
	209	* disable buffer ctrl OR[19] = 0
	210	* CSNT OR[20] = 1
	211	* ACS OR[21:22] = 11
	212	* XACS OR[23] = 1
	213	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
	214	* SETA OR[28] = 0
	215	* TRLX OR[29] = 1
	216	* EHTR OR[30] = 1
	217	* EAD extra time OR[31] = 1
	218	*
	219	* 0 4 8 12 16 20 24 28
	220	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_BCSR (0xf8000000)
67431059 AF	223
67431059 AF	224	/Chip slelect 4 - PIB/
6d0f6bcf JCPV	225	#define CONFIG_SYS_BR4_PRELIM 0xf8008801
6d0f6bcf JCPV	226	#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
67431059 AF	227
67431059 AF	228	/Chip select 5 - PIB/
6d0f6bcf JCPV	229	#define CONFIG_SYS_BR5_PRELIM 0xf8010801
6d0f6bcf JCPV	230	#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
67431059	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	233	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	234	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
67431059	235
25ddd1fb	236	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	237	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
67431059	238
6d0f6bcf JCPV	239	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	240	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
67431059 AF	241
	242	/* Serial Port */
	243	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	244	#define CONFIG_SYS_NS16550
	245	#define CONFIG_SYS_NS16550_SERIAL
	246	#define CONFIG_SYS_NS16550_REG_SIZE 1
	247	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
67431059	248
6d0f6bcf	249	#define CONFIG_SYS_BAUDRATE_TABLE \
67431059 AF	250	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
67431059 AF	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	253	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
67431059 AF	254
67431059 AF	255	/* Use the HUSH parser*/
6d0f6bcf JCPV	256	#define CONFIG_SYS_HUSH_PARSER
	257	#ifdef CONFIG_SYS_HUSH_PARSER
	258	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
67431059 AF	259	#endif
	260
	261	/* pass open firmware flat tree */
c480861b KG	262	#define CONFIG_OF_LIBFDT 1
	263	#define CONFIG_OF_BOARD_SETUP 1
	264	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
67431059 AF	265
	266	/*
	267	* I2C
	268	*/
	269	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	270	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	271	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
c59e4091	272	#define CONFIG_I2C_MULTI_BUS
6d0f6bcf JCPV	273	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	274	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	275	#define CONFIG_SYS_I2C_SLAVE 0x7F
	276	#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
	277	#define CONFIG_SYS_I2C_OFFSET 0x3000
	278	#define CONFIG_SYS_I2C2_OFFSET 0x3100
67431059 AF	279
	280	/*
	281	* General PCI
	282	* Memory Addresses are mapped 1-1. I/O is mapped from 0
	283	*/
5af0fdd8	284	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	285	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	286	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	287	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	288	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	289	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	290	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	291	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
	292
3f6f9d76	293	#define CONFIG_SYS_PCIE1_NAME "Slot"
5af0fdd8	294	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42	295	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	296	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	297	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	298	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
5f91ef6a	299	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	300	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
	301	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
	302
5f7bbd13 KG	303	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
	304	#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
	305	#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
	306	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
67431059	307
da9d4610 AF	308	#ifdef CONFIG_QE
	309	/*
	310	* QE UEC ethernet configuration
	311	*/
	312	#define CONFIG_UEC_ETH
	313	#ifndef CONFIG_TSEC_ENET
78b7a8ef	314	#define CONFIG_ETHPRIME "UEC0"
da9d4610 AF	315	#endif
	316	#define CONFIG_PHY_MODE_NEED_CHANGE
	317	#define CONFIG_eTSEC_MDIO_BUS
	318
	319	#ifdef CONFIG_eTSEC_MDIO_BUS
53677ef1	320	#define CONFIG_MIIM_ADDRESS 0xE0024520
da9d4610 AF	321	#endif
	322
	323	#define CONFIG_UEC_ETH1 /* GETH1 */
	324
	325	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	326	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	327	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
	328	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
	329	#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
	330	#define CONFIG_SYS_UEC1_PHY_ADDR 7
865ff856	331	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	332	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
da9d4610 AF	333	#endif
	334
	335	#define CONFIG_UEC_ETH2 /* GETH2 */
	336
	337	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	338	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	339	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
	340	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
	341	#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
	342	#define CONFIG_SYS_UEC2_PHY_ADDR 1
865ff856	343	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	344	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
da9d4610 AF	345	#endif
	346	#endif /* CONFIG_QE */
	347
f30ad49b HW	348	#if defined(CONFIG_PCI)
f30ad49b HW	349
53677ef1	350	#define CONFIG_PCI_PNP /* do pci plug-and-play */
f30ad49b	351
67431059 AF	352	#undef CONFIG_EEPRO100
	353	#undef CONFIG_TULIP
	354
	355	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	356	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
67431059 AF	357
	358	#endif /* CONFIG_PCI */
	359
da9d4610 AF	360	#if defined(CONFIG_TSEC_ENET)
da9d4610 AF	361
67431059	362	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	363	#define CONFIG_TSEC1 1
	364	#define CONFIG_TSEC1_NAME "eTSEC0"
	365	#define CONFIG_TSEC2 1
	366	#define CONFIG_TSEC2_NAME "eTSEC1"
67431059 AF	367
	368	#define TSEC1_PHY_ADDR 2
	369	#define TSEC2_PHY_ADDR 3
	370
	371	#define TSEC1_PHYIDX 0
	372	#define TSEC2_PHYIDX 0
	373
3a79013e AF	374	#define TSEC1_FLAGS TSEC_GIGABIT
	375	#define TSEC2_FLAGS TSEC_GIGABIT
	376
b96c83d4	377	/* Options are: eTSEC[0-1] */
67431059 AF	378	#define CONFIG_ETHPRIME "eTSEC0"
	379
	380	#endif /* CONFIG_TSEC_ENET */
	381
	382	/*
	383	* Environment
	384	*/
5a1aceb0	385	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	386	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	387	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	388	#define CONFIG_ENV_SIZE 0x2000
67431059 AF	389
67431059 AF	390	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	391	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
67431059	392
2835e518	393
079a136c JL	394	/*
	395	* BOOTP options
	396	*/
	397	#define CONFIG_BOOTP_BOOTFILESIZE
	398	#define CONFIG_BOOTP_BOOTPATH
	399	#define CONFIG_BOOTP_GATEWAY
	400	#define CONFIG_BOOTP_HOSTNAME
	401
	402
2835e518 JL	403	/*
	404	* Command line configuration.
	405	*/
	406	#include <config_cmd_default.h>
	407
	408	#define CONFIG_CMD_PING
	409	#define CONFIG_CMD_I2C
	410	#define CONFIG_CMD_MII
82ac8c97	411	#define CONFIG_CMD_ELF
1c9aa76b KG	412	#define CONFIG_CMD_IRQ
1c9aa76b KG	413	#define CONFIG_CMD_SETEXPR
199e262e	414	#define CONFIG_CMD_REGINFO
2835e518	415
67431059	416	#if defined(CONFIG_PCI)
2835e518	417	#define CONFIG_CMD_PCI
67431059	418	#endif
2835e518	419
67431059 AF	420
	421	#undef CONFIG_WATCHDOG /* watchdog disabled */
	422
	423	/*
	424	* Miscellaneous configurable options
	425	*/
6d0f6bcf	426	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	427	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	428	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf JCPV	429	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
6d0f6bcf JCPV	430	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
2835e518	431	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	432	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
67431059	433	#else
6d0f6bcf	434	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
67431059	435	#endif
6d0f6bcf JCPV	436	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	437	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	438	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	439	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
67431059 AF	440
	441	/*
	442	* For booting Linux, the board info and command line data
a832ac41	443	* have to be in the first 64 MB of memory, since this is
67431059 AF	444	* the maximum mapped by the Linux kernel during initialization.
67431059 AF	445	*/
a832ac41 KG	446	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	447	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
67431059	448
2835e518	449	#if defined(CONFIG_CMD_KGDB)
67431059 AF	450	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	451	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	452	#endif
	453
	454	/*
	455	* Environment Configuration
	456	*/
	457
	458	/* The mac addresses for all ethernet interface */
da9d4610 AF	459	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_UEC_ETH)
da9d4610 AF	460	#define CONFIG_HAS_ETH0
67431059 AF	461	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	462	#define CONFIG_HAS_ETH1
	463	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
	464	#define CONFIG_HAS_ETH2
	465	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
da9d4610 AF	466	#define CONFIG_HAS_ETH3
da9d4610 AF	467	#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
67431059 AF	468	#endif
	469
	470	#define CONFIG_IPADDR 192.168.1.253
	471
	472	#define CONFIG_HOSTNAME unknown
8b3637c6	473	#define CONFIG_ROOTPATH "/nfsroot"
67431059 AF	474	#define CONFIG_BOOTFILE your.uImage
	475
	476	#define CONFIG_SERVERIP 192.168.1.1
	477	#define CONFIG_GATEWAYIP 192.168.1.1
	478	#define CONFIG_NETMASK 255.255.255.0
	479
	480	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	481
	482	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	483	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	484
	485	#define CONFIG_BAUDRATE 115200
	486
	487	#define CONFIG_EXTRA_ENV_SETTINGS \
	488	"netdev=eth0\0" \
	489	"consoledev=ttyS0\0" \
	490	"ramdiskaddr=600000\0" \
	491	"ramdiskfile=your.ramdisk.u-boot\0" \
	492	"fdtaddr=400000\0" \
	493	"fdtfile=your.fdt.dtb\0" \
	494	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	495	"nfsroot=$serverip:$rootpath " \
	496	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	497	"console=$consoledev,$baudrate $othbootargs\0" \
	498	"ramargs=setenv bootargs root=/dev/ram rw " \
	499	"console=$consoledev,$baudrate $othbootargs\0" \
	500
	501
	502	#define CONFIG_NFSBOOTCOMMAND \
	503	"run nfsargs;" \
	504	"tftp $loadaddr $bootfile;" \
	505	"tftp $fdtaddr $fdtfile;" \
	506	"bootm $loadaddr - $fdtaddr"
	507
	508
	509	#define CONFIG_RAMBOOTCOMMAND \
	510	"run ramargs;" \
	511	"tftp $ramdiskaddr $ramdiskfile;" \
	512	"tftp $loadaddr $bootfile;" \
	513	"bootm $loadaddr $ramdiskaddr"
	514
	515	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	516
	517	#endif /* __CONFIG_H */