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129ba616 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
129ba616 KG |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8572ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
509c4c4c KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_36BIT |
f9edcc10 KG |
33 | #define CONFIG_PHYS_64BIT |
34 | #endif | |
35 | ||
cb14e93b KG |
36 | #ifdef CONFIG_NAND |
37 | #define CONFIG_NAND_U_BOOT | |
38 | #define CONFIG_RAMBOOT_NAND | |
39 | #ifdef CONFIG_NAND_SPL | |
40 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
41 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
42 | #else | |
00203c64 | 43 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds |
cb14e93b KG |
44 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
45 | #endif /* CONFIG_NAND_SPL */ | |
46 | #endif | |
47 | ||
48 | #ifndef CONFIG_SYS_TEXT_BASE | |
49 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
50 | #endif | |
51 | ||
7a577fda KG |
52 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
53 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
54 | #endif | |
55 | ||
cb14e93b KG |
56 | #ifndef CONFIG_SYS_MONITOR_BASE |
57 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
58 | #endif | |
59 | ||
129ba616 KG |
60 | /* High Level Configuration Options */ |
61 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
62 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
63 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
64 | #define CONFIG_MPC8572 1 | |
65 | #define CONFIG_MPC8572DS 1 | |
66 | #define CONFIG_MP 1 /* support multiple processors */ | |
129ba616 | 67 | |
c51fc5d5 | 68 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
129ba616 KG |
69 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
70 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
71 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
72 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
73 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
74 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
0151cbac | 75 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
129ba616 KG |
76 | |
77 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
78 | ||
79 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
80 | #define CONFIG_ENV_OVERWRITE | |
81 | ||
509c4c4c KG |
82 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
83 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
4ca06607 | 84 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
129ba616 KG |
85 | |
86 | /* | |
87 | * These can be toggled for performance analysis, otherwise use default. | |
88 | */ | |
89 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
90 | #define CONFIG_BTB /* toggle branch predition */ | |
129ba616 KG |
91 | |
92 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
93 | ||
18af1c5f KG |
94 | #ifdef CONFIG_PHYS_64BIT |
95 | #define CONFIG_ADDR_MAP 1 | |
96 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
97 | #endif | |
98 | ||
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
100 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
129ba616 KG |
101 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
102 | ||
cb14e93b KG |
103 | /* |
104 | * Config the L2 Cache as L2 SRAM | |
105 | */ | |
106 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
107 | #ifdef CONFIG_PHYS_64BIT | |
108 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
109 | #else | |
110 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
111 | #endif | |
112 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
113 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
114 | ||
e46fedfe TT |
115 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
116 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
129ba616 | 117 | |
8d22ddca | 118 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 119 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
cb14e93b KG |
120 | #endif |
121 | ||
129ba616 | 122 | /* DDR Setup */ |
f8523cb0 | 123 | #define CONFIG_VERY_BIG_RAM |
129ba616 KG |
124 | #define CONFIG_FSL_DDR2 |
125 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
126 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
127 | #define CONFIG_DDR_SPD | |
129ba616 | 128 | |
d34897d3 | 129 | #define CONFIG_DDR_ECC |
9b0ad1b1 | 130 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
129ba616 KG |
131 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
132 | ||
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
134 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
129ba616 KG |
135 | |
136 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
137 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
138 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
139 | ||
140 | /* I2C addresses of SPD EEPROMs */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
129ba616 KG |
142 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
143 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
144 | ||
145 | /* These are used when DDR doesn't use SPD. */ | |
dc889e86 DL |
146 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
147 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
148 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
149 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
150 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
151 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
152 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
153 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
6d0f6bcf | 154 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
dc889e86 | 155 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
6d0f6bcf | 156 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
dc889e86 DL |
157 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
158 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
6d0f6bcf | 159 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
dc889e86 DL |
160 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
161 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
6d0f6bcf JCPV |
162 | |
163 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
164 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
165 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
129ba616 | 166 | |
129ba616 KG |
167 | /* |
168 | * Make sure required options are set | |
169 | */ | |
170 | #ifndef CONFIG_SPD_EEPROM | |
171 | #error ("CONFIG_SPD_EEPROM is required") | |
172 | #endif | |
173 | ||
174 | #undef CONFIG_CLOCKS_IN_MHZ | |
175 | ||
176 | /* | |
177 | * Memory map | |
178 | * | |
179 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
180 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
181 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
182 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
183 | * | |
184 | * Localbus cacheable (TBD) | |
185 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
186 | * | |
187 | * Localbus non-cacheable | |
188 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
189 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
3cbd8231 | 190 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
129ba616 KG |
191 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
192 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
193 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
194 | */ | |
195 | ||
196 | /* | |
197 | * Local Bus Definitions | |
198 | */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
18af1c5f KG |
200 | #ifdef CONFIG_PHYS_64BIT |
201 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
202 | #else | |
c953ddfd | 203 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
18af1c5f | 204 | #endif |
129ba616 | 205 | |
cb14e93b KG |
206 | |
207 | #define CONFIG_FLASH_BR_PRELIM \ | |
7ee41107 | 208 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
cb14e93b | 209 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
129ba616 | 210 | |
c953ddfd KG |
211 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
212 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
129ba616 | 213 | |
18af1c5f | 214 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_QUIET_TEST |
129ba616 KG |
216 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
217 | ||
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
219 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
220 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
129ba616 | 223 | |
cb14e93b KG |
224 | #if defined(CONFIG_RAMBOOT_NAND) |
225 | #define CONFIG_SYS_RAMBOOT | |
226 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
227 | #else | |
228 | #undef CONFIG_SYS_RAMBOOT | |
229 | #endif | |
129ba616 KG |
230 | |
231 | #define CONFIG_FLASH_CFI_DRIVER | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_FLASH_CFI |
233 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
234 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
129ba616 KG |
235 | |
236 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
237 | ||
558710b9 | 238 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
129ba616 KG |
239 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
240 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
18af1c5f KG |
241 | #ifdef CONFIG_PHYS_64BIT |
242 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
243 | #else | |
52b565f5 | 244 | #define PIXIS_BASE_PHYS PIXIS_BASE |
18af1c5f | 245 | #endif |
129ba616 | 246 | |
52b565f5 | 247 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
6d0f6bcf | 248 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
129ba616 KG |
249 | |
250 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
251 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
252 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
253 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
254 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
255 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
256 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
257 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
258 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
259 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
260 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
261 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
262 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
263 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
264 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
265 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
266 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
267 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ | |
268 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ | |
269 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ | |
129ba616 KG |
270 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
271 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
272 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
273 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
274 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
275 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
276 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
277 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
278 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
279 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
280 | #define PIXIS_LED 0x25 /* LED Register */ | |
281 | ||
cb14e93b KG |
282 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
283 | ||
129ba616 KG |
284 | /* old pixis referenced names */ |
285 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
286 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 287 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
7e183cad LY |
288 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
289 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
290 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
291 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
292 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
293 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
294 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
295 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
296 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
297 | | PIXIS_VSPEED2_TSEC2SER \ | |
298 | | PIXIS_VSPEED2_TSEC3SER \ | |
299 | | PIXIS_VSPEED2_TSEC4SER) | |
300 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
301 | | PIXIS_VCFGEN1_TSEC2SER \ | |
302 | | PIXIS_VCFGEN1_TSEC3SER \ | |
303 | | PIXIS_VCFGEN1_TSEC4SER) | |
129ba616 | 304 | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
306 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 307 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
129ba616 | 308 | |
25ddd1fb | 309 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 310 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
129ba616 | 311 | |
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
313 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
129ba616 | 314 | |
cb14e93b | 315 | #ifndef CONFIG_NAND_SPL |
c013b749 | 316 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
18af1c5f KG |
317 | #ifdef CONFIG_PHYS_64BIT |
318 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
319 | #else | |
c013b749 | 320 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
18af1c5f | 321 | #endif |
cb14e93b KG |
322 | #else |
323 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
324 | #ifdef CONFIG_PHYS_64BIT | |
325 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
326 | #else | |
327 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
328 | #endif | |
329 | #endif | |
330 | ||
c013b749 HW |
331 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
332 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
333 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
334 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
335 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
c013b749 | 336 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
3cbd8231 WD |
337 | #define CONFIG_CMD_NAND 1 |
338 | #define CONFIG_NAND_FSL_ELBC 1 | |
c013b749 HW |
339 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
340 | ||
cb14e93b KG |
341 | /* NAND boot: 4K NAND loader config */ |
342 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
343 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
344 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
345 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
346 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
347 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
348 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
349 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
350 | ||
351 | ||
c013b749 | 352 | /* NAND flash config */ |
a3055c58 | 353 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
3cbd8231 WD |
354 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
355 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
356 | | BR_MS_FCM /* MSEL = FCM */ \ | |
357 | | BR_V) /* valid */ | |
a3055c58 | 358 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
3cbd8231 WD |
359 | | OR_FCM_PGS /* Large Page*/ \ |
360 | | OR_FCM_CSCT \ | |
361 | | OR_FCM_CST \ | |
362 | | OR_FCM_CHT \ | |
363 | | OR_FCM_SCY_1 \ | |
364 | | OR_FCM_TRLX \ | |
365 | | OR_FCM_EHTR) | |
c013b749 | 366 | |
cb14e93b | 367 | #ifdef CONFIG_RAMBOOT_NAND |
a3055c58 MM |
368 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
369 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
cb14e93b KG |
370 | #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
371 | #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
372 | #else | |
373 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
374 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
375 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
376 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
cb14e93b | 377 | #endif |
7ee41107 | 378 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
3cbd8231 WD |
379 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
380 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
381 | | BR_MS_FCM /* MSEL = FCM */ \ | |
382 | | BR_V) /* valid */ | |
a3055c58 | 383 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
7ee41107 | 384 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
3cbd8231 WD |
385 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
386 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
387 | | BR_MS_FCM /* MSEL = FCM */ \ | |
388 | | BR_V) /* valid */ | |
a3055c58 | 389 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c013b749 | 390 | |
7ee41107 | 391 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ |
3cbd8231 WD |
392 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
393 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
394 | | BR_MS_FCM /* MSEL = FCM */ \ | |
395 | | BR_V) /* valid */ | |
a3055c58 | 396 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c013b749 HW |
397 | |
398 | ||
129ba616 KG |
399 | /* Serial Port - controlled on board with jumper J8 |
400 | * open - index 2 | |
401 | * shorted - index 1 | |
402 | */ | |
403 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_NS16550 |
405 | #define CONFIG_SYS_NS16550_SERIAL | |
406 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
407 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
cb14e93b KG |
408 | #ifdef CONFIG_NAND_SPL |
409 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
410 | #endif | |
129ba616 | 411 | |
6d0f6bcf | 412 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
129ba616 KG |
413 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
414 | ||
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
416 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
129ba616 KG |
417 | |
418 | /* Use the HUSH parser */ | |
6d0f6bcf | 419 | #define CONFIG_SYS_HUSH_PARSER |
129ba616 KG |
420 | |
421 | /* | |
422 | * Pass open firmware flat tree | |
423 | */ | |
424 | #define CONFIG_OF_LIBFDT 1 | |
425 | #define CONFIG_OF_BOARD_SETUP 1 | |
426 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
427 | ||
129ba616 KG |
428 | /* new uImage format support */ |
429 | #define CONFIG_FIT 1 | |
430 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
431 | ||
432 | /* I2C */ | |
433 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
434 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
435 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
1f3ba317 | 436 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf JCPV |
437 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
438 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
439 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
440 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
441 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
442 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
129ba616 | 443 | |
445a7b38 HW |
444 | /* |
445 | * I2C2 EEPROM | |
446 | */ | |
447 | #define CONFIG_ID_EEPROM | |
448 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 449 | #define CONFIG_SYS_I2C_EEPROM_NXID |
445a7b38 | 450 | #endif |
6d0f6bcf JCPV |
451 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
452 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
453 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
445a7b38 | 454 | |
129ba616 KG |
455 | /* |
456 | * General PCI | |
457 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
458 | */ | |
459 | ||
129ba616 | 460 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
18ea5551 | 461 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
5af0fdd8 | 462 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
18af1c5f | 463 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 464 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
18af1c5f KG |
465 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
466 | #else | |
ad97dce1 | 467 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
5af0fdd8 | 468 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
18af1c5f | 469 | #endif |
6d0f6bcf | 470 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 471 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
5f91ef6a | 472 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
18af1c5f KG |
473 | #ifdef CONFIG_PHYS_64BIT |
474 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
475 | #else | |
6d0f6bcf | 476 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
18af1c5f | 477 | #endif |
6d0f6bcf | 478 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
479 | |
480 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
18ea5551 | 481 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
5af0fdd8 | 482 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
18af1c5f | 483 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 484 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
18af1c5f KG |
485 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
486 | #else | |
ad97dce1 | 487 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
5af0fdd8 | 488 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
18af1c5f | 489 | #endif |
6d0f6bcf | 490 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 491 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
5f91ef6a | 492 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
18af1c5f KG |
493 | #ifdef CONFIG_PHYS_64BIT |
494 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
495 | #else | |
6d0f6bcf | 496 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
18af1c5f | 497 | #endif |
6d0f6bcf | 498 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
499 | |
500 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
18ea5551 | 501 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
5af0fdd8 | 502 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
18af1c5f | 503 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 504 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
18af1c5f KG |
505 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
506 | #else | |
ad97dce1 | 507 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
5af0fdd8 | 508 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
18af1c5f | 509 | #endif |
6d0f6bcf | 510 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 511 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
5f91ef6a | 512 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
18af1c5f KG |
513 | #ifdef CONFIG_PHYS_64BIT |
514 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
515 | #else | |
6d0f6bcf | 516 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
18af1c5f | 517 | #endif |
6d0f6bcf | 518 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
519 | |
520 | #if defined(CONFIG_PCI) | |
521 | ||
522 | /*PCIE video card used*/ | |
aca5f018 | 523 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
129ba616 KG |
524 | |
525 | /* video */ | |
526 | #define CONFIG_VIDEO | |
527 | ||
528 | #if defined(CONFIG_VIDEO) | |
529 | #define CONFIG_BIOSEMU | |
530 | #define CONFIG_CFB_CONSOLE | |
531 | #define CONFIG_VIDEO_SW_CURSOR | |
532 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
533 | #define CONFIG_ATI_RADEON_FB | |
534 | #define CONFIG_VIDEO_LOGO | |
535 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
6d0f6bcf | 536 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
129ba616 KG |
537 | #endif |
538 | ||
129ba616 KG |
539 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
540 | ||
541 | #undef CONFIG_EEPRO100 | |
542 | #undef CONFIG_TULIP | |
543 | #undef CONFIG_RTL8139 | |
16855ec1 | 544 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
129ba616 | 545 | |
129ba616 | 546 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
547 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
548 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
129ba616 KG |
549 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
550 | #endif | |
551 | ||
552 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
553 | #define CONFIG_DOS_PARTITION | |
554 | #define CONFIG_SCSI_AHCI | |
555 | ||
556 | #ifdef CONFIG_SCSI_AHCI | |
557 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
558 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
559 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
560 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
561 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
129ba616 KG |
562 | #endif /* SCSI */ |
563 | ||
564 | #endif /* CONFIG_PCI */ | |
565 | ||
566 | ||
567 | #if defined(CONFIG_TSEC_ENET) | |
568 | ||
129ba616 KG |
569 | #define CONFIG_MII 1 /* MII PHY management */ |
570 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
571 | #define CONFIG_TSEC1 1 | |
572 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
573 | #define CONFIG_TSEC2 1 | |
574 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
575 | #define CONFIG_TSEC3 1 | |
576 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
577 | #define CONFIG_TSEC4 1 | |
578 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
579 | ||
7e183cad LY |
580 | #define CONFIG_PIXIS_SGMII_CMD |
581 | #define CONFIG_FSL_SGMII_RISER 1 | |
582 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
583 | ||
584 | #ifdef CONFIG_FSL_SGMII_RISER | |
585 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
586 | #endif | |
587 | ||
129ba616 KG |
588 | #define TSEC1_PHY_ADDR 0 |
589 | #define TSEC2_PHY_ADDR 1 | |
590 | #define TSEC3_PHY_ADDR 2 | |
591 | #define TSEC4_PHY_ADDR 3 | |
592 | ||
593 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
594 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
595 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
596 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
597 | ||
598 | #define TSEC1_PHYIDX 0 | |
599 | #define TSEC2_PHYIDX 0 | |
600 | #define TSEC3_PHYIDX 0 | |
601 | #define TSEC4_PHYIDX 0 | |
602 | ||
603 | #define CONFIG_ETHPRIME "eTSEC1" | |
604 | ||
605 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
606 | #endif /* CONFIG_TSEC_ENET */ | |
607 | ||
608 | /* | |
609 | * Environment | |
610 | */ | |
cb14e93b KG |
611 | |
612 | #if defined(CONFIG_SYS_RAMBOOT) | |
613 | #if defined(CONFIG_RAMBOOT_NAND) | |
614 | #define CONFIG_ENV_IS_IN_NAND 1 | |
615 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
616 | #define CONFIG_ENV_OFFSET ((512 * 1024)\ | |
617 | + CONFIG_SYS_NAND_BLOCK_SIZE) | |
618 | #endif | |
619 | ||
129ba616 | 620 | #else |
cb14e93b KG |
621 | #define CONFIG_ENV_IS_IN_FLASH 1 |
622 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
623 | #define CONFIG_ENV_ADDR 0xfff80000 | |
624 | #else | |
625 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
626 | #endif | |
627 | #define CONFIG_ENV_SIZE 0x2000 | |
628 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
129ba616 | 629 | #endif |
129ba616 KG |
630 | |
631 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 632 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
129ba616 KG |
633 | |
634 | /* | |
635 | * Command line configuration. | |
636 | */ | |
637 | #include <config_cmd_default.h> | |
638 | ||
67f94476 | 639 | #define CONFIG_CMD_ERRATA |
129ba616 KG |
640 | #define CONFIG_CMD_IRQ |
641 | #define CONFIG_CMD_PING | |
642 | #define CONFIG_CMD_I2C | |
643 | #define CONFIG_CMD_MII | |
644 | #define CONFIG_CMD_ELF | |
1c9aa76b | 645 | #define CONFIG_CMD_SETEXPR |
199e262e | 646 | #define CONFIG_CMD_REGINFO |
129ba616 KG |
647 | |
648 | #if defined(CONFIG_PCI) | |
649 | #define CONFIG_CMD_PCI | |
129ba616 KG |
650 | #define CONFIG_CMD_NET |
651 | #define CONFIG_CMD_SCSI | |
652 | #define CONFIG_CMD_EXT2 | |
653 | #endif | |
654 | ||
863a3eac ZC |
655 | /* |
656 | * USB | |
657 | */ | |
658 | #define CONFIG_USB_EHCI | |
659 | ||
660 | #ifdef CONFIG_USB_EHCI | |
661 | #define CONFIG_CMD_USB | |
662 | #define CONFIG_USB_EHCI_PCI | |
663 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
664 | #define CONFIG_USB_STORAGE | |
665 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
666 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 | |
667 | #endif | |
668 | ||
129ba616 KG |
669 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
670 | ||
671 | /* | |
672 | * Miscellaneous configurable options | |
673 | */ | |
6d0f6bcf | 674 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
675 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
676 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
677 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
678 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
129ba616 | 679 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 680 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
129ba616 | 681 | #else |
6d0f6bcf | 682 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
129ba616 | 683 | #endif |
6d0f6bcf JCPV |
684 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
685 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
686 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
687 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
129ba616 KG |
688 | |
689 | /* | |
690 | * For booting Linux, the board info and command line data | |
a832ac41 | 691 | * have to be in the first 64 MB of memory, since this is |
129ba616 KG |
692 | * the maximum mapped by the Linux kernel during initialization. |
693 | */ | |
a832ac41 KG |
694 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
695 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
129ba616 | 696 | |
129ba616 KG |
697 | #if defined(CONFIG_CMD_KGDB) |
698 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
699 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
700 | #endif | |
701 | ||
702 | /* | |
703 | * Environment Configuration | |
704 | */ | |
705 | ||
706 | /* The mac addresses for all ethernet interface */ | |
707 | #if defined(CONFIG_TSEC_ENET) | |
708 | #define CONFIG_HAS_ETH0 | |
709 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
710 | #define CONFIG_HAS_ETH1 | |
711 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
712 | #define CONFIG_HAS_ETH2 | |
713 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
714 | #define CONFIG_HAS_ETH3 | |
715 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
716 | #endif | |
717 | ||
718 | #define CONFIG_IPADDR 192.168.1.254 | |
719 | ||
720 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 721 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 722 | #define CONFIG_BOOTFILE "uImage" |
129ba616 KG |
723 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
724 | ||
725 | #define CONFIG_SERVERIP 192.168.1.1 | |
726 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
727 | #define CONFIG_NETMASK 255.255.255.0 | |
728 | ||
729 | /* default location for tftp and bootm */ | |
730 | #define CONFIG_LOADADDR 1000000 | |
731 | ||
732 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
733 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
734 | ||
735 | #define CONFIG_BAUDRATE 115200 | |
736 | ||
737 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
238e1467 | 738 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ |
5368c55d MV |
739 | "netdev=eth0\0" \ |
740 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
741 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
742 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
743 | " +$filesize; " \ | |
744 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
745 | " +$filesize; " \ | |
746 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
747 | " $filesize; " \ | |
748 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
749 | " +$filesize; " \ | |
750 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
751 | " $filesize\0" \ | |
752 | "consoledev=ttyS0\0" \ | |
753 | "ramdiskaddr=2000000\0" \ | |
754 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
755 | "fdtaddr=c00000\0" \ | |
756 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ | |
757 | "bdev=sda3\0" | |
129ba616 KG |
758 | |
759 | #define CONFIG_HDBOOT \ | |
760 | "setenv bootargs root=/dev/$bdev rw " \ | |
761 | "console=$consoledev,$baudrate $othbootargs;" \ | |
762 | "tftp $loadaddr $bootfile;" \ | |
763 | "tftp $fdtaddr $fdtfile;" \ | |
764 | "bootm $loadaddr - $fdtaddr" | |
765 | ||
766 | #define CONFIG_NFSBOOTCOMMAND \ | |
767 | "setenv bootargs root=/dev/nfs rw " \ | |
768 | "nfsroot=$serverip:$rootpath " \ | |
769 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
770 | "console=$consoledev,$baudrate $othbootargs;" \ | |
771 | "tftp $loadaddr $bootfile;" \ | |
772 | "tftp $fdtaddr $fdtfile;" \ | |
773 | "bootm $loadaddr - $fdtaddr" | |
774 | ||
775 | #define CONFIG_RAMBOOTCOMMAND \ | |
776 | "setenv bootargs root=/dev/ram rw " \ | |
777 | "console=$consoledev,$baudrate $othbootargs;" \ | |
778 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
779 | "tftp $loadaddr $bootfile;" \ | |
780 | "tftp $fdtaddr $fdtfile;" \ | |
781 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
782 | ||
783 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
784 | ||
785 | #endif /* __CONFIG_H */ |