projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d4ca31c4 | 1 | /* |
| 23c5d253 | 2 | * (C) Copyright 2000-2014 |
| d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| d4ca31c4 WD |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * board/config.h - configuration options, board specific | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| 15 | /* | |
| 16 | * High Level Configuration Options | |
| 17 | * (easy to change) | |
| 18 | */ | |
| 19 | ||
| 20 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
| 21 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
| 23c5d253 | 22 | #define CONFIG_DISPLAY_BOARDINFO |
| d4ca31c4 | 23 | |
| 2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 25 | ||
| 66ca92a5 | 26 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
| 6d0f6bcf JCPV |
27 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
| 28 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
| 66ca92a5 | 29 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ |
| c178d3da WD |
30 | /* (it will be used if there is no */ |
| 31 | /* 'cpuclk' variable with valid value) */ | |
| d4ca31c4 | 32 | |
| 6d0f6bcf | 33 | #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ |
| 75d1ea7f WD |
34 | /* (function measure_gclk() */ |
| 35 | /* will be called) */ | |
| 6d0f6bcf JCPV |
36 | #ifdef CONFIG_SYS_MEASURE_CPUCLK |
| 37 | #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
| 75d1ea7f WD |
38 | #endif |
| 39 | ||
| c178d3da | 40 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 3cb7a480 WD |
41 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
| 42 | #define CONFIG_SYS_MAXIDLE 10 | |
| d4ca31c4 WD |
43 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
| 44 | ||
| c178d3da | 45 | #define CONFIG_BOOTCOUNT_LIMIT |
| d4ca31c4 WD |
46 | |
| 47 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 48 | ||
| 49 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
| 50 | ||
| c178d3da | 51 | #define CONFIG_PREBOOT "echo;" \ |
| 32bf3d14 | 52 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| d4ca31c4 WD |
53 | "echo" |
| 54 | ||
| 55 | #undef CONFIG_BOOTARGS | |
| 56 | ||
| c178d3da | 57 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| d4ca31c4 WD |
58 | "netdev=eth0\0" \ |
| 59 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| fe126d8b | 60 | "nfsroot=${serverip}:${rootpath}\0" \ |
| d4ca31c4 | 61 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| fe126d8b WD |
62 | "addip=setenv bootargs ${bootargs} " \ |
| 63 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 64 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| d4ca31c4 | 65 | "flash_nfs=run nfsargs addip;" \ |
| fe126d8b | 66 | "bootm ${kernel_addr}\0" \ |
| d4ca31c4 | 67 | "flash_self=run ramargs addip;" \ |
| fe126d8b WD |
68 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 69 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
| d4ca31c4 | 70 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
| 29f8f58f WD |
71 | "hostname=TQM866M\0" \ |
| 72 | "bootfile=TQM866M/uImage\0" \ | |
| 9ef57bbe MK |
73 | "fdt_addr=400C0000\0" \ |
| 74 | "kernel_addr=40100000\0" \ | |
| eb6da805 | 75 | "ramdisk_addr=40280000\0" \ |
| 29f8f58f | 76 | "u-boot=TQM866M/u-image.bin\0" \ |
| 9ef57bbe | 77 | "load=tftp 200000 ${u-boot}\0" \ |
| 29f8f58f WD |
78 | "update=prot off 40000000 +${filesize};" \ |
| 79 | "era 40000000 +${filesize};" \ | |
| 9ef57bbe | 80 | "cp.b 200000 40000000 ${filesize};" \ |
| 29f8f58f | 81 | "sete filesize;save\0" \ |
| d4ca31c4 WD |
82 | "" |
| 83 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 84 | ||
| 85 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 86 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| d4ca31c4 WD |
87 | |
| 88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 89 | ||
| c178d3da | 90 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| d4ca31c4 WD |
91 | |
| 92 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 93 | ||
| 94 | /* enable I2C and select the hardware/software driver */ | |
| ea818dbb HS |
95 | #define CONFIG_SYS_I2C |
| 96 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
| 97 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
| 98 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
| d4ca31c4 | 99 | |
| d4ca31c4 WD |
100 | /* |
| 101 | * Software (bit-bang) I2C driver configuration | |
| 102 | */ | |
| 103 | #define PB_SCL 0x00000020 /* PB 26 */ | |
| 104 | #define PB_SDA 0x00000010 /* PB 27 */ | |
| 105 | ||
| 106 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
| 107 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
| 108 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
| 109 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
| 110 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
| c178d3da | 111 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
| d4ca31c4 | 112 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
| c178d3da | 113 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
| d4ca31c4 | 114 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
| d4ca31c4 | 115 | |
| 6d0f6bcf JCPV |
116 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ |
| 117 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
| 118 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
| 119 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| d4ca31c4 | 120 | |
| 37d4bb70 JL |
121 | /* |
| 122 | * BOOTP options | |
| 123 | */ | |
| 124 | #define CONFIG_BOOTP_SUBNETMASK | |
| 125 | #define CONFIG_BOOTP_GATEWAY | |
| 126 | #define CONFIG_BOOTP_HOSTNAME | |
| 127 | #define CONFIG_BOOTP_BOOTPATH | |
| 128 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 129 | ||
| d4ca31c4 WD |
130 | |
| 131 | #define CONFIG_MAC_PARTITION | |
| 132 | #define CONFIG_DOS_PARTITION | |
| 133 | ||
| a6cccaea WD |
134 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
| 135 | ||
| 136 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
| d4ca31c4 | 137 | |
| d4ca31c4 | 138 | |
| 2694690e JL |
139 | /* |
| 140 | * Command line configuration. | |
| 141 | */ | |
| 2694690e JL |
142 | #define CONFIG_CMD_ASKENV |
| 143 | #define CONFIG_CMD_DHCP | |
| 144 | #define CONFIG_CMD_EEPROM | |
| 9a63b7f4 | 145 | #define CONFIG_CMD_EXT2 |
| 2694690e | 146 | #define CONFIG_CMD_IDE |
| 29f8f58f | 147 | #define CONFIG_CMD_JFFS2 |
| 29f8f58f WD |
148 | #define CONFIG_CMD_SNTP |
| 149 | ||
| 150 | ||
| 151 | #define CONFIG_NETCONSOLE | |
| 2694690e | 152 | |
| d4ca31c4 WD |
153 | |
| 154 | /* | |
| 155 | * Miscellaneous configurable options | |
| 156 | */ | |
| 6d0f6bcf | 157 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| d4ca31c4 | 158 | |
| 2751a95a | 159 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| d4ca31c4 | 160 | |
| 2694690e | 161 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 162 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| d4ca31c4 | 163 | #else |
| 6d0f6bcf | 164 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| d4ca31c4 | 165 | #endif |
| 6d0f6bcf JCPV |
166 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 167 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| d4ca31c4 | 169 | |
| 6d0f6bcf JCPV |
170 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 171 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| d4ca31c4 | 172 | |
| 6d0f6bcf | 173 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| d4ca31c4 | 174 | |
| d4ca31c4 WD |
175 | /* |
| 176 | * Low Level Configuration Settings | |
| 177 | * (address mappings, register initial values, etc.) | |
| 178 | * You should know what you are doing if you make changes here. | |
| 179 | */ | |
| 180 | /*----------------------------------------------------------------------- | |
| 181 | * Internal Memory Mapped Register | |
| 182 | */ | |
| 6d0f6bcf | 183 | #define CONFIG_SYS_IMMR 0xFFF00000 |
| d4ca31c4 WD |
184 | |
| 185 | /*----------------------------------------------------------------------- | |
| 186 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 187 | */ | |
| 6d0f6bcf | 188 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 553f0982 | 189 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
| 25ddd1fb | 190 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 191 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| d4ca31c4 WD |
192 | |
| 193 | /*----------------------------------------------------------------------- | |
| 194 | * Start addresses for the final memory configuration | |
| 195 | * (Set up by the startup code) | |
| 6d0f6bcf | 196 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| d4ca31c4 | 197 | */ |
| 6d0f6bcf JCPV |
198 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 199 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| 200 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 201 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| 202 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
| d4ca31c4 WD |
203 | |
| 204 | /* | |
| 205 | * For booting Linux, the board info and command line data | |
| 206 | * have to be in the first 8 MB of memory, since this is | |
| 207 | * the maximum mapped by the Linux kernel during initialization. | |
| 208 | */ | |
| 6d0f6bcf | 209 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| d4ca31c4 WD |
210 | |
| 211 | /*----------------------------------------------------------------------- | |
| 212 | * FLASH organization | |
| 213 | */ | |
| e318d9e9 | 214 | /* use CFI flash driver */ |
| 6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 00b1883a | 216 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
| 6d0f6bcf JCPV |
217 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 218 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 219 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
| 220 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 221 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
| d4ca31c4 | 222 | |
| 5a1aceb0 | 223 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 JCPV |
224 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
| 225 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
| 226 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
| d4ca31c4 WD |
227 | |
| 228 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
229 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
| 230 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| d4ca31c4 | 231 | |
| 6d0f6bcf | 232 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
| 67c31036 | 233 | |
| 7c803be2 WD |
234 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
| 235 | ||
| 29f8f58f WD |
236 | /*----------------------------------------------------------------------- |
| 237 | * Dynamic MTD partition support | |
| 238 | */ | |
| 68d7d651 | 239 | #define CONFIG_CMD_MTDPARTS |
| 942556a9 SR |
240 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 241 | #define CONFIG_FLASH_CFI_MTD | |
| 29f8f58f WD |
242 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
| 243 | ||
| 244 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
| 245 | "128k(dtb)," \ | |
| 246 | "1920k(kernel)," \ | |
| 247 | "5632(rootfs)," \ | |
| cd82919e | 248 | "4m(data)" |
| 29f8f58f | 249 | |
| d4ca31c4 WD |
250 | /*----------------------------------------------------------------------- |
| 251 | * Hardware Information Block | |
| 252 | */ | |
| 6d0f6bcf JCPV |
253 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 254 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 255 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| d4ca31c4 WD |
256 | |
| 257 | /*----------------------------------------------------------------------- | |
| 258 | * Cache Configuration | |
| 259 | */ | |
| 6d0f6bcf | 260 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| 2694690e | 261 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 262 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| d4ca31c4 WD |
263 | #endif |
| 264 | ||
| 265 | /*----------------------------------------------------------------------- | |
| 266 | * SYPCR - System Protection Control 11-9 | |
| 267 | * SYPCR can only be written once after reset! | |
| 268 | *----------------------------------------------------------------------- | |
| 269 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 270 | */ | |
| 271 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 272 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| d4ca31c4 WD |
273 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 274 | #else | |
| 6d0f6bcf | 275 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| d4ca31c4 WD |
276 | #endif |
| 277 | ||
| 278 | /*----------------------------------------------------------------------- | |
| 279 | * SIUMCR - SIU Module Configuration 11-6 | |
| 280 | *----------------------------------------------------------------------- | |
| 281 | * PCMCIA config., multi-function pin tri-state | |
| 282 | */ | |
| c178d3da | 283 | #ifndef CONFIG_CAN_DRIVER |
| 6d0f6bcf | 284 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| d4ca31c4 | 285 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 6d0f6bcf | 286 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| d4ca31c4 WD |
287 | #endif /* CONFIG_CAN_DRIVER */ |
| 288 | ||
| 289 | /*----------------------------------------------------------------------- | |
| 290 | * TBSCR - Time Base Status and Control 11-26 | |
| 291 | *----------------------------------------------------------------------- | |
| 292 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 293 | */ | |
| 6d0f6bcf | 294 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| d4ca31c4 | 295 | |
| d4ca31c4 WD |
296 | /*----------------------------------------------------------------------- |
| 297 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 298 | *----------------------------------------------------------------------- | |
| 299 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 300 | */ | |
| 6d0f6bcf | 301 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
| d4ca31c4 | 302 | |
| d4ca31c4 WD |
303 | /*----------------------------------------------------------------------- |
| 304 | * SCCR - System Clock and reset Control Register 15-27 | |
| 305 | *----------------------------------------------------------------------- | |
| 306 | * Set clock output, timebase and RTC source and divider, | |
| 307 | * power management and some other internal clocks | |
| 308 | */ | |
| 309 | #define SCCR_MASK SCCR_EBDF11 | |
| 6d0f6bcf | 310 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| d4ca31c4 WD |
311 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 312 | SCCR_DFALCD00) | |
| d4ca31c4 WD |
313 | |
| 314 | /*----------------------------------------------------------------------- | |
| 315 | * PCMCIA stuff | |
| 316 | *----------------------------------------------------------------------- | |
| 317 | * | |
| 318 | */ | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 320 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 321 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| 322 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 323 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| 324 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 325 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| 326 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| d4ca31c4 WD |
327 | |
| 328 | /*----------------------------------------------------------------------- | |
| 329 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 330 | *----------------------------------------------------------------------- | |
| 331 | */ | |
| 332 | ||
| 8d1165e1 | 333 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
| c178d3da | 334 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| d4ca31c4 | 335 | |
| c178d3da WD |
336 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 337 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| d4ca31c4 WD |
338 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 339 | ||
| 6d0f6bcf JCPV |
340 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 341 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| d4ca31c4 | 342 | |
| 6d0f6bcf | 343 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| d4ca31c4 | 344 | |
| 6d0f6bcf | 345 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
| d4ca31c4 WD |
346 | |
| 347 | /* Offset for data I/O */ | |
| 6d0f6bcf | 348 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| d4ca31c4 WD |
349 | |
| 350 | /* Offset for normal register accesses */ | |
| 6d0f6bcf | 351 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| d4ca31c4 WD |
352 | |
| 353 | /* Offset for alternate registers */ | |
| 6d0f6bcf | 354 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
| d4ca31c4 WD |
355 | |
| 356 | /*----------------------------------------------------------------------- | |
| 357 | * | |
| 358 | *----------------------------------------------------------------------- | |
| 359 | * | |
| 360 | */ | |
| 6d0f6bcf | 361 | #define CONFIG_SYS_DER 0 |
| d4ca31c4 WD |
362 | |
| 363 | /* | |
| 364 | * Init Memory Controller: | |
| 365 | * | |
| 366 | * BR0/1 and OR0/1 (FLASH) | |
| 367 | */ | |
| 368 | ||
| 369 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 370 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
| 371 | ||
| 372 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 373 | * restrict access enough to keep SRAM working (if any) | |
| 374 | * but not too much to meddle with FLASH accesses | |
| 375 | */ | |
| 6d0f6bcf JCPV |
376 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 377 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| d4ca31c4 WD |
378 | |
| 379 | /* | |
| c178d3da | 380 | * FLASH timing: Default value of OR0 after reset |
| d4ca31c4 | 381 | */ |
| 6d0f6bcf | 382 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
| c178d3da | 383 | OR_SCY_15_CLK | OR_TRLX) |
| d4ca31c4 | 384 | |
| 6d0f6bcf JCPV |
385 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 386 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 387 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
| d4ca31c4 | 388 | |
| 6d0f6bcf JCPV |
389 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
| 390 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
| 391 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
| d4ca31c4 WD |
392 | |
| 393 | /* | |
| 394 | * BR2/3 and OR2/3 (SDRAM) | |
| 395 | * | |
| 396 | */ | |
| 397 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 398 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
| c178d3da | 399 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
| d4ca31c4 WD |
400 | |
| 401 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 6d0f6bcf | 402 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
| d4ca31c4 | 403 | |
| 6d0f6bcf JCPV |
404 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
| 405 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| d4ca31c4 | 406 | |
| c178d3da | 407 | #ifndef CONFIG_CAN_DRIVER |
| 6d0f6bcf JCPV |
408 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
| 409 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| d4ca31c4 | 410 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
| 6d0f6bcf JCPV |
411 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
| 412 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
| 413 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
| 414 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
| d4ca31c4 WD |
415 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
| 416 | #endif /* CONFIG_CAN_DRIVER */ | |
| 417 | ||
| c178d3da | 418 | /* |
| c178d3da WD |
419 | * 4096 Rows from SDRAM example configuration |
| 420 | * 1000 factor s -> ms | |
| 421 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 422 | * 4 Number of refresh cycles per period | |
| 423 | * 64 Refresh cycle in ms per number of rows | |
| 424 | */ | |
| 6d0f6bcf | 425 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
| c178d3da | 426 | |
| d4ca31c4 | 427 | /* |
| d43e489b MK |
428 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
| 429 | * | |
| 430 | * CPUclock(MHz) * 31.2 | |
| 6d0f6bcf | 431 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
| d43e489b MK |
432 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
| 433 | * | |
| 6d0f6bcf JCPV |
434 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
| 435 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
| 436 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
| 437 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
| d43e489b MK |
438 | * |
| 439 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
| 440 | * be met also in the default configuration, i.e. if environment variable | |
| 441 | * 'cpuclk' is not set. | |
| d4ca31c4 | 442 | */ |
| 6d0f6bcf | 443 | #define CONFIG_SYS_MAMR_PTA 97 |
| d4ca31c4 WD |
444 | |
| 445 | /* | |
| d43e489b | 446 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
| d4ca31c4 | 447 | */ |
| d43e489b | 448 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
| 6d0f6bcf | 449 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
| d43e489b | 450 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
| 6d0f6bcf | 451 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
| d4ca31c4 WD |
452 | |
| 453 | /* | |
| 454 | * MAMR settings for SDRAM | |
| 455 | */ | |
| 456 | ||
| 457 | /* 8 column SDRAM */ | |
| 6d0f6bcf | 458 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| d4ca31c4 WD |
459 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 460 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 461 | /* 9 column SDRAM */ | |
| 6d0f6bcf | 462 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| d4ca31c4 WD |
463 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 464 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| c178d3da | 465 | /* 10 column SDRAM */ |
| 6d0f6bcf | 466 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| c178d3da WD |
467 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
| 468 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| d4ca31c4 | 469 | |
| d4ca31c4 WD |
470 | #define CONFIG_SCC1_ENET |
| 471 | #define CONFIG_FEC_ENET | |
| 48690d80 | 472 | #define CONFIG_ETHPRIME "SCC" |
| d4ca31c4 | 473 | |
| 7026ead0 HS |
474 | #define CONFIG_HWCONFIG 1 |
| 475 | ||
| d4ca31c4 | 476 | #endif /* __CONFIG_H */ |