[people/ms/u-boot.git] / include / configs / ls2080a_common.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147

#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

/* We need architecture specific misc initializations */

#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */

/* Link Definitions */
#ifndef CONFIG_QSPI_BOOT
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE		0x80400000
#else
#define CONFIG_SYS_TEXT_BASE		0x30100000
#endif
#endif

#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2

/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
/*
 * DDR controller use 0 as the base address for binding.
 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 */
#define CONFIG_SYS_DP_DDR_BASE_PHY	0
#define CONFIG_DP_DDR_CTRL		2
#define CONFIG_DP_DDR_NUM_CTRLS		1
#endif

/* Generic Timer Definitions */
/*
 * This is not an accurate number. It is used in start.S. The frequency
 * will be udpated later when get_bus_freq(0) is available.
 */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */

/* Serial Port */
#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* IFC */
#define CONFIG_FSL_IFC

/*
 * During booting, IFC is mapped at the region of 0x30000000.
 * But this region is limited to 256MB. To accommodate NOR, promjet
 * and FPGA. This region is divided as below:
 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 *
 * To accommodate bigger NOR flash and other devices, we will map IFC
 * chip selects to as below:
 * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
 * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
 * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
 * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
 * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
 *
 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */

#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000

#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define QIXIS_BASE				get_qixis_addr()
#define QIXIS_BASE_PHYS				0x20000000
#define QIXIS_BASE_PHYS_EARLY			0xC000000
#define QIXIS_STAT_PRES1			0xb
#define QIXIS_SDID_MASK				0x07
#define QIXIS_ESDHC_NO_ADAPTER			0x7

#define CONFIG_SYS_NAND_BASE			0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000

/* MC firmware */
#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
/* For LS2085A */
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000

/*
 * Carve out a DDR region which will not be used by u-boot/Linux
 *
 * It will be used by MC and Debug Server. The MC region must be
 * 512MB aligned, so the min size to hide is 512MB.
 */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
#define CONFIG_SYS_MC_RSV_MEM_ALIGN			(512UL * 1024 * 1024)
#endif

/* Command line configuration */
#define CONFIG_CMD_ENV

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_NR_DRAM_BANKS		3

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581200000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyAMA0,38400n8\0"		\
	"mcinitcmd=fsl_mc start mc 0x580300000"	\
	" 0x580800000 \0"

#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0500 " \
				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
				" hugepagesz=2m hugepages=256"
#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
				" cp.b $kernel_start $kernel_load" \
				" $kernel_size && bootm $kernel_load"

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE		0x16000
#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x1800a000

#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_MONITOR_LEN		(640 * 1024)

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#endif /* __LS2_COMMON_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_COMMON_H
	8	#define __LS2_COMMON_H
	9
f749db3a	10	#define CONFIG_REMAKE_ELF
9f3183d2	11	#define CONFIG_FSL_LAYERSCAPE
9f3183d2	12	#define CONFIG_MP
f749db3a	13	#define CONFIG_GICV3
9c66ce66	14	#define CONFIG_FSL_TZPC_BP147
f749db3a	15
44937214	16	#include <asm/arch/ls2080a_stream_id.h>
9f3183d2	17	#include <asm/arch/config.h>
31d34c6c	18
9f3183d2 MH	19	/* Link Definitions */
	20	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	21
422cb08a	22	/* We need architecture specific misc initializations */
422cb08a	23
bcb55f67 AB	24	#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
bcb55f67 AB	25
f749db3a	26	/* Link Definitions */
a646f669	27	#ifndef CONFIG_QSPI_BOOT
b2d5ac59 SW	28	#ifdef CONFIG_SPL
	29	#define CONFIG_SYS_TEXT_BASE 0x80400000
	30	#else
f3f8c564	31	#define CONFIG_SYS_TEXT_BASE 0x30100000
b2d5ac59	32	#endif
a646f669	33	#endif
f749db3a	34
e211c12e	35	#ifdef CONFIG_EMU
f749db3a	36	#define CONFIG_SYS_NO_FLASH
e211c12e	37	#endif
f749db3a YS	38
	39	#define CONFIG_SUPPORT_RAW_INITRD
	40
	41	#define CONFIG_SKIP_LOWLEVEL_INIT
f749db3a	42
b2d5ac59	43	#ifndef CONFIG_SPL
f749db3a	44	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
b2d5ac59	45	#endif
f749db3a	46	#ifndef CONFIG_SYS_FSL_DDR4
f749db3a YS	47	#define CONFIG_SYS_DDR_RAW_TIMING
f749db3a YS	48	#endif
f749db3a YS	49
	50	#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
	51
9f3183d2	52	#define CONFIG_VERY_BIG_RAM
f749db3a YS	53	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	54	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	55	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	56	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
d9c68b14 YS	57	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
d9c68b14 YS	58
8bfa301b YS	59	/*
	60	* SMP Definitinos
	61	*/
	62	#define CPU_RELEASE_ADDR secondary_boot_func
	63
d9c68b14	64	#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
44937214	65	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
d9c68b14 YS	66	#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
	67	/*
	68	* DDR controller use 0 as the base address for binding.
	69	* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
	70	*/
	71	#define CONFIG_SYS_DP_DDR_BASE_PHY 0
	72	#define CONFIG_DP_DDR_CTRL 2
	73	#define CONFIG_DP_DDR_NUM_CTRLS 1
44937214	74	#endif
f749db3a YS	75
f749db3a YS	76	/* Generic Timer Definitions */
207774b2 YS	77	/*
	78	* This is not an accurate number. It is used in start.S. The frequency
	79	* will be udpated later when get_bus_freq(0) is available.
	80	*/
	81	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
f749db3a YS	82
f749db3a YS	83	/* Size of malloc() pool */
aa66acbf	84	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
f749db3a YS	85
f749db3a YS	86	/* I2C */
f749db3a YS	87	#define CONFIG_SYS_I2C
f749db3a YS	88	#define CONFIG_SYS_I2C_MXC
03544c66 AA	89	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	90	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e YS	91	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f8cb101e YS	92	#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
f749db3a YS	93
f749db3a YS	94	/* Serial Port */
7288c2c2	95	#define CONFIG_CONS_INDEX 1
f749db3a YS	96	#define CONFIG_SYS_NS16550_SERIAL
f749db3a YS	97	#define CONFIG_SYS_NS16550_REG_SIZE 1
3564208e	98	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f749db3a YS	99
	100	#define CONFIG_BAUDRATE 115200
	101	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	102
	103	/* IFC */
	104	#define CONFIG_FSL_IFC
f3f8c564	105
f749db3a	106	/*
7288c2c2 YS	107	* During booting, IFC is mapped at the region of 0x30000000.
	108	* But this region is limited to 256MB. To accommodate NOR, promjet
	109	* and FPGA. This region is divided as below:
	110	* 0x30000000 - 0x37ffffff : 128MB : NOR flash
	111	* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
	112	* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
	113	*
	114	* To accommodate bigger NOR flash and other devices, we will map IFC
	115	* chip selects to as below:
	116	* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
	117	* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
	118	* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
	119	* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
	120	* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
	121	*
	122	* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
f749db3a YS	123	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	124	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	125	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	126	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	127	*/
7288c2c2	128
f749db3a YS	129	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	130	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	131	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	132
7288c2c2 YS	133	#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
	134	#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
	135
7288c2c2 YS	136	#ifndef __ASSEMBLY__
	137	unsigned long long get_qixis_addr(void);
	138	#endif
	139	#define QIXIS_BASE get_qixis_addr()
	140	#define QIXIS_BASE_PHYS 0x20000000
	141	#define QIXIS_BASE_PHYS_EARLY 0xC000000
8b06460e YL	142	#define QIXIS_STAT_PRES1 0xb
	143	#define QIXIS_SDID_MASK 0x07
	144	#define QIXIS_ESDHC_NO_ADAPTER 0x7
7288c2c2 YS	145
	146	#define CONFIG_SYS_NAND_BASE 0x530000000ULL
	147	#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
e211c12e	148
f749db3a YS	149	/* MC firmware */
f749db3a YS	150	#define CONFIG_FSL_MC_ENET
f749db3a	151	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
125e2bc1 GR	152	#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
	153	#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
	154	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
	155	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
3c1d218a	156	/* For LS2085A */
c1000c12 GR	157	#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
c1000c12 GR	158	#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
f749db3a	159
5c055089 PK	160	/*
	161	* Carve out a DDR region which will not be used by u-boot/Linux
	162	*
	163	* It will be used by MC and Debug Server. The MC region must be
	164	* 512MB aligned, so the min size to hide is 512MB.
	165	*/
b63a9506	166	#ifdef CONFIG_FSL_MC_ENET
52c11d4f	167	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
c0492141	168	#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
f749db3a YS	169	#endif
	170
	171	/* Command line configuration */
f749db3a	172	#define CONFIG_CMD_ENV
f749db3a YS	173
	174	/* Miscellaneous configurable options */
	175	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
	176
	177	/* Physical Memory Map */
	178	/* fixme: these need to be checked against the board */
	179	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
f749db3a	180
d9c68b14	181	#define CONFIG_NR_DRAM_BANKS 3
f749db3a	182
f749db3a YS	183	#define CONFIG_HWCONFIG
	184	#define HWCONFIG_BUFFER_SIZE 128
	185
1d3a76fa AW	186	/* Allow to overwrite serial and ethaddr */
	187	#define CONFIG_ENV_OVERWRITE
	188
f749db3a YS	189	/* Initial environment variables */
	190	#define CONFIG_EXTRA_ENV_SETTINGS \
	191	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	192	"loadaddr=0x80100000\0" \
	193	"kernel_addr=0x100000\0" \
	194	"ramdisk_addr=0x800000\0" \
	195	"ramdisk_size=0x2000000\0" \
f3f8c564	196	"fdt_high=0xa0000000\0" \
f749db3a YS	197	"initrd_high=0xffffffffffffffff\0" \
f749db3a YS	198	"kernel_start=0x581200000\0" \
052ddd5c	199	"kernel_load=0xa0000000\0" \
97421bd2	200	"kernel_size=0x2800000\0" \
16ed8560 PK	201	"console=ttyAMA0,38400n8\0" \
	202	"mcinitcmd=fsl_mc start mc 0x580300000" \
	203	" 0x580800000 \0"
f749db3a	204
56cd0760	205	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
ed77b704	206	"earlycon=uart8250,mmio,0x21c0500 " \
34cc7546	207	"ramdisk_size=0x2000000 default_hugepagesz=2m" \
9e71bb9c	208	" hugepagesz=2m hugepages=256"
9f3e1b8a PK	209	#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
	210	" cp.b $kernel_start $kernel_load" \
	211	" $kernel_size && bootm $kernel_load"
f749db3a	212
f749db3a YS	213	/* Monitor Command Prompt */
f749db3a YS	214	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f749db3a YS	215	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
f749db3a YS	216	sizeof(CONFIG_SYS_PROMPT) + 16)
f749db3a YS	217	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	218	#define CONFIG_SYS_LONGHELP
	219	#define CONFIG_CMDLINE_EDITING 1
f3f8c564	220	#define CONFIG_AUTO_COMPLETE
f749db3a YS	221	#define CONFIG_SYS_MAXARGS 64 /* max command args */
f749db3a YS	222
f3f8c564 PK	223	#define CONFIG_PANIC_HANG /* do not reset board on panic */
f3f8c564 PK	224
b2d5ac59 SW	225	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
b2d5ac59 SW	226	#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
b2d5ac59	227	#define CONFIG_SPL_FRAMEWORK
b2d5ac59	228	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
b2d5ac59	229	#define CONFIG_SPL_MAX_SIZE 0x16000
b2d5ac59 SW	230	#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
	231	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	232	#define CONFIG_SPL_TEXT_BASE 0x1800a000
	233
	234	#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
	235	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	236	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
	237	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
74cac00c	238	#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
b2d5ac59	239
34cc7546 BS	240	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
34cc7546 BS	241
bcb55f67 AB	242	/* Hash command with SHA acceleration supported in hardware */
	243	#ifdef CONFIG_FSL_CAAM
	244	#define CONFIG_CMD_HASH
	245	#define CONFIG_SHA_HW_ACCEL
	246	#endif
	247
f749db3a	248	#endif /* __LS2_COMMON_H */