[people/ms/u-boot.git] / include / configs / ms7722se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7722
 *
 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7722SE_H
#define __MS7722SE_H

#define CONFIG_CPU_SH7722	1
#define CONFIG_MS7722SE		1

#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_SDRAM

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"

#define CONFIG_VERSION_VARIABLE
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SMC9111 */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE    (0xB8000000)

/* MEMORY */
#define MS7722SE_SDRAM_BASE	(0x8C000000)
#define MS7722SE_FLASH_BASE_1	(0xA0000000)
#define MS7722SE_FLASH_BANK_SIZE	(8*1024 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
#define CONFIG_SYS_BARGSIZE		512		/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF0	1
#undef  CONFIG_SYS_CONSOLE_INFO_QUIET			/* Suppress display of console information at boot */
#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE

#define CONFIG_SYS_MEMTEST_START	(MS7722SE_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

#undef  CONFIG_SYS_ALT_MEMTEST		/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH	/* Scratch address used by the alternate memory test */

#undef  CONFIG_SYS_LOADS_BAUD_CHANGE	/* Enable temporary baudrate change while serial download */

#define CONFIG_SYS_SDRAM_BASE	(MS7722SE_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)	/* maybe more, but if so u-boot doesn't know about it... */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */

#define CONFIG_SYS_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image
							in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)		/* */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO			/* print 'E' for empty sector on flinfo */

#define CONFIG_SYS_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */

#define CONFIG_SYS_MAX_FLASH_SECT	150		/* Max number of sectors on each
							Flash chip */

/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	2
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
				  CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
				}

#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)	/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)	/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)	/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)	/* Timeout for Flash clear lock bit operations (in ms) */

#undef  CONFIG_SYS_FLASH_PROTECTION			/* Use hardware flash sectors protection instead of U-Boot software protection */

#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(8 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#endif	/* __MS7722SE_H */
Commit	Line	Data
6c0bbdcc NI	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7722
	3	*
	4	* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
6c0bbdcc NI	7	*/
	8
	9	#ifndef __MS7722SE_H
	10	#define __MS7722SE_H
	11
6c0bbdcc NI	12	#define CONFIG_CPU_SH7722 1
	13	#define CONFIG_MS7722SE 1
	14
5783758f	15	#define CONFIG_CMD_JFFS2
6c0bbdcc	16	#define CONFIG_CMD_SDRAM
6c0bbdcc NI	17
	18	#define CONFIG_BAUDRATE 115200
	19	#define CONFIG_BOOTDELAY 3
53677ef1	20	#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
6c0bbdcc NI	21
	22	#define CONFIG_VERSION_VARIABLE
	23	#undef CONFIG_SHOW_BOOT_PROGRESS
	24
	25	/* SMC9111 */
7194ab80	26	#define CONFIG_SMC91111
6c0bbdcc NI	27	#define CONFIG_SMC91111_BASE (0xB8000000)
	28
	29	/* MEMORY */
	30	#define MS7722SE_SDRAM_BASE (0x8C000000)
	31	#define MS7722SE_FLASH_BASE_1 (0xA0000000)
6c0bbdcc NI	32	#define MS7722SE_FLASH_BANK_SIZE (81024 1024)
6c0bbdcc NI	33
5c1877d6	34	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	35	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	36	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	37	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	38	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
	39	#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
	40	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
6c0bbdcc NI	41
6c0bbdcc NI	42	/* SCIF */
6c58a030	43	#define CONFIG_SCIF_CONSOLE 1
6c0bbdcc	44	#define CONFIG_CONS_SCIF0 1
6d0f6bcf JCPV	45	#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
	46	#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	47	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
6c0bbdcc	48
6d0f6bcf JCPV	49	#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
6d0f6bcf JCPV	50	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
6c0bbdcc	51
6d0f6bcf JCPV	52	#undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */
6d0f6bcf JCPV	53	#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
6c0bbdcc	54
6d0f6bcf	55	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
6c0bbdcc	56
6d0f6bcf JCPV	57	#define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE)
6d0f6bcf JCPV	58	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
6c0bbdcc	59
6d0f6bcf	60	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
6c0bbdcc	61
6d0f6bcf	62	#define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
53677ef1	63	in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf JCPV	64	#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
6d0f6bcf JCPV	65	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
6d0f6bcf	66	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6c0bbdcc NI	67
6c0bbdcc NI	68	/* FLASH */
6d0f6bcf	69	#define CONFIG_SYS_FLASH_CFI
00b1883a	70	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	71	#undef CONFIG_SYS_FLASH_QUIET_TEST
6d0f6bcf JCPV	72	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6c0bbdcc	73
6d0f6bcf	74	#define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
6c0bbdcc	75
6d0f6bcf	76	#define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each
53677ef1	77	Flash chip */
6c0bbdcc NI	78
6c0bbdcc NI	79	/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
6d0f6bcf JCPV	80	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	81	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
	82	CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
6c0bbdcc NI	83	}
6c0bbdcc NI	84
6d0f6bcf JCPV	85	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
	86	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
	87	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
	88	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
6c0bbdcc	89
6d0f6bcf	90	#undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */
6c0bbdcc	91
6d0f6bcf	92	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
6c0bbdcc	93
5a1aceb0	94	#define CONFIG_ENV_IS_IN_FLASH
6c0bbdcc	95	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	96	#define CONFIG_ENV_SECT_SIZE (8 * 1024)
0e8d1586 JCPV	97	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	98	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
6d0f6bcf JCPV	99	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
0e8d1586	100	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	101	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
6c0bbdcc NI	102
	103	/* Board Clock */
	104	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	105	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	106	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	107	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
6c0bbdcc NI	108
6c0bbdcc NI	109	#endif /* __MS7722SE_H */