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8449f287 ML |
1 | /* |
2 | * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> | |
3 | * | |
4 | * (C) Copyright 2004 | |
5 | * Texas Instruments. | |
6 | * Richard Woodruff <r-woodruff2@ti.com> | |
7 | * Kshitij Gupta <kshitij@ti.com> | |
8 | * | |
9 | * Configuration settings for the Freescale i.MX31 PDK board. | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
8449f287 ML |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
86271115 | 17 | #include <asm/arch/imx-regs.h> |
38a8b3ea | 18 | |
8449f287 | 19 | /* High Level Configuration Options */ |
e89f1f91 FE |
20 | #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ |
21 | #define CONFIG_MX31 /* in a mx31 */ | |
8449f287 | 22 | |
f93f2190 ML |
23 | #define CONFIG_SYS_GENERIC_BOARD |
24 | ||
8449f287 ML |
25 | #define CONFIG_DISPLAY_CPUINFO |
26 | #define CONFIG_DISPLAY_BOARDINFO | |
27 | ||
e89f1f91 FE |
28 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
29 | #define CONFIG_SETUP_MEMORY_TAGS | |
30 | #define CONFIG_INITRD_TAG | |
8449f287 | 31 | |
9aa3c6a1 FE |
32 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS |
33 | ||
da962b71 BT |
34 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
35 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
36 | #define CONFIG_SPL_MAX_SIZE 2048 | |
37 | #define CONFIG_SPL_NAND_SUPPORT | |
b1573153 | 38 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
da962b71 BT |
39 | |
40 | #define CONFIG_SPL_TEXT_BASE 0x87dc0000 | |
41 | #define CONFIG_SYS_TEXT_BASE 0x87e00000 | |
42 | ||
43 | #ifndef CONFIG_SPL_BUILD | |
8449f287 | 44 | #define CONFIG_SKIP_LOWLEVEL_INIT |
d08e5ca3 | 45 | #endif |
8449f287 ML |
46 | |
47 | /* | |
48 | * Size of malloc() pool | |
49 | */ | |
38a8b3ea | 50 | #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) |
8449f287 ML |
51 | |
52 | /* | |
53 | * Hardware drivers | |
54 | */ | |
55 | ||
e89f1f91 | 56 | #define CONFIG_MXC_UART |
40f6fffe | 57 | #define CONFIG_MXC_UART_BASE UART1_BASE |
6f2a4be9 | 58 | #define CONFIG_MXC_GPIO |
8449f287 | 59 | |
e89f1f91 FE |
60 | #define CONFIG_HARD_SPI |
61 | #define CONFIG_MXC_SPI | |
8449f287 | 62 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 63 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
8449f287 | 64 | |
877a438a | 65 | /* PMIC Controller */ |
be3b51aa ŁM |
66 | #define CONFIG_POWER |
67 | #define CONFIG_POWER_SPI | |
68 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
69 | #define CONFIG_FSL_PMIC_BUS 1 |
70 | #define CONFIG_FSL_PMIC_CS 2 | |
71 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 72 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
877a438a | 73 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 74 | #define CONFIG_RTC_MC13XXX |
8449f287 | 75 | |
8449f287 ML |
76 | /* allow to overwrite serial and ethaddr */ |
77 | #define CONFIG_ENV_OVERWRITE | |
78 | #define CONFIG_CONS_INDEX 1 | |
79 | #define CONFIG_BAUDRATE 115200 | |
8449f287 ML |
80 | |
81 | /*********************************************************** | |
82 | * Command definition | |
83 | ***********************************************************/ | |
84 | ||
85 | #include <config_cmd_default.h> | |
86 | ||
87 | #define CONFIG_CMD_MII | |
88 | #define CONFIG_CMD_PING | |
fc971028 | 89 | #define CONFIG_CMD_DHCP |
8449f287 ML |
90 | #define CONFIG_CMD_SPI |
91 | #define CONFIG_CMD_DATE | |
38a8b3ea | 92 | #define CONFIG_CMD_NAND |
0c23d84c | 93 | #define CONFIG_CMD_BOOTZ |
8449f287 ML |
94 | |
95 | /* | |
96 | * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require | |
97 | * that CFG_NO_FLASH is undefined). | |
98 | */ | |
99 | #undef CONFIG_CMD_IMLS | |
100 | ||
9660e442 | 101 | #define CONFIG_BOARD_LATE_INIT |
b73850f7 | 102 | |
562e6c62 | 103 | #define CONFIG_BOOTDELAY 1 |
8449f287 ML |
104 | |
105 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
106 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
107 | "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ | |
108 | "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ | |
109 | "bootcmd=run bootcmd_net\0" \ | |
110 | "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ | |
38a8b3ea | 111 | "tftpboot 0x81000000 uImage-mx31; bootm\0" \ |
da962b71 | 112 | "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ |
38a8b3ea ML |
113 | "nand erase 0x0 0x40000; " \ |
114 | "nand write 0x81000000 0x0 0x40000\0" | |
8449f287 | 115 | |
e89f1f91 | 116 | #define CONFIG_SMC911X |
736fead8 | 117 | #define CONFIG_SMC911X_BASE 0xB6000000 |
e89f1f91 | 118 | #define CONFIG_SMC911X_32_BIT |
8449f287 ML |
119 | |
120 | /* | |
121 | * Miscellaneous configurable options | |
122 | */ | |
123 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8449f287 ML |
124 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
125 | /* Print Buffer Size */ | |
126 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
127 | sizeof(CONFIG_SYS_PROMPT)+16) | |
128 | /* max number of command args */ | |
129 | #define CONFIG_SYS_MAXARGS 16 | |
130 | /* Boot Argument Buffer Size */ | |
131 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
132 | ||
133 | /* memtest works on */ | |
134 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
304e49e6 | 135 | #define CONFIG_SYS_MEMTEST_END 0x80010000 |
8449f287 ML |
136 | |
137 | /* default load address */ | |
138 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 | |
139 | ||
e89f1f91 | 140 | #define CONFIG_CMDLINE_EDITING |
8449f287 | 141 | |
8449f287 ML |
142 | /*----------------------------------------------------------------------- |
143 | * Physical Memory Map | |
144 | */ | |
145 | #define CONFIG_NR_DRAM_BANKS 1 | |
146 | #define PHYS_SDRAM_1 CSD0_BASE | |
147 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
e89f1f91 | 148 | #define CONFIG_BOARD_EARLY_INIT_F |
8449f287 | 149 | |
ed3df72d FE |
150 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
151 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
152 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
026ca659 FE |
153 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
154 | GENERATED_GBL_DATA_SIZE) | |
155 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
da962b71 | 156 | CONFIG_SYS_INIT_RAM_SIZE) |
ed3df72d | 157 | |
8449f287 ML |
158 | /*----------------------------------------------------------------------- |
159 | * FLASH and environment organization | |
160 | */ | |
161 | /* No NOR flash present */ | |
e89f1f91 | 162 | #define CONFIG_SYS_NO_FLASH |
8449f287 | 163 | |
e89f1f91 | 164 | #define CONFIG_ENV_IS_IN_NAND |
38a8b3ea ML |
165 | #define CONFIG_ENV_OFFSET 0x40000 |
166 | #define CONFIG_ENV_OFFSET_REDUND 0x60000 | |
167 | #define CONFIG_ENV_SIZE (128 * 1024) | |
8449f287 | 168 | |
38a8b3ea ML |
169 | /* |
170 | * NAND driver | |
171 | */ | |
172 | #define CONFIG_NAND_MXC | |
173 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR | |
174 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
175 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
176 | #define CONFIG_MXC_NAND_HWECC | |
177 | #define CONFIG_SYS_NAND_LARGEPAGE | |
8449f287 | 178 | |
d08e5ca3 ML |
179 | /* NAND configuration for the NAND_SPL */ |
180 | ||
181 | /* Start copying real U-boot from the second page */ | |
da962b71 BT |
182 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
183 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 | |
d08e5ca3 | 184 | /* Load U-Boot to this address */ |
da962b71 | 185 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
d08e5ca3 ML |
186 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
187 | ||
188 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
189 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
190 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
191 | #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) | |
192 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
193 | ||
194 | ||
195 | /* Configuration of lowlevel_init.S (clocks and SDRAM) */ | |
196 | #define CCM_CCMR_SETUP 0x074B0BF5 | |
9e0081d5 BT |
197 | #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ |
198 | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ | |
199 | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ | |
200 | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) | |
201 | #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ | |
d08e5ca3 ML |
202 | PLL_MFN(12)) |
203 | ||
204 | #define ESDMISC_MDDR_SETUP 0x00000004 | |
205 | #define ESDMISC_MDDR_RESET_DL 0x0000000c | |
206 | #define ESDCFG0_MDDR_SETUP 0x006ac73a | |
207 | ||
208 | #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) | |
209 | #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ | |
210 | ESDCTL_DSIZ(2) | ESDCTL_BL(1)) | |
211 | #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) | |
212 | #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) | |
213 | #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) | |
214 | #define ESDCTL_RW ESDCTL_SETTINGS | |
215 | ||
8449f287 | 216 | #endif /* __CONFIG_H */ |