[people/ms/u-boot.git] / include / configs / socfpga_common.h

/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET

/*
 * High level configuration
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_CLOCKS

#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/* add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x0
#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
#endif
#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
#endif

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * EPCS/EPCQx1 Serial Flash Controller
 */
#ifdef CONFIG_ALTERA_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
/*
 * The base address is configurable in QSys, each board must specify the
 * base address based on it's particular FPGA configuration. Please note
 * that the address here is incremented by  0x400  from the Base address
 * selected in QSys, since the SPI registers are at offset +0x400.
 * #define CONFIG_SYS_SPI_BASE		0xff240400
 */
#endif

/*
 * Ethernet on SoC (EMAC)
 */
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TIMER_RATE		2400000
#else
#define CONFIG_SYS_TIMER_RATE		25000000
#endif

/*
 * L4 Watchdog
 */
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000
#define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
#endif

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#endif

/*
 * I2C support
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SPEED3		100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE		0x02
#define CONFIG_SYS_I2C_SLAVE1		0x02
#define CONFIG_SYS_I2C_SLAVE2		0x02
#define CONFIG_SYS_I2C_SLAVE3		0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
#endif

/*
 * QSPI support
 */
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif

/*
 * Designware SPI support
 */

/*
 * Serial Driver
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_NS16550_CLK		1000000
#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
#define CONFIG_SYS_NS16550_CLK		100000000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
#define CONFIG_SYS_NS16550_CLK		50000000
#endif
#define CONFIG_CONS_INDEX		1

/*
 * USB
 */

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE			(8 * 1024)
#endif

/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
#define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
#endif

/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET		0x00100000
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#endif

/*
 * mtd partitioning for serial NOR flash
 *
 * device nor0 <ff705000.spi.0>, # parts = 6
 * #: name                size            offset          mask_flags
 * 0: u-boot              0x00100000      0x00000000      0
 * 1: env1                0x00040000      0x00100000      0
 * 2: env2                0x00040000      0x00140000      0
 * 3: UBI                 0x03e80000      0x00180000      0
 * 4: boot                0x00e80000      0x00180000      0
 * 5: rootfs              0x01000000      0x01000000      0
 *
 */

/*
 * SPL
 *
 * SRAM Memory layout:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Malloc area
 * 0xFFFF_zzzz ...... Global Data
 * 0xFFFF_FF00 ...... End of SRAM
 */
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
#endif
#endif

/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
#endif

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#endif

/*
 * Stack setup
 */
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR

/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>

#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif

#ifdef CONFIG_CMD_PXE
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif

#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif

#define BOOT_TARGET_DEVICES(func) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_PXE(func) \
	BOOT_TARGET_DEVICES_DHCP(func)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	"fdt_addr_r=0x02000000\0" \
	"scriptaddr=0x02100000\0" \
	"pxefile_addr_r=0x02200000\0" \
	"ramdisk_addr_r=0x02300000\0" \
	BOOTENV

#endif
#endif

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
5095ee08 PM	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
48275c96 DN	6	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	7	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	8
5095ee08 PM	9	/* Virtual target or real hardware */
	10	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
	11
5095ee08 PM	12	/*
	13	* High level configuration
	14	*/
7287d5f0	15	#define CONFIG_DISPLAY_BOARDINFO_LATE
5095ee08 PM	16	#define CONFIG_CLOCKS
5095ee08 PM	17
5095ee08 PM	18	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	19
	20	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	21
dc0a1a08 MV	22	/* add target to build it automatically upon "make" */
	23	#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
	24
5095ee08 PM	25	/*
	26	* Memory configurations
	27	*/
	28	#define CONFIG_NR_DRAM_BANKS 1
	29	#define PHYS_SDRAM_1 0x0
0223a95c	30	#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
5095ee08 PM	31	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
5095ee08 PM	32	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
1b259403	33	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
5095ee08	34	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
7599b53d	35	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
1b259403 LFT	36	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	37	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
	38	#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
	39	#endif
7599b53d MV	40	#define CONFIG_SYS_INIT_SP_OFFSET \
	41	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	42	#define CONFIG_SYS_INIT_SP_ADDR \
	43	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
5095ee08 PM	44
5095ee08 PM	45	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
5095ee08 PM	46
	47	/*
	48	* U-Boot general configurations
	49	*/
	50	#define CONFIG_SYS_LONGHELP
	51	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5095ee08 PM	52	/* Print buffer size */
	53	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	54	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	55	/* Boot argument buffer size */
5095ee08 PM	56	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
5095ee08 PM	57	#define CONFIG_CMDLINE_EDITING /* Command history etc */
5095ee08	58
ea082346 MV	59	#ifndef CONFIG_SYS_HOSTNAME
	60	#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
	61	#endif
	62
5095ee08 PM	63	/*
	64	* Cache
	65	*/
5095ee08 PM	66	#define CONFIG_SYS_L2_PL310
	67	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	68
8a78ca9e MV	69	/*
	70	* EPCS/EPCQx1 Serial Flash Controller
	71	*/
	72	#ifdef CONFIG_ALTERA_SPI
8a78ca9e	73	#define CONFIG_SF_DEFAULT_SPEED 30000000
8a78ca9e MV	74	/*
	75	* The base address is configurable in QSys, each board must specify the
	76	* base address based on it's particular FPGA configuration. Please note
	77	* that the address here is incremented by 0x400 from the Base address
	78	* selected in QSys, since the SPI registers are at offset +0x400.
	79	* #define CONFIG_SYS_SPI_BASE 0xff240400
	80	*/
	81	#endif
	82
5095ee08 PM	83	/*
	84	* Ethernet on SoC (EMAC)
	85	*/
	86	#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
5095ee08 PM	87	#define CONFIG_DW_ALTDESCRIPTOR
5095ee08 PM	88	#define CONFIG_MII
5095ee08 PM	89	#endif
	90
	91	/*
	92	* FPGA Driver
	93	*/
	94	#ifdef CONFIG_CMD_FPGA
5095ee08 PM	95	#define CONFIG_FPGA_COUNT 1
5095ee08 PM	96	#endif
9af91b7c	97
5095ee08 PM	98	/*
	99	* L4 OSC1 Timer 0
	100	*/
	101	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	102	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	103	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	104	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	105	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	106	#define CONFIG_SYS_TIMER_RATE 2400000
	107	#else
	108	#define CONFIG_SYS_TIMER_RATE 25000000
	109	#endif
	110
	111	/*
	112	* L4 Watchdog
	113	*/
	114	#ifdef CONFIG_HW_WATCHDOG
	115	#define CONFIG_DESIGNWARE_WATCHDOG
	116	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	117	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
ea926511	118	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
5095ee08 PM	119	#endif
	120
	121	/*
	122	* MMC Driver
	123	*/
	124	#ifdef CONFIG_CMD_MMC
5095ee08	125	#define CONFIG_BOUNCE_BUFFER
5095ee08 PM	126	/* FIXME */
	127	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	128	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	129	#endif
	130
c339ea5b MV	131	/*
	132	* NAND Support
	133	*/
	134	#ifdef CONFIG_NAND_DENALI
	135	#define CONFIG_SYS_MAX_NAND_DEVICE 1
c339ea5b	136	#define CONFIG_SYS_NAND_ONFI_DETECTION
c339ea5b MV	137	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
c339ea5b MV	138	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
c339ea5b MV	139	#endif
c339ea5b MV	140
7fb0f596	141	/*
ebcaf966 SR	142	* I2C support
	143	*/
	144	#define CONFIG_SYS_I2C
ebcaf966 SR	145	#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
	146	#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
	147	#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
	148	#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
	149	/* Using standard mode which the speed up to 100Kb/s */
	150	#define CONFIG_SYS_I2C_SPEED 100000
	151	#define CONFIG_SYS_I2C_SPEED1 100000
	152	#define CONFIG_SYS_I2C_SPEED2 100000
	153	#define CONFIG_SYS_I2C_SPEED3 100000
	154	/* Address of device when used as slave */
	155	#define CONFIG_SYS_I2C_SLAVE 0x02
	156	#define CONFIG_SYS_I2C_SLAVE1 0x02
	157	#define CONFIG_SYS_I2C_SLAVE2 0x02
	158	#define CONFIG_SYS_I2C_SLAVE3 0x02
	159	#ifndef __ASSEMBLY__
	160	/* Clock supplied to I2C controller in unit of MHz */
	161	unsigned int cm_get_l4_sp_clk_hz(void);
	162	#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
	163	#endif
ebcaf966	164
7fb0f596 SR	165	/*
	166	* QSPI support
	167	*/
7fb0f596	168	/* Enable multiple SPI NOR flash manufacturers */
cbc9544d	169	#ifndef CONFIG_SPL_BUILD
7fb0f596	170	#define CONFIG_SPI_FLASH_MTD
55b4312b MV	171	#define CONFIG_MTD_DEVICE
55b4312b MV	172	#define CONFIG_MTD_PARTITIONS
cbc9544d	173	#endif
7fb0f596 SR	174	/* QSPI reference clock */
	175	#ifndef __ASSEMBLY__
	176	unsigned int cm_get_qspi_controller_clk_hz(void);
	177	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	178	#endif
7fb0f596	179
0c745d00 MV	180	/*
	181	* Designware SPI support
	182	*/
a6e73591	183
5095ee08 PM	184	/*
	185	* Serial Driver
	186	*/
5095ee08 PM	187	#define CONFIG_SYS_NS16550_SERIAL
5095ee08 PM	188	#define CONFIG_SYS_NS16550_REG_SIZE -4
5095ee08 PM	189	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
5095ee08 PM	190	#define CONFIG_SYS_NS16550_CLK 1000000
1b259403 LFT	191	#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
1b259403 LFT	192	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
5095ee08	193	#define CONFIG_SYS_NS16550_CLK 100000000
1b259403 LFT	194	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	195	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
	196	#define CONFIG_SYS_NS16550_CLK 50000000
5095ee08 PM	197	#endif
5095ee08 PM	198	#define CONFIG_CONS_INDEX 1
5095ee08	199
20cadbbe MV	200	/*
	201	* USB
	202	*/
20cadbbe	203
0223a95c MV	204	/*
	205	* USB Gadget (DFU, UMS)
	206	*/
	207	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
55ce55fa	208	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
0223a95c MV	209	#define DFU_DEFAULT_POLL_TIMEOUT 300
	210
	211	/* USB IDs */
e6c0bc06 SP	212	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	213	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	214	#endif
0223a95c MV	215
5095ee08 PM	216	/*
	217	* U-Boot environment
	218	*/
ead2fb29	219	#if !defined(CONFIG_ENV_SIZE)
451e8241	220	#define CONFIG_ENV_SIZE (8 * 1024)
ead2fb29	221	#endif
5095ee08	222
79cc48e7 CLS	223	/* Environment for SDMMC boot */
79cc48e7 CLS	224	#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
451e8241 DW	225	#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
451e8241 DW	226	#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
79cc48e7 CLS	227	#endif
79cc48e7 CLS	228
ec8b7528 CLS	229	/* Environment for QSPI boot */
	230	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
	231	#define CONFIG_ENV_OFFSET 0x00100000
	232	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	233	#endif
	234
55702fe2 CLS	235	/*
	236	* mtd partitioning for serial NOR flash
	237	*
	238	* device nor0 <ff705000.spi.0>, # parts = 6
	239	* #: name size offset mask_flags
	240	* 0: u-boot 0x00100000 0x00000000 0
	241	* 1: env1 0x00040000 0x00100000 0
	242	* 2: env2 0x00040000 0x00140000 0
	243	* 3: UBI 0x03e80000 0x00180000 0
	244	* 4: boot 0x00e80000 0x00180000 0
	245	* 5: rootfs 0x01000000 0x01000000 0
	246	*
	247	*/
55702fe2	248
5095ee08 PM	249	/*
5095ee08 PM	250	* SPL
34584d19 MV	251	*
	252	* SRAM Memory layout:
	253	*
	254	* 0xFFFF_0000 ...... Start of SRAM
	255	* 0xFFFF_xxxx ...... Top of stack (grows down)
	256	* 0xFFFF_yyyy ...... Malloc area
	257	* 0xFFFF_zzzz ...... Global Data
	258	* 0xFFFF_FF00 ...... End of SRAM
5095ee08	259	*/
34584d19	260	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
1b259403	261	#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
5095ee08	262
d3f34e75 MV	263	/* SPL SDMMC boot support */
	264	#ifdef CONFIG_SPL_MMC_SUPPORT
	265	#if defined(CONFIG_SPL_FAT_SUPPORT) \|\| defined(CONFIG_SPL_EXT_SUPPORT)
d3f34e75	266	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
451e8241 DW	267	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	268	#endif
	269	#else
	270	#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
	271	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
d3f34e75 MV	272	#endif
d3f34e75 MV	273	#endif
5095ee08	274
346d6f56 MV	275	/* SPL QSPI boot support */
346d6f56 MV	276	#ifdef CONFIG_SPL_SPI_SUPPORT
346d6f56 MV	277	#define CONFIG_SPL_SPI_LOAD
	278	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
	279	#endif
	280
c339ea5b MV	281	/* SPL NAND boot support */
c339ea5b MV	282	#ifdef CONFIG_SPL_NAND_SUPPORT
c339ea5b MV	283	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	284	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	285	#endif
	286
a717b811 DN	287	/*
	288	* Stack setup
	289	*/
	290	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	291
451e8241 DW	292	/* Extra Environment */
	293	#ifndef CONFIG_SPL_BUILD
	294	#include <config_distro_defaults.h>
	295
1c7fa793 SG	296	#ifdef CONFIG_CMD_DHCP
	297	#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
	298	#else
	299	#define BOOT_TARGET_DEVICES_DHCP(func)
	300	#endif
	301
451e8241 DW	302	#ifdef CONFIG_CMD_PXE
	303	#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
	304	#else
	305	#define BOOT_TARGET_DEVICES_PXE(func)
	306	#endif
	307
	308	#ifdef CONFIG_CMD_MMC
	309	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
	310	#else
	311	#define BOOT_TARGET_DEVICES_MMC(func)
	312	#endif
	313
	314	#define BOOT_TARGET_DEVICES(func) \
	315	BOOT_TARGET_DEVICES_MMC(func) \
	316	BOOT_TARGET_DEVICES_PXE(func) \
1c7fa793	317	BOOT_TARGET_DEVICES_DHCP(func)
451e8241 DW	318
	319	#include <config_distro_bootcmd.h>
	320
	321	#ifndef CONFIG_EXTRA_ENV_SETTINGS
	322	#define CONFIG_EXTRA_ENV_SETTINGS \
	323	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	324	"bootm_size=0xa000000\0" \
	325	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	326	"fdt_addr_r=0x02000000\0" \
	327	"scriptaddr=0x02100000\0" \
	328	"pxefile_addr_r=0x02200000\0" \
	329	"ramdisk_addr_r=0x02300000\0" \
	330	BOOTENV
	331
	332	#endif
	333	#endif
	334
48275c96	335	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */