[people/ms/u-boot.git] / include / configs / socfpga_common.h

/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET

/*
 * High level configuration
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_CLOCKS

#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/* add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x0
#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
#endif
#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE		0x08000040
#else
#define CONFIG_SYS_TEXT_BASE		0x01000040
#endif

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
#endif

#define CONFIG_CMD_PXE
#define CONFIG_MENU

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * EPCS/EPCQx1 Serial Flash Controller
 */
#ifdef CONFIG_ALTERA_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
/*
 * The base address is configurable in QSys, each board must specify the
 * base address based on it's particular FPGA configuration. Please note
 * that the address here is incremented by  0x400  from the Base address
 * selected in QSys, since the SPI registers are at offset +0x400.
 * #define CONFIG_SYS_SPI_BASE		0xff240400
 */
#endif

/*
 * Ethernet on SoC (EMAC)
 */
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TIMER_RATE		2400000
#else
#define CONFIG_SYS_TIMER_RATE		25000000
#endif

/*
 * L4 Watchdog
 */
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000
#define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
#endif

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#endif

/*
 * I2C support
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SPEED3		100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE		0x02
#define CONFIG_SYS_I2C_SLAVE1		0x02
#define CONFIG_SYS_I2C_SLAVE2		0x02
#define CONFIG_SYS_I2C_SLAVE3		0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
#endif

/*
 * QSPI support
 */
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_CQSPI_DECODER		0
#define CONFIG_BOUNCE_BUFFER

/*
 * Designware SPI support
 */

/*
 * Serial Driver
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_NS16550_CLK		1000000
#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
#define CONFIG_SYS_NS16550_CLK		100000000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
#define CONFIG_SYS_NS16550_CLK		50000000
#endif
#define CONFIG_CONS_INDEX		1

/*
 * USB
 */

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_FUNCTION_MASS_STORAGE

#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE			(8 * 1024)
#endif

/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
#define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
#endif

/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET		0x00100000
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#endif

/*
 * mtd partitioning for serial NOR flash
 *
 * device nor0 <ff705000.spi.0>, # parts = 6
 * #: name                size            offset          mask_flags
 * 0: u-boot              0x00100000      0x00000000      0
 * 1: env1                0x00040000      0x00100000      0
 * 2: env2                0x00040000      0x00140000      0
 * 3: UBI                 0x03e80000      0x00180000      0
 * 4: boot                0x00e80000      0x00180000      0
 * 5: rootfs              0x01000000      0x01000000      0
 *
 */

/*
 * SPL
 *
 * SRAM Memory layout:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Malloc area
 * 0xFFFF_zzzz ...... Global Data
 * 0xFFFF_FF00 ...... End of SRAM
 */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
#endif
#endif

/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
#endif

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#endif

/*
 * Stack setup
 */
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR

/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>

#ifdef CONFIG_CMD_PXE
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif

#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif

#define BOOT_TARGET_DEVICES(func) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_PXE(func) \
	func(DHCP, dhcp, na)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	"fdt_addr_r=0x02000000\0" \
	"scriptaddr=0x02100000\0" \
	"pxefile_addr_r=0x02200000\0" \
	"ramdisk_addr_r=0x02300000\0" \
	BOOTENV

#endif
#endif

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
5095ee08 PM	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
48275c96 DN	6	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	7	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	8
5095ee08 PM	9	/* Virtual target or real hardware */
	10	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
	11
5095ee08 PM	12	/*
	13	* High level configuration
	14	*/
7287d5f0	15	#define CONFIG_DISPLAY_BOARDINFO_LATE
5095ee08 PM	16	#define CONFIG_CLOCKS
5095ee08 PM	17
5095ee08 PM	18	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	19
	20	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	21
dc0a1a08 MV	22	/* add target to build it automatically upon "make" */
	23	#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
	24
5095ee08 PM	25	/*
	26	* Memory configurations
	27	*/
	28	#define CONFIG_NR_DRAM_BANKS 1
	29	#define PHYS_SDRAM_1 0x0
0223a95c	30	#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
5095ee08 PM	31	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
5095ee08 PM	32	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
1b259403	33	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
5095ee08	34	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
7599b53d	35	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
1b259403 LFT	36	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	37	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
	38	#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
	39	#endif
7599b53d MV	40	#define CONFIG_SYS_INIT_SP_OFFSET \
	41	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	42	#define CONFIG_SYS_INIT_SP_ADDR \
	43	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
5095ee08 PM	44
	45	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	46	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	47	#define CONFIG_SYS_TEXT_BASE 0x08000040
	48	#else
	49	#define CONFIG_SYS_TEXT_BASE 0x01000040
	50	#endif
	51
	52	/*
	53	* U-Boot general configurations
	54	*/
	55	#define CONFIG_SYS_LONGHELP
	56	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5095ee08 PM	57	/* Print buffer size */
	58	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	59	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	60	/* Boot argument buffer size */
5095ee08 PM	61	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
5095ee08 PM	62	#define CONFIG_CMDLINE_EDITING /* Command history etc */
5095ee08	63
ea082346 MV	64	#ifndef CONFIG_SYS_HOSTNAME
	65	#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
	66	#endif
	67
451e8241 DW	68	#define CONFIG_CMD_PXE
	69	#define CONFIG_MENU
	70
5095ee08 PM	71	/*
	72	* Cache
	73	*/
5095ee08 PM	74	#define CONFIG_SYS_L2_PL310
	75	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	76
8a78ca9e MV	77	/*
	78	* EPCS/EPCQx1 Serial Flash Controller
	79	*/
	80	#ifdef CONFIG_ALTERA_SPI
8a78ca9e	81	#define CONFIG_SF_DEFAULT_SPEED 30000000
8a78ca9e MV	82	/*
	83	* The base address is configurable in QSys, each board must specify the
	84	* base address based on it's particular FPGA configuration. Please note
	85	* that the address here is incremented by 0x400 from the Base address
	86	* selected in QSys, since the SPI registers are at offset +0x400.
	87	* #define CONFIG_SYS_SPI_BASE 0xff240400
	88	*/
	89	#endif
	90
5095ee08 PM	91	/*
	92	* Ethernet on SoC (EMAC)
	93	*/
	94	#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
5095ee08 PM	95	#define CONFIG_DW_ALTDESCRIPTOR
5095ee08 PM	96	#define CONFIG_MII
5095ee08 PM	97	#endif
	98
	99	/*
	100	* FPGA Driver
	101	*/
	102	#ifdef CONFIG_CMD_FPGA
5095ee08 PM	103	#define CONFIG_FPGA_COUNT 1
5095ee08 PM	104	#endif
9af91b7c	105
5095ee08 PM	106	/*
	107	* L4 OSC1 Timer 0
	108	*/
	109	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	110	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	111	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	112	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	113	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	114	#define CONFIG_SYS_TIMER_RATE 2400000
	115	#else
	116	#define CONFIG_SYS_TIMER_RATE 25000000
	117	#endif
	118
	119	/*
	120	* L4 Watchdog
	121	*/
	122	#ifdef CONFIG_HW_WATCHDOG
	123	#define CONFIG_DESIGNWARE_WATCHDOG
	124	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	125	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
ea926511	126	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
5095ee08 PM	127	#endif
	128
	129	/*
	130	* MMC Driver
	131	*/
	132	#ifdef CONFIG_CMD_MMC
5095ee08	133	#define CONFIG_BOUNCE_BUFFER
5095ee08 PM	134	/* FIXME */
	135	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	136	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	137	#endif
	138
c339ea5b MV	139	/*
	140	* NAND Support
	141	*/
	142	#ifdef CONFIG_NAND_DENALI
	143	#define CONFIG_SYS_MAX_NAND_DEVICE 1
c339ea5b	144	#define CONFIG_SYS_NAND_ONFI_DETECTION
c339ea5b MV	145	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
c339ea5b MV	146	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
c339ea5b MV	147	#endif
c339ea5b MV	148
7fb0f596	149	/*
ebcaf966 SR	150	* I2C support
	151	*/
	152	#define CONFIG_SYS_I2C
ebcaf966 SR	153	#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
	154	#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
	155	#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
	156	#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
	157	/* Using standard mode which the speed up to 100Kb/s */
	158	#define CONFIG_SYS_I2C_SPEED 100000
	159	#define CONFIG_SYS_I2C_SPEED1 100000
	160	#define CONFIG_SYS_I2C_SPEED2 100000
	161	#define CONFIG_SYS_I2C_SPEED3 100000
	162	/* Address of device when used as slave */
	163	#define CONFIG_SYS_I2C_SLAVE 0x02
	164	#define CONFIG_SYS_I2C_SLAVE1 0x02
	165	#define CONFIG_SYS_I2C_SLAVE2 0x02
	166	#define CONFIG_SYS_I2C_SLAVE3 0x02
	167	#ifndef __ASSEMBLY__
	168	/* Clock supplied to I2C controller in unit of MHz */
	169	unsigned int cm_get_l4_sp_clk_hz(void);
	170	#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
	171	#endif
ebcaf966	172
7fb0f596 SR	173	/*
	174	* QSPI support
	175	*/
7fb0f596	176	/* Enable multiple SPI NOR flash manufacturers */
cbc9544d	177	#ifndef CONFIG_SPL_BUILD
7fb0f596	178	#define CONFIG_SPI_FLASH_MTD
55b4312b MV	179	#define CONFIG_MTD_DEVICE
55b4312b MV	180	#define CONFIG_MTD_PARTITIONS
cbc9544d	181	#endif
7fb0f596 SR	182	/* QSPI reference clock */
	183	#ifndef __ASSEMBLY__
	184	unsigned int cm_get_qspi_controller_clk_hz(void);
	185	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	186	#endif
	187	#define CONFIG_CQSPI_DECODER 0
57897c13	188	#define CONFIG_BOUNCE_BUFFER
7fb0f596	189
0c745d00 MV	190	/*
	191	* Designware SPI support
	192	*/
a6e73591	193
5095ee08 PM	194	/*
	195	* Serial Driver
	196	*/
5095ee08 PM	197	#define CONFIG_SYS_NS16550_SERIAL
5095ee08 PM	198	#define CONFIG_SYS_NS16550_REG_SIZE -4
5095ee08 PM	199	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
5095ee08 PM	200	#define CONFIG_SYS_NS16550_CLK 1000000
1b259403 LFT	201	#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
1b259403 LFT	202	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
5095ee08	203	#define CONFIG_SYS_NS16550_CLK 100000000
1b259403 LFT	204	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	205	#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
	206	#define CONFIG_SYS_NS16550_CLK 50000000
5095ee08 PM	207	#endif
5095ee08 PM	208	#define CONFIG_CONS_INDEX 1
5095ee08	209
20cadbbe MV	210	/*
	211	* USB
	212	*/
20cadbbe	213
0223a95c MV	214	/*
	215	* USB Gadget (DFU, UMS)
	216	*/
	217	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
01acd6ab	218	#define CONFIG_USB_FUNCTION_MASS_STORAGE
0223a95c	219
55ce55fa	220	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
0223a95c MV	221	#define DFU_DEFAULT_POLL_TIMEOUT 300
	222
	223	/* USB IDs */
e6c0bc06 SP	224	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	225	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	226	#endif
0223a95c MV	227
5095ee08 PM	228	/*
	229	* U-Boot environment
	230	*/
ead2fb29	231	#if !defined(CONFIG_ENV_SIZE)
451e8241	232	#define CONFIG_ENV_SIZE (8 * 1024)
ead2fb29	233	#endif
5095ee08	234
79cc48e7 CLS	235	/* Environment for SDMMC boot */
79cc48e7 CLS	236	#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
451e8241 DW	237	#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
451e8241 DW	238	#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
79cc48e7 CLS	239	#endif
79cc48e7 CLS	240
ec8b7528 CLS	241	/* Environment for QSPI boot */
	242	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
	243	#define CONFIG_ENV_OFFSET 0x00100000
	244	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	245	#endif
	246
55702fe2 CLS	247	/*
	248	* mtd partitioning for serial NOR flash
	249	*
	250	* device nor0 <ff705000.spi.0>, # parts = 6
	251	* #: name size offset mask_flags
	252	* 0: u-boot 0x00100000 0x00000000 0
	253	* 1: env1 0x00040000 0x00100000 0
	254	* 2: env2 0x00040000 0x00140000 0
	255	* 3: UBI 0x03e80000 0x00180000 0
	256	* 4: boot 0x00e80000 0x00180000 0
	257	* 5: rootfs 0x01000000 0x01000000 0
	258	*
	259	*/
55702fe2	260
5095ee08 PM	261	/*
5095ee08 PM	262	* SPL
34584d19 MV	263	*
	264	* SRAM Memory layout:
	265	*
	266	* 0xFFFF_0000 ...... Start of SRAM
	267	* 0xFFFF_xxxx ...... Top of stack (grows down)
	268	* 0xFFFF_yyyy ...... Malloc area
	269	* 0xFFFF_zzzz ...... Global Data
	270	* 0xFFFF_FF00 ...... End of SRAM
5095ee08 PM	271	*/
5095ee08 PM	272	#define CONFIG_SPL_FRAMEWORK
34584d19	273	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
1b259403	274	#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
5095ee08	275
d3f34e75 MV	276	/* SPL SDMMC boot support */
	277	#ifdef CONFIG_SPL_MMC_SUPPORT
	278	#if defined(CONFIG_SPL_FAT_SUPPORT) \|\| defined(CONFIG_SPL_EXT_SUPPORT)
d3f34e75	279	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
451e8241 DW	280	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	281	#endif
	282	#else
	283	#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
	284	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
d3f34e75 MV	285	#endif
d3f34e75 MV	286	#endif
5095ee08	287
346d6f56 MV	288	/* SPL QSPI boot support */
346d6f56 MV	289	#ifdef CONFIG_SPL_SPI_SUPPORT
346d6f56 MV	290	#define CONFIG_SPL_SPI_LOAD
	291	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
	292	#endif
	293
c339ea5b MV	294	/* SPL NAND boot support */
c339ea5b MV	295	#ifdef CONFIG_SPL_NAND_SUPPORT
c339ea5b MV	296	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	297	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	298	#endif
	299
a717b811 DN	300	/*
	301	* Stack setup
	302	*/
	303	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	304
451e8241 DW	305	/* Extra Environment */
	306	#ifndef CONFIG_SPL_BUILD
	307	#include <config_distro_defaults.h>
	308
	309	#ifdef CONFIG_CMD_PXE
	310	#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
	311	#else
	312	#define BOOT_TARGET_DEVICES_PXE(func)
	313	#endif
	314
	315	#ifdef CONFIG_CMD_MMC
	316	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
	317	#else
	318	#define BOOT_TARGET_DEVICES_MMC(func)
	319	#endif
	320
	321	#define BOOT_TARGET_DEVICES(func) \
	322	BOOT_TARGET_DEVICES_MMC(func) \
	323	BOOT_TARGET_DEVICES_PXE(func) \
	324	func(DHCP, dhcp, na)
	325
	326	#include <config_distro_bootcmd.h>
	327
	328	#ifndef CONFIG_EXTRA_ENV_SETTINGS
	329	#define CONFIG_EXTRA_ENV_SETTINGS \
	330	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	331	"bootm_size=0xa000000\0" \
	332	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	333	"fdt_addr_r=0x02000000\0" \
	334	"scriptaddr=0x02100000\0" \
	335	"pxefile_addr_r=0x02200000\0" \
	336	"ramdisk_addr_r=0x02300000\0" \
	337	BOOTENV
	338
	339	#endif
	340	#endif
	341
48275c96	342	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */