]>
Commit | Line | Data |
---|---|---|
5095ee08 PM |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
48275c96 DN |
6 | #ifndef __CONFIG_SOCFPGA_COMMON_H__ |
7 | #define __CONFIG_SOCFPGA_COMMON_H__ | |
5095ee08 | 8 | |
5095ee08 PM |
9 | /* Virtual target or real hardware */ |
10 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
11 | ||
5095ee08 PM |
12 | #define CONFIG_SYS_THUMB_BUILD |
13 | ||
5095ee08 PM |
14 | /* |
15 | * High level configuration | |
16 | */ | |
17 | #define CONFIG_DISPLAY_CPUINFO | |
7287d5f0 | 18 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
9ec7414e | 19 | #define CONFIG_ARCH_MISC_INIT |
fc520894 | 20 | #define CONFIG_ARCH_EARLY_INIT_R |
5095ee08 PM |
21 | #define CONFIG_SYS_NO_FLASH |
22 | #define CONFIG_CLOCKS | |
23 | ||
251faa20 MV |
24 | #define CONFIG_CRC32_VERIFY |
25 | ||
5095ee08 PM |
26 | #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) |
27 | ||
28 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
29 | ||
dc0a1a08 MV |
30 | /* add target to build it automatically upon "make" */ |
31 | #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" | |
32 | ||
5095ee08 PM |
33 | /* |
34 | * Memory configurations | |
35 | */ | |
36 | #define CONFIG_NR_DRAM_BANKS 1 | |
37 | #define PHYS_SDRAM_1 0x0 | |
0223a95c | 38 | #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) |
5095ee08 PM |
39 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
40 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE | |
41 | ||
42 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 | |
7599b53d MV |
43 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
44 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
45 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
46 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
47 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
5095ee08 PM |
48 | |
49 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
50 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
51 | #define CONFIG_SYS_TEXT_BASE 0x08000040 | |
52 | #else | |
53 | #define CONFIG_SYS_TEXT_BASE 0x01000040 | |
54 | #endif | |
55 | ||
56 | /* | |
57 | * U-Boot general configurations | |
58 | */ | |
59 | #define CONFIG_SYS_LONGHELP | |
60 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ | |
61 | #define CONFIG_SYS_PBSIZE \ | |
62 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
63 | /* Print buffer size */ | |
64 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ | |
65 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
66 | /* Boot argument buffer size */ | |
5095ee08 PM |
67 | #define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
68 | #define CONFIG_CMDLINE_EDITING /* Command history etc */ | |
5095ee08 | 69 | |
ea082346 MV |
70 | #ifndef CONFIG_SYS_HOSTNAME |
71 | #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD | |
72 | #endif | |
73 | ||
5095ee08 PM |
74 | /* |
75 | * Cache | |
76 | */ | |
5095ee08 PM |
77 | #define CONFIG_SYS_L2_PL310 |
78 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | |
79 | ||
cdd4e6cc DN |
80 | /* |
81 | * SDRAM controller | |
82 | */ | |
83 | #define CONFIG_ALTERA_SDRAM | |
84 | ||
8a78ca9e MV |
85 | /* |
86 | * EPCS/EPCQx1 Serial Flash Controller | |
87 | */ | |
88 | #ifdef CONFIG_ALTERA_SPI | |
8a78ca9e | 89 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
8a78ca9e MV |
90 | /* |
91 | * The base address is configurable in QSys, each board must specify the | |
92 | * base address based on it's particular FPGA configuration. Please note | |
93 | * that the address here is incremented by 0x400 from the Base address | |
94 | * selected in QSys, since the SPI registers are at offset +0x400. | |
95 | * #define CONFIG_SYS_SPI_BASE 0xff240400 | |
96 | */ | |
97 | #endif | |
98 | ||
5095ee08 PM |
99 | /* |
100 | * Ethernet on SoC (EMAC) | |
101 | */ | |
102 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) | |
5095ee08 PM |
103 | #define CONFIG_DW_ALTDESCRIPTOR |
104 | #define CONFIG_MII | |
105 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) | |
5095ee08 PM |
106 | #define CONFIG_PHY_GIGE |
107 | #endif | |
108 | ||
109 | /* | |
110 | * FPGA Driver | |
111 | */ | |
112 | #ifdef CONFIG_CMD_FPGA | |
113 | #define CONFIG_FPGA | |
114 | #define CONFIG_FPGA_ALTERA | |
115 | #define CONFIG_FPGA_SOCFPGA | |
116 | #define CONFIG_FPGA_COUNT 1 | |
117 | #endif | |
118 | ||
119 | /* | |
120 | * L4 OSC1 Timer 0 | |
121 | */ | |
122 | /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ | |
123 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS | |
124 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
125 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | |
126 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
127 | #define CONFIG_SYS_TIMER_RATE 2400000 | |
128 | #else | |
129 | #define CONFIG_SYS_TIMER_RATE 25000000 | |
130 | #endif | |
131 | ||
132 | /* | |
133 | * L4 Watchdog | |
134 | */ | |
135 | #ifdef CONFIG_HW_WATCHDOG | |
136 | #define CONFIG_DESIGNWARE_WATCHDOG | |
137 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS | |
138 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 | |
d0e932de | 139 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 |
5095ee08 PM |
140 | #endif |
141 | ||
142 | /* | |
143 | * MMC Driver | |
144 | */ | |
145 | #ifdef CONFIG_CMD_MMC | |
146 | #define CONFIG_MMC | |
147 | #define CONFIG_BOUNCE_BUFFER | |
148 | #define CONFIG_GENERIC_MMC | |
149 | #define CONFIG_DWMMC | |
150 | #define CONFIG_SOCFPGA_DWMMC | |
151 | #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 | |
5095ee08 PM |
152 | /* FIXME */ |
153 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ | |
154 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ | |
155 | #endif | |
156 | ||
c339ea5b MV |
157 | /* |
158 | * NAND Support | |
159 | */ | |
160 | #ifdef CONFIG_NAND_DENALI | |
161 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
162 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
163 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
164 | #define CONFIG_NAND_DENALI_ECC_SIZE 512 | |
165 | #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS | |
166 | #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS | |
167 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
168 | #endif | |
169 | ||
7fb0f596 | 170 | /* |
ebcaf966 SR |
171 | * I2C support |
172 | */ | |
173 | #define CONFIG_SYS_I2C | |
ebcaf966 SR |
174 | #define CONFIG_SYS_I2C_BUS_MAX 4 |
175 | #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS | |
176 | #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS | |
177 | #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS | |
178 | #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS | |
179 | /* Using standard mode which the speed up to 100Kb/s */ | |
180 | #define CONFIG_SYS_I2C_SPEED 100000 | |
181 | #define CONFIG_SYS_I2C_SPEED1 100000 | |
182 | #define CONFIG_SYS_I2C_SPEED2 100000 | |
183 | #define CONFIG_SYS_I2C_SPEED3 100000 | |
184 | /* Address of device when used as slave */ | |
185 | #define CONFIG_SYS_I2C_SLAVE 0x02 | |
186 | #define CONFIG_SYS_I2C_SLAVE1 0x02 | |
187 | #define CONFIG_SYS_I2C_SLAVE2 0x02 | |
188 | #define CONFIG_SYS_I2C_SLAVE3 0x02 | |
189 | #ifndef __ASSEMBLY__ | |
190 | /* Clock supplied to I2C controller in unit of MHz */ | |
191 | unsigned int cm_get_l4_sp_clk_hz(void); | |
192 | #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) | |
193 | #endif | |
ebcaf966 | 194 | |
7fb0f596 SR |
195 | /* |
196 | * QSPI support | |
197 | */ | |
7fb0f596 | 198 | /* Enable multiple SPI NOR flash manufacturers */ |
cbc9544d | 199 | #ifndef CONFIG_SPL_BUILD |
7fb0f596 | 200 | #define CONFIG_SPI_FLASH_MTD |
55b4312b MV |
201 | #define CONFIG_CMD_MTDPARTS |
202 | #define CONFIG_MTD_DEVICE | |
203 | #define CONFIG_MTD_PARTITIONS | |
55702fe2 | 204 | #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" |
cbc9544d | 205 | #endif |
7fb0f596 SR |
206 | /* QSPI reference clock */ |
207 | #ifndef __ASSEMBLY__ | |
208 | unsigned int cm_get_qspi_controller_clk_hz(void); | |
209 | #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() | |
210 | #endif | |
211 | #define CONFIG_CQSPI_DECODER 0 | |
7fb0f596 | 212 | |
0c745d00 MV |
213 | /* |
214 | * Designware SPI support | |
215 | */ | |
a6e73591 | 216 | |
5095ee08 PM |
217 | /* |
218 | * Serial Driver | |
219 | */ | |
5095ee08 PM |
220 | #define CONFIG_SYS_NS16550_SERIAL |
221 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
222 | #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS | |
223 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
224 | #define CONFIG_SYS_NS16550_CLK 1000000 | |
225 | #else | |
226 | #define CONFIG_SYS_NS16550_CLK 100000000 | |
227 | #endif | |
228 | #define CONFIG_CONS_INDEX 1 | |
229 | #define CONFIG_BAUDRATE 115200 | |
230 | ||
20cadbbe MV |
231 | /* |
232 | * USB | |
233 | */ | |
234 | #ifdef CONFIG_CMD_USB | |
235 | #define CONFIG_USB_DWC2 | |
20cadbbe MV |
236 | #endif |
237 | ||
0223a95c MV |
238 | /* |
239 | * USB Gadget (DFU, UMS) | |
240 | */ | |
241 | #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) | |
01acd6ab | 242 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
0223a95c | 243 | |
01acd6ab | 244 | #define CONFIG_USB_FUNCTION_DFU |
eba522a0 | 245 | #ifdef CONFIG_DM_MMC |
0223a95c | 246 | #define CONFIG_DFU_MMC |
eba522a0 | 247 | #endif |
0223a95c MV |
248 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) |
249 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
250 | ||
251 | /* USB IDs */ | |
e6c0bc06 SP |
252 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 |
253 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 | |
0223a95c MV |
254 | #endif |
255 | ||
5095ee08 PM |
256 | /* |
257 | * U-Boot environment | |
258 | */ | |
259 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
260 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
261 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
ead2fb29 | 262 | #if !defined(CONFIG_ENV_SIZE) |
5095ee08 | 263 | #define CONFIG_ENV_SIZE 4096 |
ead2fb29 | 264 | #endif |
5095ee08 | 265 | |
79cc48e7 CLS |
266 | /* Environment for SDMMC boot */ |
267 | #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) | |
268 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ | |
269 | #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ | |
270 | #endif | |
271 | ||
ec8b7528 CLS |
272 | /* Environment for QSPI boot */ |
273 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) | |
274 | #define CONFIG_ENV_OFFSET 0x00100000 | |
275 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
276 | #endif | |
277 | ||
55702fe2 CLS |
278 | /* |
279 | * mtd partitioning for serial NOR flash | |
280 | * | |
281 | * device nor0 <ff705000.spi.0>, # parts = 6 | |
282 | * #: name size offset mask_flags | |
283 | * 0: u-boot 0x00100000 0x00000000 0 | |
284 | * 1: env1 0x00040000 0x00100000 0 | |
285 | * 2: env2 0x00040000 0x00140000 0 | |
286 | * 3: UBI 0x03e80000 0x00180000 0 | |
287 | * 4: boot 0x00e80000 0x00180000 0 | |
288 | * 5: rootfs 0x01000000 0x01000000 0 | |
289 | * | |
290 | */ | |
291 | #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) | |
292 | #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ | |
293 | "1m(u-boot)," \ | |
294 | "256k(env1)," \ | |
295 | "256k(env2)," \ | |
296 | "14848k(boot)," \ | |
297 | "16m(rootfs)," \ | |
298 | "-@1536k(UBI)\0" | |
299 | #endif | |
300 | ||
6cdd465c CLS |
301 | /* UBI and UBIFS support */ |
302 | #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) | |
303 | #define CONFIG_CMD_UBI | |
304 | #define CONFIG_CMD_UBIFS | |
305 | #define CONFIG_RBTREE | |
306 | #define CONFIG_LZO | |
307 | #endif | |
308 | ||
5095ee08 PM |
309 | /* |
310 | * SPL | |
34584d19 MV |
311 | * |
312 | * SRAM Memory layout: | |
313 | * | |
314 | * 0xFFFF_0000 ...... Start of SRAM | |
315 | * 0xFFFF_xxxx ...... Top of stack (grows down) | |
316 | * 0xFFFF_yyyy ...... Malloc area | |
317 | * 0xFFFF_zzzz ...... Global Data | |
318 | * 0xFFFF_FF00 ...... End of SRAM | |
5095ee08 PM |
319 | */ |
320 | #define CONFIG_SPL_FRAMEWORK | |
5095ee08 | 321 | #define CONFIG_SPL_RAM_DEVICE |
34584d19 | 322 | #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR |
6868160a | 323 | #define CONFIG_SPL_MAX_SIZE (64 * 1024) |
5095ee08 | 324 | |
5095ee08 PM |
325 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
326 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
327 | #define CONFIG_SPL_SERIAL_SUPPORT | |
4197a0f4 | 328 | #ifdef CONFIG_DM_MMC |
d3f34e75 | 329 | #define CONFIG_SPL_MMC_SUPPORT |
4197a0f4 MV |
330 | #endif |
331 | #ifdef CONFIG_DM_SPI | |
346d6f56 | 332 | #define CONFIG_SPL_SPI_SUPPORT |
4197a0f4 | 333 | #endif |
c339ea5b MV |
334 | #ifdef CONFIG_SPL_NAND_DENALI |
335 | #define CONFIG_SPL_NAND_SUPPORT | |
336 | #endif | |
d3f34e75 MV |
337 | |
338 | /* SPL SDMMC boot support */ | |
339 | #ifdef CONFIG_SPL_MMC_SUPPORT | |
340 | #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) | |
341 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 | |
342 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" | |
343 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
344 | #else | |
61520ac4 | 345 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 |
d31e9c57 SL |
346 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */ |
347 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
d3f34e75 MV |
348 | #endif |
349 | #endif | |
5095ee08 | 350 | |
346d6f56 MV |
351 | /* SPL QSPI boot support */ |
352 | #ifdef CONFIG_SPL_SPI_SUPPORT | |
346d6f56 MV |
353 | #define CONFIG_SPL_SPI_FLASH_SUPPORT |
354 | #define CONFIG_SPL_SPI_LOAD | |
355 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 | |
356 | #endif | |
357 | ||
c339ea5b MV |
358 | /* SPL NAND boot support */ |
359 | #ifdef CONFIG_SPL_NAND_SUPPORT | |
360 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
361 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
362 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 | |
363 | #endif | |
364 | ||
a717b811 DN |
365 | /* |
366 | * Stack setup | |
367 | */ | |
368 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | |
369 | ||
48275c96 | 370 | #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ |