[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK		12288000
#define CONFIG_SYS_NS16550_REG_SIZE	-2
#endif

/* TODO: move to Kconfig and device tree */
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif

#define CONFIG_SMC911X

/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE	0
#define CONFIG_SMC911X_32_BIT

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_CACHELINE_SIZE	32

/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

/*
 * uncomment the following to disable FLASH related code.
 */
/* #define CONFIG_SYS_NO_FLASH */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for out supoort card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */
#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_GENERIC_BOARD

#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE				0x2000
#define CONFIG_ENV_OFFSET			0x0
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000

/*
 * By default, ARP timeout is 5 sec.
 * The first ARP request does not seem to work.
 * So we need to retry ARP request anyway.
 * We want to shrink the interval until the second ARP request.
 */
#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */

#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

#define CONFIG_BOOTDELAY			3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	"tftpboot; bootm;"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0"
#else
#define CONFIG_BOOTFILE			"uImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
	"kernel_addr=0x00200000\0" \
	"kernel_addr_r=0x84200000\0" \
	"kernel_size=0x00800000\0" \
	"ramdisk_addr=0x00a00000\0" \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
		"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
		"setexpr fdt_addr $nor_base + $fdt_addr &&" \
		"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"norbase=0x42000000\0"					\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl-dtb.bin &&"		\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot-dtb.img &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	LINUXBOOT_ENV_SETTINGS

/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_NR_DRAM_BANKS		2

#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
	defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
	defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#else
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#define CONFIG_SPL_STACK		(0x0ff08000)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT

#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

#define CONFIG_SPL_MAX_FOOTPRINT		0x10000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
f8f35944	2	* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	/* U-boot - Common settings for UniPhier Family */
	8
	9	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	10	#define __CONFIG_UNIPHIER_COMMON_H__
	11
233e42a9 MY	12	#define CONFIG_I2C_EEPROM
	13	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	14
d064cbff	15	#ifdef CONFIG_SYS_NS16550_SERIAL
5894ca00 MY	16	#define CONFIG_SYS_NS16550
	17	#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
	18	#define CONFIG_SYS_NS16550_CLK 12288000
	19	#define CONFIG_SYS_NS16550_REG_SIZE -2
d064cbff	20	#endif
5894ca00	21
f5d0b9b2 MY	22	/* TODO: move to Kconfig and device tree */
	23	#if 0
	24	#define CONFIG_SYS_NS16550_SERIAL
	25	#endif
	26
	27	#define CONFIG_SMC911X
	28
d7728aa4 MY	29	/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
d7728aa4 MY	30	#define CONFIG_SMC911X_BASE 0
5894ca00 MY	31	#define CONFIG_SMC911X_32_BIT
5894ca00 MY	32
5894ca00 MY	33	/*-----------------------------------------------------------------------
	34	* MMU and Cache Setting
	35	----------------------------------------------------------------------/
	36
	37	/* Comment out the following to enable L1 cache */
	38	/* #define CONFIG_SYS_ICACHE_OFF */
	39	/* #define CONFIG_SYS_DCACHE_OFF */
	40
53c45d4e MY	41	#define CONFIG_SYS_CACHELINE_SIZE 32
53c45d4e MY	42
5894ca00 MY	43	/* Comment out the following to enable L2 cache */
	44	#define CONFIG_UNIPHIER_L2CACHE_ON
	45
	46	#define CONFIG_DISPLAY_CPUINFO
	47	#define CONFIG_DISPLAY_BOARDINFO
08fda258	48	#define CONFIG_MISC_INIT_F
84ccd791	49	#define CONFIG_BOARD_EARLY_INIT_F
7a3620b2	50	#define CONFIG_BOARD_EARLY_INIT_R
5894ca00 MY	51	#define CONFIG_BOARD_LATE_INIT
	52
	53	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	54
	55	#define CONFIG_TIMESTAMP
	56
	57	/* FLASH related */
	58	#define CONFIG_MTD_DEVICE
	59
	60	/*
	61	* uncomment the following to disable FLASH related code.
	62	*/
	63	/* #define CONFIG_SYS_NO_FLASH */
	64
	65	#define CONFIG_FLASH_CFI_DRIVER
	66	#define CONFIG_SYS_FLASH_CFI
	67
	68	#define CONFIG_SYS_MAX_FLASH_SECT 256
	69	#define CONFIG_SYS_MONITOR_BASE 0
	70	#define CONFIG_SYS_FLASH_BASE 0
	71
	72	/*
	73	* flash_toggle does not work for out supoort card.
	74	* We need to use flash_status_poll.
	75	*/
	76	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	77
	78	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	79
9879842c	80	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	81
	82	/* serial console configuration */
	83	#define CONFIG_BAUDRATE 115200
	84
	85	#define CONFIG_SYS_GENERIC_BOARD
	86
	87	#if !defined(CONFIG_SPL_BUILD)
	88	#define CONFIG_USE_ARCH_MEMSET
	89	#define CONFIG_USE_ARCH_MEMCPY
	90	#endif
	91
	92	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	93
	94	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	95	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	96	/* Print Buffer Size */
	97	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	98	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	99	/* Boot Argument Buffer Size */
	100	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	101
	102	#define CONFIG_CONS_INDEX 1
	103
	104	/*
	105	* For NAND booting the environment is embedded in the U-Boot image. Please take
	106	* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
	107	*/
	108	/* #define CONFIG_ENV_IS_IN_NAND */
	109	#define CONFIG_ENV_IS_NOWHERE
	110	#define CONFIG_ENV_SIZE 0x2000
	111	#define CONFIG_ENV_OFFSET 0x0
	112	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
	113
	114	/* Time clock 1MHz */
	115	#define CONFIG_SYS_TIMER_RATE 1000000
	116
	117	/*
	118	* By default, ARP timeout is 5 sec.
	119	* The first ARP request does not seem to work.
	120	* So we need to retry ARP request anyway.
	121	* We want to shrink the interval until the second ARP request.
	122	*/
	123	#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
	124
5894ca00 MY	125	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	126	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	127	#define CONFIG_SYS_NAND_ONFI_DETECTION
	128
	129	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	130
8497ccc4	131	#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
3365b4eb MY	132	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	133	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	134	#else
5894ca00 MY	135	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	136	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	137	#endif
5894ca00 MY	138
	139	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	140
	141	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	142	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	143
495deb44	144	/* USB */
495deb44	145	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
53c45d4e	146	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	147	#define CONFIG_CMD_FAT
	148	#define CONFIG_FAT_WRITE
	149	#define CONFIG_DOS_PARTITION
	150
5894ca00 MY	151	/* memtest works on */
	152	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	153	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	154
	155	#define CONFIG_BOOTDELAY 3
	156	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
5894ca00 MY	157
	158	/*
	159	* Network Configuration
	160	*/
5894ca00 MY	161	#define CONFIG_SERVERIP 192.168.11.1
	162	#define CONFIG_IPADDR 192.168.11.10
	163	#define CONFIG_GATEWAYIP 192.168.11.1
	164	#define CONFIG_NETMASK 255.255.255.0
	165
	166	#define CONFIG_LOADADDR 0x84000000
	167	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	168
	169	#define CONFIG_CMDLINE_EDITING /* add command line history */
	170
	171	#define CONFIG_BOOTCOMMAND "run $bootmode"
	172
	173	#define CONFIG_ROOTPATH "/nfs/root/path"
	174	#define CONFIG_NFSBOOTCOMMAND \
	175	"setenv bootargs $bootargs root=/dev/nfs rw " \
	176	"nfsroot=$serverip:$rootpath " \
	177	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	178	"tftpboot; bootm;"
	179
421376ae MY	180	#ifdef CONFIG_FIT
	181	#define CONFIG_BOOTFILE "fitImage"
	182	#define LINUXBOOT_ENV_SETTINGS \
	183	"fit_addr=0x00100000\0" \
	184	"fit_addr_r=0x84100000\0" \
	185	"fit_size=0x00f00000\0" \
5451b777	186	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae	187	"bootm $fit_addr\0" \
5451b777	188	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c	189	"bootm $fit_addr_r\0" \
5451b777	190	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
421376ae MY	191	"bootm $fit_addr_r\0"
	192	#else
	193	#define CONFIG_BOOTFILE "uImage"
	194	#define LINUXBOOT_ENV_SETTINGS \
	195	"fdt_addr=0x00100000\0" \
	196	"fdt_addr_r=0x84100000\0" \
	197	"fdt_size=0x00008000\0" \
e037db0c	198	"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
421376ae MY	199	"kernel_addr=0x00200000\0" \
	200	"kernel_addr_r=0x84200000\0" \
	201	"kernel_size=0x00800000\0" \
	202	"ramdisk_addr=0x00a00000\0" \
	203	"ramdisk_addr_r=0x84a00000\0" \
	204	"ramdisk_size=0x00600000\0" \
e037db0c	205	"ramdisk_file=rootfs.cpio.uboot\0" \
5451b777	206	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
d5ed8c57 MY	207	"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
d5ed8c57 MY	208	"setexpr fdt_addr $nor_base + $fdt_addr &&" \
421376ae	209	"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
5451b777	210	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
421376ae MY	211	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
421376ae MY	212	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
e037db0c	213	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
5451b777	214	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
e037db0c MY	215	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
e037db0c MY	216	"tftpboot $fdt_addr_r $fdt_file &&" \
421376ae MY	217	"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
	218	#endif
	219
	220	#define CONFIG_EXTRA_ENV_SETTINGS \
	221	"netdev=eth0\0" \
	222	"verify=n\0" \
d5ed8c57	223	"norbase=0x42000000\0" \
421376ae	224	"nandupdate=nand erase 0 0x00100000 &&" \
f4e190e3	225	"tftpboot u-boot-spl-dtb.bin &&" \
421376ae MY	226	"nand write $loadaddr 0 0x00010000 &&" \
	227	"tftpboot u-boot-dtb.img &&" \
	228	"nand write $loadaddr 0x00010000 0x000f0000\0" \
421376ae	229	LINUXBOOT_ENV_SETTINGS
5894ca00	230
5894ca00 MY	231	/* Open Firmware flat tree */
	232	#define CONFIG_OF_LIBFDT
	233
cf88affa	234	#define CONFIG_SYS_SDRAM_BASE 0x80000000
5894ca00	235	#define CONFIG_NR_DRAM_BANKS 2
5894ca00	236
8497ccc4 MY	237	#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) \|\| \
	238	defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) \|\| \
	239	defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
f5d0b9b2	240	#define CONFIG_SPL_TEXT_BASE 0x00040000
323d1f9d	241	#else
f5d0b9b2 MY	242	#define CONFIG_SPL_TEXT_BASE 0x00100000
	243	#endif
	244
ce3a6390	245	#define CONFIG_SPL_STACK (0x0ff08000)
8cddc279	246	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	247
a286039b MY	248	#define CONFIG_PANIC_HANG
a286039b MY	249
5894ca00	250	#define CONFIG_SPL_FRAMEWORK
499785b9	251	#define CONFIG_SPL_SERIAL_SUPPORT
5894ca00 MY	252	#define CONFIG_SPL_NAND_SUPPORT
	253
	254	#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
	255	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	256
	257	#define CONFIG_SPL_BOARD_INIT
	258
	259	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
	260
6a3cffe8 MY	261	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
6a3cffe8 MY	262
5894ca00	263	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */