[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-Boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK		12288000
#define CONFIG_SYS_NS16550_REG_SIZE	-2
#endif

/* TODO: move to Kconfig and device tree */
#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif

#define CONFIG_SMC911X

/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE	0
#define CONFIG_SMC911X_32_BIT

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_CACHELINE_SIZE	32

/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

/*
 * uncomment the following to disable FLASH related code.
 */
/* #define CONFIG_SYS_NO_FLASH */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for out supoort card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */
#define CONFIG_BAUDRATE			115200


#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE				0x2000
#define CONFIG_ENV_OFFSET			0x0
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000

/*
 * By default, ARP timeout is 5 sec.
 * The first ARP request does not seem to work.
 * So we need to retry ARP request anyway.
 * We want to shrink the interval until the second ARP request.
 */
#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */

#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

#define CONFIG_BOOTDELAY			3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	"tftpboot; bootm;"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0"
#else
#define CONFIG_CMD_BOOTZ
#define CONFIG_BOOTFILE			"zImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"kernel_addr=0x00200000\0" \
	"kernel_addr_r=0x80208000\0" \
	"kernel_size=0x00800000\0" \
	"ramdisk_addr=0x00a00000\0" \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
		"setexpr kernel_addr $nor_base + $kernel_addr &&" \
		"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
		"setexpr fdt_addr $nor_base + $fdt_addr &&" \
		"bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
	"nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
		"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
		"tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"norbase=0x42000000\0"					\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl-dtb.bin &&"		\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot-dtb.img &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	LINUXBOOT_ENV_SETTINGS

#define CONFIG_SYS_BOOTMAPSZ			0x20000000

/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_NR_DRAM_BANKS		2

#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
	defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
	defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#else
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#define CONFIG_SPL_STACK		(0x0ff08000)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT

#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

#define CONFIG_SPL_MAX_FOOTPRINT		0x10000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
f8f35944	2	* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
a187559e	7	/* U-Boot - Common settings for UniPhier Family */
5894ca00 MY	8
	9	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	10	#define __CONFIG_UNIPHIER_COMMON_H__
	11
233e42a9 MY	12	#define CONFIG_I2C_EEPROM
	13	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	14
d064cbff	15	#ifdef CONFIG_SYS_NS16550_SERIAL
5894ca00 MY	16	#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
	17	#define CONFIG_SYS_NS16550_CLK 12288000
	18	#define CONFIG_SYS_NS16550_REG_SIZE -2
d064cbff	19	#endif
5894ca00	20
f5d0b9b2 MY	21	/* TODO: move to Kconfig and device tree */
	22	#if 0
	23	#define CONFIG_SYS_NS16550_SERIAL
	24	#endif
	25
	26	#define CONFIG_SMC911X
	27
d7728aa4 MY	28	/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
d7728aa4 MY	29	#define CONFIG_SMC911X_BASE 0
5894ca00 MY	30	#define CONFIG_SMC911X_32_BIT
5894ca00 MY	31
5894ca00 MY	32	/*-----------------------------------------------------------------------
	33	* MMU and Cache Setting
	34	----------------------------------------------------------------------/
	35
	36	/* Comment out the following to enable L1 cache */
	37	/* #define CONFIG_SYS_ICACHE_OFF */
	38	/* #define CONFIG_SYS_DCACHE_OFF */
	39
53c45d4e MY	40	#define CONFIG_SYS_CACHELINE_SIZE 32
53c45d4e MY	41
5894ca00 MY	42	/* Comment out the following to enable L2 cache */
	43	#define CONFIG_UNIPHIER_L2CACHE_ON
	44
	45	#define CONFIG_DISPLAY_CPUINFO
	46	#define CONFIG_DISPLAY_BOARDINFO
08fda258	47	#define CONFIG_MISC_INIT_F
84ccd791	48	#define CONFIG_BOARD_EARLY_INIT_F
7a3620b2	49	#define CONFIG_BOARD_EARLY_INIT_R
5894ca00 MY	50	#define CONFIG_BOARD_LATE_INIT
	51
	52	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	53
	54	#define CONFIG_TIMESTAMP
	55
	56	/* FLASH related */
	57	#define CONFIG_MTD_DEVICE
	58
	59	/*
	60	* uncomment the following to disable FLASH related code.
	61	*/
	62	/* #define CONFIG_SYS_NO_FLASH */
	63
	64	#define CONFIG_FLASH_CFI_DRIVER
	65	#define CONFIG_SYS_FLASH_CFI
	66
	67	#define CONFIG_SYS_MAX_FLASH_SECT 256
	68	#define CONFIG_SYS_MONITOR_BASE 0
	69	#define CONFIG_SYS_FLASH_BASE 0
	70
	71	/*
	72	* flash_toggle does not work for out supoort card.
	73	* We need to use flash_status_poll.
	74	*/
	75	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	76
	77	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	78
9879842c	79	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	80
	81	/* serial console configuration */
	82	#define CONFIG_BAUDRATE 115200
	83
5894ca00 MY	84
	85	#if !defined(CONFIG_SPL_BUILD)
	86	#define CONFIG_USE_ARCH_MEMSET
	87	#define CONFIG_USE_ARCH_MEMCPY
	88	#endif
	89
	90	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	91
	92	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	93	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	94	/* Print Buffer Size */
	95	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	96	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	97	/* Boot Argument Buffer Size */
	98	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	99
	100	#define CONFIG_CONS_INDEX 1
	101
	102	/*
	103	* For NAND booting the environment is embedded in the U-Boot image. Please take
	104	* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
	105	*/
	106	/* #define CONFIG_ENV_IS_IN_NAND */
	107	#define CONFIG_ENV_IS_NOWHERE
	108	#define CONFIG_ENV_SIZE 0x2000
	109	#define CONFIG_ENV_OFFSET 0x0
	110	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
	111
	112	/* Time clock 1MHz */
	113	#define CONFIG_SYS_TIMER_RATE 1000000
	114
	115	/*
	116	* By default, ARP timeout is 5 sec.
	117	* The first ARP request does not seem to work.
	118	* So we need to retry ARP request anyway.
	119	* We want to shrink the interval until the second ARP request.
	120	*/
	121	#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
	122
5894ca00 MY	123	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	124	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	125	#define CONFIG_SYS_NAND_ONFI_DETECTION
	126
	127	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	128
8497ccc4	129	#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
3365b4eb MY	130	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	131	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	132	#else
5894ca00 MY	133	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	134	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	135	#endif
5894ca00 MY	136
	137	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	138
	139	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	140	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	141
495deb44	142	/* USB */
495deb44	143	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
53c45d4e	144	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	145	#define CONFIG_CMD_FAT
	146	#define CONFIG_FAT_WRITE
	147	#define CONFIG_DOS_PARTITION
	148
5894ca00 MY	149	/* memtest works on */
	150	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	151	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	152
	153	#define CONFIG_BOOTDELAY 3
	154	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
5894ca00 MY	155
	156	/*
	157	* Network Configuration
	158	*/
5894ca00 MY	159	#define CONFIG_SERVERIP 192.168.11.1
	160	#define CONFIG_IPADDR 192.168.11.10
	161	#define CONFIG_GATEWAYIP 192.168.11.1
	162	#define CONFIG_NETMASK 255.255.255.0
	163
	164	#define CONFIG_LOADADDR 0x84000000
	165	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	166
	167	#define CONFIG_CMDLINE_EDITING /* add command line history */
	168
	169	#define CONFIG_BOOTCOMMAND "run $bootmode"
	170
	171	#define CONFIG_ROOTPATH "/nfs/root/path"
	172	#define CONFIG_NFSBOOTCOMMAND \
	173	"setenv bootargs $bootargs root=/dev/nfs rw " \
	174	"nfsroot=$serverip:$rootpath " \
	175	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
	176	"tftpboot; bootm;"
	177
421376ae MY	178	#ifdef CONFIG_FIT
	179	#define CONFIG_BOOTFILE "fitImage"
	180	#define LINUXBOOT_ENV_SETTINGS \
	181	"fit_addr=0x00100000\0" \
	182	"fit_addr_r=0x84100000\0" \
	183	"fit_size=0x00f00000\0" \
5451b777	184	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae	185	"bootm $fit_addr\0" \
5451b777	186	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c	187	"bootm $fit_addr_r\0" \
5451b777	188	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
421376ae MY	189	"bootm $fit_addr_r\0"
421376ae MY	190	#else
89835b35 MY	191	#define CONFIG_CMD_BOOTZ
89835b35 MY	192	#define CONFIG_BOOTFILE "zImage"
421376ae MY	193	#define LINUXBOOT_ENV_SETTINGS \
	194	"fdt_addr=0x00100000\0" \
	195	"fdt_addr_r=0x84100000\0" \
	196	"fdt_size=0x00008000\0" \
	197	"kernel_addr=0x00200000\0" \
89835b35	198	"kernel_addr_r=0x80208000\0" \
421376ae MY	199	"kernel_size=0x00800000\0" \
	200	"ramdisk_addr=0x00a00000\0" \
	201	"ramdisk_addr_r=0x84a00000\0" \
	202	"ramdisk_size=0x00600000\0" \
e037db0c	203	"ramdisk_file=rootfs.cpio.uboot\0" \
25d4eb80 MY	204	"norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
25d4eb80 MY	205	"setexpr kernel_addr $nor_base + $kernel_addr &&" \
d5ed8c57 MY	206	"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
d5ed8c57 MY	207	"setexpr fdt_addr $nor_base + $fdt_addr &&" \
89835b35	208	"bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
25d4eb80 MY	209	"nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
25d4eb80 MY	210	"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
421376ae MY	211	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
421376ae MY	212	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
89835b35	213	"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
25d4eb80 MY	214	"tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
25d4eb80 MY	215	"tftpboot $kernel_addr_r $bootfile &&" \
e037db0c MY	216	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
e037db0c MY	217	"tftpboot $fdt_addr_r $fdt_file &&" \
89835b35	218	"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
421376ae MY	219	#endif
	220
	221	#define CONFIG_EXTRA_ENV_SETTINGS \
	222	"netdev=eth0\0" \
	223	"verify=n\0" \
d5ed8c57	224	"norbase=0x42000000\0" \
421376ae	225	"nandupdate=nand erase 0 0x00100000 &&" \
f4e190e3	226	"tftpboot u-boot-spl-dtb.bin &&" \
421376ae MY	227	"nand write $loadaddr 0 0x00010000 &&" \
	228	"tftpboot u-boot-dtb.img &&" \
	229	"nand write $loadaddr 0x00010000 0x000f0000\0" \
421376ae	230	LINUXBOOT_ENV_SETTINGS
5894ca00	231
17bd4a21 MY	232	#define CONFIG_SYS_BOOTMAPSZ 0x20000000
17bd4a21 MY	233
5894ca00 MY	234	/* Open Firmware flat tree */
	235	#define CONFIG_OF_LIBFDT
	236
cf88affa	237	#define CONFIG_SYS_SDRAM_BASE 0x80000000
5894ca00	238	#define CONFIG_NR_DRAM_BANKS 2
5894ca00	239
8497ccc4 MY	240	#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) \|\| \
	241	defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) \|\| \
	242	defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
f5d0b9b2	243	#define CONFIG_SPL_TEXT_BASE 0x00040000
323d1f9d	244	#else
f5d0b9b2 MY	245	#define CONFIG_SPL_TEXT_BASE 0x00100000
	246	#endif
	247
ce3a6390	248	#define CONFIG_SPL_STACK (0x0ff08000)
8cddc279	249	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	250
a286039b MY	251	#define CONFIG_PANIC_HANG
a286039b MY	252
5894ca00	253	#define CONFIG_SPL_FRAMEWORK
499785b9	254	#define CONFIG_SPL_SERIAL_SUPPORT
5894ca00 MY	255	#define CONFIG_SPL_NAND_SUPPORT
	256
	257	#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
	258	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	259
	260	#define CONFIG_SPL_BOARD_INIT
	261
	262	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
	263
6a3cffe8 MY	264	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
6a3cffe8 MY	265
5894ca00	266	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */